yroux [Tue, 26 Aug 2014 13:11:41 +0000 (13:11 +0000)]
gcc/testsuite/
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213701.
2014-08-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.dg/pr61756.c: Remove arm-specific dg-options.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214517
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 13:05:05 +0000 (13:05 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213627.
2014-08-05 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_simd_builtin_type_mode): Delete.
(v8qi_UP): Remap to V8QImode.
(v4hi_UP): Remap to V4HImode.
(v2si_UP): Remap to V2SImode.
(v2sf_UP): Remap to V2SFmode.
(v1df_UP): Remap to V1DFmode.
(di_UP): Remap to DImode.
(df_UP): Remap to DFmode.
(v16qi_UP):V16QImode.
(v8hi_UP): Remap to V8HImode.
(v4si_UP): Remap to V4SImode.
(v4sf_UP): Remap to V4SFmode.
(v2di_UP): Remap to V2DImode.
(v2df_UP): Remap to V2DFmode.
(ti_UP): Remap to TImode.
(ei_UP): Remap to EImode.
(oi_UP): Remap to OImode.
(ci_UP): Map to CImode.
(xi_UP): Remap to XImode.
(si_UP): Remap to SImode.
(sf_UP): Remap to SFmode.
(hi_UP): Remap to HImode.
(qi_UP): Remap to QImode.
(aarch64_simd_builtin_datum): Make mode a machine_mode.
(VAR1): Build builtin name.
(aarch64_init_simd_builtins): Remove dead code.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214516
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:56:05 +0000 (12:56 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213713.
2014-08-07 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (*cmov<mode>): Set type attribute to fcsel.
* config/arm/types.md (f_sels, f_seld): Delete.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214515
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:53:08 +0000 (12:53 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213711.
2014-08-07 Ian Bolton <ian.bolton@arm.com>
Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_mov_immediate):
Use MOVN when one of the half-words is 0xffff.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214514
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:48:57 +0000 (12:48 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213632.
2014-08-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/cortex-a15.md (cortex_a15_alu_shift): Add crc type
to reservation.
* config/arm/cortex-a53.md (cortex_a53_alu_shift): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214513
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:45:00 +0000 (12:45 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213630.
2014-08-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (clzsi2): Set predicable_short_it attr to no.
(rbitsi2): Likewise.
(*arm_rev): Set predicable and predicable_short_it attributes.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214512
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:38:40 +0000 (12:38 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213557.
2014-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
James Greenhalgh <james.greenhalgh@arm.com>
* doc/md.texi (clrsb): Document.
(clz): Change reference to x into operand 1.
(ctz): Likewise.
(popcount): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214511
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:34:43 +0000 (12:34 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213551, r213556.
2014-08-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* sched-deps.c (try_group_insn): Generalise macro fusion hook usage
to any two insns. Update comment. Rename to sched_macro_fuse_insns.
(sched_analyze_insn): Update use of try_group_insn to
sched_macro_fuse_insns.
* config/i386/i386.c (ix86_macro_fusion_pair_p): Reject 2nd
arguments that are not conditional jumps.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214509
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:29:51 +0000 (12:29 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213490.
2014-08-01 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd-builtins.def (dup_lane, get_lane): Delete.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214507
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:24:32 +0000 (12:24 +0000)]
gcc/
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213488.
2014-08-01 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_classify_address): Accept all offset
for frame access when strict_p is false.
gcc/testsuite/
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213488, r213489.
2014-08-01 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/legitimize_stack_var_before_reload_1.c: New
testcase.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214506
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:17:31 +0000 (12:17 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213485, r213486, r213487.
2014-08-01 Renlin Li <renlin.li@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (offset_7bit_signed_scaled_p): Rename to
aarch64_offset_7bit_signed_scaled_p, remove static and use it.
* config/aarch64/aarch64-protos.h (aarch64_offset_7bit_signed_scaled_p):
Declaration.
* config/aarch64/predicates.md (aarch64_mem_pair_offset): Define new
predicate.
* config/aarch64/aarch64.md (loadwb_pair, storewb_pair): Use
aarch64_mem_pair_offset.
2014-08-01 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.md (loadwb_pair<GPI:mode>_<P:mode>): Fix
offset.
(loadwb_pair<GPI:mode>_<P:mode>): Likewise.
* config/aarch64/aarch64.c (aarch64_gen_loadwb_pair): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214505
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 12:11:06 +0000 (12:11 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213379.
2014-07-31 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_gimple_fold_builtin): Don't fold reduction operations for
BYTES_BIG_ENDIAN.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214504
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 26 Aug 2014 11:47:28 +0000 (11:47 +0000)]
2014-08-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213378.
2014-07-31 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_simd_vect_par_cnst_half): Vary
the generated mask based on BYTES_BIG_ENDIAN.
(aarch64_simd_check_vect_par_cnst_half): New.
* config/aarch64/aarch64-protos.h
(aarch64_simd_check_vect_par_cnst_half): New.
* config/aarch64/predicates.md (vect_par_cnst_hi_half): Refactor
the check out to aarch64_simd_check_vect_par_cnst_half.
(vect_par_cnst_lo_half): Likewise.
* config/aarch64/aarch64-simd.md
(aarch64_simd_move_hi_quad_<mode>): Always use vec_par_cnst_lo_half.
(move_hi_quad_<mode>): Always generate a low mask.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214502
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 22 Aug 2014 11:41:54 +0000 (11:41 +0000)]
gcc/
2014-08-22 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212927, r213304.
2014-07-30 Jiong Wang <jiong.wang@arm.com>
* config/arm/arm.c (arm_get_frame_offsets): Adjust condition for
Thumb2.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/arm/arm.c (arm_get_frame_offsets): If both r3 and other
callee-saved registers are available for padding purpose
and r3 is not mandatory, then prefer use those callee-saved
instead of r3.
gcc/testsuite/
2014-08-22 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212927.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* gcc.dg/ira-shrinkwrap-prep-1.c (target): Add arm_nothumb.
* gcc.dg/ira-shrinkwrap-prep-2.c (target): Likewise.
* gcc.dg/pr10474.c (target): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214314
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 22 Aug 2014 10:59:41 +0000 (10:59 +0000)]
2014-08-22 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211717, r213692.
2014-08-07 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/arm/arm.c (bdesc_2arg): Fix typo.
(arm_atomic_assign_expand_fenv): Remove The default implementation.
2014-06-17 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/arm/arm.c (arm_atomic_assign_expand_fenv): call
default_atomic_assign_expand_fenv for !TARGET_HARD_FLOAT.
(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
__builtins_arm_get_fpscr only when TARGET_HARD_FLOAT.
* config/arm/vfp.md (set_fpscr): Make pattern conditional on
TARGET_HARD_FLOAT.
(get_fpscr) : Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214313
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 22 Aug 2014 10:48:22 +0000 (10:48 +0000)]
2014-08-22 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212989, r213628.
2014-08-05 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* convert.c (convert_to_integer): Guard transformation to lrint by
-fno-math-errno.
2014-07-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR middle-end/61876
* convert.c (convert_to_integer): Do not convert BUILT_IN_ROUND and cast
when flag_errno_math is on.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214312
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 15 Aug 2014 19:21:06 +0000 (19:21 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214036
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 15 Aug 2014 19:14:58 +0000 (19:14 +0000)]
Make Linaro GCC 4.9-2014.08.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@214032
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 14 Aug 2014 08:19:37 +0000 (08:19 +0000)]
Merge branches/gcc-4_9-branch rev 213803
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213943
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Mon, 11 Aug 2014 15:09:48 +0000 (15:09 +0000)]
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212912, r212913.
2014-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle CLRSB, CLZ.
(case UNSPEC): Handle UNSPEC_RBIT.
2014-07-22 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md: Delete UNSPEC_CLS.
(clrsb<mode>2): Use clrsb RTL code instead of UNSPEC_CLS.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213817
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 23:03:16 +0000 (23:03 +0000)]
gcc/
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213555.
2014-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/61713
* gcc/optabs.c (expand_atomic_test_and_set): Do not try to emit
move to subtarget in serial version if result is ignored.
gcc/testsuite
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213555.
2014-08-04 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR target/61713
* gcc.dg/pr61756.c: New test.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213801
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 22:59:19 +0000 (22:59 +0000)]
gcc/
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213376.
2014-07-31 Charles Baylis <charles.baylis@linaro.org>
PR target/61948
* config/arm/neon.md (ashldi3_neon): Don't emit arm_ashldi3_1bit unless
constraints are satisfied.
(<shift>di3_neon): Likewise.
gcc/testsuite
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r213376.
2014-07-31 Charles Baylis <charles.baylis@linaro.org>
PR target/61948
* gcc.target/arm/pr61948.c: New test case.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213800
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 22:53:28 +0000 (22:53 +0000)]
gcc/
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211270, r211271, r211273, r211275, r212943,
r212945, r212946, r212947, r212949, r212950, r212951, r212952, r212954,
r212955, r212956, r212957, r212958, r212976, r212996, r212997, r212999,
r213000.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_popwb_single_reg): New function.
(aarch64_expand_epilogue): Optimize epilogue when !frame_pointer_needed.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_pushwb_single_reg): New function.
(aarch64_expand_prologue): Optimize prologue when !frame_pointer_needed.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_restore_callee_saves)
(aarch64_save_callee_saves): New parameter "skip_wb".
(aarch64_expand_prologue, aarch64_expand_epilogue): Update call site.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.h (frame): New fields "wb_candidate1" and
"wb_candidate2".
* config/aarch64/aarch64.c (aarch64_layout_frame): Initialize above.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_epilogue): Don't
subtract outgoing area size when restoring stack_pointer_rtx.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_popwb_pair_reg)
(aarch64_gen_loadwb_pair): New helper function.
(aarch64_expand_epilogue): Simplify code using new helper functions.
* config/aarch64/aarch64.md (loadwb_pair<GPF:mode>_<P:mode>): Define.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_pushwb_pair_reg)
(aarch64_gen_storewb_pair): New helper function.
(aarch64_expand_prologue): Simplify code using new helper functions.
* config/aarch64/aarch64.md (storewb_pair<GPF:mode>_<P:mode>): Define.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.md: (aarch64_save_or_restore_callee_saves):
Rename to aarch64_save_callee_saves, remove restore code.
(aarch64_restore_callee_saves): New function.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Deleted.
(aarch64_save_callee_saves): New function to handle reg save
for both core and vectore regs.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_gen_load_pair)
(aarch64_gen_store_pair): New helper function.
(aarch64_save_or_restore_callee_save_registers)
(aarch64_save_or_restore_fprs): Use new helper functions.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_next_callee_save): New function.
(aarch64_save_or_restore_callee_save_registers)
(aarch64_save_or_restore_fprs): Use aarch64_next_callee_save.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c
(aarch64_save_or_restore_callee_save_registers)
(aarch64_save_or_restore_fprs): Hoist calculation of register rtx.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c
(aarch64_save_or_restore_callee_save_registers)
(aarch64_save_or_restore_fprs): Remove 'increment'.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c
(aarch64_save_or_restore_callee_save_registers)
(aarch64_save_or_restore_fprs): Use register offset in
cfun->machine->frame.reg_offset.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c
(aarch64_save_or_restore_callee_save_registers)
(aarch64_save_or_restore_fprs): Remove base_rtx.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c
(aarch64_save_or_restore_callee_save_registers): Rename 'offset'
to 'start_offset'. Remove local variable 'start_offset'.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Change
type to HOST_WIDE_INT.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_prologue)
(aarch64_save_or_restore_fprs)
(aarch64_save_or_restore_callee_save_registers): GNU-Stylize code.
2014-06-05 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.h (aarch64_frame): Add hard_fp_offset and
frame_size.
* config/aarch64/aarch64.c (aarch64_layout_frame): Initialize
aarch64_frame hard_fp_offset and frame_size.
(aarch64_expand_prologue): Use aarch64_frame hard_fp_offset and
frame_size; remove original_frame_size.
(aarch64_expand_epilogue, aarch64_final_eh_return_addr): Likewise.
(aarch64_initial_elimination_offset): Remove frame_size and
offset. Use aarch64_frame frame_size.
2014-06-05 Marcus Shawcroft <marcus.shawcroft@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_layout_frame): Correct
initialization of R30 offset. Update offset. Iterate core
regisers upto X30. Remove X29, X30 specific code.
2014-06-05 Marcus Shawcroft <marcus.shawcroft@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (SLOT_NOT_REQUIRED, SLOT_REQUIRED): Define.
(aarch64_layout_frame): Use SLOT_NOT_REQUIRED and SLOT_REQUIRED.
(aarch64_register_saved_on_entry): Adjust test.
2014-06-05 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.h (machine_function): Move
saved_varargs_size from here...
(aarch64_frameGTY): ... to here.
* config/aarch64/aarch64.c (aarch64_expand_prologue)
(aarch64_expand_epilogue, aarch64_final_eh_return_addr)
(aarch64_initial_elimination_offset)
(aarch64_setup_incoming_varargs): Adjust location of
saved_varargs_size.
gcc/testsuite/
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212959, r212976, r212999, r213000.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/test_frame_1.c: Match optimized instruction
sequences.
* gcc.target/aarch64/test_frame_2.c: Likewise.
* gcc.target/aarch64/test_frame_4.c: Likewise.
* gcc.target/aarch64/test_frame_6.c: Likewise.
* gcc.target/aarch64/test_frame_7.c: Likewise.
* gcc.target/aarch64/test_frame_8.c: Likewise.
* gcc.target/aarch64/test_frame_10.c: Likewise.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/test_frame_1.c: Match optimized instruction
sequences.
* gcc.target/aarch64/test_frame_10.c: Likewise.
* gcc.target/aarch64/test_frame_2.c: Likewise.
* gcc.target/aarch64/test_frame_4.c: Likewise.
* gcc.target/aarch64/test_frame_6.c: Likewise.
* gcc.target/aarch64/test_frame_7.c: Likewise.
* gcc.target/aarch64/test_frame_8.c: Likewise.
* gcc.target/aarch64/test_fp_attribute_1.c: Likewise.
2014-07-24 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/test_frame_12.c: Match optimized instruction
sequences.
2014-07-23 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/test_frame_common.h: New file.
* gcc.target/aarch64/test_frame_1.c: Likewise.
* gcc.target/aarch64/test_frame_2.c: Likewise.
* gcc.target/aarch64/test_frame_3.c: Likewise.
* gcc.target/aarch64/test_frame_4.c: Likewise.
* gcc.target/aarch64/test_frame_5.c: Likewise.
* gcc.target/aarch64/test_frame_6.c: Likewise.
* gcc.target/aarch64/test_frame_7.c: Likewise.
* gcc.target/aarch64/test_frame_8.c: Likewise.
* gcc.target/aarch64/test_frame_9.c: Likewise.
* gcc.target/aarch64/test_frame_10.c: Likewise.
* gcc.target/aarch64/test_frame_11.c: Likewise.
* gcc.target/aarch64/test_frame_12.c: Likewise.
* gcc.target/aarch64/test_frame_13.c: Likewise.
* gcc.target/aarch64/test_frame_14.c: Likewise.
* gcc.target/aarch64/test_frame_15.c: Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213799
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 22:46:17 +0000 (22:46 +0000)]
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212753.
2014-07-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (aarch64_frint_unspec_p): New function.
(aarch64_rtx_costs): Handle FIX, UNSIGNED_FIX, UNSPEC.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213798
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 22:43:26 +0000 (22:43 +0000)]
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212752.
2014-07-17 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/arm_neon.h (vmlal_high_lane_s16): Fix type.
(vmlal_high_lane_s32): Likewise.
(vmlal_high_lane_u16): Likewise.
(vmlal_high_lane_u32): Likewise.
(vmlsl_high_lane_s16): Likewise.
(vmlsl_high_lane_s32): Likewise.
(vmlsl_high_lane_u16): Likewise.
(vmlsl_high_lane_u32): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213797
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 22:38:40 +0000 (22:38 +0000)]
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212512.
2014-07-14 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/cortex-a15.md (cortex_a15_alu): Handle clz, rbit.
* config/arm/cortex-a5.md (cortex_a5_alu): Likewise.
* config/arm/cortex-a53.md (cortex_a53_alu): Likewise.
* config/arm/cortex-a7.md (cortex_a7_alu_reg): Likewise.
* config/arm/cortex-a9.md (cortex_a9_dp): Likewise.
* config/arm/cortex-m4.md (cortex_m4_alu): Likewise.
* config/arm/cortex-r4.md (cortex_r4_alu): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213796
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 22:32:57 +0000 (22:32 +0000)]
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212358.
2014-07-08 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (cortexa5_extra_costs): New table.
(arm_cortex_a5_tune): Use cortexa5_extra_costs.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213795
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 22:29:06 +0000 (22:29 +0000)]
2014-08-11 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212296.
2014-07-04 Tom de Vries <tom@codesourcery.com>
* config/aarch64/aarch64-simd.md
(define_insn "vec_unpack_trunc_<mode>"): Fix constraint.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213794
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 15:28:41 +0000 (15:28 +0000)]
2014-08-10 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212142, r212225.
2014-07-02 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Delete unused
variable i.
2014-06-30 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md (vec_perm): Enable for bigendian.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm): Remove assert
against bigendian and adjust indices.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213793
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 15:25:05 +0000 (15:25 +0000)]
gcc/testsuite/
2014-08-10 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r212023, r212024.
2014-06-26 Vidya Praveen <vidyapraveen@arm.com>
* gcc.dg/inline-22.c: Add bind_pic_locally.
* gcc.dg/inline_4.c: Ditto.
* gcc.dg/fail_always_inline.c: Ditto.
* g++.dg/ipa/devirt-25.C: Ditto.
2014-06-26 Vidya Praveen <vidyapraveen@arm.com>
* lib/target-support.exp (bind_pic_locally): Save the flags to
'flags_to_postpone' instead of appending to 'flags'.
* lib/gcc.exp (gcc_target_compile): Append board_info's multilib_flags
with flags_to_postpone and revert after target_compile.
* lib/g++.exp (g++_target_compile): Ditto.
* lib/gfortran.exp (gfortran_target_compile): Ditto.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213792
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 15:19:00 +0000 (15:19 +0000)]
2014-08-10 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211779.
2014-06-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm_neon.h (vadd_f32): Change #ifdef to __FAST_MATH.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213791
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 10 Aug 2014 15:05:54 +0000 (15:05 +0000)]
2014-07-30 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211503.
2014-06-12 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/arm_neon.h (vmlaq_n_f64, vmlsq_n_f64, vrsrtsq_f64,
vcge_p8, vcgeq_p8, vcgez_p8, vcgez_u8, vcgez_u16, vcgez_u32, vcgez_u64,
vcgezq_p8, vcgezq_u8, vcgezq_u16, vcgezq_u32, vcgezq_u64, vcgezd_u64,
vcgt_p8, vcgtq_p8, vcgtz_p8, vcgtz_u8, vcgtz_u16, vcgtz_u32, vcgtz_u64,
vcgtzq_p8, vcgtzq_u8, vcgtzq_u16, vcgtzq_u32, vcgtzq_u64, vcgtzd_u64,
vcle_p8, vcleq_p8, vclez_p8, vclez_u64, vclezq_p8, vclezd_u64, vclt_p8,
vcltq_p8, vcltz_p8, vcltzq_p8, vcltzd_u64): Remove functions as they are
not in the spec.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213790
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 1 Aug 2014 13:12:39 +0000 (13:12 +0000)]
2014-07-30 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211140.
2014-06-02 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.md (set_fpcr): Drop ISB after FPCR write.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213455
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 31 Jul 2014 12:34:02 +0000 (12:34 +0000)]
Fix gcc/ChangeLog.linaro.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213348
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 29 Jul 2014 09:36:51 +0000 (09:36 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213151
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 29 Jul 2014 09:33:33 +0000 (09:33 +0000)]
Make Linaro GCC 4.9-2014.07-1.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@213148
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 24 Jul 2014 11:02:04 +0000 (11:02 +0000)]
Merge branches/gcc-4_9-branch rev 212635
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212977
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sun, 20 Jul 2014 12:04:22 +0000 (12:04 +0000)]
2014-07-20 Yvan Roux <yvan.roux@linaro.org>
Revert:
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211129.
2014-06-02 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/61154
* config/arm/arm.h (TARGET_SUPPORTS_WIDE_INT): Define.
* config/arm/arm.md (mov64 splitter): Replace const_double_operand
with immediate_operand.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212866
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sat, 19 Jul 2014 08:52:39 +0000 (08:52 +0000)]
Bump version number, post release and fixed ChangeLog.linaro.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212836
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Sat, 19 Jul 2014 08:21:08 +0000 (08:21 +0000)]
Make Linaro GCC 4.9-2014.07.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212834
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 17 Jul 2014 06:28:10 +0000 (06:28 +0000)]
gcc/
2014-07-17 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211887, r211899.
2014-06-23 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md (addsi3_aarch64): Set "simd" attr to
"yes" where needed.
2014-06-23 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.md (*addsi3_aarch64): Add alternative in
vector registers.
gcc/testsuite
2014-07-17 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211887.
2014-06-23 James Greenhalgh <james.greenhalgh@arm.com>
* gcc.target/aarch64/scalar_shift_1.c: Fix expected assembler.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212722
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 17 Jul 2014 06:21:27 +0000 (06:21 +0000)]
gcc/
2014-07-17 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211440.
2014-06-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config.gcc (aarch64*-*-*): Add arm_acle.h to extra headers.
* Makefile.in (TEXI_GCC_FILES): Add aarch64-acle-intrinsics.texi to
dependencies.
* config/aarch64/aarch64-builtins.c (AARCH64_CRC32_BUILTINS): Define.
(aarch64_crc_builtin_datum): New struct.
(aarch64_crc_builtin_data): New.
(aarch64_init_crc32_builtins): New function.
(aarch64_init_builtins): Initialise CRC32 builtins when appropriate.
(aarch64_crc32_expand_builtin): New.
(aarch64_expand_builtin): Add CRC32 builtin expansion case.
* config/aarch64/aarch64.h (TARGET_CPU_CPP_BUILTINS): Define
__ARM_FEATURE_CRC32 when appropriate.
(TARGET_CRC32): Define.
* config/aarch64/aarch64.md (UNSPEC_CRC32B, UNSPEC_CRC32H,
UNSPEC_CRC32W, UNSPEC_CRC32X, UNSPEC_CRC32CB, UNSPEC_CRC32CH,
UNSPEC_CRC32CW, UNSPEC_CRC32CX): New unspec values.
(aarch64_<crc_variant>): New pattern.
* config/aarch64/arm_acle.h: New file.
* config/aarch64/iterators.md (CRC): New int iterator.
(crc_variant, crc_mode): New int attributes.
* doc/aarch64-acle-intrinsics.texi: New file.
* doc/extend.texi (aarch64): Document aarch64 ACLE intrinsics.
Include aarch64-acle-intrinsics.texi.
gcc/testsuite
2014-07-17 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211441.
2014-06-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/acle/acle.exp: New.
* gcc.target/aarch64/acle/crc32b.c: New test.
* gcc.target/aarch64/acle/crc32cb.c: Likewise.
* gcc.target/aarch64/acle/crc32cd.c: Likewise.
* gcc.target/aarch64/acle/crc32ch.c: Likewise.
* gcc.target/aarch64/acle/crc32cw.c: Likewise.
* gcc.target/aarch64/acle/crc32d.c: Likewise.
* gcc.target/aarch64/acle/crc32h.c: Likewise.
* gcc.target/aarch64/acle/crc32w.c: Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212720
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 17 Jul 2014 06:02:20 +0000 (06:02 +0000)]
gcc/
2014-07-17 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211174.
2014-06-03 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-simd.md (aarch64_rev<REVERSE:rev-op><mode>):
New pattern.
* config/aarch64/aarch64.c (aarch64_evpc_rev): New function.
(aarch64_expand_vec_perm_const_1): Add call to aarch64_evpc_rev.
* config/aarch64/iterators.md (REVERSE): New iterator.
(UNSPEC_REV64, UNSPEC_REV32, UNSPEC_REV16): New enum elements.
(rev_op): New int_attribute.
* config/aarch64/arm_neon.h (vrev16_p8, vrev16_s8, vrev16_u8,
vrev16q_p8, vrev16q_s8, vrev16q_u8, vrev32_p8, vrev32_p16, vrev32_s8,
vrev32_s16, vrev32_u8, vrev32_u16, vrev32q_p8, vrev32q_p16, vrev32q_s8,
vrev32q_s16, vrev32q_u8, vrev32q_u16, vrev64_f32, vrev64_p8,
vrev64_p16, vrev64_s8, vrev64_s16, vrev64_s32, vrev64_u8, vrev64_u16,
vrev64_u32, vrev64q_f32, vrev64q_p8, vrev64q_p16, vrev64q_s8,
vrev64q_s16, vrev64q_s32, vrev64q_u8, vrev64q_u16, vrev64q_u32):
Replace temporary __asm__ with __builtin_shuffle.
gcc/testsuite
2014-07-17 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210153.
2014-05-07 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/vrev16p8_1.c: New file.
* gcc.target/aarch64/simd/vrev16p8.x: New file.
* gcc.target/aarch64/simd/vrev16qp8_1.c: New file.
* gcc.target/aarch64/simd/vrev16qp8.x: New file.
* gcc.target/aarch64/simd/vrev16qs8_1.c: New file.
* gcc.target/aarch64/simd/vrev16qs8.x: New file.
* gcc.target/aarch64/simd/vrev16qu8_1.c: New file.
* gcc.target/aarch64/simd/vrev16qu8.x: New file.
* gcc.target/aarch64/simd/vrev16s8_1.c: New file.
* gcc.target/aarch64/simd/vrev16s8.x: New file.
* gcc.target/aarch64/simd/vrev16u8_1.c: New file.
* gcc.target/aarch64/simd/vrev16u8.x: New file.
* gcc.target/aarch64/simd/vrev32p16_1.c: New file.
* gcc.target/aarch64/simd/vrev32p16.x: New file.
* gcc.target/aarch64/simd/vrev32p8_1.c: New file.
* gcc.target/aarch64/simd/vrev32p8.x: New file.
* gcc.target/aarch64/simd/vrev32qp16_1.c: New file.
* gcc.target/aarch64/simd/vrev32qp16.x: New file.
* gcc.target/aarch64/simd/vrev32qp8_1.c: New file.
* gcc.target/aarch64/simd/vrev32qp8.x: New file.
* gcc.target/aarch64/simd/vrev32qs16_1.c: New file.
* gcc.target/aarch64/simd/vrev32qs16.x: New file.
* gcc.target/aarch64/simd/vrev32qs8_1.c: New file.
* gcc.target/aarch64/simd/vrev32qs8.x: New file.
* gcc.target/aarch64/simd/vrev32qu16_1.c: New file.
* gcc.target/aarch64/simd/vrev32qu16.x: New file.
* gcc.target/aarch64/simd/vrev32qu8_1.c: New file.
* gcc.target/aarch64/simd/vrev32qu8.x: New file.
* gcc.target/aarch64/simd/vrev32s16_1.c: New file.
* gcc.target/aarch64/simd/vrev32s16.x: New file.
* gcc.target/aarch64/simd/vrev32s8_1.c: New file.
* gcc.target/aarch64/simd/vrev32s8.x: New file.
* gcc.target/aarch64/simd/vrev32u16_1.c: New file.
* gcc.target/aarch64/simd/vrev32u16.x: New file.
* gcc.target/aarch64/simd/vrev32u8_1.c: New file.
* gcc.target/aarch64/simd/vrev32u8.x: New file.
* gcc.target/aarch64/simd/vrev64f32_1.c: New file.
* gcc.target/aarch64/simd/vrev64f32.x: New file.
* gcc.target/aarch64/simd/vrev64p16_1.c: New file.
* gcc.target/aarch64/simd/vrev64p16.x: New file.
* gcc.target/aarch64/simd/vrev64p8_1.c: New file.
* gcc.target/aarch64/simd/vrev64p8.x: New file.
* gcc.target/aarch64/simd/vrev64qf32_1.c: New file.
* gcc.target/aarch64/simd/vrev64qf32.x: New file.
* gcc.target/aarch64/simd/vrev64qp16_1.c: New file.
* gcc.target/aarch64/simd/vrev64qp16.x: New file.
* gcc.target/aarch64/simd/vrev64qp8_1.c: New file.
* gcc.target/aarch64/simd/vrev64qp8.x: New file.
* gcc.target/aarch64/simd/vrev64qs16_1.c: New file.
* gcc.target/aarch64/simd/vrev64qs16.x: New file.
* gcc.target/aarch64/simd/vrev64qs32_1.c: New file.
* gcc.target/aarch64/simd/vrev64qs32.x: New file.
* gcc.target/aarch64/simd/vrev64qs8_1.c: New file.
* gcc.target/aarch64/simd/vrev64qs8.x: New file.
* gcc.target/aarch64/simd/vrev64qu16_1.c: New file.
* gcc.target/aarch64/simd/vrev64qu16.x: New file.
* gcc.target/aarch64/simd/vrev64qu32_1.c: New file.
* gcc.target/aarch64/simd/vrev64qu32.x: New file.
* gcc.target/aarch64/simd/vrev64qu8_1.c: New file.
* gcc.target/aarch64/simd/vrev64qu8.x: New file.
* gcc.target/aarch64/simd/vrev64s16_1.c: New file.
* gcc.target/aarch64/simd/vrev64s16.x: New file.
* gcc.target/aarch64/simd/vrev64s32_1.c: New file.
* gcc.target/aarch64/simd/vrev64s32.x: New file.
* gcc.target/aarch64/simd/vrev64s8_1.c: New file.
* gcc.target/aarch64/simd/vrev64s8.x: New file.
* gcc.target/aarch64/simd/vrev64u16_1.c: New file.
* gcc.target/aarch64/simd/vrev64u16.x: New file.
* gcc.target/aarch64/simd/vrev64u32_1.c: New file.
* gcc.target/aarch64/simd/vrev64u32.x: New file.
* gcc.target/aarch64/simd/vrev64u8_1.c: New file.
* gcc.target/aarch64/simd/vrev64u8.x: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212715
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 17 Jul 2014 05:51:44 +0000 (05:51 +0000)]
2014-07-17 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210216, r210218, r210219.
2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm_neon.h: Update comment.
* config/arm/neon-docgen.ml: Delete.
* config/arm/neon-gen.ml: Delete.
* doc/arm-neon-intrinsics.texi: Update comment.
2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm_neon_builtins.def (vadd, vsub): Only define the v2sf
and v4sf versions.
(vand, vorr, veor, vorn, vbic): Remove.
* config/arm/neon.md (neon_vadd, neon_vsub, neon_vadd_unspec): Adjust
iterator.
(neon_vsub_unspec): Likewise.
(neon_vorr, neon_vand, neon_vbic, neon_veor, neon_vorn): Remove.
2014-05-08 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm_neon.h (vadd_s8): GNU C implementation
(vadd_s16): Likewise.
(vadd_s32): Likewise.
(vadd_f32): Likewise.
(vadd_u8): Likewise.
(vadd_u16): Likewise.
(vadd_u32): Likewise.
(vadd_s64): Likewise.
(vadd_u64): Likewise.
(vaddq_s8): Likewise.
(vaddq_s16): Likewise.
(vaddq_s32): Likewise.
(vaddq_s64): Likewise.
(vaddq_f32): Likewise.
(vaddq_u8): Likewise.
(vaddq_u16): Likewise.
(vaddq_u32): Likewise.
(vaddq_u64): Likewise.
(vmul_s8): Likewise.
(vmul_s16): Likewise.
(vmul_s32): Likewise.
(vmul_f32): Likewise.
(vmul_u8): Likewise.
(vmul_u16): Likewise.
(vmul_u32): Likewise.
(vmul_p8): Likewise.
(vmulq_s8): Likewise.
(vmulq_s16): Likewise.
(vmulq_s32): Likewise.
(vmulq_f32): Likewise.
(vmulq_u8): Likewise.
(vmulq_u16): Likewise.
(vmulq_u32): Likewise.
(vsub_s8): Likewise.
(vsub_s16): Likewise.
(vsub_s32): Likewise.
(vsub_f32): Likewise.
(vsub_u8): Likewise.
(vsub_u16): Likewise.
(vsub_u32): Likewise.
(vsub_s64): Likewise.
(vsub_u64): Likewise.
(vsubq_s8): Likewise.
(vsubq_s16): Likewise.
(vsubq_s32): Likewise.
(vsubq_s64): Likewise.
(vsubq_f32): Likewise.
(vsubq_u8): Likewise.
(vsubq_u16): Likewise.
(vsubq_u32): Likewise.
(vsubq_u64): Likewise.
(vand_s8): Likewise.
(vand_s16): Likewise.
(vand_s32): Likewise.
(vand_u8): Likewise.
(vand_u16): Likewise.
(vand_u32): Likewise.
(vand_s64): Likewise.
(vand_u64): Likewise.
(vandq_s8): Likewise.
(vandq_s16): Likewise.
(vandq_s32): Likewise.
(vandq_s64): Likewise.
(vandq_u8): Likewise.
(vandq_u16): Likewise.
(vandq_u32): Likewise.
(vandq_u64): Likewise.
(vorr_s8): Likewise.
(vorr_s16): Likewise.
(vorr_s32): Likewise.
(vorr_u8): Likewise.
(vorr_u16): Likewise.
(vorr_u32): Likewise.
(vorr_s64): Likewise.
(vorr_u64): Likewise.
(vorrq_s8): Likewise.
(vorrq_s16): Likewise.
(vorrq_s32): Likewise.
(vorrq_s64): Likewise.
(vorrq_u8): Likewise.
(vorrq_u16): Likewise.
(vorrq_u32): Likewise.
(vorrq_u64): Likewise.
(veor_s8): Likewise.
(veor_s16): Likewise.
(veor_s32): Likewise.
(veor_u8): Likewise.
(veor_u16): Likewise.
(veor_u32): Likewise.
(veor_s64): Likewise.
(veor_u64): Likewise.
(veorq_s8): Likewise.
(veorq_s16): Likewise.
(veorq_s32): Likewise.
(veorq_s64): Likewise.
(veorq_u8): Likewise.
(veorq_u16): Likewise.
(veorq_u32): Likewise.
(veorq_u64): Likewise.
(vbic_s8): Likewise.
(vbic_s16): Likewise.
(vbic_s32): Likewise.
(vbic_u8): Likewise.
(vbic_u16): Likewise.
(vbic_u32): Likewise.
(vbic_s64): Likewise.
(vbic_u64): Likewise.
(vbicq_s8): Likewise.
(vbicq_s16): Likewise.
(vbicq_s32): Likewise.
(vbicq_s64): Likewise.
(vbicq_u8): Likewise.
(vbicq_u16): Likewise.
(vbicq_u32): Likewise.
(vbicq_u64): Likewise.
(vorn_s8): Likewise.
(vorn_s16): Likewise.
(vorn_s32): Likewise.
(vorn_u8): Likewise.
(vorn_u16): Likewise.
(vorn_u32): Likewise.
(vorn_s64): Likewise.
(vorn_u64): Likewise.
(vornq_s8): Likewise.
(vornq_s16): Likewise.
(vornq_s32): Likewise.
(vornq_s64): Likewise.
(vornq_u8): Likewise.
(vornq_u16): Likewise.
(vornq_u32): Likewise.
(vornq_u64): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212714
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 21:51:49 +0000 (21:51 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210151.
2014-05-07 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/arm_neon.h (vtrn1_f32, vtrn1_p8, vtrn1_p16, vtrn1_s8,
vtrn1_s16, vtrn1_s32, vtrn1_u8, vtrn1_u16, vtrn1_u32, vtrn1q_f32,
vtrn1q_f64, vtrn1q_p8, vtrn1q_p16, vtrn1q_s8, vtrn1q_s16, vtrn1q_s32,
vtrn1q_s64, vtrn1q_u8, vtrn1q_u16, vtrn1q_u32, vtrn1q_u64, vtrn2_f32,
vtrn2_p8, vtrn2_p16, vtrn2_s8, vtrn2_s16, vtrn2_s32, vtrn2_u8,
vtrn2_u16, vtrn2_u32, vtrn2q_f32, vtrn2q_f64, vtrn2q_p8, vtrn2q_p16,
vtrn2q_s8, vtrn2q_s16, vtrn2q_s32, vtrn2q_s64, vtrn2q_u8, vtrn2q_u16,
vtrn2q_u32, vtrn2q_u64): Replace temporary asm with __builtin_shuffle.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210148, 210151, 210422.
2014-05-07 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/vtrnf32_1.c: New file.
* gcc.target/aarch64/simd/vtrnf32.x: New file.
* gcc.target/aarch64/simd/vtrnp16_1.c: New file.
* gcc.target/aarch64/simd/vtrnp16.x: New file.
* gcc.target/aarch64/simd/vtrnp8_1.c: New file.
* gcc.target/aarch64/simd/vtrnp8.x: New file.
* gcc.target/aarch64/simd/vtrnqf32_1.c: New file.
* gcc.target/aarch64/simd/vtrnqf32.x: New file.
* gcc.target/aarch64/simd/vtrnqp16_1.c: New file.
* gcc.target/aarch64/simd/vtrnqp16.x: New file.
* gcc.target/aarch64/simd/vtrnqp8_1.c: New file.
* gcc.target/aarch64/simd/vtrnqp8.x: New file.
* gcc.target/aarch64/simd/vtrnqs16_1.c: New file.
* gcc.target/aarch64/simd/vtrnqs16.x: New file.
* gcc.target/aarch64/simd/vtrnqs32_1.c: New file.
* gcc.target/aarch64/simd/vtrnqs32.x: New file.
* gcc.target/aarch64/simd/vtrnqs8_1.c: New file.
* gcc.target/aarch64/simd/vtrnqs8.x: New file.
* gcc.target/aarch64/simd/vtrnqu16_1.c: New file.
* gcc.target/aarch64/simd/vtrnqu16.x: New file.
* gcc.target/aarch64/simd/vtrnqu32_1.c: New file.
* gcc.target/aarch64/simd/vtrnqu32.x: New file.
* gcc.target/aarch64/simd/vtrnqu8_1.c: New file.
* gcc.target/aarch64/simd/vtrnqu8.x: New file.
* gcc.target/aarch64/simd/vtrns16_1.c: New file.
* gcc.target/aarch64/simd/vtrns16.x: New file.
* gcc.target/aarch64/simd/vtrns32_1.c: New file.
* gcc.target/aarch64/simd/vtrns32.x: New file.
* gcc.target/aarch64/simd/vtrns8_1.c: New file.
* gcc.target/aarch64/simd/vtrns8.x: New file.
* gcc.target/aarch64/simd/vtrnu16_1.c: New file.
* gcc.target/aarch64/simd/vtrnu16.x: New file.
* gcc.target/aarch64/simd/vtrnu32_1.c: New file.
* gcc.target/aarch64/simd/vtrnu32.x: New file.
* gcc.target/aarch64/simd/vtrnu8_1.c: New file.
* gcc.target/aarch64/simd/vtrnu8.x: New file.
2014-05-07 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vtrns32.c: Expect zip[12] insn rather than trn[12].
* gcc.target/aarch64/vtrnu32.c: Likewise.
* gcc.target/aarch64/vtrnf32.c: Likewise.
2014-05-14 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/vtrnqf32_1.c: New file.
* gcc.target/arm/simd/vtrnqp16_1.c: New file.
* gcc.target/arm/simd/vtrnqp8_1.c: New file.
* gcc.target/arm/simd/vtrnqs16_1.c: New file.
* gcc.target/arm/simd/vtrnqs32_1.c: New file.
* gcc.target/arm/simd/vtrnqs8_1.c: New file.
* gcc.target/arm/simd/vtrnqu16_1.c: New file.
* gcc.target/arm/simd/vtrnqu32_1.c: New file.
* gcc.target/arm/simd/vtrnqu8_1.c: New file.
* gcc.target/arm/simd/vtrnf32_1.c: New file.
* gcc.target/arm/simd/vtrnp16_1.c: New file.
* gcc.target/arm/simd/vtrnp8_1.c: New file.
* gcc.target/arm/simd/vtrns16_1.c: New file.
* gcc.target/arm/simd/vtrns32_1.c: New file.
* gcc.target/arm/simd/vtrns8_1.c: New file.
* gcc.target/arm/simd/vtrnu16_1.c: New file.
* gcc.target/arm/simd/vtrnu32_1.c: New file.
* gcc.target/arm/simd/vtrnu8_1.c: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212698
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 20:14:34 +0000 (20:14 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209794.
2014-04-25 Marek Polacek <polacek@redhat.com>
PR c/60114
* c-parser.c (c_parser_initelt): Pass input_location to
process_init_element.
(c_parser_initval): Pass loc to process_init_element.
* c-tree.h (process_init_element): Adjust declaration.
* c-typeck.c (push_init_level): Pass input_location to
process_init_element.
(pop_init_level): Likewise.
(set_designator): Likewise.
(output_init_element): Add location_t parameter. Pass loc to
digest_init.
(output_pending_init_elements): Pass input_location to
output_init_element.
(process_init_element): Add location_t parameter. Pass loc to
output_init_element.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209794, 209858.
2014-04-25 Marek Polacek <polacek@redhat.com>
PR c/60114
* gcc.dg/pr60114.c: New test.
2014-04-28 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
PR c/60983
* gcc.dg/pr60114.c: Use signed chars.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212697
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 19:45:04 +0000 (19:45 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211771.
2014-06-18 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* genattrtab.c (n_bypassed): New variable.
(process_bypasses): Initialise n_bypassed.
Count number of bypassed reservations.
(make_automaton_attrs): Allocate space for bypassed reservations
rather than number of bypasses.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212696
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 18:59:39 +0000 (18:59 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210861.
2014-05-23 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/predicates.md (aarch64_call_insn_operand): New
predicate.
* config/aarch64/constraints.md ("Ucs", "Usf"): New constraints.
* config/aarch64/aarch64.md (*sibcall_insn, *sibcall_value_insn):
Adjust for tailcalling through registers.
* config/aarch64/aarch64.h (enum reg_class): New caller save
register class.
(REG_CLASS_NAMES): Likewise.
(REG_CLASS_CONTENTS): Likewise.
* config/aarch64/aarch64.c (aarch64_function_ok_for_sibcall):
Allow tailcalling without decls.
gcc/testsuite
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210861.
2014-05-23 Jiong Wang <jiong.wang@arm.com>
* gcc.target/aarch64/tail_indirect_call_1.c: New.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212695
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 17:07:12 +0000 (17:07 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211314.
2014-06-06 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_expand_movmem): New.
* config/aarch64/aarch64.c (aarch64_move_pointer): New.
(aarch64_progress_pointer): Likewise.
(aarch64_copy_one_part_and_move_pointers): Likewise.
(aarch64_expand_movmen): Likewise.
* config/aarch64/aarch64.h (MOVE_RATIO): Set low.
* config/aarch64/aarch64.md (movmem<mode>): New.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211314.
2014-06-06 James Greenhalgh <james.greenhalgh@arm.com>
* gcc.dg/tree-ssa/pr42585.c: Skip for AArch64.
* gcc.dg/tree-ssa/sra-12.c: Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212691
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 17:01:59 +0000 (17:01 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211185, 211186.
2014-06-03 Alan Lawrence <alan.lawrence@arm.com>
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_uus_qualifiers,
aarch64_types_shift_to_unsigned_qualifiers,
aarch64_types_unsigned_shiftacc_qualifiers): Define.
* gcc/config/aarch64/aarch64-simd-builtins.def (uqshl, uqrshl, uqadd,
uqsub, usqadd, usra_n, ursra_n, uqshrn_n, uqrshrn_n, usri_n, usli_n,
sqshlu_n, uqshl_n): Update qualifiers.
* gcc/config/aarch64/arm_neon.h (vqadd_u8, vqadd_u16, vqadd_u32,
vqadd_u64, vqaddq_u8, vqaddq_u16, vqaddq_u32, vqaddq_u64, vqsub_u8,
vqsub_u16, vqsub_u32, vqsub_u64, vqsubq_u8, vqsubq_u16, vqsubq_u32,
vqsubq_u64, vqaddb_u8, vqaddh_u16, vqadds_u32, vqaddd_u64, vqrshl_u8,
vqrshl_u16, vqrshl_u32, vqrshl_u64, vqrshlq_u8, vqrshlq_u16,
vqrshlq_u32, vqrshlq_u64, vqrshlb_u8, vqrshlh_u16, vqrshls_u32,
vqrshld_u64, vqrshrn_n_u16, vqrshrn_n_u32, vqrshrn_n_u64,
vqrshrnh_n_u16, vqrshrns_n_u32, vqrshrnd_n_u64, vqshl_u8, vqshl_u16,
vqshl_u32, vqshl_u64, vqshlq_u8, vqshlq_u16, vqshlq_u32, vqshlq_u64,
vqshlb_u8, vqshlh_u16, vqshls_u32, vqshld_u64, vqshl_n_u8, vqshl_n_u16,
vqshl_n_u32, vqshl_n_u64, vqshlq_n_u8, vqshlq_n_u16, vqshlq_n_u32,
vqshlq_n_u64, vqshlb_n_u8, vqshlh_n_u16, vqshls_n_u32, vqshld_n_u64,
vqshlu_n_s8, vqshlu_n_s16, vqshlu_n_s32, vqshlu_n_s64, vqshluq_n_s8,
vqshluq_n_s16, vqshluq_n_s32, vqshluq_n_s64, vqshlub_n_s8,
vqshluh_n_s16, vqshlus_n_s32, vqshlud_n_s64, vqshrn_n_u16,
vqshrn_n_u32, vqshrn_n_u64, vqshrnh_n_u16, vqshrns_n_u32,
vqshrnd_n_u64, vqsubb_u8, vqsubh_u16, vqsubs_u32, vqsubd_u64,
vrsra_n_u8, vrsra_n_u16, vrsra_n_u32, vrsra_n_u64, vrsraq_n_u8,
vrsraq_n_u16, vrsraq_n_u32, vrsraq_n_u64, vrsrad_n_u64, vsli_n_u8,
vsli_n_u16, vsli_n_u32,vsli_n_u64, vsliq_n_u8, vsliq_n_u16,
vsliq_n_u32, vsliq_n_u64, vslid_n_u64, vsqadd_u8, vsqadd_u16,
vsqadd_u32, vsqadd_u64, vsqaddq_u8, vsqaddq_u16, vsqaddq_u32,
vsqaddq_u64, vsqaddb_u8, vsqaddh_u16, vsqadds_u32, vsqaddd_u64,
vsra_n_u8, vsra_n_u16, vsra_n_u32, vsra_n_u64, vsraq_n_u8,
vsraq_n_u16, vsraq_n_u32, vsraq_n_u64, vsrad_n_u64, vsri_n_u8,
vsri_n_u16, vsri_n_u32, vsri_n_u64, vsriq_n_u8, vsriq_n_u16,
vsriq_n_u32, vsriq_n_u64, vsrid_n_u64): Remove casts.
2014-06-03 Alan Lawrence <alan.lawrence@arm.com>
* gcc/config/aarch64/aarch64-builtins.c
(aarch64_types_binop_ssu_qualifiers): New static data.
(TYPES_BINOP_SSU): Define.
* gcc/config/aarch64/aarch64-simd-builtins.def (suqadd, ushl, urshl,
urshr_n, ushll_n): Use appropriate unsigned qualifiers. 47
* gcc/config/aarch64/arm_neon.h (vrshl_u8, vrshl_u16, vrshl_u32,
vrshl_u64, vrshlq_u8, vrshlq_u16, vrshlq_u32, vrshlq_u64, vrshld_u64,
vrshr_n_u8, vrshr_n_u16, vrshr_n_u32, vrshr_n_u64, vrshrq_n_u8, 50
vrshrq_n_u16, vrshrq_n_u32, vrshrq_n_u64, vrshrd_n_u64, vshll_n_u8,
vshll_n_u16, vshll_n_u32, vuqadd_s8, vuqadd_s16, vuqadd_s32, 52
vuqadd_s64, vuqaddq_s8, vuqaddq_s16, vuqaddq_s32, vuqaddq_s64, 53
vuqaddb_s8, vuqaddh_s16, vuqadds_s32, vuqaddd_s64): Add signedness
suffix to builtin function name, remove cast. 55
(vshl_s8, vshl_s16, vshl_s32, vshl_s64, vshl_u8, vshl_u16, vshl_u32,
vshl_u64, vshlq_s8, vshlq_s16, vshlq_s32, vshlq_s64, vshlq_u8, 57
vshlq_u16, vshlq_u32, vshlq_u64, vshld_s64, vshld_u64): Remove cast.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212690
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:55:21 +0000 (16:55 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211408, 211416.
2014-06-10 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs): Fix
REG_CFA_RESTORE mode.
2014-06-10 Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.c (aarch64_save_or_restore_fprs)
(aarch64_save_or_restore_callee_save_registers): Fix layout.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212689
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:51:50 +0000 (16:51 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211418.
2014-06-10 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-simd.md (move_lo_quad_<mode>):
Change second alternative type to f_mcr.
* config/aarch64/aarch64.md (*movsi_aarch64): Change 11th
and 12th alternatives' types to f_mcr and f_mrc.
(*movdi_aarch64): Same for 12th and 13th alternatives.
(*movsf_aarch64): Change 9th alternatives' type to mov_reg.
(aarch64_movtilow_tilow): Change type to fmov.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212688
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:49:02 +0000 (16:49 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211371.
2014-06-09 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/arm/arm-modes.def: Remove XFmode.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212687
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:46:48 +0000 (16:46 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211268.
2014-06-05 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_expand_prologue): Update stack
layout comment.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212686
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:44:09 +0000 (16:44 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211129.
2014-06-02 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
PR target/61154
* config/arm/arm.h (TARGET_SUPPORTS_WIDE_INT): Define.
* config/arm/arm.md (mov64 splitter): Replace const_double_operand
with immediate_operand.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212685
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:40:07 +0000 (16:40 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211073.
2014-05-30 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/thumb2.md (*thumb2_movhi_insn): Set type of movw
to mov_imm.
* config/arm/vfp.md (*thumb2_movsi_vfp): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212683
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:37:52 +0000 (16:37 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211050.
2014-05-29 Richard Earnshaw <rearnsha@arm.com>
Richard Sandiford <rdsandiford@googlemail.com>
* arm/iterators.md (shiftable_ops): New code iterator.
(t2_binop0, arith_shift_insn): New code attributes.
* arm/predicates.md (shift_nomul_operator): New predicate.
* arm/arm.md (insn_enabled): Delete.
(enabled): Remove insn_enabled test.
(*arith_shiftsi): Delete. Replace with ...
(*<arith_shift_insn>_multsi): ... new pattern.
(*<arith_shift_insn>_shiftsi): ... new pattern.
* config/arm/arm.c (arm_print_operand): Handle operand format 'b'.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212682
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:31:56 +0000 (16:31 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210996.
2014-05-27 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.md (stack_protect_set_<mode>):
Use <w> for the register in assembly template.
(stack_protect_test): Use the mode of operands[0] for the
result.
(stack_protect_test_<mode>): Use <w> for the register
in assembly template.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212681
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:28:26 +0000 (16:28 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210967.
2014-05-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/neon.md (neon_bswap<mode>): New pattern.
* config/arm/arm.c (neon_itype): Add NEON_BSWAP.
(arm_init_neon_builtins): Handle NEON_BSWAP.
Define required type nodes.
(arm_expand_neon_builtin): Handle NEON_BSWAP.
(arm_builtin_vectorized_function): Handle BUILTIN_BSWAP builtins.
* config/arm/arm_neon_builtins.def (bswap): Define builtins.
* config/arm/iterators.md (VDQHSD): New mode iterator.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210967.
2014-05-27 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* lib/target-supports.exp (check_effective_target_vect_bswap):
Specify arm*-*-* support.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212680
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:18:41 +0000 (16:18 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210471.
2014-05-15 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_option_override): Use the SCHED_PRESSURE_MODEL
enum name for PARAM_SCHED_PRESSURE_ALGORITHM.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212679
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:15:26 +0000 (16:15 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210369.
2014-05-13 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (neon_itype): Remove NEON_RESULTPAIR.
(arm_init_neon_builtins): Remove handling of NEON_RESULTPAIR.
Remove associated type declarations and initialisations.
(arm_expand_neon_builtin): Likewise.
(neon_emit_pair_result_insn): Delete.
* config/arm/arm_neon_builtins (vtrn, vzip, vuzp): Delete.
* config/arm/neon.md (neon_vtrn<mode>): Delete.
(neon_vzip<mode>): Likewise.
(neon_vuzp<mode>): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212678
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 16:03:58 +0000 (16:03 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211058, 211177.
2014-05-29 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64-builtins.c (aarch64_types_binopv_qualifiers,
TYPES_BINOPV): New static data.
* config/aarch64/aarch64-simd-builtins.def (im_lane_bound): New builtin.
* config/aarch64/aarch64-simd.md (aarch64_ext, aarch64_im_lane_boundsi):
New patterns.
* config/aarch64/aarch64.c (aarch64_expand_vec_perm_const_1): Match
patterns for EXT.
(aarch64_evpc_ext): New function.
* config/aarch64/iterators.md (UNSPEC_EXT): New enum element.
* config/aarch64/arm_neon.h (vext_f32, vext_f64, vext_p8, vext_p16,
vext_s8, vext_s16, vext_s32, vext_s64, vext_u8, vext_u16, vext_u32,
vext_u64, vextq_f32, vextq_f64, vextq_p8, vextq_p16, vextq_s8,
vextq_s16, vextq_s32, vextq_s64, vextq_u8, vextq_u16, vextq_u32,
vextq_u64): Replace __asm with __builtin_shuffle and im_lane_boundsi.
2014-06-03 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.c (aarch64_evpc_ext): allow and handle
location == 0.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210152, 211059.
2014-05-29 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/vextQf32_1.c: New file.
* gcc.target/arm/simd/vextQp16_1.c: New file.
* gcc.target/arm/simd/vextQp8_1.c: New file.
* gcc.target/arm/simd/vextQs16_1.c: New file.
* gcc.target/arm/simd/vextQs32_1.c: New file.
* gcc.target/arm/simd/vextQs64_1.c: New file.
* gcc.target/arm/simd/vextQs8_1.c: New file.
* gcc.target/arm/simd/vextQu16_1.c: New file.
* gcc.target/arm/simd/vextQu32_1.c: New file.
* gcc.target/arm/simd/vextQu64_1.c: New file.
* gcc.target/arm/simd/vextQu8_1.c: New file.
* gcc.target/arm/simd/vextQp64_1.c: New file.
* gcc.target/arm/simd/vextf32_1.c: New file.
* gcc.target/arm/simd/vextp16_1.c: New file.
* gcc.target/arm/simd/vextp8_1.c: New file.
* gcc.target/arm/simd/vexts16_1.c: New file.
* gcc.target/arm/simd/vexts32_1.c: New file.
* gcc.target/arm/simd/vexts64_1.c: New file.
* gcc.target/arm/simd/vexts8_1.c: New file.
* gcc.target/arm/simd/vextu16_1.c: New file.
* gcc.target/arm/simd/vextu32_1.c: New file.
* gcc.target/arm/simd/vextu64_1.c: New file.
* gcc.target/arm/simd/vextu8_1.c: New file.
* gcc.target/arm/simd/vextp64_1.c: New file.
2014-05-07 Alan Lawrence <alan.lawrence@arm.com>
gcc.target/aarch64/simd/ext_f32.x: New file.
gcc.target/aarch64/simd/ext_f32_1.c: New file.
gcc.target/aarch64/simd/ext_p16.x: New file.
gcc.target/aarch64/simd/ext_p16_1.c: New file.
gcc.target/aarch64/simd/ext_p8.x: New file.
gcc.target/aarch64/simd/ext_p8_1.c: New file.
gcc.target/aarch64/simd/ext_s16.x: New file.
gcc.target/aarch64/simd/ext_s16_1.c: New file.
gcc.target/aarch64/simd/ext_s32.x: New file.
gcc.target/aarch64/simd/ext_s32_1.c: New file.
gcc.target/aarch64/simd/ext_s64.x: New file.
gcc.target/aarch64/simd/ext_s64_1.c: New file.
gcc.target/aarch64/simd/ext_s8.x: New file.
gcc.target/aarch64/simd/ext_s8_1.c: New file.
gcc.target/aarch64/simd/ext_u16.x: New file.
gcc.target/aarch64/simd/ext_u16_1.c: New file.
gcc.target/aarch64/simd/ext_u32.x: New file.
gcc.target/aarch64/simd/ext_u32_1.c: New file.
gcc.target/aarch64/simd/ext_u64.x: New file.
gcc.target/aarch64/simd/ext_u64_1.c: New file.
gcc.target/aarch64/simd/ext_u8.x: New file.
gcc.target/aarch64/simd/ext_u8_1.c: New file.
gcc.target/aarch64/simd/ext_f64.c: New file.
gcc.target/aarch64/simd/extq_f32.x: New file.
gcc.target/aarch64/simd/extq_f32_1.c: New file.
gcc.target/aarch64/simd/extq_p16.x: New file.
gcc.target/aarch64/simd/extq_p16_1.c: New file.
gcc.target/aarch64/simd/extq_p8.x: New file.
gcc.target/aarch64/simd/extq_p8_1.c: New file.
gcc.target/aarch64/simd/extq_s16.x: New file.
gcc.target/aarch64/simd/extq_s16_1.c: New file.
gcc.target/aarch64/simd/extq_s32.x: New file.
gcc.target/aarch64/simd/extq_s32_1.c: New file.
gcc.target/aarch64/simd/extq_s64.x: New file.
gcc.target/aarch64/simd/extq_s64_1.c: New file.
gcc.target/aarch64/simd/extq_s8.x: New file.
gcc.target/aarch64/simd/extq_s8_1.c: New file.
gcc.target/aarch64/simd/extq_u16.x: New file.
gcc.target/aarch64/simd/extq_u16_1.c: New file.
gcc.target/aarch64/simd/extq_u32.x: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212677
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 15:49:51 +0000 (15:49 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209797.
2014-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p):
Use HOST_WIDE_INT_C for mask literal.
(aarch_rev16_shleft_mask_imm_p): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212675
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 15:45:43 +0000 (15:45 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211148.
2014-06-02 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64-linux.h (GLIBC_DYNAMIC_LINKER):
/lib/ld-linux32-aarch64.so.1 is used for ILP32.
(LINUX_TARGET_LINK_SPEC): Update linker script for ILP32.
file whose name depends on -mabi= and -mbig-endian.
* config/aarch64/t-aarch64-linux (MULTILIB_OSDIRNAMES): Handle LP64
better and handle ilp32 too.
(MULTILIB_OPTIONS): Delete.
(MULTILIB_DIRNAMES): Delete.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212673
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 15:39:57 +0000 (15:39 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210828, r211103.
2014-05-31 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/arm/arm.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New define.
(arm_builtins) : Add ARM_BUILTIN_GET_FPSCR and ARM_BUILTIN_SET_FPSCR.
(bdesc_2arg) : Add description for builtins __builtins_arm_set_fpscr
and __builtins_arm_get_fpscr.
(arm_init_builtins) : Initialize builtins __builtins_arm_set_fpscr and
__builtins_arm_get_fpscr.
(arm_expand_builtin) : Expand builtins __builtins_arm_set_fpscr and
__builtins_arm_ldfpscr.
(arm_atomic_assign_expand_fenv): New function.
* config/arm/vfp.md (set_fpscr): New pattern.
(get_fpscr) : Likewise.
* config/arm/unspecs.md (unspecv): Add VUNSPEC_GET_FPSCR and
VUNSPEC_SET_FPSCR.
* doc/extend.texi (AARCH64 Built-in Functions) : Document
__builtins_arm_set_fpscr, __builtins_arm_get_fpscr.
2014-05-23 Kugan Vivekanandarajah <kuganv@linaro.org>
* config/aarch64/aarch64.c (TARGET_ATOMIC_ASSIGN_EXPAND_FENV): New
define.
* config/aarch64/aarch64-protos.h (aarch64_atomic_assign_expand_fenv):
New function declaration.
* config/aarch64/aarch64-builtins.c (aarch64_builtins) : Add
AARCH64_BUILTIN_GET_FPCR, AARCH64_BUILTIN_SET_FPCR.
AARCH64_BUILTIN_GET_FPSR and AARCH64_BUILTIN_SET_FPSR.
(aarch64_init_builtins) : Initialize builtins
__builtins_aarch64_set_fpcr, __builtins_aarch64_get_fpcr.
__builtins_aarch64_set_fpsr and __builtins_aarch64_get_fpsr.
(aarch64_expand_builtin) : Expand builtins __builtins_aarch64_set_fpcr
__builtins_aarch64_get_fpcr, __builtins_aarch64_get_fpsr,
and __builtins_aarch64_set_fpsr.
(aarch64_atomic_assign_expand_fenv): New function.
* config/aarch64/aarch64.md (set_fpcr): New pattern.
(get_fpcr) : Likewise.
(set_fpsr) : Likewise.
(get_fpsr) : Likewise.
(unspecv): Add UNSPECV_GET_FPCR and UNSPECV_SET_FPCR, UNSPECV_GET_FPSR
and UNSPECV_SET_FPSR.
* doc/extend.texi (AARCH64 Built-in Functions) : Document
__builtins_aarch64_set_fpcr, __builtins_aarch64_get_fpcr.
__builtins_aarch64_set_fpsr and __builtins_aarch64_get_fpsr.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212672
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 15:24:13 +0000 (15:24 +0000)]
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210355.
2014-05-13 Ian Bolton <ian.bolton@arm.com>
* config/aarch64/aarch64-protos.h
(aarch64_hard_regno_caller_save_mode): New prototype.
* config/aarch64/aarch64.c (aarch64_hard_regno_caller_save_mode):
New function.
* config/aarch64/aarch64.h (HARD_REGNO_CALLER_SAVE_MODE): New macro.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212669
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 15:04:27 +0000 (15:04 +0000)]
gcc/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209943.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/arm_neon.h (vuzp1_f32, vuzp1_p8, vuzp1_p16, vuzp1_s8,
vuzp1_s16, vuzp1_s32, vuzp1_u8, vuzp1_u16, vuzp1_u32, vuzp1q_f32,
vuzp1q_f64, vuzp1q_p8, vuzp1q_p16, vuzp1q_s8, vuzp1q_s16, vuzp1q_s32,
vuzp1q_s64, vuzp1q_u8, vuzp1q_u16, vuzp1q_u32, vuzp1q_u64, vuzp2_f32,
vuzp2_p8, vuzp2_p16, vuzp2_s8, vuzp2_s16, vuzp2_s32, vuzp2_u8,
vuzp2_u16, vuzp2_u32, vuzp2q_f32, vuzp2q_f64, vuzp2q_p8, vuzp2q_p16,
vuzp2q_s8, vuzp2q_s16, vuzp2q_s32, vuzp2q_s64, vuzp2q_u8, vuzp2q_u16,
vuzp2q_u32, vuzp2q_u64): Replace temporary asm with __builtin_shuffle.
gcc/testsuite/
2014-07-16 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209940, `r209943, r209947.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/vuzpqf32_1.c: New file.
* gcc.target/arm/simd/vuzpqp16_1.c: New file.
* gcc.target/arm/simd/vuzpqp8_1.c: New file.
* gcc.target/arm/simd/vuzpqs16_1.c: New file.
* gcc.target/arm/simd/vuzpqs32_1.c: New file.
* gcc.target/arm/simd/vuzpqs8_1.c: New file.
* gcc.target/arm/simd/vuzpqu16_1.c: New file.
* gcc.target/arm/simd/vuzpqu32_1.c: New file.
* gcc.target/arm/simd/vuzpqu8_1.c: New file.
* gcc.target/arm/simd/vuzpf32_1.c: New file.
* gcc.target/arm/simd/vuzpp16_1.c: New file.
* gcc.target/arm/simd/vuzpp8_1.c: New file.
* gcc.target/arm/simd/vuzps16_1.c: New file.
* gcc.target/arm/simd/vuzps32_1.c: New file.
* gcc.target/arm/simd/vuzps8_1.c: New file.
* gcc.target/arm/simd/vuzpu16_1.c: New file.
* gcc.target/arm/simd/vuzpu32_1.c: New file.
* gcc.target/arm/simd/vuzpu8_1.c: New file.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/vuzps32_1.c: Expect zip1/2 insn rather than uzp1/2.
* gcc.target/aarch64/vuzpu32_1.c: Likewise.
* gcc.target/aarch64/vuzpf32_1.c: Likewise.
2014-04-30 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/vuzpf32_1.c: New file.
* gcc.target/aarch64/simd/vuzpf32.x: New file.
* gcc.target/aarch64/simd/vuzpp16_1.c: New file.
* gcc.target/aarch64/simd/vuzpp16.x: New file.
* gcc.target/aarch64/simd/vuzpp8_1.c: New file.
* gcc.target/aarch64/simd/vuzpp8.x: New file.
* gcc.target/aarch64/simd/vuzpqf32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqf32.x: New file.
* gcc.target/aarch64/simd/vuzpqp16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqp16.x: New file.
* gcc.target/aarch64/simd/vuzpqp8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqp8.x: New file.
* gcc.target/aarch64/simd/vuzpqs16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs16.x: New file.
* gcc.target/aarch64/simd/vuzpqs32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs32.x: New file.
* gcc.target/aarch64/simd/vuzpqs8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqs8.x: New file.
* gcc.target/aarch64/simd/vuzpqu16_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu16.x: New file.
* gcc.target/aarch64/simd/vuzpqu32_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu32.x: New file.
* gcc.target/aarch64/simd/vuzpqu8_1.c: New file.
* gcc.target/aarch64/simd/vuzpqu8.x: New file.
* gcc.target/aarch64/simd/vuzps16_1.c: New file.
* gcc.target/aarch64/simd/vuzps16.x: New file.
* gcc.target/aarch64/simd/vuzps32_1.c: New file.
* gcc.target/aarch64/simd/vuzps32.x: New file.
* gcc.target/aarch64/simd/vuzps8_1.c: New file.
* gcc.target/aarch64/simd/vuzps8.x: New file.
* gcc.target/aarch64/simd/vuzpu16_1.c: New file.
* gcc.target/aarch64/simd/vuzpu16.x: New file.
* gcc.target/aarch64/simd/vuzpu32_1.c: New file.
* gcc.target/aarch64/simd/vuzpu32.x: New file.
* gcc.target/aarch64/simd/vuzpu8_1.c: New file.
* gcc.target/aarch64/simd/vuzpu8.x: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212665
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 16 Jul 2014 14:43:37 +0000 (14:43 +0000)]
Merge branches/gcc-4_9-branch rev 212419
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212661
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 26 Jun 2014 07:44:46 +0000 (07:44 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212012
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 26 Jun 2014 07:39:54 +0000 (07:39 +0000)]
Make Linaro GCC 4.9-2014.06-1.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@212009
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Wed, 25 Jun 2014 13:10:09 +0000 (13:10 +0000)]
Merge branches/gcc-4_9-branch rev 211964
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211979
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Tue, 24 Jun 2014 14:14:35 +0000 (14:14 +0000)]
2014-06-24 Yvan Roux <yvan.roux@linaro.org>
Revert:
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209643.
2014-04-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211940
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 20 Jun 2014 08:59:14 +0000 (08:59 +0000)]
2014-06-13 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210493, 210494, 210495, 210496, 210497, 210498,
210499, 210500, 210501, 210502, 210503, 210504, 210505, 210506, 210507,
210508, 210509, 210510, 210512, 211205, 211206.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-protos.h (scale_addr_mode_cost): New.
(cpu_addrcost_table): Use it.
* config/aarch64/aarch64.c (generic_addrcost_table): Initialize it.
(aarch64_address_cost): Rewrite using aarch64_classify_address,
move it.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (cortexa57_addrcost_table): New.
(cortexa57_vector_cost): Likewise.
(cortexa57_tunings): Use them.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs_wrapper): New.
(TARGET_RTX_COSTS): Call it.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_build_constant): Conditionally
emit instructions, return number of instructions which would
be emitted.
(aarch64_add_constant): Update call to aarch64_build_constant.
(aarch64_output_mi_thunk): Likewise.
(aarch64_rtx_costs): Estimate cost of a CONST_INT, cost
a CONST_DOUBLE.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_strip_shift_or_extend): Rename
to...
(aarch64_strip_extend): ...this, don't strip shifts, check RTX is
well formed.
(aarch64_rtx_mult_cost): New.
(aarch64_rtx_costs): Use it, refactor as appropriate.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Set default costs.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philip Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costing
for SET RTX.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Use address
costs when costing loads and stores to memory.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve cost for
logical operations.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost
ZERO_EXTEND and SIGN_EXTEND better.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
rotates and shifts.
2014-03-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_arith_op_extract_p): New.
(aarch64_rtx_costs): Improve costs for SIGN/ZERO_EXTRACT.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Improve costs for
DIV/MOD.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost comparison
operators.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost FMA,
FLOAT_EXTEND, FLOAT_TRUNCATE, ABS, SMAX, and SMIN.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost TRUNCATE.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Cost SYMBOL_REF,
HIGH, LO_SUM.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle the case
where we were unable to cost an RTX.
2014-05-16 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_mult_cost): Fix FNMUL case.
2014-06-03 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): New function.
(aarch64_rtx_costs): Use aarch64_if_then_else_costs.
2014-06-03 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch64_if_then_else_costs): Allow non
comparisons for OP0.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211843
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 13 Jun 2014 08:01:29 +0000 (08:01 +0000)]
Bump version number, post release.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211609
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Fri, 13 Jun 2014 07:57:25 +0000 (07:57 +0000)]
Make Linaro GCC 4.9-2014.06.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211607
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:55:11 +0000 (12:55 +0000)]
2014-06-04 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r211211.
2014-06-04 Bin Cheng <bin.cheng@arm.com>
* config/aarch64/aarch64.c (aarch64_classify_address)
(aarch64_legitimize_reload_address): Support full addressing modes
for vector modes.
* config/aarch64/aarch64.md (mov<mode>, movmisalign<mode>)
(*aarch64_simd_mov<mode>, *aarch64_simd_mov<mode>): Relax predicates.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211584
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:52:45 +0000 (12:52 +0000)]
2014-05-26 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r210615.
2014-05-19 Richard Henderson <rth@redhat.com>
* config/aarch64/sjlj.S: New file.
* config/aarch64/target.h: New file.
* configure.tgt: Enable aarch64.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211583
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:48:58 +0000 (12:48 +0000)]
gcc/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209906.
2014-04-29 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/arm_neon.h (vzip1_f32, vzip1_p8, vzip1_p16, vzip1_s8,
vzip1_s16, vzip1_s32, vzip1_u8, vzip1_u16, vzip1_u32, vzip1q_f32,
vzip1q_f64, vzip1q_p8, vzip1q_p16, vzip1q_s8, vzip1q_s16, vzip1q_s32,
vzip1q_s64, vzip1q_u8, vzip1q_u16, vzip1q_u32, vzip1q_u64, vzip2_f32,
vzip2_p8, vzip2_p16, vzip2_s8, vzip2_s16, vzip2_s32, vzip2_u8,
vzip2_u16, vzip2_u32, vzip2q_f32, vzip2q_f64, vzip2q_p8, vzip2q_p16,
vzip2q_s8, vzip2q_s16, vzip2q_s32, vzip2q_s64, vzip2q_u8, vzip2q_u16,
vzip2q_u32, vzip2q_u64): Replace inline __asm__ with __builtin_shuffle.
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209908.
2013-04-29 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/arm/simd/simd.exp: New file.
* gcc.target/arm/simd/vzipqf32_1.c: New file.
* gcc.target/arm/simd/vzipqp16_1.c: New file.
* gcc.target/arm/simd/vzipqp8_1.c: New file.
* gcc.target/arm/simd/vzipqs16_1.c: New file.
* gcc.target/arm/simd/vzipqs32_1.c: New file.
* gcc.target/arm/simd/vzipqs8_1.c: New file.
* gcc.target/arm/simd/vzipqu16_1.c: New file.
* gcc.target/arm/simd/vzipqu32_1.c: New file.
* gcc.target/arm/simd/vzipqu8_1.c: New file.
* gcc.target/arm/simd/vzipf32_1.c: New file.
* gcc.target/arm/simd/vzipp16_1.c: New file.
* gcc.target/arm/simd/vzipp8_1.c: New file.
* gcc.target/arm/simd/vzips16_1.c: New file.
* gcc.target/arm/simd/vzips32_1.c: New file.
* gcc.target/arm/simd/vzips8_1.c: New file.
* gcc.target/arm/simd/vzipu16_1.c: New file.
* gcc.target/arm/simd/vzipu32_1.c: New file.
* gcc.target/arm/simd/vzipu8_1.c: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211582
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:44:00 +0000 (12:44 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209897.
2014-04-29 James Greenhalgh <james.greenhalgh@arm.com>
* calls.c (initialize_argument_information): Always treat
PUSH_ARGS_REVERSED as 1, simplify code accordingly.
(expand_call): Likewise.
(emit_library_call_calue_1): Likewise.
* expr.c (PUSH_ARGS_REVERSED): Do not define.
(emit_push_insn): Always treat PUSH_ARGS_REVERSED as 1, simplify
code accordingly.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211581
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:40:56 +0000 (12:40 +0000)]
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209893.
2014-04-29 Alan Lawrence <alan.lawrence@arm.com>
* gcc.target/aarch64/simd/simd.exp: New file.
* gcc.target/aarch64/simd/vzipf32_1.c: New file.
* gcc.target/aarch64/simd/vzipf32.x: New file.
* gcc.target/aarch64/simd/vzipp16_1.c: New file.
* gcc.target/aarch64/simd/vzipp16.x: New file.
* gcc.target/aarch64/simd/vzipp8_1.c: New file.
* gcc.target/aarch64/simd/vzipp8.x: New file.
* gcc.target/aarch64/simd/vzipqf32_1.c: New file.
* gcc.target/aarch64/simd/vzipqf32.x: New file.
* gcc.target/aarch64/simd/vzipqp16_1.c: New file.
* gcc.target/aarch64/simd/vzipqp16.x: New file.
* gcc.target/aarch64/simd/vzipqp8_1.c: New file.
* gcc.target/aarch64/simd/vzipqp8.x: New file.
* gcc.target/aarch64/simd/vzipqs16_1.c: New file.
* gcc.target/aarch64/simd/vzipqs16.x: New file.
* gcc.target/aarch64/simd/vzipqs32_1.c: New file.
* gcc.target/aarch64/simd/vzipqs32.x: New file.
* gcc.target/aarch64/simd/vzipqs8_1.c: New file.
* gcc.target/aarch64/simd/vzipqs8.x: New file.
* gcc.target/aarch64/simd/vzipqu16_1.c: New file.
* gcc.target/aarch64/simd/vzipqu16.x: New file.
* gcc.target/aarch64/simd/vzipqu32_1.c: New file.
* gcc.target/aarch64/simd/vzipqu32.x: New file.
* gcc.target/aarch64/simd/vzipqu8_1.c: New file.
* gcc.target/aarch64/simd/vzipqu8.x: New file.
* gcc.target/aarch64/simd/vzips16_1.c: New file.
* gcc.target/aarch64/simd/vzips16.x: New file.
* gcc.target/aarch64/simd/vzips32_1.c: New file.
* gcc.target/aarch64/simd/vzips32.x: New file.
* gcc.target/aarch64/simd/vzips8_1.c: New file.
* gcc.target/aarch64/simd/vzips8.x: New file.
* gcc.target/aarch64/simd/vzipu16_1.c: New file.
* gcc.target/aarch64/simd/vzipu16.x: New file.
* gcc.target/aarch64/simd/vzipu32_1.c: New file.
* gcc.target/aarch64/simd/vzipu32.x: New file.
* gcc.target/aarch64/simd/vzipu8_1.c: New file.
* gcc.target/aarch64/simd/vzipu8.x: New file.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211580
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:36:45 +0000 (12:36 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209880.
2014-04-28 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_types_storestruct_lane_qualifiers): New.
(TYPES_STORESTRUCT_LANE): Likewise.
* config/aarch64/aarch64-simd-builtins.def (st2_lane): New.
(st3_lane): Likewise.
(st4_lane): Likewise.
* config/aarch64/aarch64-simd.md (vec_store_lanesoi_lane<mode>): New.
(vec_store_lanesci_lane<mode>): Likewise.
(vec_store_lanesxi_lane<mode>): Likewise.
(aarch64_st2_lane<VQ:mode>): Likewise.
(aarch64_st3_lane<VQ:mode>): Likewise.
(aarch64_st4_lane<VQ:mode>): Likewise.
* config/aarch64/aarch64.md (unspec): Add UNSPEC_ST{2,3,4}_LANE.
* config/aarch64/arm_neon.h
(__ST2_LANE_FUNC): Rewrite using builtins, update use points to
use new macro arguments.
(__ST3_LANE_FUNC): Likewise.
(__ST4_LANE_FUNC): Likewise.
* config/aarch64/iterators.md (V_TWO_ELEM): New.
(V_THREE_ELEM): Likewise.
(V_FOUR_ELEM): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211579
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:33:49 +0000 (12:33 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209878.
2014-04-28 James Greenhalgh <james.greenhalgh@arm.com>
* config/aarch64/aarch64-protos.h (aarch64_modes_tieable_p): New.
* config/aarch64/aarch64.c
(aarch64_cannot_change_mode_class): Weaken conditions.
(aarch64_modes_tieable_p): New.
* config/aarch64/aarch64.h (MODES_TIEABLE_P): Use it.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211578
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:31:13 +0000 (12:31 +0000)]
gcc/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209808.
2014-04-25 Jiong Wang <jiong.wang@arm.com>
* config/arm/predicates.md (call_insn_operand): Add long_call check.
* config/arm/arm.md (sibcall, sibcall_value): Force the address to
reg for long_call.
* config/arm/arm.c (arm_function_ok_for_sibcall): Remove long_call
restriction.
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209808.
2014-04-25 Jiong Wang <jiong.wang@arm.com>
* gcc.target/arm/tail-long-call.c: New test.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211577
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:27:08 +0000 (12:27 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209806.
2014-04-25 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_cortex_a8_tune): Initialise
T16-related fields.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211576
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:21:40 +0000 (12:21 +0000)]
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209747.
2014-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* configure.ac: Quote usage of ac_cv_func_clock_gettime in if test.
* configure: Regenerate.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211575
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:17:03 +0000 (12:17 +0000)]
gcc/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209742, 209749.
2014-04-24 Alan Lawrence <alan.lawrence@arm.com>
* config/aarch64/aarch64.c (aarch64_evpc_tbl): Enable for bigendian.
2014-04-24 Tejas Belagod <tejas.belagod@arm.com>
* config/aarch64/aarch64.c (aarch64_evpc_tbl): Reverse order of elements
for big-endian.
gcc/testsuite/
2014-05-25 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209749.
2014-04-24 Alan Lawrence <alan.lawrence@arm.com>
* lib/target-supports.exp (check_effective_target_vect_perm): Return
true for aarch64_be.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211574
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:12:37 +0000 (12:12 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209736.
2014-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64-builtins.c
(aarch64_builtin_vectorized_function): Handle BUILT_IN_BSWAP16,
BUILT_IN_BSWAP32, BUILT_IN_BSWAP64.
* config/aarch64/aarch64-simd.md (bswap<mode>): New pattern.
* config/aarch64/aarch64-simd-builtins.def: Define vector bswap
builtins.
* config/aarch64/iterator.md (VDQHSD): New mode iterator.
(Vrevsuff): New mode attribute.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209736.
2014-04-24 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* lib/target-supports.exp (check_effective_target_vect_bswap): New.
* gcc.dg/vect/vect-bswap16: New test.
* gcc.dg/vect/vect-bswap32: Likewise.
* gcc.dg/vect/vect-bswap64: Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211573
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:07:45 +0000 (12:07 +0000)]
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209713.
2014-04-23 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vdup_lane_1.c: New testcase.
* gcc.target/aarch64/vdup_lane_2.c: New testcase.
* gcc.target/aarch64/vdup_n_1.c: New testcase.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211560
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:05:13 +0000 (12:05 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209712.
2014-04-23 Venkataramanan Kumar <venkataramanan.kumar@linaro.org>
* config/aarch64/aarch64.md (stack_protect_set, stack_protect_test)
(stack_protect_set_<mode>, stack_protect_test_<mode>): Add
machine descriptions for Stack Smashing Protector.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211530
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 12:02:58 +0000 (12:02 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209711.
2014-04-23 Richard Earnshaw <rearnsha@arm.com>
* aarch64.md (<optab>_rol<mode>3): New pattern.
(<optab>_rolsi3_uxtw): Likewise.
* aarch64.c (aarch64_strip_shift): Handle ROTATE and ROTATERT.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211524
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:59:51 +0000 (11:59 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209710.
2014-04-23 James Greenhalgh <james.greenhalgh@arm.com>
* config/arm/arm.c (arm_cortex_a57_tune): Initialize all fields.
(arm_cortex_a12_tune): Likewise.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211523
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:57:21 +0000 (11:57 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209706.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle BSWAP.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211521
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:54:42 +0000 (11:54 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209701, 209702, 209703, 209704, 209705.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.md (arm_rev16si2): New pattern.
(arm_rev16si2_alt): Likewise.
* config/arm/arm.c (arm_new_rtx_costs): Handle rev16 case.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/aarch64/aarch64.md (rev16<mode>2): New pattern.
(rev16<mode>2_alt): Likewise.
* config/aarch64/aarch64.c (aarch64_rtx_costs): Handle rev16 case.
* config/arm/aarch-common.c (aarch_rev16_shright_mask_imm_p): New.
(aarch_rev16_shleft_mask_imm_p): Likewise.
(aarch_rev16_p_1): Likewise.
(aarch_rev16_p): Likewise.
* config/arm/aarch-common-protos.h (aarch_rev16_p): Declare extern.
(aarch_rev16_shright_mask_imm_p): Likewise.
(aarch_rev16_shleft_mask_imm_p): Likewise.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/aarch-common-protos.h (alu_cost_table): Add rev field.
* config/arm/aarch-cost-tables.h (generic_extra_costs): Specify
rev cost.
(cortex_a53_extra_costs): Likewise.
(cortex_a57_extra_costs): Likewise.
* config/arm/arm.c (cortexa9_extra_costs): Likewise.
(cortexa7_extra_costs): Likewise.
(cortexa8_extra_costs): Likewise.
(cortexa12_extra_costs): Likewise.
(cortexa15_extra_costs): Likewise.
(v7m_extra_costs): Likewise.
(arm_new_rtx_costs): Handle BSWAP.
2013-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (cortexa8_extra_costs): New table.
(arm_cortex_a8_tune): New tuning struct.
* config/arm/arm-cores.def (cortex-a8): Use cortex_a8 tuning struct.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* config/arm/arm.c (arm_new_rtx_costs): Handle FMA.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209704, 209705.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/arm/rev16.c: New test.
2014-04-23 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
* gcc.target/aarch64/rev16_1.c: New test.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211520
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:48:36 +0000 (11:48 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209659.
2014-04-22 Richard Henderson <rth@redhat.com>
* config/aarch64/aarch64 (addti3, subti3): New expanders.
(add<GPI>3_compare0): Remove leading * from name.
(add<GPI>3_carryin): Likewise.
(sub<GPI>3_compare0): Likewise.
(sub<GPI>3_carryin): Likewise.
(<su_optab>mulditi3): New expander.
(multi3): New expander.
(madd<GPI>): Remove leading * from name.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211519
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:45:47 +0000 (11:45 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209649.
2014-04-22 Yufeng Zhang <yufeng.zhang@arm.com>
* longlong.h: Merge from glibc.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211518
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:43:21 +0000 (11:43 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209645.
2014-04-22 Andrew Pinski <apinski@cavium.com>
* config/aarch64/aarch64.c (aarch64_load_symref_appropriately):
Handle TLS for ILP32.
* config/aarch64/aarch64.md (tlsie_small): Rename to ...
(tlsie_small_<mode>): this and handle PTR.
(tlsie_small_sidi): New pattern.
(tlsle_small): Change to an expand to handle ILP32.
(tlsle_small_<mode>): New pattern.
(tlsdesc_small): Rename to ...
(tlsdesc_small_<mode>): this and handle PTR.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211517
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:40:26 +0000 (11:40 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209643.
2014-04-22 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
* config/aarch64/aarch64.c (TARGET_FLAGS_REGNUM): Define.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211516
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:36:54 +0000 (11:36 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209641, 209642.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
(aarch64_types_signed_unsigned_qualifiers): Qualifier added.
(aarch64_types_signed_poly_qualifiers): Likewise.
(aarch64_types_unsigned_signed_qualifiers): Likewise.
(aarch64_types_poly_signed_qualifiers): Likewise.
(TYPES_REINTERP_SS): Type macro added.
(TYPES_REINTERP_SU): Likewise.
(TYPES_REINTERP_SP): Likewise.
(TYPES_REINTERP_US): Likewise.
(TYPES_REINTERP_PS): Likewise.
(aarch64_fold_builtin): New expression folding added.
* config/aarch64/aarch64-simd-builtins.def (REINTERP):
Declarations removed.
(REINTERP_SS): Declarations added.
(REINTERP_US): Likewise.
(REINTERP_PS): Likewise.
(REINTERP_SU): Likewise.
(REINTERP_SP): Likewise.
* config/aarch64/arm_neon.h (vreinterpret_p8_f64): Implemented.
(vreinterpretq_p8_f64): Likewise.
(vreinterpret_p16_f64): Likewise.
(vreinterpretq_p16_f64): Likewise.
(vreinterpret_f32_f64): Likewise.
(vreinterpretq_f32_f64): Likewise.
(vreinterpret_f64_f32): Likewise.
(vreinterpret_f64_p8): Likewise.
(vreinterpret_f64_p16): Likewise.
(vreinterpret_f64_s8): Likewise.
(vreinterpret_f64_s16): Likewise.
(vreinterpret_f64_s32): Likewise.
(vreinterpret_f64_s64): Likewise.
(vreinterpret_f64_u8): Likewise.
(vreinterpret_f64_u16): Likewise.
(vreinterpret_f64_u32): Likewise.
(vreinterpret_f64_u64): Likewise.
(vreinterpretq_f64_f32): Likewise.
(vreinterpretq_f64_p8): Likewise.
(vreinterpretq_f64_p16): Likewise.
(vreinterpretq_f64_s8): Likewise.
(vreinterpretq_f64_s16): Likewise.
(vreinterpretq_f64_s32): Likewise.
(vreinterpretq_f64_s64): Likewise.
(vreinterpretq_f64_u8): Likewise.
(vreinterpretq_f64_u16): Likewise.
(vreinterpretq_f64_u32): Likewise.
(vreinterpretq_f64_u64): Likewise.
(vreinterpret_s64_f64): Likewise.
(vreinterpretq_s64_f64): Likewise.
(vreinterpret_u64_f64): Likewise.
(vreinterpretq_u64_f64): Likewise.
(vreinterpret_s8_f64): Likewise.
(vreinterpretq_s8_f64): Likewise.
(vreinterpret_s16_f64): Likewise.
(vreinterpretq_s16_f64): Likewise.
(vreinterpret_s32_f64): Likewise.
(vreinterpretq_s32_f64): Likewise.
(vreinterpret_u8_f64): Likewise.
(vreinterpretq_u8_f64): Likewise.
(vreinterpret_u16_f64): Likewise.
(vreinterpretq_u16_f64): Likewise.
(vreinterpret_u32_f64): Likewise.
(vreinterpretq_u32_f64): Likewise.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* config/aarch64/aarch64/aarch64-builtins.c (TYPES_REINTERP): Removed.
* config/aarch64/aarch64/aarch64-simd-builtins.def (REINTERP): Removed.
(vreinterpret_p8_s8): Likewise.
* config/aarch64/aarch64/arm_neon.h (vreinterpret_p8_s8): Uses cast.
(vreinterpret_p8_s16): Likewise.
(vreinterpret_p8_s32): Likewise.
(vreinterpret_p8_s64): Likewise.
(vreinterpret_p8_f32): Likewise.
(vreinterpret_p8_u8): Likewise.
(vreinterpret_p8_u16): Likewise.
(vreinterpret_p8_u32): Likewise.
(vreinterpret_p8_u64): Likewise.
(vreinterpret_p8_p16): Likewise.
(vreinterpretq_p8_s8): Likewise.
(vreinterpretq_p8_s16): Likewise.
(vreinterpretq_p8_s32): Likewise.
(vreinterpretq_p8_s64): Likewise.
(vreinterpretq_p8_f32): Likewise.
(vreinterpretq_p8_u8): Likewise.
(vreinterpretq_p8_u16): Likewise.
(vreinterpretq_p8_u32): Likewise.
(vreinterpretq_p8_u64): Likewise.
(vreinterpretq_p8_p16): Likewise.
(vreinterpret_p16_s8): Likewise.
(vreinterpret_p16_s16): Likewise.
(vreinterpret_p16_s32): Likewise.
(vreinterpret_p16_s64): Likewise.
(vreinterpret_p16_f32): Likewise.
(vreinterpret_p16_u8): Likewise.
(vreinterpret_p16_u16): Likewise.
(vreinterpret_p16_u32): Likewise.
(vreinterpret_p16_u64): Likewise.
(vreinterpret_p16_p8): Likewise.
(vreinterpretq_p16_s8): Likewise.
(vreinterpretq_p16_s16): Likewise.
(vreinterpretq_p16_s32): Likewise.
(vreinterpretq_p16_s64): Likewise.
(vreinterpretq_p16_f32): Likewise.
(vreinterpretq_p16_u8): Likewise.
(vreinterpretq_p16_u16): Likewise.
(vreinterpretq_p16_u32): Likewise.
(vreinterpretq_p16_u64): Likewise.
(vreinterpretq_p16_p8): Likewise.
(vreinterpret_f32_s8): Likewise.
(vreinterpret_f32_s16): Likewise.
(vreinterpret_f32_s32): Likewise.
(vreinterpret_f32_s64): Likewise.
(vreinterpret_f32_u8): Likewise.
(vreinterpret_f32_u16): Likewise.
(vreinterpret_f32_u32): Likewise.
(vreinterpret_f32_u64): Likewise.
(vreinterpret_f32_p8): Likewise.
(vreinterpret_f32_p16): Likewise.
(vreinterpretq_f32_s8): Likewise.
(vreinterpretq_f32_s16): Likewise.
(vreinterpretq_f32_s32): Likewise.
(vreinterpretq_f32_s64): Likewise.
(vreinterpretq_f32_u8): Likewise.
(vreinterpretq_f32_u16): Likewise.
(vreinterpretq_f32_u32): Likewise.
(vreinterpretq_f32_u64): Likewise.
(vreinterpretq_f32_p8): Likewise.
(vreinterpretq_f32_p16): Likewise.
(vreinterpret_s64_s8): Likewise.
(vreinterpret_s64_s16): Likewise.
(vreinterpret_s64_s32): Likewise.
(vreinterpret_s64_f32): Likewise.
(vreinterpret_s64_u8): Likewise.
(vreinterpret_s64_u16): Likewise.
(vreinterpret_s64_u32): Likewise.
(vreinterpret_s64_u64): Likewise.
(vreinterpret_s64_p8): Likewise.
(vreinterpret_s64_p16): Likewise.
(vreinterpretq_s64_s8): Likewise.
(vreinterpretq_s64_s16): Likewise.
(vreinterpretq_s64_s32): Likewise.
(vreinterpretq_s64_f32): Likewise.
(vreinterpretq_s64_u8): Likewise.
(vreinterpretq_s64_u16): Likewise.
(vreinterpretq_s64_u32): Likewise.
(vreinterpretq_s64_u64): Likewise.
(vreinterpretq_s64_p8): Likewise.
(vreinterpretq_s64_p16): Likewise.
(vreinterpret_u64_s8): Likewise.
(vreinterpret_u64_s16): Likewise.
(vreinterpret_u64_s32): Likewise.
(vreinterpret_u64_s64): Likewise.
(vreinterpret_u64_f32): Likewise.
(vreinterpret_u64_u8): Likewise.
(vreinterpret_u64_u16): Likewise.
(vreinterpret_u64_u32): Likewise.
(vreinterpret_u64_p8): Likewise.
(vreinterpret_u64_p16): Likewise.
(vreinterpretq_u64_s8): Likewise.
(vreinterpretq_u64_s16): Likewise.
(vreinterpretq_u64_s32): Likewise.
(vreinterpretq_u64_s64): Likewise.
(vreinterpretq_u64_f32): Likewise.
(vreinterpretq_u64_u8): Likewise.
(vreinterpretq_u64_u16): Likewise.
(vreinterpretq_u64_u32): Likewise.
(vreinterpretq_u64_p8): Likewise.
(vreinterpretq_u64_p16): Likewise.
(vreinterpret_s8_s16): Likewise.
(vreinterpret_s8_s32): Likewise.
(vreinterpret_s8_s64): Likewise.
(vreinterpret_s8_f32): Likewise.
(vreinterpret_s8_u8): Likewise.
(vreinterpret_s8_u16): Likewise.
(vreinterpret_s8_u32): Likewise.
(vreinterpret_s8_u64): Likewise.
(vreinterpret_s8_p8): Likewise.
(vreinterpret_s8_p16): Likewise.
(vreinterpretq_s8_s16): Likewise.
(vreinterpretq_s8_s32): Likewise.
(vreinterpretq_s8_s64): Likewise.
(vreinterpretq_s8_f32): Likewise.
(vreinterpretq_s8_u8): Likewise.
(vreinterpretq_s8_u16): Likewise.
(vreinterpretq_s8_u32): Likewise.
(vreinterpretq_s8_u64): Likewise.
(vreinterpretq_s8_p8): Likewise.
(vreinterpretq_s8_p16): Likewise.
(vreinterpret_s16_s8): Likewise.
(vreinterpret_s16_s32): Likewise.
(vreinterpret_s16_s64): Likewise.
(vreinterpret_s16_f32): Likewise.
(vreinterpret_s16_u8): Likewise.
(vreinterpret_s16_u16): Likewise.
(vreinterpret_s16_u32): Likewise.
(vreinterpret_s16_u64): Likewise.
(vreinterpret_s16_p8): Likewise.
(vreinterpret_s16_p16): Likewise.
(vreinterpretq_s16_s8): Likewise.
(vreinterpretq_s16_s32): Likewise.
(vreinterpretq_s16_s64): Likewise.
(vreinterpretq_s16_f32): Likewise.
(vreinterpretq_s16_u8): Likewise.
(vreinterpretq_s16_u16): Likewise.
(vreinterpretq_s16_u32): Likewise.
(vreinterpretq_s16_u64): Likewise.
(vreinterpretq_s16_p8): Likewise.
(vreinterpretq_s16_p16): Likewise.
(vreinterpret_s32_s8): Likewise.
(vreinterpret_s32_s16): Likewise.
(vreinterpret_s32_s64): Likewise.
(vreinterpret_s32_f32): Likewise.
(vreinterpret_s32_u8): Likewise.
(vreinterpret_s32_u16): Likewise.
(vreinterpret_s32_u32): Likewise.
(vreinterpret_s32_u64): Likewise.
(vreinterpret_s32_p8): Likewise.
(vreinterpret_s32_p16): Likewise.
(vreinterpretq_s32_s8): Likewise.
(vreinterpretq_s32_s16): Likewise.
(vreinterpretq_s32_s64): Likewise.
(vreinterpretq_s32_f32): Likewise.
(vreinterpretq_s32_u8): Likewise.
(vreinterpretq_s32_u16): Likewise.
(vreinterpretq_s32_u32): Likewise.
(vreinterpretq_s32_u64): Likewise.
(vreinterpretq_s32_p8): Likewise.
(vreinterpretq_s32_p16): Likewise.
(vreinterpret_u8_s8): Likewise.
(vreinterpret_u8_s16): Likewise.
(vreinterpret_u8_s32): Likewise.
(vreinterpret_u8_s64): Likewise.
(vreinterpret_u8_f32): Likewise.
(vreinterpret_u8_u16): Likewise.
(vreinterpret_u8_u32): Likewise.
(vreinterpret_u8_u64): Likewise.
(vreinterpret_u8_p8): Likewise.
(vreinterpret_u8_p16): Likewise.
(vreinterpretq_u8_s8): Likewise.
(vreinterpretq_u8_s16): Likewise.
(vreinterpretq_u8_s32): Likewise.
(vreinterpretq_u8_s64): Likewise.
(vreinterpretq_u8_f32): Likewise.
(vreinterpretq_u8_u16): Likewise.
(vreinterpretq_u8_u32): Likewise.
(vreinterpretq_u8_u64): Likewise.
(vreinterpretq_u8_p8): Likewise.
(vreinterpretq_u8_p16): Likewise.
(vreinterpret_u16_s8): Likewise.
(vreinterpret_u16_s16): Likewise.
(vreinterpret_u16_s32): Likewise.
(vreinterpret_u16_s64): Likewise.
(vreinterpret_u16_f32): Likewise.
(vreinterpret_u16_u8): Likewise.
(vreinterpret_u16_u32): Likewise.
(vreinterpret_u16_u64): Likewise.
(vreinterpret_u16_p8): Likewise.
(vreinterpret_u16_p16): Likewise.
(vreinterpretq_u16_s8): Likewise.
(vreinterpretq_u16_s16): Likewise.
(vreinterpretq_u16_s32): Likewise.
(vreinterpretq_u16_s64): Likewise.
(vreinterpretq_u16_f32): Likewise.
(vreinterpretq_u16_u8): Likewise.
(vreinterpretq_u16_u32): Likewise.
(vreinterpretq_u16_u64): Likewise.
(vreinterpretq_u16_p8): Likewise.
(vreinterpretq_u16_p16): Likewise.
(vreinterpret_u32_s8): Likewise.
(vreinterpret_u32_s16): Likewise.
(vreinterpret_u32_s32): Likewise.
(vreinterpret_u32_s64): Likewise.
(vreinterpret_u32_f32): Likewise.
(vreinterpret_u32_u8): Likewise.
(vreinterpret_u32_u16): Likewise.
(vreinterpret_u32_u64): Likewise.
(vreinterpret_u32_p8): Likewise.
(vreinterpret_u32_p16): Likewise.
(vreinterpretq_u32_s8): Likewise.
(vreinterpretq_u32_s16): Likewise.
(vreinterpretq_u32_s32): Likewise.
(vreinterpretq_u32_s64): Likewise.
(vreinterpretq_u32_f32): Likewise.
(vreinterpretq_u32_u8): Likewise.
(vreinterpretq_u32_u16): Likewise.
(vreinterpretq_u32_u64): Likewise.
(vreinterpretq_u32_p8): Likewise.
(vreinterpretq_u32_p16): Likewise.
gcc/testsuite
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209642.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vreinterpret_f64_1.c: New.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211515
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:09:50 +0000 (11:09 +0000)]
gcc/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209640.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc/config/aarch64/aarch64-simd.md (aarch64_s<optab><mode>):
Pattern extended.
* config/aarch64/aarch64-simd-builtins.def (sqneg): Iterator
extended.
(sqabs): Likewise.
* config/aarch64/arm_neon.h (vqneg_s64): New intrinsic.
(vqnegd_s64): Likewise.
(vqabs_s64): Likewise.
(vqabsd_s64): Likewise.
gcc/testsuite/
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209640.
2014-04-22 Alex Velenko <Alex.Velenko@arm.com>
* gcc.target/aarch64/vqneg_s64_1.c: New testcase.
* gcc.target/aarch64/vqabs_s64_1.c: New testcase.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211514
138bc75d-0d04-0410-961f-
82ee72b054a4
yroux [Thu, 12 Jun 2014 11:05:18 +0000 (11:05 +0000)]
2014-05-23 Yvan Roux <yvan.roux@linaro.org>
Backport from trunk r209627, 209636.
2014-04-22 Renlin <renlin.li@arm.com>
Jiong Wang <jiong.wang@arm.com>
* config/aarch64/aarch64.h (aarch64_frame): Delete "fp_lr_offset".
* config/aarch64/aarch64.c (aarch64_layout_frame)
(aarch64_initial_elimination_offset): Likewise.
2014-04-22 Marcus Shawcroft <marcus.shawcroft@arm.com>
* config/aarch64/aarch64.c (aarch64_initial_elimination_offset):
Fix indentation.
git-svn-id: svn://gcc.gnu.org/svn/gcc/branches/linaro/gcc-4_9-branch@211512
138bc75d-0d04-0410-961f-
82ee72b054a4
projects / platform / upstream / gcc49.git / log