Yaxun (Sam) Liu [Thu, 27 Oct 2022 16:40:35 +0000 (12:40 -0400)]
[HIP] add fmax/fmin for fp16
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D136859
Arthur Eubanks [Fri, 28 Oct 2022 17:26:58 +0000 (10:26 -0700)]
Revert "[LegacyPM] Remove pipeline extension mechanism"
This reverts commit
4ea6ffb7e8edcea7f2cfb22acc907640a9ba44b9.
Breaks various backends.
Arthur Eubanks [Fri, 28 Oct 2022 17:25:23 +0000 (10:25 -0700)]
[polly] Format RegisterPasses.cpp
Erich Keane [Fri, 28 Oct 2022 17:02:04 +0000 (10:02 -0700)]
[Concepts] Fix an assert when trying to form a recovery expr on a
concept
When we failed the lookup of the function, we tried to form a
RecoveryExpr that caused us to recursively re-check the same constraint,
which caused us to try to double-insert the satisfaction into the cache.
This patch makes us just return the inner-cached version instead. We DO
end up double-evaluating thanks to the recovery-expr, but there isn't a
good way around that.
Arthur Eubanks [Wed, 26 Oct 2022 18:33:02 +0000 (11:33 -0700)]
[clang] Remove no-op -fexperimental-new-pass-manager/-fno-legacy-pass-manager flags
These have been no-op for a while and keeping them around may be confusing.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D136789
Craig Topper [Fri, 28 Oct 2022 17:16:57 +0000 (10:16 -0700)]
[RISCV] Optimize i64 insertelt on RV32.
We can use tail undisturbed vslide1down to insert into the vector.
This should make D136640 unneeded.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D136738
Arthur Eubanks [Mon, 24 Oct 2022 17:21:39 +0000 (10:21 -0700)]
[LegacyPM] Remove pipeline extension mechanism
Part of gradually removing the legacy PM optimization pipeline.
Reviewed By: MaskRay
Differential Revision: https://reviews.llvm.org/D136622
Arthur Eubanks [Mon, 24 Oct 2022 17:12:32 +0000 (10:12 -0700)]
[polly] Remove legacy pass manager hooks
And some options that only throw errors with the new PM.
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D136621
Caroline Concatto [Thu, 27 Oct 2022 14:49:36 +0000 (15:49 +0100)]
[AArch64]SME2 Outer Product and Accumulate instructions
This patch adds the assembly/disassembly for the following instructions:
BMOPA: Bitwise exclusive NOR population count outer product and accumulate.
BMOPS: Bitwise exclusive NOR population count outer product and subtract.
SMOPA (2-way): Signed integer sum of outer products and accumulate.
SMOPS (2-way): Signed integer sum of outer products and subtract.
UMOPA (2-way): Unsigned integer sum of outer products and accumulate.
UMOPS (2-way): Signed integer sum of outer products and accumulate.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential Revision: https://reviews.llvm.org/D136077
Aaron Ballman [Fri, 28 Oct 2022 16:45:56 +0000 (12:45 -0400)]
Add test coverage for WG14 N2322
The changes in this paper add a new recommended practice. I had
originally marked Clang as supporting this paper because we're not
obligated to follow a recommended practice. However, in retrospect, it
seems more useful to document whether we implement the recommendation
or not. This adds a test for those changes.
Caroline Concatto [Tue, 25 Oct 2022 10:26:53 +0000 (11:26 +0100)]
[AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors LONG INT MLA sources
This patch adds the assembly/disassembly for the following instructions:
SMLALL: (multiple and indexed vector): Multi-vector signed integer multiply-add long long by indexed element.
(multiple and single vector): Multi-vector signed integer multiply-add long long by vector.
(multiple vectors): Multi-vector signed integer multiply-add long long.
SMLSLL: (multiple and indexed vector): Multi-vector signed integer multiply-subtract long long by indexed element.
(multiple and single vector): Multi-vector signed integer multiply-subtract long long by vector.
(multiple vectors): Multi-vector signed integer multiply-subtract long long.
SUMLALL: (multiple and indexed vector): Multi-vector signed by unsigned integer multiply-add long long by indexed element.
(multiple and single vector): Multi-vector signed by unsigned integer multiply-add long long by vector.
UMLALL: (multiple and indexed vector): Multi-vector unsigned integer multiply-add long long by indexed element.
(multiple and single vector): Multi-vector unsigned integer multiply-add long long by vector.
(multiple vectors): Multi-vector unsigned integer multiply-add long long.
UMLSLL: (multiple and indexed vector): Multi-vector unsigned integer multiply-subtract long long by indexed element.
(multiple and single vector): Multi-vector unsigned integer multiply-subtract long long by vector.
(multiple vectors): Multi-vector unsigned integer multiply-subtract long long.
USMLALL: (multiple and indexed vector): Multi-vector unsigned by signed integer multiply-add long long by indexed element.
(multiple and single vector): Multi-vector unsigned by signed integer multiply-add long long by vector.
(multiple vectors): Multi-vector unsigned by signed integer multiply-add long long.
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
It also adds a new immediate:
uimm2s4range for off2
uimm1s4range for o1
to represent the vector select offset.
The new operands have the range between the first and the last vector position.
Depends on : D135785
Differential Revision: https://reviews.llvm.org/D136075
Simon Pilgrim [Fri, 28 Oct 2022 16:10:36 +0000 (17:10 +0100)]
[DAG] ExpandIntRes_MINMAX - simplify cases with sufficient number of sign bits
When legalizing a smax/smin/umax/umin op, if we know that the upper half is all sign bits, then we can perform the op on the lower half and then sign extend the result to the upper half.
Alive2: https://alive2.llvm.org/ce/z/rk8Rfd
Fixes #58630
Simon Pilgrim [Fri, 28 Oct 2022 13:41:56 +0000 (14:41 +0100)]
[X86] Add basic test coverage for Issue #58630
If we have sufficient sign bits, we should be able to expand the IMINMAX using only the lower half (and then sign-extend the result to the upper half)
Timm Bäder [Fri, 28 Oct 2022 16:06:40 +0000 (18:06 +0200)]
[clang][Interp] Add missing expected test output
Matt Devereau [Fri, 28 Oct 2022 15:56:12 +0000 (15:56 +0000)]
[InstCombine] Add shuffle-binop tests
These tests are a precommit for https://reviews.llvm.org/D135876
Timm Bäder [Fri, 21 Oct 2022 07:10:29 +0000 (09:10 +0200)]
[clang][Interp] Implement inc and dec operators
Differential Revision: https://reviews.llvm.org/D136423
Timm Bäder [Fri, 21 Oct 2022 06:46:33 +0000 (08:46 +0200)]
[clang][Interp][NFC] Use right visit() function
visit (lowercase V) sets DiscardValue to false and calls Visit
(uppercase V). So we can't just call Visit (uppercase V) ourselves,
since then we aren't handling DiscardValue correctly.
This is currently irrelevant but will make a difference later.
Also, the naming isn't my fault and might change later.
Yaxun (Sam) Liu [Thu, 27 Oct 2022 16:04:45 +0000 (12:04 -0400)]
[HIP] add --offload-add-rpath
Add an option --[no-]offload-add-rpath to control whether to
pass -rpath to linker for HIP runtime library. By default it
is off to match gcc/clang behavior for not adding -rpath
for runtime library by default.
Reviewed by: Artem Belevich
Differential Revision: https://reviews.llvm.org/D136854
Kevin P. Neal [Fri, 28 Oct 2022 15:37:04 +0000 (11:37 -0400)]
[clang][Docs] Correct typo: "may_trap" is rejected, the value is "maytrap".
Nikita Popov [Fri, 28 Oct 2022 15:29:07 +0000 (17:29 +0200)]
[GVN] Regenerate test checks (NFC)
Craig Topper [Fri, 28 Oct 2022 15:13:35 +0000 (08:13 -0700)]
[RISCV] Adjust RV64I data layout by using n32:64 in layout string
Although i32 type is illegal in the backend, RV64I has pretty good support for i32 types by using W instructions.
By adding n32 to the DataLayout string, middle end optimizations will consider i32 to be a native type. One known effect of this is enabling LoopStrengthReduce on loops with i32 induction variables. This can be beneficial because C/C++ code often has loops with i32 induction variables due to the use of `int` or `unsigned int`.
If this patch exposes performance issues, those are better addressed by tuning LSR or other passes.
Reviewed By: asb, frasercrmck
Differential Revision: https://reviews.llvm.org/D116735
Shilei Tian [Fri, 28 Oct 2022 15:22:07 +0000 (11:22 -0400)]
[NFC][OpenMP] Fix compile warnings introduced by D134396
Momchil Velikov [Fri, 28 Oct 2022 10:30:41 +0000 (11:30 +0100)]
[FuncSpec][NFC] Avoid redundant computations of DominatorTree/LoopInfo
The `FunctionSpecialization` pass needs loop analysis results for its
cost function. For this purpose, it computes the `DominatorTree` and
`LoopInfo` for a function in `getSpecializationBonus`. This function,
however, is called O(number of call sites x number of arguments), but
the DominatorTree/LoopInfo can be computed just once.
This patch plugs into the PassManager infrastructure to obtain
LoopInfo for a function and removes ad-hoc computation from
`getSpecializatioBonus`.
Reviewed By: ChuanqiXu, labrinea
Differential Revision: https://reviews.llvm.org/D136332
Eduard Zingerman [Fri, 28 Oct 2022 14:59:08 +0000 (07:59 -0700)]
[clang][DebugInfo] Emit DISubprogram for extern functions with reserved names
Callsite `DISubprogram` entries are not generated for:
- builtin functions;
- external functions with reserved names (e.g. names starting from "__").
This limitation was added by the commit [1] as a workaround for the
situation described in [2] that triggered the IR verifier error.
The goal of the present commit is to lift this limitation by adjusting
the IR verifier logic.
The logic behind [1] is to avoid the following situation:
- a `DISubprogram` is added for some builtin function;
- there is some location where this builtin is also emitted by a
transformation (w/o debug location);
- the `Verifier::visitCallBase` sees a call to a function with
`DISubprogram` but w/o debug location and emits an error.
Here is an updated example of such situation taken from [2]:
```
extern "C" int memcmp(void *, void *, long);
struct a { int b; int c; int d; };
struct e { int f[1000]; };
bool foo(e g, e &h) {
// DISubprogram for memcmp is created here when [1] is commented out
return memcmp(&g, &h, sizeof(e));
}
bool bar(a &g, a &h) {
// memcmp might be generated here by MergeICmps
return g.b == h.b && g.c == h.c && g.d == h.d;
}
```
This triggers the verifier error when:
- compiled for AArch64:
`clang++ -c -g -Oz -target aarch64-unknown-linux-android21 test.cpp`;
- [1] check is commented out.
Instead of forbidding generation of `DISubprogram` entries as in [1]
one can instead adjust the verifier to additionally check if callee
has a body. Functions w/o bodies cannot be inlined and thus verifier
warning is not necessary.
E.g. `llvm::InlineFunction` requires functions for which
`GlobalValue::isDeclaration() == false`.
[1]
568db780bb7267651a902da8e85bc59fc89aea70
[2] https://bugs.chromium.org/p/chromium/issues/detail?id=1022296
Differential Revision: https://reviews.llvm.org/D136041
Timm Bäder [Thu, 27 Oct 2022 09:32:31 +0000 (11:32 +0200)]
[clang][Interp] Make sure we free() allocated InitMaps
They get allocated when calling initialize() on a primitive array. And
they get free'd when the array is fully initialized. However, when that
never happens, they get leaked. Fix that by calling the destructor of
global variables.
Differential Revision: https://reviews.llvm.org/D136826
Timm Bäder [Sat, 15 Oct 2022 07:56:26 +0000 (09:56 +0200)]
[clang][Interp] Fix ignoring expression return values
Randomly noticed this. We need to honor DiscardResult here.
Differential Revision: https://reviews.llvm.org/D136013
Timm Bäder [Sat, 15 Oct 2022 07:22:34 +0000 (09:22 +0200)]
[clang][Interp] Fix record members of reference type
When assigning to them, we can't classify the expression type, because
that doesn't contain the right information.
And when reading from them, we need to do the extra deref, just like we
do when reading from a DeclRefExpr.
Differential Revision: https://reviews.llvm.org/D136012
Timm Bäder [Fri, 28 Oct 2022 13:06:24 +0000 (15:06 +0200)]
[clang][Interp] Remove unused getGlobalIdx()
Remove the only use with the version we already use in
VisitDeclRefExpr().
Nicolai Hähnle [Thu, 22 Sep 2022 16:14:45 +0000 (18:14 +0200)]
clang-tblgen build: avoid duplicate inclusion of libLLVMSupport
TableGen executables are supposed to never be linked against libLLVM-*.so,
even when LLVM_LINK_LLVM_DYLIB=ON, presumably for cross-compilation.
It turns out that clang-tblgen *did* link against libLLVM-*.so,
indirectly so via the clangSupport.
This lead to a regression in what should have been unrelated work of
cleaning up ManagedStatics in LLVMSupport. A running clang-tblgen
process ended up with two copies of a cl::opt static global:
- one from libLLVMSupport linked statically into clang-tblgen as a
direct dependency
- one from libLLVMSupport linked into libLLVM-*.so, which clang-tblgen
linked against due to the clangSupport dependency
For a bit more context, see the discussion at
https://discourse.llvm.org/t/flang-aarch64-dylib-buildbot-need-help-understanding-a-regression-in-clang-tblgen/64871/
None of the potential solutions I could find are perfect. Presumably one
possible solution would be to remove "Support" from the explicit
dependencies of clang-tblgen. However, relying on the transitive
inclusion via clangSupport seems risky, and in any case this wouldn't
address the issue of clang-tblgen surprisingly linking against libLLVM-*.so.
This change instead creates a second version of the clangSupport library
that is explicitly linked statically, to be used by clang-tblgen.
v2:
- define an alias so that clang-tblgen can always link against
"clangSupport_tablegen"
- use add_llvm_library(... BUILDTREE_ONLY ...)
v3:
- use the object library version of clangSupport if available
Differential Revision: https://reviews.llvm.org/D134637
Alexander Belyaev [Fri, 28 Oct 2022 13:24:34 +0000 (15:24 +0200)]
[mlir] Rename getInputs->getDpsInputs and getOutputs->getDpsInits in DPS interface.
https://discourse.llvm.org/t/rfc-interface-for-destination-style-ops/64056
Differential Revision: https://reviews.llvm.org/D136943
John Brawn [Fri, 28 Oct 2022 13:38:33 +0000 (14:38 +0100)]
Revert "[MachineCSE] Allow PRE of instructions that read physical registers"
This reverts commit
628467e53f4ceecd2b5f0797f07591c66d9d9d2a.
This is causing a miscompile in ffmpeg when compiled for armv7.
Sanjay Patel [Fri, 28 Oct 2022 12:41:57 +0000 (08:41 -0400)]
[SDAG] avoid crash from mismatched types in scalar-to-vector fold
This bug was introduced with D136713 /
54eeadcf442df91aed0 .
As an enhancement, we could cast operands to the expected type,
but we need to make sure that is done correctly (zext vs. sext).
It's also possible (but seems unlikely) that an operand can have
a type larger than the result type.
Fixes #58661
Qiongsi Wu [Fri, 28 Oct 2022 12:33:57 +0000 (08:33 -0400)]
[clang][LTO] Passing vec-extabi to the Backend on AIX
This patch passes on the `vec-extabi` mabi option on AIX.
Reviewed By: w2yehia
Differential Revision: https://reviews.llvm.org/D136874
Kadir Cetinkaya [Mon, 24 Oct 2022 15:14:52 +0000 (17:14 +0200)]
[llvm] Fix minimum Apple Clang requirement
This was stated as 9.3, but as pointed out in
https://discourse.llvm.org/t/rfc-bump-minimal-requirements-apple-clang-9-3-10-0-0-before-4th-tue-in-january/66156/7?u=kadircet
9.3 doesn't exist, hence this was effectively 10.0.
This patch merely reflects the reality more closely.
Differential Revision: https://reviews.llvm.org/D136609
Martin Storsjö [Fri, 28 Oct 2022 13:10:17 +0000 (16:10 +0300)]
[clang] Fix a -Wcast-qual GCC warning. NFC.
This fixes the following warning:
../tools/clang/lib/AST/Interp/Disasm.cpp: In member function ‘void clang::interp::Function::dump(llvm::raw_ostream&) const’:
../tools/clang/lib/AST/Interp/Disasm.cpp:43:25: warning: cast from type ‘const clang::interp::Function*’ to type ‘void*’ casts away qualifiers [-Wcast-qual]
43 | OS << " " << (void*)this << ":\n";
| ^~~~
Haojian Wu [Fri, 28 Oct 2022 13:08:41 +0000 (15:08 +0200)]
Timm Bäder [Fri, 28 Oct 2022 11:49:30 +0000 (13:49 +0200)]
[clang][Interp] Implement String- and CharacterLiterals
Differential Revision: https://reviews.llvm.org/D135366
Haojian Wu [Fri, 28 Oct 2022 12:47:01 +0000 (14:47 +0200)]
Kristof Beyls [Thu, 27 Oct 2022 19:05:56 +0000 (21:05 +0200)]
Online sync-ups: remove Windows/COFF entry.
They stopped a while ago.
Differential Revision: https://reviews.llvm.org/D136876
Nenad Mikša [Fri, 28 Oct 2022 12:18:38 +0000 (08:18 -0400)]
Disambiguate type names when printing NTTP types
When printing NTTP template types, ensure that type name of the NTTP is
printed.
Fixes #57562
Differential Revision: https://reviews.llvm.org/D134453
Aaron Ballman [Fri, 28 Oct 2022 12:16:19 +0000 (08:16 -0400)]
Add some more C11 DR tests and update the status page
Nikita Popov [Fri, 28 Oct 2022 12:08:34 +0000 (14:08 +0200)]
[InstCombine] Convert test to opaque pointers (NFC)
With some manual fixup for different alloca types and variable name
clashes.
Victor Campos [Fri, 7 Oct 2022 14:37:42 +0000 (15:37 +0100)]
[Object] Prevent null pointer dereference in BigArchiveMemberHeader
The pointer argument Err from BigArchiveMemberHeader's constructor can
be null. This pointer was dereferenced without any null checks.
This patch adds a check to avoid a null dereference.
Reviewed By: brenoguim
Differential Revision: https://reviews.llvm.org/D135449
Guray Ozen [Fri, 28 Oct 2022 11:45:44 +0000 (13:45 +0200)]
[mlir][nvvm] Introduce performance tuning directives
PTX programming models provides some performance tuning directives; see https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#performance-tuning-directives
The downstream compiler namely `ptxas` leverages these information for better register allocation or to handle other resource management that improves the performance.
This revision introduce all the kernel based directives to MLIR's NVVM dialect. The list is below
```
maxnreg -> max register per thread in CTA
maxntid -> max threads per CTA
reqntid -> exact number of threads per CTA
minnctapersm -> min CTA per SM
```
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D136931
Timm Bäder [Fri, 28 Oct 2022 11:33:26 +0000 (13:33 +0200)]
Revert "[clang][Interp] Implement String- and CharacterLiterals"
This reverts commit
6fa1795d1fd4770f9f5c00f5a30937d68c3feb17.
This breaks a windows builder:
../../clang/lib/AST/Interp/ByteCodeExprGen.h(236,11): error: call to constructor of 'clang::interp::APInt' (aka 'llvm::APInt') is ambiguous
APInt WrappedValue(getIntWidth(Ty), Value, std::is_signed<T>::value);
^ ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
../../clang/lib/AST/Interp/ByteCodeExprGen.cpp(409,16): note: in instantiation of function template specialization 'clang::interp::ByteCodeExprGen<clang::interp::ByteCodeEmitter>::emitConst<unsigned int>' requested here
return this->emitConst(E, E->getValue());
^
../../clang/lib/AST/Interp/ByteCodeExprGen.cpp(1149,16): note: in instantiation of member function 'clang::interp::ByteCodeExprGen<clang::interp::ByteCodeEmitter>::VisitCharacterLiteral' requested here
template class ByteCodeExprGen<ByteCodeEmitter>;
^
../../llvm/include\llvm/ADT/APInt.h(108,3): note: candidate constructor
APInt(unsigned numBits, uint64_t val, bool isSigned = false)
^
../../llvm/include\llvm/ADT/APInt.h(134,3): note: candidate constructor
APInt(unsigned numBits, unsigned numWords, const uint64_t bigVal[]);
^
Simon Pilgrim [Fri, 28 Oct 2022 11:11:00 +0000 (12:11 +0100)]
[DAG] visitXOR - fold XOR(A,B) -> OR(A,B) iff A and B have no common bits
Alive2: https://alive2.llvm.org/ce/z/7wvfns
Part of Issue #58624
Nikita Popov [Fri, 28 Oct 2022 11:03:39 +0000 (13:03 +0200)]
[InstCombine] Convert some tests to opaque pointers (NFC)
Conversion was performed (without manual fixup) using:
https://gist.github.com/nikic/
98357b71fd67756b0f064c9517b62a34
Timm Bäder [Fri, 28 Oct 2022 10:48:40 +0000 (12:48 +0200)]
[clang][Interp][NFC] Fix instance method check
This was a change suggested by Aaron that I forgot to commit.
Timm Bäder [Mon, 10 Oct 2022 11:00:38 +0000 (13:00 +0200)]
[clang][Interp] Implement String- and CharacterLiterals
Differential Revision: https://reviews.llvm.org/D135366
Timm Bäder [Thu, 27 Oct 2022 04:19:19 +0000 (06:19 +0200)]
[clang][Interp][NFC] Print more info in Program::dump()
Number of functions and global variables is useful to know.
Timm Bäder [Wed, 26 Oct 2022 09:25:25 +0000 (11:25 +0200)]
[clang][Interp][NFC] Remove leftover comment fragment
Timm Bäder [Fri, 28 Oct 2022 07:27:49 +0000 (09:27 +0200)]
[clang][Interp][NFC] Fix a file header comment
Timm Bäder [Wed, 26 Oct 2022 09:24:41 +0000 (11:24 +0200)]
[clang][Interp][NFC] Add Record::getName()
Useful for debugging.
Simon Pilgrim [Fri, 28 Oct 2022 10:48:33 +0000 (11:48 +0100)]
[DAG] visitFSUBForFMACombine - pass callbacks by reference in isContractableAndReassociableFMUL lambda capture. NFC.
Fixes a coverity remark about large copies by value
Martin Storsjö [Thu, 27 Oct 2022 19:48:24 +0000 (22:48 +0300)]
[LLD] [COFF] Include "rust_eh_personality" among the known personality functions
These need to have special treatment wrt to .eh_frame sections
and GC - as long as we don't have a full parser of the .eh_frame
section in the COFF linker.
This fixes Rust unwind issues on i686 mingw as discussed in
https://github.com/msys2/MINGW-packages/issues/9091.
Differential Revision: https://reviews.llvm.org/D136879
Michael Buch [Wed, 26 Oct 2022 13:40:34 +0000 (14:40 +0100)]
[lldb][Docs][NFC] Fix sphinx warnings/errors for LLDB docs
Ran `ninja docs-lldb-html` and made sure the docs are fixed.
Differential Revision: https://reviews.llvm.org/D136766
Momchil Velikov [Fri, 28 Oct 2022 09:36:47 +0000 (10:36 +0100)]
Recommit: [FuncSpec][NFC] Refactor finding specialisation opportunities
[recommitting after recommitting a dependency]
This patch reorders the traversal of function call sites and function
formal parameters to:
* do various argument feasibility checks (`isArgumentInteresting` )
only once per argument, i.e. doing N-args checks instead of
N-calls x N-args checks.
* do hash table lookups only once per call site, i.e. N-calls
lookups/inserts instead of N-call x N-args lookups/inserts.
Reviewed By: ChuanqiXu, labrinea
Differential Revision: https://reviews.llvm.org/D135968
Change-Id: I7d21081a2479cbdb62deac15f903d6da4f3b8529
Simon Pilgrim [Fri, 28 Oct 2022 10:19:53 +0000 (11:19 +0100)]
ConstraintElimination - pass const DataLayout by reference in (recursive) MergeResults lambda capture. NFC.
There's no need to copy this and fixes a coverity remark about large copy by value
Jay Foad [Fri, 28 Oct 2022 10:17:21 +0000 (11:17 +0100)]
[AMDGPU] Regenerate checks in waitcnt-overflow.mir. NFC.
Simon Pilgrim [Fri, 28 Oct 2022 10:05:26 +0000 (11:05 +0100)]
IndirectBrExpandPass - remove unused DL from lambda capture. NFC.
Oddly I wasn't seeing an unused variable warning - this came up in a coverity remark about large copy by values!
Stephen Thomas [Fri, 28 Oct 2022 09:59:03 +0000 (10:59 +0100)]
[AMDGPU] Small cleanups in wait counter code
A small number of cleanups and refactors intended to enhance readability in
two passes that deal with s_waitcnt instructions.
Differential Revision: https://reviews.llvm.org/D136677
Andrzej Warzynski [Fri, 21 Oct 2022 15:27:57 +0000 (15:27 +0000)]
[mlir][aarch64] XFAIL correctness.mlir
There are some discrepancies between the expected and the generated
output on AArch64 for this test. I reported these on GitHub:
* https://github.com/llvm/llvm-project/issues/58531
I'm XFAILing this test as a temporary measure while this is being
investigated.
Differential Revision: https://reviews.llvm.org/D136458
Haojian Wu [Fri, 28 Oct 2022 09:36:02 +0000 (11:36 +0200)]
Revert "[clang] Instantiate NTTPs and template default arguments with sugar"
This patch reverts
- commit
d4b1964f0554046b1e64908e5c1cd701b25f4c9e
- commit
59f0827e2cf3755834620e7e0b6d946832440f80([clang] Instantiate alias templates with sugar)
As it makes clang fail to pass some code it used to compile.
See comments: https://reviews.llvm.org/D136564#3891065
wanglei [Fri, 28 Oct 2022 09:49:47 +0000 (17:49 +0800)]
[LoongArch] Add emergency spill slot for GPR for large frames
An emergency spill slot is created when the stack size cannot be
represented by an 11-bit signed number.
This patch also modifies how the `sp` is adjusted in the prologue.
`RegScavenger` will place the spill instruction before the prologue
if a VReg is created in the prologue. This will pollute the caller's
stack data. Therefore, until there is better way, we just use the
`addi.w/d` instruction for stack adjustment to ensure that VReg will
not be created. (RISCV has the same issue #58286)
Due to the addition of emergency spill slot, some test cases that use
exact stacksize need to be updated.
Differential Revision: https://reviews.llvm.org/D135757
Jay Foad [Thu, 27 Oct 2022 14:05:35 +0000 (15:05 +0100)]
[AMDGPU] Clean up calls to MachineOperand::setIsDead and friends. NFC.
Oleg Shyshkov [Fri, 28 Oct 2022 09:31:58 +0000 (11:31 +0200)]
Revert "Revert "[mlir][linalg] Add nicer builders for `map` and `reduce`.""
This reverts commit
7eef3ea5f4fe4f4cc461b191bac031e3962d0347.
Oleg Shyshkov [Fri, 28 Oct 2022 08:29:01 +0000 (10:29 +0200)]
[mlir][linalg] Fix linalg.transpose region builder.
The region should yield the first argument (input) not the last argument
(output). Also fix a few tests that were affected by this bug.
Differential Revision: https://reviews.llvm.org/D136924
David Green [Fri, 28 Oct 2022 09:15:41 +0000 (10:15 +0100)]
[InstCombine] Don't change switch table from desirable to illegal types
In InstCombine we treat i8/i16 as desirable, even if they are not legal.
The current logic in shouldChangeType will decide to convert from an
illegal but desirable type (such as an i8) to an illegal and undesirable
type (such as i3). This patch prevents changing the switch conditions to
an irregular type on like Arm/AArch64 where i8/i16 are not legal.
This is the same issue as https://reviews.llvm.org/D54115. In the case I
was looking it is was converting an i32 switch to an i8 switch, which
then became a i3 switch.
Differential Revision: https://reviews.llvm.org/D136763
eopXD [Thu, 27 Oct 2022 07:42:46 +0000 (00:42 -0700)]
[Clang] Improve diagnostic message for loop hint pragma
Originally the loop hint is not displayed correctly in the diagnostic.
This patch fixes it.
Reviewed By: Meinersbur
Differential Revision: https://reviews.llvm.org/D136784
wanglei [Fri, 28 Oct 2022 08:18:40 +0000 (16:18 +0800)]
[LoongArch] Split SP adjustment
This patch split the SP adjustment to reduce the instructions in
prologue and epilogue. In this way, the offset of the callee saved
register could fit in a single store.
Similar to D68011(RISCV).
Differential Revision: https://reviews.llvm.org/D136222
Christian Sigg [Thu, 27 Oct 2022 08:08:52 +0000 (10:08 +0200)]
[mlir][gpu] Unroll ops on vectors which map to intrinsic calls
Unroll ops that map to intrinsics when lowering to LLVM, because intrinsics don't support vector operands/results.
Reviewed By: herhut
Differential Revision: https://reviews.llvm.org/D136345
chenglin.bi [Fri, 28 Oct 2022 08:30:14 +0000 (16:30 +0800)]
Revert "[AArch64] Adjust operand sequence for Add+Sub to combine more inline shift"
This reverts commit
ada9ab610727917561370e976eaea26dbbc20cce.
Nikita Popov [Wed, 26 Oct 2022 11:05:20 +0000 (13:05 +0200)]
[ARM] Use DefaultAttrsIntrinsics
Use DefaultAttrsIntrinsics for most ARM intrinsics. This adds the
WillReturn, NoSync, NoFree and NoCallback attributes and is needed
to avoid regressions in the future.
I've switched to DefaultAttrIntrinsics for everything doing arithmetic
and load/store. I've left some TODOs in cases where all DefaultsAttrs
are not correct (e.g. ldrex etc are clearly not nosync) or it wasn't
entirely obvious to me (e.g. stuff interacting with a coprocessor).
Differential Revision: https://reviews.llvm.org/D136758
Oleg Shyshkov [Fri, 28 Oct 2022 07:56:59 +0000 (09:56 +0200)]
Revert "[mlir][linalg] Add nicer builders for `map` and `reduce`."
This reverts commit
aebde280476943e58f5bcd9993fdd7e36cdbe47e.
Juan Manuel MARTINEZ CAAMAÑO [Wed, 26 Oct 2022 08:57:36 +0000 (03:57 -0500)]
[StructurizeCFG][DebugInfo] Maintain DILocations in the branches created by StructurizeCFG
Make StructurizeCFG preserve the debug locations of the branch instructions it introduces.
Differential Revision: https://reviews.llvm.org/D135967
Michał Górny [Mon, 24 Oct 2022 13:50:41 +0000 (15:50 +0200)]
[flang] Fix building against clang dylib
Differential Revision: https://reviews.llvm.org/D136606
Sander de Smalen [Fri, 28 Oct 2022 07:08:08 +0000 (07:08 +0000)]
[AArch64][SME] Set fn attributes correctly on __arm_tpidr2_save call.
Changing the way the attribute is created changes the way the attribute
is added. Now it seems to be correctly added as a function attribute, whereas
before it was not. This led ISel ignoring attributes and setting up a lazy-save
buffer for the call to __arm_tpidr2_save.
This patch also marks the intrinsic call as 'preserves_za' which together with the
above prevents the code-generator from setting up a lazy-save buffer.
Reviewed By: kmclaughlin
Differential Revision: https://reviews.llvm.org/D136342
Pavel Labath [Fri, 28 Oct 2022 07:04:14 +0000 (09:04 +0200)]
[lldb/qemu] Stub out process info functions
These functions return the information about the host process (so they
show the executable as "qemu" and have the "wrong" architecture), which
isn't useful and can confuse lldb.
We could theoretically try to identify which host processes are running
an emulator, and translate the process information, but that would be
tricky to implement, and the usefulness of it would be fairly limited as
qemu does not support attaching to a running process.
Valery Pykhtin [Fri, 28 Oct 2022 07:15:37 +0000 (09:15 +0200)]
Revert "[AMDGPU] Add EXPENSIVE_CHECK into GCNRPTracker::reset"
This reverts commit
fecf067db40ffa1a6d5d665769c90cd29547f502.
The change introduces 420 test failures with EXPENSIVE_CHECK in AMDGPU which I don't want to disable.
Going to fix the failures and recommit the check.
David Sherwood [Wed, 19 Oct 2022 14:29:51 +0000 (14:29 +0000)]
[AArch64][SVE2] Add the SVE2.1 extract-and-narrow instructions
This patch adds the assembly/disassembly for the following instructions:
sqcvtn : Signed saturating extract narrow and interleave
sqcvtun : Signed saturating unsigned extract narrow and interleave
uqcvtn : Unsigned saturating extract narrow and interleave
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Differential revision: https://reviews.llvm.org/D136689
Oleg Shyshkov [Thu, 27 Oct 2022 18:48:04 +0000 (20:48 +0200)]
[mlir][linalg] Add nicer builders for `map` and `reduce`.
The new builders get a list of additional attrs, a lambda to build the region
body and infer return types from `init`.
Differential Revision: https://reviews.llvm.org/D136838
Michał Górny [Mon, 24 Oct 2022 04:58:55 +0000 (06:58 +0200)]
[llvm] [cmake] Silence GNUInstallDirs warning in LLVMInstallSymlink
Set a dummy CMAKE_INSTALL_LIBDIR in order to silence the following CMake
warning when executing LLVMInstallSymlink.cmake script:
CMake Warning (dev) at /usr/share/cmake/Modules/GNUInstallDirs.cmake:243 (message):
Unable to determine default CMAKE_INSTALL_LIBDIR directory because no
target architecture is known. Please enable at least one language before
including GNUInstallDirs.
Call Stack (most recent call first):
/usr/lib/llvm/16/lib64/cmake/llvm/LLVMInstallSymlink.cmake:5 (include)
tools/lld/cmake_install.cmake:66 (include)
cmake_install.cmake:52 (include)
Differential Revision: https://reviews.llvm.org/D136573
Michał Górny [Mon, 24 Oct 2022 04:31:37 +0000 (06:31 +0200)]
Harmonize cmake_policy() across standalone builds of all projects
Move `cmake_policy()` settings from `llvm/CMakeLists.txt` into a shared
`cmake/modules/CMakePolicy.cmake`. Include it from all relevant
projects that support standalone builds, in order to ensure that
the policies are consistently set whether they are built in-tree
or stand-alone.
Differential Revision: https://reviews.llvm.org/D136572
Valery Pykhtin [Thu, 27 Oct 2022 07:06:27 +0000 (09:06 +0200)]
[AMDGPU] Add EXPENSIVE_CHECK into GCNRPTracker::reset
This would check if passed in live-ins registers match those calculated using LIS.
This check currently breaks 420 lit tests when enabled.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D136860
Pierre van Houtryve [Fri, 28 Oct 2022 06:28:35 +0000 (06:28 +0000)]
[DAGCombiner] Use `getAnyExtOrTrunc` instead of TRUNCATE in ExtractVectorElt combine
ScalarVT isn't guaranteed to be smaller than the BCSrc.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D136849
Valentin Clement [Fri, 28 Oct 2022 06:30:53 +0000 (08:30 +0200)]
[flang] Carry polymoprhic dynamic type when using coordinate_of polymoprhic array
Dynamic type of a polymorphic array element was retrieved by finding the
coordinate operation and use the base array. This patch remove this hack and use
the newly PolymorphicValue to carray the dynamic type together with the element.
The patch also rearrange some tests in the `allocatable-polymorphic.f90`.
Depends on D136824
Reviewed By: PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D136857
Advenam Tacet [Fri, 28 Oct 2022 05:14:14 +0000 (22:14 -0700)]
[1b/3][ASan][compiler-rt] API for annotating objects memory
This revision is a part of a series of patches extending AddressSanitizer C++ container overflow detection capabilities by adding annotations, similar to those existing in std::vector, to std::string and std::deque collections. These changes allow ASan to detect cases when the instrumented program accesses memory which is internally allocated by the collection but is still not in-use (accesses before or after the stored elements for std::deque, or between the size and capacity bounds for std::string).
The motivation for the research and those changes was a bug, found by Trail of Bits, in a real code where an out-of-bounds read could happen as two strings were compared via a std::equals function that took iter1_begin, iter1_end, iter2_begin iterators (with a custom comparison function). When object iter1 was longer than iter2, read out-of-bounds on iter2 could happen. Container sanitization would detect it.
This revision extends a compiler-rt ASan sanitization API function sanitizer_annotate_contiguous_container used to sanitize/annotate containers like std::vector to support different allocators and situations when granules are shared between objects. Those changes are necessary to support annotating objects' self memory (in contrast to annotating memory allocated by an object) like short std::basic_string (with short string optimization). That also allows use of non-standard memory allocators, as alignment requirement is no longer necessary.
This also updates an API function to verify if a double ended contiguous container is correctly annotated (__sanitizer_verify_contiguous_container).
If you have any questions, please email:
advenam.tacet@trailofbits.com
disconnect3d@trailofbits.com
Reviewed By: #sanitizers, vitalybuka
Differential Revision: https://reviews.llvm.org/D132522
Carlos Alberto Enciso [Fri, 28 Oct 2022 06:20:15 +0000 (07:20 +0100)]
[llvm-debuginfo-analyzer] (08/09) - ELF Reader - Disable test.
Disable the test case: 06-dwarf-full-logical-view.test
It produces incorrect data on ARM:
https://lab.llvm.org/buildbot/#/builders/182/builds/4232
https://lab.llvm.org/buildbot/#/builders/187/builds/9483
Expected:
189 (100.00%) : [0x000000000b][001] {CompileUnit}
110 ( 58.20%) : [0x000000002a][002] 2 {Function}
27 ( 14.29%) : [0x0000000071][003] {Block}
Generated:
3432 ( 0.00%) : [0x000000000b][001] {CompileUnit}
3351 ( 0.00%) : [0x000000002a][002] 2 {Function}
3234 ( 0.00%) : [0x0000000071][003] {Block}
Alexander Shaposhnikov [Fri, 28 Oct 2022 05:30:19 +0000 (05:30 +0000)]
[clang-tidy] Skip template ctors in modernize-use-equals-default
Skip template ctors in modernize-use-equals-default,
such constructors may be enabled/disabled via SFINAE,
it is not safe to make them "= default".
Test plan: ninja check-all
Differential revision: https://reviews.llvm.org/D136797
Wael Yehia [Thu, 27 Oct 2022 18:37:26 +0000 (14:37 -0400)]
[PGO] Simplify InstrProfilingRuntime.cpp
Differential Revision: https://reviews.llvm.org/D136192
Vitaly Buka [Fri, 28 Oct 2022 04:35:08 +0000 (21:35 -0700)]
[test] Disable the test with asan
There is a memory leak.
See comments in https://reviews.llvm.org/D125783
Ye Luo [Thu, 27 Oct 2022 19:01:18 +0000 (14:01 -0500)]
[DeviceRTL] Fix incremental build
Need both add_custom_command to resolve file-level dependency and add_custom_target to resolve target-level dependency.
From CMake add_custom_command doc:
Do not list the output in more than one independent target that may build in parallel or the two instances of the rule may conflict (instead use the add_custom_target() command to drive the command and make the other targets depend on that one).
${CMAKE_CURRENT_BINARY_DIR}/${bclib_name} is used by multiple targets and thus requires a custom target to avoid racing.
Differential Revision: https://reviews.llvm.org/D136911
LLVM GN Syncbot [Fri, 28 Oct 2022 02:40:48 +0000 (02:40 +0000)]
[gn build] Port
23f02693ec58
Freddy Ye [Fri, 28 Oct 2022 01:43:38 +0000 (09:43 +0800)]
[X86] Add AVX-VNNI-INT8 instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei, skan
Differential Revision: https://reviews.llvm.org/D135938
Valery Pykhtin [Tue, 25 Oct 2022 18:07:13 +0000 (20:07 +0200)]
[AMDGPU] Refactor debug printing routines for GCNRPTracker
Use Printable to enhance syntax, remove duplication, unify.
Reviewed By: arsenm, rampitec
Differential Revision: https://reviews.llvm.org/D136704
LLVM GN Syncbot [Fri, 28 Oct 2022 01:53:34 +0000 (01:53 +0000)]
[gn build] Port
0e720e6adad1
Emilio Cota [Fri, 28 Oct 2022 01:40:33 +0000 (21:40 -0400)]
[mlir][spirv] fix Bazel build of Passes.h
I cannot repro this with CMake, but on Bazel this is failing with
```
error: incomplete result type 'mlir::spirv::TargetEnvAttr' in function definition
[...]
note: in instantiation of member function 'std::function<mlir::spirv::TargetEnvAttr (mlir::spirv::ModuleOp)>::function' requested here
createUnifyAliasedResourcePass(GetTargetEnvFn getTargetEnv = nullptr);
```
Reviewed By: antiagainst
Differential Revision: https://reviews.llvm.org/D136909
Freddy Ye [Fri, 28 Oct 2022 01:11:29 +0000 (09:11 +0800)]
[X86] Add AVX-IFMA instructions.
For more details about these instructions, please refer to the latest ISE document: https://www.intel.com/content/www/us/en/develop/download/intel-architecture-instruction-set-extensions-programming-reference.html
Reviewed By: pengfei, skan
Differential Revision: https://reviews.llvm.org/D135932
Carl Ritson [Fri, 28 Oct 2022 00:26:50 +0000 (09:26 +0900)]
[AMDGPU] Add pseudo wavemode to optimize strict_wqm
Strict WQM does not require a WQM transistion if it occurs within
an existing WQM section.
This occurs heavily in GFX11 pixel shaders with LDS_PARAM_LOAD.
Which leads to unnecessary EXEC mask manipulation.
To avoid these transitions, detect WQM -> Strict WQM -> WQM
and substitute new ENTER_PSEUDO_WM/EXIT_PSEUDO_WM markers instead.
These are treat similarly by WWM register pre-allocation pass,
but do not manipulate EXEC or use registers to save EXEC state.
Reviewed By: piotr
Differential Revision: https://reviews.llvm.org/D136813
Katherine Rasmussen [Thu, 27 Oct 2022 00:15:08 +0000 (17:15 -0700)]
[flang] Add atomic_fetch_xor to list of intrinsics
Add the atomic subroutine, atomic_fetch_xor, to the list of
intrinsic subroutines, add its last dummy argument to a check
for coindexed-object, and update test.
Reviewed By: PeteSteinfeld
Differential Revision: https://reviews.llvm.org/D136804