Joseph Myers [Thu, 29 Apr 2021 20:08:42 +0000 (20:08 +0000)]
Update gcc sv.po.
* sv.po: Update.
Uros Bizjak [Thu, 29 Apr 2021 20:02:00 +0000 (22:02 +0200)]
i386: Optimize carry flag comparisons a bit
In ix86_int_compare, opportunistically swap operands of GTU and LEU comparisons
to emit carry flag comparison, with the expectation that the comparison will
combine to *add<mode>3_carry_0 or *sub<mode>3_carry_0 insn pattern.
Do not use ix86_expand_carry_flag_compare because this function prefers
carry flag comparisons too much - it forces the constants into registers
and/or emits additional arithmetic instructions to convert simple
comparisons into carry flag comparisons - but simply swap operands to
convert GTU and LEU comparisons into GEU and LTU ones.
Also, change the insn predicates of *add<mode>3_carry_0 and
*sub<mode>3_carry_0 insn patterns to allow more combine opportunities
with memory operands.
2021-04-29 Uroš Bizjak <ubizjak@gmail.com>
gcc/
* config/i386/i386-expand.c (ix86_expand_int_compare):
Swap operands of GTU and LEU comparison to emit carry flag comparison.
* config/i386/i386.md (*add<mode>3_carry_0): Change insn
predicate to allow more combine opportunities with memory operands.
(*sub<mode>3_carry_0): Ditto.
Joseph Myers [Thu, 29 Apr 2021 19:50:47 +0000 (19:50 +0000)]
preprocessor: Handle digit separators in #line [PR82359]
As reported in bug 82359, the preprocessor does not allow C++ digit
separators in the line number in a #line directive, despite the
standard syntax for that directive using digit-sequence which allows
digit separators.
There is some confusion in that bug about whether C++ is meant to
allow digit separators there or not, but the last comment there
suggests they are meant to be allowed, and the version of digit
separators accepted for C2X at the March meeting explicitly mentions
digit separators in the #line specification to avoid any ambiguity
there.
This patch thus adds code to handle digit separators in the line
number in #line, as part of the preparation for enabling digit
separators in C2X mode. The code changed does not contain any
conditionals for whether digit separators are supported in the chosen
language version, because that was handled earlier in pp-number lexing
and if they aren't supported they won't appear in the string passed to
that function. It does however make sure not to allow adjacent digit
separators because those are only handled at a later stage of lexing
at present. (Problems with how certain source character sequences
involving digit separators that don't actually match the pp-number
syntax get lexed as a pp-number and only diagnosed later, if at all,
are bugs 83873 and 97604, to be addressed separately.)
Making the change in this location will have the effect of allowing
digit separators in the "# <line-number> <file> <flags>" form of
directive as well as #line; I don't think that's a problem.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
libcpp/
PR preprocessor/82359
* directives.c (strtolinenum): Handle digit separators.
gcc/testsuite/
PR preprocessor/82359
* g++.dg/cpp1y/digit-sep-line.C,
g++.dg/cpp1y/digit-sep-line-neg.C: New tests.
Jason Merrill [Wed, 30 Dec 2020 18:07:57 +0000 (13:07 -0500)]
c++: Add using-declaration testcase
gcc/testsuite/ChangeLog:
* g++.dg/lookup/using-decl1.C: New test.
Jason Merrill [Mon, 25 Jan 2021 22:02:57 +0000 (17:02 -0500)]
c++: Use empty field in constexpr eval.
In discussion of PR98463, Jakub noted that cxx_fold_indirect_ref_1 was
bailing out early for empty bases even when we do have fields for them (in
C++17 mode or later). This corrects that.
gcc/cp/ChangeLog:
* constexpr.c (cxx_fold_indirect_ref_1): Only set *empty_base if we
don't find a field.
Jason Merrill [Fri, 5 Feb 2021 15:36:49 +0000 (10:36 -0500)]
c++: Fix friend attributes [PR51344]
51344 was a problem with calling save_template_attributes twice for the same
friend function: once from do_friend and once from grokmethod. The 2012
patch for the bug avoided creating an infinite loop when this happens, but
it's better to avoid the duplication in the first place. This also restores
the dependent attributes to the beginning of the attribute list, as
originally intended. And then apply_late_template_attributes can avoid
copying the non-dependent attributes.
gcc/cp/ChangeLog:
PR c++/51344
* decl2.c (grokfield): Call cplus_decl_attributes for friend.
(save_template_attributes): Use chainon.
* friend.c (do_friend): Remove attrlist parm.
* cp-tree.h (do_friend): Adjust.
* class.c (add_implicitly_declared_members): Adjust.
* decl.c (grokdeclarator): Adjust.
* pt.c (apply_late_template_attributes): Optimize.
Jason Merrill [Sat, 10 Apr 2021 18:00:15 +0000 (14:00 -0400)]
c++: ICE with anonymous union [PR97974]
While working on the GCC 11 patch, it occurred to me that we could move
the errors about invalid members from finish_struct_anon_r to here, so we
properly get a diagnostic in g++.law/union4.C.
gcc/cp/ChangeLog:
PR c++/97974
* class.c (finish_struct_anon_r): Drop complain parm.
Remove non-field diagnostic.
(finish_struct_anon): Adjust.
* decl.c (fixup_anonymous_aggr): Move non-field diagnostic here.
gcc/testsuite/ChangeLog:
PR c++/97974
* g++.old-deja/g++.law/union4.C: Add expected diagnostic.
Jason Merrill [Wed, 14 Apr 2021 15:24:50 +0000 (11:24 -0400)]
c++: constant expressions are evaluated [PR93314]
My GCC 11 patch for PR93314 turned off cp_unevaluated_operand while
processing an id-expression that names a non-static data member, but the
broader issue is that in general, a constant-expression is evaluated even in
an unevaluated operand.
gcc/cp/ChangeLog:
* cp-tree.h (cp_evaluated): Add reset parm to constructor.
* parser.c (cp_parser_constant_expression): Change
allow_non_constant_p to int. Use cp_evaluated.
(cp_parser_initializer_clause): Pass 2 to allow_non_constant_p.
* semantics.c (finish_id_expression_1): Don't mess with
cp_unevaluated_operand here.
Jason Merrill [Thu, 15 Apr 2021 21:04:24 +0000 (17:04 -0400)]
c++: unset COMPOUND_LITERAL_P [PR100079]
Once a CONSTRUCTOR has been digested and used as an initializer, it no
longer represents a compound literal by itself, so we can clear the flag,
letting us use it consistently to distinguish between digested and
undigested initializer-lists.
gcc/cp/ChangeLog:
* cp-tree.h: Clarify comments.
* pt.c (get_template_parm_object): Add assert.
* semantics.c (finish_compound_literal): Clear TREE_HAS_CONSTRUCTOR.
* tree.c (zero_init_expr_p): Check TREE_HAS_CONSTRUCTOR.
* typeck2.c (store_init_value): Likewise.
Patrick Palka [Thu, 29 Apr 2021 17:43:00 +0000 (13:43 -0400)]
c++: Overeager use of deleted function before ADL [PR68942]
Here, at template definition time, ordinary name lookup for 'foo(t)'
finds only the deleted function, and so we form a CALL_EXPR thereof.
Later at instantiation time, when initially substituting into this
CALL_EXPR with T=N::A, we end up calling mark_used on this deleted
function (since it's the only function in the overload set), triggering
a bogus "use of deleted function error", before we get to augment the
overload set via ADL.
This patch fixes this issue by using the tf_conv flag to disable
mark_used during the initial substitution into the callee of a
CALL_EXPR when KOENIG_P, since at this point we're still figuring out
which functions are candidates.
gcc/cp/ChangeLog:
PR c++/68942
* pt.c (tsubst_copy_and_build) <case CALL_EXPR>: When KOENIG_P,
set tf_conv during the initial substitution into the function.
gcc/testsuite/ChangeLog:
PR c++/68942
* g++.dg/template/koenig12.C: New test.
Marek Polacek [Thu, 29 Apr 2021 17:30:39 +0000 (13:30 -0400)]
c++: Add testcase for already fixed PR [PR94102]
We correctly accept this testcase since r11-1571.
gcc/testsuite/ChangeLog:
PR c++/94102
* g++.dg/cpp1z/class-deduction87.C: New test.
Joseph Myers [Thu, 29 Apr 2021 16:37:41 +0000 (16:37 +0000)]
Update gcc fr.po.
* fr.po: Update.
Richard Sandiford [Thu, 29 Apr 2021 16:24:57 +0000 (17:24 +0100)]
rtl-ssa: Fix -fcompare-debug failure [PR100303]
This patch fixes an oversight in the handling of debug instructions
in rtl-ssa. At the moment (and whether this is a good idea or not
remains to be seen), we maintain a linear RPO sequence of definitions
and non-debug uses. If a register is defined more than once, we use
a degenerate phi to reestablish a previous definition where necessary.
However, debug instructions shouldn't of course affect codegen,
so we can't create a new definition just for them. In those situations
we instead hang the debug use off the real definition (meaning that
debug uses do not follow a linear order wrt definitions). Again,
it remains to be seen whether that's a good idea.
The problem in the PR was that we weren't taking this into account
when increasing (or potentially increasing) the live range of an
existing definition. We'd create the phi even if it would only
be used by debug instructions.
The patch goes for the simple but inelegant approach of passing
a bool to say whether the use is a debug use or not. I imagine
this area will need some tweaking based on experience in future.
gcc/
PR rtl-optimization/100303
* rtl-ssa/accesses.cc (function_info::make_use_available): Take a
boolean that indicates whether the use will only be used in
debug instructions. Treat it in the same way that existing
cross-EBB debug references would be handled if so.
(function_info::make_uses_available): Likewise.
* rtl-ssa/functions.h (function_info::make_uses_available): Update
prototype accordingly.
(function_info::make_uses_available): Likewise.
* fwprop.c (try_fwprop_subst): Update call accordingly.
Jeff Law [Thu, 29 Apr 2021 15:08:56 +0000 (09:08 -0600)]
Fix nios2 build failure
gcc
* config/nios2/nios2-protos.h (nios2_fpu_insn_enabled): Move outside
of RTX_CODE guard.
Uros Bizjak [Thu, 29 Apr 2021 14:43:33 +0000 (16:43 +0200)]
i386: Mark x86 masked load builtins pure [PR100312]
Mark x86 AVX and AVX2 masked load builtins pure to enable dead code
elimination and more appropriate alias analysis.
2021-04-29 Uroš Bizjak <ubizjak@gmail.com>
Richard Biener <rguenther@suse.de>
gcc/
PR target/100312
* config/i386/i386-builtin.def (IX86_BUILTIN_MASKLOADPD)
(IX86_BUILTIN_MASKLOADPS, IX86_BUILTIN_MASKLOADPD256)
(IX86_BUILTIN_MASKLOADPS256, IX86_BUILTIN_MASKLOADD)
(IX86_BUILTIN_MASKLOADQ, IX86_BUILTIN_MASKLOADD256)
(IX86_BUILTIN_MASKLOADQ256): Move from SPECIAL_ARGS
to PURE_ARGS category.
* config/i386/i386-builtins.c (ix86_init_mmx_sse_builtins):
Handle PURE_ARGS category.
* config/i386/i386-expand.c (ix86_expand_builtin): Ditto.
Eric Botcazou [Thu, 29 Apr 2021 12:03:09 +0000 (14:03 +0200)]
Add parallelism support to gcov for MinGW platforms
If you attempt a profiled bootstrap on the MinGW platforms with -jN, N > 1,
it miserably fails because of profile mismatches all over the place, the
reason being that gcov has no support for parallelism on these platforms.
libgcc/
* libgcov.h: For the target, define GCOV_LOCKED_WITH_LOCKING
if __MSVCRT__ and, for the host, define it if HOST_HAS_LK_LOCK.
* libgcov-driver.c: Add directives if GCOV_LOCKED_WITH_LOCKING.
gcc/
* configure.ac: Check for the presence of sys/locking.h header and
for whether _LK_LOCK is supported by _locking.
* configure: Regenerate.
* config.in: Likewise.
* gcov-io.h: Define GCOV_LOCKED_WITH_LOCKING if HOST_HAS_LK_LOCK.
* gcov-io.c (gcov_open): Add support for GCOV_LOCKED_WITH_LOCKING.
* system.h: Include <sys/locking.h> if HAVE_SYS_LOCKING_H.
Uros Bizjak [Thu, 29 Apr 2021 13:24:51 +0000 (15:24 +0200)]
i386: Cleanup comparison predicates.
CCCmode is allowed only with GEU and LTU comparison codes. Also allow
CCGZmode for these two codes. There is no need to check for trivial FP
comparison operator, ix86_fp_compare_code_to_integer will return
UNKNOWN code for unsupported operators.
2021-04-29 Uroš Bizjak <ubizjak@gmail.com>
gcc/
* config/i386/predicates.md (fcmov_comparison_operator):
Do not check for trivial FP comparison operator.
<case GEU, case LTU>: Allow CCGZmode.
<case GTU, case LEU>: Do not allow CCCmode.
(ix86_comparison_operator) <case GTU, case LEU>: Allow only CCmode.
(ix86_carry_flag_operator): Match only LTU and UNLT code.
Do not check for trivial FP comparison operator. Allow CCGZmode.
Tom de Vries [Thu, 1 Oct 2020 16:11:02 +0000 (18:11 +0200)]
[omp, simt] Handle alternative IV
Consider the test-case libgomp.c/pr81778.c added in this commit, with
this core loop (note: CANARY_SIZE set to 0 for simplicity):
...
int s = 1;
#pragma omp target simd
for (int i = N - 1; i > -1; i -= s)
a[i] = 1;
...
which, given that N is 32, sets a[0..31] to 1.
After omp-expand, this looks like:
...
<bb 5> :
simduid.7 = .GOMP_SIMT_ENTER (simduid.7);
.omp_simt.8 = .GOMP_SIMT_ENTER_ALLOC (simduid.7);
D.3193 = -s;
s.9 = s;
D.3204 = .GOMP_SIMT_LANE ();
D.3205 = -s.9;
D.3206 = (int) D.3204;
D.3207 = D.3205 * D.3206;
i = D.3207 + 31;
D.3209 = 0;
D.3210 = -s.9;
D.3211 = D.3210 - i;
D.3210 = -s.9;
D.3212 = D.3211 / D.3210;
D.3213 = (unsigned int) D.3212;
D.3213 = i >= 0 ? D.3213 : 0;
<bb 19> :
if (D.3209 < D.3213)
goto <bb 6>; [87.50%]
else
goto <bb 7>; [12.50%]
<bb 6> :
a[i] = 1;
D.3215 = -s.9;
D.3219 = .GOMP_SIMT_VF ();
D.3216 = (int) D.3219;
D.3220 = D.3215 * D.3216;
i = D.3220 + i;
D.3209 = D.3209 + 1;
goto <bb 19>; [100.00%]
...
On nvptx, the first time bb6 is executed, i is in the 0..31 range (depending
on the lane that is executing) at bb entry.
So we have the following sequence:
- a[0..31] is set to 1
- i is updated to -32..-1
- D.3209 is updated to 1 (being 0 initially)
- bb19 is executed, and if condition (D.3209 < D.3213) == (1 < 32) evaluates
to true
- bb6 is once more executed, which should not happen because all the elements
that needed to be handled were already handled.
- consequently, elements that should not be written are written
- with CANARY_SIZE == 0, we may run into a libgomp error:
...
libgomp: cuCtxSynchronize error: an illegal memory access was encountered
...
and with CANARY_SIZE unmodified, we run into:
...
Expected 0, got 1 at base[-961]
Aborted (core dumped)
...
The cause of this is as follows:
- because the step s is a variable rather than a constant, an alternative
IV (D.3209 in our example) is generated in expand_omp_simd, and the
loop condition is tested in terms of the alternative IV rather than
the original IV (i in our example).
- the SIMT code in expand_omp_simd works by modifying step and initial value.
- The initial value fd->loop.n1 is loaded into a variable n1, which is
modified by the SIMT code and then used there-after.
- The step fd->loop.step is loaded into a variable step, which is modified
by the SIMT code, but afterwards there are uses of both step and
fd->loop.step.
- There are uses of fd->loop.step in the alternative IV handling code,
which should use step instead.
Fix this by introducing an additional variable orig_step, which is not
modified by the SIMT code and replacing all remaining uses of fd->loop.step
by either step or orig_step.
Build on x86_64-linux with nvptx accelerator, tested libgomp.
This fixes for-5.c and for-6.c FAILs I'm currently seeing on a quadro m1200
with driver 450.66.
gcc/ChangeLog:
2020-10-02 Tom de Vries <tdevries@suse.de>
* omp-expand.c (expand_omp_simd): Add step_orig, and replace uses of
fd->loop.step by either step or orig_step.
libgomp/ChangeLog:
2020-10-02 Tom de Vries <tdevries@suse.de>
* testsuite/libgomp.c/pr81778.c: New test.
Eric Botcazou [Thu, 29 Apr 2021 11:34:27 +0000 (13:34 +0200)]
Small housekeeping work in SPARC back-end
gcc/
* config/sparc/sparc.c (gen_load_pcrel_sym): Delete.
(load_got_register): Do the PIC dance here.
(sparc_legitimize_tls_address): Simplify.
(sparc_emit_probe_stack_range): Likewise.
(sparc32_initialize_trampoline): Likewise.
(sparc64_initialize_trampoline): Likewise.
* config/sparc/sparc.md (load_pcrel_sym<P:mode>): Add @ marker.
(probe_stack_range<P:mode>): Likewise.
(flush<P:mode>): Likewise.
(tgd_hi22<P:mode>): Likewise.
(tgd_lo10<P:mode>): Likewise.
(tgd_add<P:mode>): Likewise.
(tgd_call<P:mode>): Likewise.
(tldm_hi22<P:mode>): Likewise.
(tldm_lo10<P:mode>): Likewise.
(tldm_add<P:mode>): Likewise.
(tldm_call<P:mode>): Likewise.
(tldo_hix22<P:mode>): Likewise.
(tldo_lox10<P:mode>): Likewise.
(tldo_add<P:mode>): Likewise.
(tie_hi22<P:mode>): Likewise.
(tie_lo10<P:mode>): Likewise.
(tie_add<P:mode>): Likewise.
(tle_hix22<P:mode>): Likewise.
(tle_lox10<P:mode>): Likewise.
(stack_protect_setsi): Rename to...
(stack_protect_set32): ...this.
(stack_protect_setdi): Rename to...
(stack_protect_set64): ...this.
(stack_protect_set): Adjust calls to above.
(stack_protect_testsi): Rename to...
(stack_protect_test32): ...this.
(stack_protect_testdi): Rename to...
(stack_protect_test64): ...this.
(stack_protect_test): Adjust calls to above.
H.J. Lu [Mon, 10 Jun 2019 16:57:15 +0000 (09:57 -0700)]
Generate offset adjusted operation for op_by_pieces operations
Add an overlap_op_by_pieces_p target hook for op_by_pieces operations
between two areas of memory to generate one offset adjusted operation
in the smallest integer mode for the remaining bytes on the last piece
operation of a memory region to avoid doing more than one smaller
operations.
Pass the RTL information from the previous iteration to m_constfn in
op_by_pieces operation so that builtin_memset_[read|gen]_str can
generate the new RTL from the previous RTL.
Tested on Linux/x86-64.
gcc/
PR middle-end/90773
* builtins.c (builtin_memcpy_read_str): Add a dummy argument.
(builtin_strncpy_read_str): Likewise.
(builtin_memset_read_str): Add an argument for the previous RTL
information and generate the new RTL from the previous RTL info.
(builtin_memset_gen_str): Likewise.
* builtins.h (builtin_strncpy_read_str): Update the prototype.
(builtin_memset_read_str): Likewise.
* expr.c (by_pieces_ninsns): If targetm.overlap_op_by_pieces_p()
returns true, round up size and alignment to the widest integer
mode for maximum size.
(pieces_addr::adjust): Add a pointer to by_pieces_prev argument
and pass it to m_constfn.
(op_by_pieces_d): Add m_push and m_overlap_op_by_pieces.
(op_by_pieces_d::op_by_pieces_d): Add a bool argument to
initialize m_push. Initialize m_overlap_op_by_pieces with
targetm.overlap_op_by_pieces_p ().
(op_by_pieces_d::run): Pass the previous RTL information to
pieces_addr::adjust and generate overlapping operations if
m_overlap_op_by_pieces is true.
(PUSHG_P): New.
(move_by_pieces_d::move_by_pieces_d): Updated for op_by_pieces_d
change.
(store_by_pieces_d::store_by_pieces_d): Updated for op_by_pieces_d
change.
(can_store_by_pieces): Use by_pieces_constfn on constfun.
(store_by_pieces): Use by_pieces_constfn on constfun. Updated
for op_by_pieces_d change.
(clear_by_pieces_1): Add a dummy argument.
(clear_by_pieces): Updated for op_by_pieces_d change.
(compare_by_pieces_d::compare_by_pieces_d): Likewise.
(string_cst_read_str): Add a dummy argument.
* expr.h (by_pieces_constfn): Add a dummy argument.
(by_pieces_prev): New.
* target.def (overlap_op_by_pieces_p): New target hook.
* config/i386/i386.c (TARGET_OVERLAP_OP_BY_PIECES_P): New.
* doc/tm.texi.in: Add TARGET_OVERLAP_OP_BY_PIECES_P.
* doc/tm.texi: Regenerated.
gcc/testsuite/
PR middle-end/90773
* g++.dg/pr90773-1.h: New test.
* g++.dg/pr90773-1a.C: Likewise.
* g++.dg/pr90773-1b.C: Likewise.
* g++.dg/pr90773-1c.C: Likewise.
* g++.dg/pr90773-1d.C: Likewise.
* gcc.target/i386/pr90773-1.c: Likewise.
* gcc.target/i386/pr90773-2.c: Likewise.
* gcc.target/i386/pr90773-3.c: Likewise.
* gcc.target/i386/pr90773-4.c: Likewise.
* gcc.target/i386/pr90773-5.c: Likewise.
* gcc.target/i386/pr90773-6.c: Likewise.
* gcc.target/i386/pr90773-7.c: Likewise.
* gcc.target/i386/pr90773-8.c: Likewise.
* gcc.target/i386/pr90773-9.c: Likewise.
* gcc.target/i386/pr90773-10.c: Likewise.
* gcc.target/i386/pr90773-11.c: Likewise.
* gcc.target/i386/pr90773-12.c: Likewise.
* gcc.target/i386/pr90773-13.c: Likewise.
* gcc.target/i386/pr90773-14.c: Likewise.
Richard Biener [Thu, 29 Apr 2021 09:52:08 +0000 (11:52 +0200)]
tree-optimization/100253 - fix bogus aligned vectorized loads/stores
At some point DR_MISALIGNMENT was supposed to be -1 when the
access was not element aligned. That's obviously not true at this
point so this adjusts both store and load vectorizing to no longer
assume this which in turn allows simplifying the code.
2021-04-29 Richard Biener <rguenther@suse.de>
PR tree-optimization/100253
* tree-vect-stmts.c (vectorizable_load): Do not assume
element alignment when DR_MISALIGNMENT is -1.
(vectorizable_store): Likewise.
* g++.dg/pr100253.C: New testcase.
Jakub Jelinek [Thu, 29 Apr 2021 09:42:08 +0000 (11:42 +0200)]
testsuite: Remove dg-options from pr100305.c [PR100305]
The test FAILs on i?86-linux (due to -Wpsabi warnings). But, on closer
inspection it seems there is another problem, the dg-options in the testcase
means that the test is compiled with -O0 -O, -O1 -O, -O2 -O, -O3 -O, -Os -O
etc. options, so effectively is tested multiple times with the same options.
Fixed by dropping the dg-options line, then we have -w by default and iterate
over all the optimization levels (including the -O).
2021-04-29 Jakub Jelinek <jakub@redhat.com>
PR target/100305
* gcc.c-torture/compile/pr100305.c: Remove dg-options. Add PR line.
Jakub Jelinek [Thu, 29 Apr 2021 09:34:50 +0000 (11:34 +0200)]
aarch64: Fix ICE in aarch64_add_offset_1_temporaries [PR100302]
In PR94121 I've changed aarch64_add_offset_1 to use absu_hwi instead of
abs_hwi because offset can be HOST_WIDE_INT_MIN. As can be seen with
the testcase below, aarch64_add_offset_1_temporaries suffers from the same
problem and should be in sync with aarch64_add_offset_1, i.e. for
HOST_WIDE_INT_MIN it needs a temporary.
2021-04-29 Jakub Jelinek <jakub@redhat.com>
PR target/100302
* config/aarch64/aarch64.c (aarch64_add_offset_1_temporaries): Use
absu_hwi instead of abs_hwi.
* gcc.target/aarch64/sve/pr100302.c: New test.
Jakub Jelinek [Thu, 29 Apr 2021 09:11:37 +0000 (11:11 +0200)]
c++: Fix up detach clause vs. data-sharing clause checking [PR100319]
The standard says that "The event-handle will be considered as if it
was specified on a firstprivate clause." which means that it can't
be explicitly specified in some other data-sharing clause.
The checking is implemented correctly for C, but for C++ when detach_seen
is true (i.e. the construct had detach clause) we were comparing
OMP_CLAUSE_DECL (c) with t, which was previously initialized to
OMP_CLAUSE_DECL (c), which means it complained about any explicit
data-sharing clause on the same construct with a detach clause.
Fixed by remembering the detach clause in detach_seen (instead of a boolean
flag) and comparing against its OMP_CLAUSE_DECL.
2021-04-29 Jakub Jelinek <jakub@redhat.com>
PR c++/100319
* semantics.c (finish_omp_clauses): Fix up check that variable
mentioned in detach clause doesn't appear in data-sharing clauses.
* c-c++-common/gomp/task-detach-3.c: New test.
Richard Biener [Thu, 29 Apr 2021 06:32:00 +0000 (08:32 +0200)]
middle-end/38474 - speedup PTA constraint solving
In testcases like PR38474 and PR99912 we're seeing very slow
PTA solving. One can observe an excessive amount of forwarding,
mostly during sd constraint solving. The way we solve the graph
does not avoid forwarding the same bits through multiple paths,
and especially when such alternate path involves ESCAPED as
intermediate this causes the ESCAPED solution to be expanded
in receivers.
The following adds heuristic to add_graph_edge which adds
forwarding edges but also guards the initial solution forwarding
(which is the expensive part) to detect the case of ESCAPED
receiving the same set and the destination already containing
ESCAPED.
This speeds up the PTA solving process by more than 50%.
2021-04-29 Richard Biener <rguenther@suse.de>
PR middle-end/38474
* tree-ssa-structalias.c (add_graph_edge): Avoid direct
forwarding when indirect forwarding through ESCAPED
alread happens.
Eric Botcazou [Mon, 21 Dec 2020 15:22:53 +0000 (16:22 +0100)]
[Ada] Eliminate useless 128-bit overflow check for conversion
gcc/ada/
* exp_attr.adb (Expand_N_Attribute_Reference)
<Attribute_Max_Size_In_Storage_Elements>: Apply the checks for
universal integer contexts only in the default case.
* exp_ch4.adb (Get_Size_For_Range): Move to library level.
(Expand_N_Type_Conversion): If the operand has Universal_Integer
type and the conversion requires an overflow check, try to do an
intermediate conversion to a narrower type.
Arnaud Charlet [Tue, 15 Dec 2020 20:36:54 +0000 (15:36 -0500)]
[Ada] Self reference access discriminant
gcc/ada/
* sem_ch3.adb (Check_Anonymous_Access_Component): Factor out
core processing of Check_Anonymous_Access_Components.
(Check_Anonymous_Access_Components): Call
Check_Anonymous_Access_Component.
(Process_Discriminants): Call Check_Anonymous_Access_Component.
* freeze.adb (Freeze_Record_Type): Code cleanups and add more tree
checking to handle changes in sem_ch3.adb.
* sem_ch8.adb (Find_Type): Remove special case for access
discriminant in task types, these are now supported.
Eric Botcazou [Sat, 19 Dec 2020 10:55:29 +0000 (11:55 +0100)]
[Ada] Fix interaction of 128-bit integer types and -gnato2 mode
gcc/ada/
* exp_ch4.adb (Expand_Compare_Minimize_Eliminate_Overflow): Remove
entry condition.
(Expand_N_In): Call Minimized_Eliminated_Overflow_Check on the left
operand before doing the special overflow expansion.
(Expand_N_Op_Eq): Likewise.
(Expand_N_Op_Ge): Likewise.
(Expand_N_Op_Gt): Likewise.
(Expand_N_Op_Le): Likewise.
(Expand_N_Op_Lt): Likewise.
(Expand_N_Op_Ne): Likewise.
(Minimized_Eliminated_Overflow_Check): Return False for Minimized
if the size of the type is greater than that of Long_Long_Integer.
Arnaud Charlet [Thu, 17 Dec 2020 17:23:08 +0000 (18:23 +0100)]
[Ada] Tree inconsistency between -O0 and -O1
gcc/ada/
* exp_ch5.adb (Expand_N_If_Statement): Only perform the
simplification on return True/False for internal nodes when
-fpreserve-control-flow is not set.
Eric Botcazou [Sat, 19 Dec 2020 10:46:06 +0000 (11:46 +0100)]
[Ada] Change rounding mode of 'Machine for static floating point
gcc/ada/
* sem_attr.adb (Eval_Attribute) <Attribute_Machine>: Use
Round_Even instead of Round in the call to the Machine routine.
Bob Duff [Fri, 18 Dec 2020 19:59:45 +0000 (14:59 -0500)]
[Ada] Error on T'Reduce of when T is not a container
gcc/ada/
* sem_attr.adb (Analyze_Attribute): Change "$" to "&".
Otherwise, Errout will trip over an uninitialized (invalid)
variable (Error_Msg_Unit_1).
Eric Botcazou [Fri, 18 Dec 2020 17:49:31 +0000 (18:49 +0100)]
[Ada] Fix minor issue in Scan_Decimal_Digits
gcc/ada/
* libgnat/s-valuer.adb (Scan_Decimal_Digits): Set Extra to zero
when the precision limit is reached by means of trailing zeros
and prevent it from being overwritten later.
Yannick Moy [Thu, 17 Dec 2020 08:56:16 +0000 (09:56 +0100)]
[Ada] Add colors to GNATprove messages output to a terminal
gcc/ada/
* errout.adb (Output_Messages): Insert SGR strings where needed.
* erroutc.adb (Output_Message_Txt): Insert SGR strings where
needed in the text of the message itself.
(Output_Msg_Text): Allow for style message not to start
with (style).
* erroutc.ads: Add new constants and functions to control colors
in messages output to the terminal. Add variable Use_SGR_Control
that should be set to True for using SGR color control strings.
Yannick Moy [Wed, 16 Dec 2020 13:37:22 +0000 (14:37 +0100)]
[Ada] Fix evaluation of expressions in inlined code
gcc/ada/
* sem_eval.adb (Check_Non_Static_Context_For_Overflow): Apply
compile-time checking for overflows in non-static contexts
including inlined code.
(Eval_Arithmetic_Op): Use the new procedure.
(Eval_Unary_Op, Eval_Op_Expon): Add call to the new procedure.
Justin Squirek [Wed, 16 Dec 2020 07:00:56 +0000 (02:00 -0500)]
[Ada] Missing access-to-discriminated conversion check
gcc/ada/
* checks.adb (Apply_Type_Conversion_Checks): Move out constraint
check generation, and add case for general access types with
constraints.
(Make_Discriminant_Constraint_Check): Created to centralize
generation of constraint checks for stored discriminants.
Eric Botcazou [Wed, 16 Dec 2020 14:18:13 +0000 (15:18 +0100)]
[Ada] Fix internal consistency error with Duration and 32-bit target file
gcc/ada/
* gnat1drv.adb (Adjust_Global_Switches): Force a 32-bit Duration
type if the maximum integer size is lower than 64 bits.
Arnaud Charlet [Wed, 16 Dec 2020 08:19:40 +0000 (03:19 -0500)]
[Ada] Clean up Makefile.rtl
gcc/ada/
* Makefile.rtl (ADA_EXCLUDE_SRCS): Remove unused files.
(ADA_INCLUDE_SRCS): Remove libgnat/system.ads
Arnaud Charlet [Thu, 10 Dec 2020 13:19:55 +0000 (08:19 -0500)]
[Ada] Bad handling of array sliding in aggregate
gcc/ada/
* exp_aggr.adb (Collect_Initialization_Statements): Removed.
(Convert_Aggr_In_Object_Decl, Expand_Array_Aggregate): Fix
creation and insertion of Initialization_Statements. Do not set
Initialization_Statements when a transient scope is involved.
Move processing of Array_Slice here. Ensure that an object with
an Array_Slice call gets its array component initialized. Add
comments.
* exp_ch7.adb: Update comments.
(Store_Actions_In_Scope): Deal properly with an empty list which
might now be generated by Convert_Aggr_In_Object_Decl.
* exp_ch3.adb: Update comments.
(Expand_N_Object_Declaration): Remove processing of Array_Slice.
Arnaud Charlet [Mon, 14 Dec 2020 10:10:21 +0000 (05:10 -0500)]
[Ada] Ada 2020 AI12-0401: Renaming of qualified expression of variable
gcc/ada/
* sem_ch8.adb (Analyze_Object_Renaming): Update check for
AI12-0401.
Patrick Bernardi [Wed, 16 Dec 2020 01:44:57 +0000 (20:44 -0500)]
[Ada] System.Storage_Elements: cleanup comment
gcc/ada/
* libgnat/s-stoele.ads (Storage_Offset): Cleanup comment.
Gary Dismukes [Mon, 14 Dec 2020 20:31:52 +0000 (15:31 -0500)]
[Ada] SPARK needs DIC expressions within partial DIC procedures for abstract types
gcc/ada/
* exp_util.adb (Add_Own_DIC): Relax the suppression of adding a
DIC Check pragma that's done for abstract types by still doing
it in the case where GNATprove_Mode is set.
Joel Brobecker [Tue, 15 Dec 2020 13:58:10 +0000 (08:58 -0500)]
[Ada] Makefile.rtl:ADA_EXCLUDE_SRCS update after some System.GCC unit renames
gcc/ada/
* Makefile.rtl (ADA_EXCLUDE_SRCS): Remove s-gcc.adb, s-gcc.ads,
s-gccdiv.adb, s-gccdiv.ads, s-gccshi.adb and s-gccshi.ads.
Piotr Trojanek [Mon, 14 Dec 2020 13:49:02 +0000 (14:49 +0100)]
[Ada] Refine type of a local size variable
gcc/ada/
* layout.adb (Layout_Type): Refine type of a local variable with
the required size of object from Int to Pos (it is initialized
with 8 and only multiplied by 2); fix unbalanced parens in
comment.
Eric Botcazou [Mon, 14 Dec 2020 22:58:59 +0000 (23:58 +0100)]
[Ada] Couple of minor tweaks to Eval_Fat.Succ
gcc/ada/
* eval_fat.adb (Succ): Use Ureal_Half in a couple of places.
Ed Schonberg [Mon, 14 Dec 2020 18:54:28 +0000 (13:54 -0500)]
[Ada] Crash on predicated constrained out_parameter
gcc/ada/
* sem_util.adb (Build_Constrained_Itype): Inhibit the generation
of predicate functions for this Itype, which is created for an
aggregate of a discriminated type. The object to which the
aggregate is assigned, e.g a writable actual parameter, will
apply the predicates if any are inherited from the base type.
Piotr Trojanek [Sat, 12 Dec 2020 23:01:24 +0000 (00:01 +0100)]
[Ada] Fix handling of visibility when categorization from pragmas
gcc/ada/
* sem_cat.adb (Set_Categorization_From_Pragmas): Remove special
case for generic child units; remove optimization for empty list
of pragmas; properly restore visibility.
Piotr Trojanek [Sat, 12 Dec 2020 22:59:34 +0000 (23:59 +0100)]
[Ada] Extend Find_Related_Context to deal with child instances
gcc/ada/
* sem_elab.adb (Process_SPARK_Instantiation): Fix typo in
comment.
* sem_prag.adb (Find_Related_Context): Add missing reference to
No_Caching in the comment; handle pragmas on compilation units.
Piotr Trojanek [Mon, 14 Dec 2020 14:25:18 +0000 (15:25 +0100)]
[Ada] Consistent wording for permissible-vs-allowed prefix
gcc/ada/
* doc/gnat_rm/implementation_defined_attributes.rst: Change all
occurrences of "permissible prefix" to "allowed prefix", for
consistency.
* gnat_rm.texi: Regenerate.
Eric Botcazou [Mon, 14 Dec 2020 14:58:49 +0000 (15:58 +0100)]
[Ada] Fix static computation of 'Succ for floating point without denormals
gcc/ada/
* eval_fat.adb (Succ): Add a special case for zero if the type does
not support denormalized numbers. Always use the canonical formula
in other cases and add commentary throughout the function.
Eric Botcazou [Sun, 13 Dec 2020 22:32:29 +0000 (23:32 +0100)]
[Ada] Reimplement Pred and Succ atttributes for floating-point types
gcc/ada/
* libgnat/s-fatgen.adb: Remove with clause for Interfaces and
use type clauses for Interfaces.Unsigned_{16,32,64}.
(Small16): Remove.
(Small32): Likewise
(Small64): Likewise.
(Small80): Likewise.
(Tiny16): Likewise.
(Tiny32): Likewise.
(Tiny64): Likewise.
(Tiny80): Likewise.
(Siz): Always use 16.
(NR): New constant.
(Rep_Last): Use it in the computation.
(Exp_Factor): Remove special case for 80-bit.
(Sign_Mask): Likewise.
(Finite_Succ): New function implementing the Succ attribute for
finite numbers.
(Pred): Rewrite in terms of Finite_Succ.
(Succ): Likewise.
Arnaud Charlet [Mon, 14 Dec 2020 10:25:13 +0000 (05:25 -0500)]
[Ada] Remove obsolete comment
gcc/ada/
* debug_a.adb (Debug_Output_Astring): Remove obsolete comment.
Arnaud Charlet [Sun, 13 Dec 2020 17:58:26 +0000 (12:58 -0500)]
[Ada] Spurious error on 'Image
gcc/ada/
* sem_attr.adb (Check_Image_Type): Protect against empty
Image_Type.
Arnaud Charlet [Fri, 11 Dec 2020 08:57:08 +0000 (03:57 -0500)]
[Ada] AI12-0407: Fixups on Big_Integers and Big_Reals
gcc/ada/
* libgnat/a-nbnbin.ads (From_Universal_Image): New.
(Big_Integer): Update definition.
* libgnat/a-nbnbre.ads, libgnat/a-nbnbre.adb
(From_Universal_Image): New.
(From_String): Remove alternate body, replaced by
From_Universal_Image.
(Big_Real): Update definition.
Gary Dismukes [Fri, 11 Dec 2020 06:01:11 +0000 (01:01 -0500)]
[Ada] Warning for 'Class applied to untagged incomplete type
gcc/ada/
* sem_ch8.adb (Find_Type): Check the No_Obsolescent_Features
restriction for 'Class applied to an untagged incomplete
type (when Ada_Version >= Ada_2005). Remove disabling of the
warning message for such usage, along with the ??? comment,
which no longer applies (because the -gnatg switch no longer
sets Warn_On_Obsolescent_Feature).
Yannick Moy [Fri, 11 Dec 2020 10:32:07 +0000 (11:32 +0100)]
[Ada] Fixes in the use of spans for error locations
gcc/ada/
* errout.adb (Error_Msg_NEL): Extract span from node.
(First_And_Last_Nodes): Use spans for subtype indications and
attribute definition clauses.
(Write_Source_Code_Lines): Fix for tabulation characters. Change
output for large spans to skip intermediate lines.
* sem_case.adb (Check_Choice_Set): Report duplicate choice on
the Original_Node for the case.
(Generic_Check_Choices): Set the Original_Node for the rewritten
case, so that the subtree used in spans has the correct
locations.
Tom de Vries [Wed, 28 Apr 2021 14:00:01 +0000 (16:00 +0200)]
[omp, simt] Fix expand_GOMP_SIMT_*
When running the test-case included in this patch using an
nvptx accelerator, it fails in execution.
The problem is that the expansion of GOMP_SIMT_XCHG_BFLY is optimized away
during pass_jump as "trivially dead insns".
This is caused by this code in expand_GOMP_SIMT_XCHG_BFLY:
...
class expand_operand ops[3];
create_output_operand (&ops[0], target, mode);
...
expand_insn (targetm.code_for_omp_simt_xchg_bfly, 3, ops);
...
which doesn't guarantee that target is assigned to by the expanded insn.
F.i., if target is:
...
(gdb) call debug_rtx ( target )
(subreg/s/u:QI (reg:SI 40 [ _61 ]) 0)
...
then after expand_insn, we have:
...
(gdb) call debug_rtx ( ops[0].value )
(reg:QI 57)
...
See commit
3af3bec2e4d "internal-fn: Avoid dropping the lhs of some
calls [PR94941]" for a similar problem.
Fix this in the same way, by adding:
...
if (!rtx_equal_p (target, ops[0].value))
emit_move_insn (target, ops[0].value);
...
where applicable in the expand_GOMP_SIMT_* functions.
Tested libgomp on x86_64 with nvptx accelerator.
gcc/ChangeLog:
2021-04-28 Tom de Vries <tdevries@suse.de>
PR target/100232
* internal-fn.c (expand_GOMP_SIMT_ENTER_ALLOC)
(expand_GOMP_SIMT_LAST_LANE, expand_GOMP_SIMT_ORDERED_PRED)
(expand_GOMP_SIMT_VOTE_ANY, expand_GOMP_SIMT_XCHG_BFLY)
(expand_GOMP_SIMT_XCHG_IDX): Ensure target is assigned to.
Richard Biener [Tue, 27 Apr 2021 12:32:27 +0000 (14:32 +0200)]
tree-optimization/99912 - delete trivially dead stmts during DSE
DSE performs a backwards walk over stmts removing stores but it
leaves removing resulting dead SSA defs to later passes. This
eats into its own alias walking budget if the removed stores kept
loads live. The following patch adds removal of trivially dead
SSA defs which helps in this situation and reduces the amount of
garbage followup passes need to deal with.
2021-04-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/99912
* tree-ssa-dse.c (dse_dom_walker::m_need_cfg_cleanup): New.
(dse_dom_walker::todo): Likewise.
(dse_dom_walker::dse_optimize_stmt): Move VDEF check to the
caller.
(dse_dom_walker::before_dom_children): Remove trivially
dead SSA defs and schedule CFG cleanup if we removed all
PHIs in a block.
(pass_dse::execute): Get TODO as computed by the DOM walker
and return it. Wipe dominator info earlier.
* gcc.dg/pr95580.c: Disable DSE.
* gcc.dg/Wrestrict-8.c: Place a use after each memcpy.
* c-c++-common/ubsan/overflow-negate-3.c: Make asms volatile
to prevent them from being removed.
* c-c++-common/ubsan/overflow-sub-4.c: Likewise.
Richard Biener [Wed, 28 Apr 2021 07:34:03 +0000 (09:34 +0200)]
ipa/100308 - properly update the callgraph when pruning EH in IPA CP
This makes sure to fall into the delete_unreachable_blocks_update_callgraph
handling to remove blocks becoming unreachable when removing EH edges
by tracking blocks to need EH cleanup and doing that after releasing
dominance info.
This fixes an ICE seen with gfortran.dg/gomp/pr88933.f90 when enhancing
DSE.
2021-04-28 Richard Biener <rguenther@suse.de>
PR ipa/100308
* ipa-prop.c (ipcp_modif_dom_walker::before_dom_children):
Track blocks to cleanup EH in new m_need_eh_cleanup.
(ipcp_modif_dom_walker::cleanup_eh): New.
(ipcp_transform_function): Release dominator info before
doing EH cleanup.
Martin Sebor [Thu, 29 Apr 2021 01:11:34 +0000 (19:11 -0600)]
PR middle-end/100250 - ICE related to -Wmaybe-uninitialized
gcc/ChangeLog:
PR middle-end/100250
* attribs.c (attr_access::array_as_string): Avoid dereferencing
a pointer when it's null.
gcc/testsuite/ChangeLog:
PR middle-end/100250
* gcc.dg/uninit-pr100250.c: New test.
Martin Sebor [Thu, 29 Apr 2021 01:01:40 +0000 (19:01 -0600)]
Move pass free_lang_data to its own file.
gcc/ChangeLog:
* Makefile.in (OBJS): Add ipa-free-lang-data.o.
* ipa-free-lang-data.cc: New file.
* tree.c: Move pass free_lang_data to file above.
(build_array_type_1): Declare extern.
* tree.h (build_array_type_1): Declare.
Joseph Myers [Thu, 29 Apr 2021 00:50:35 +0000 (00:50 +0000)]
c: C2x changes to function type compatibility
WG14 N2432, the C2x removal of old-style function definitions, also
changed the function type compatibility rules so that an unprototyped
declaration can be compatible with a non-variadic prototyped
declaration even if some function arguments are changed by the default
argument promotions. I missed that change in the initial
implementation for GCC of the rest of the N2432 changes, but
discussion on the WG14 reflector in February suggests that this is
indeed an intended change. Implement this in the C front end.
Note that while this may be of use in some cases for use of pointers
to unprototyped function types as a kind of generic function pointer,
it's *not* possible to call such a function without a prototype
visible, without getting runtime undefined behavior from the
(promoted) type used in the call being incompatible with the
(unpromoted) type in the prototype.
Note also that GCC has a longstanding extension to allow compatibility
of such a prototype with an old-style definition specifying the same
type as in the prototype (which is not valid in ISO C, before
old-style definitions were removed in C2x).
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
gcc/c/
* c-typeck.c (function_types_compatible_p): For C2X, treat
unprototyped function as compatible with non-variadic prototyped
function even if some argument types are changed by the default
argument promotions.
gcc/testsuite/
* gcc.dg/c11-unproto-1.c, gcc.dg/c11-unproto-2.c,
gcc.dg/c2x-unproto-1.c, gcc.dg/c2x-unproto-2.c: New tests.
GCC Administrator [Thu, 29 Apr 2021 00:17:01 +0000 (00:17 +0000)]
Daily bump.
Tobias Burnus [Wed, 28 Apr 2021 20:35:06 +0000 (22:35 +0200)]
Fortran/OpenMP: Fix var-list expr parsing with array/dt
gcc/fortran/ChangeLog:
* openmp.c (gfc_match_omp_variable_list): Gobble whitespace before
checking whether a '%' or parenthesis-open follows as next character.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/map-5.f90: New test.
Jonathan Wright [Thu, 22 Apr 2021 14:04:19 +0000 (15:04 +0100)]
aarch64: Remove unspecs from [su]qmovn RTL pattern
Saturating truncation can be expressed using the RTL expressions
ss_truncate and us_truncate. This patch changes the implementation
of the vqmovn_* intrinsics to use these RTL expressions rather than
a pair of unspecs. The redundant unspecs are removed along with their
code iterator.
gcc/ChangeLog:
2021-04-12 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Modify comment to
make consistent with updated RTL pattern.
* config/aarch64/aarch64-simd.md (aarch64_<sur>qmovn<mode>):
Implement using ss_truncate and us_truncate rather than
unspecs.
* config/aarch64/iterators.md: Remove redundant unspecs and
iterator: UNSPEC_[SU]QXTN and SUQMOVN respectively.
Jonathan Wright [Thu, 18 Mar 2021 16:23:50 +0000 (16:23 +0000)]
aarch64: Update attributes of arm_acle.h intrinsics
Update the attributes of all intrinsics defined in arm_acle.h to be
consistent with the attributes of the intrinsics defined in
arm_neon.h. Specifically, this means updating the attributes from:
__extension__ static __inline <type>
__attribute__ ((__always_inline__))
to:
__extension__ extern __inline <type>
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
gcc/ChangeLog:
2021-03-18 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/arm_acle.h (__attribute__): Make intrinsic
attributes consistent with those defined in arm_neon.h.
Jonathan Wright [Thu, 18 Mar 2021 12:14:48 +0000 (12:14 +0000)]
aarch64: Update attributes of arm_fp16.h intrinsics
Update the attributes of all intrinsics defined in arm_fp16.h to be
consistent with the attributes of the intrinsics defined in
arm_neon.h. Specifically, this means updating the attributes from:
__extension__ static __inline <type>
__attribute__ ((__always_inline__))
to:
__extension__ extern __inline <type>
__attribute__ ((__always_inline__, __gnu_inline__, __artificial__))
gcc/ChangeLog:
2021-03-18 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/arm_fp16.h (__attribute__): Make intrinsic
attributes consistent with those defined in arm_neon.h.
Jonathan Wright [Thu, 18 Feb 2021 23:27:00 +0000 (23:27 +0000)]
aarch64: Use RTL builtins for vcvtx intrinsics
Rewrite vcvtx Neon intrinsics to use RTL builtins rather than inline
assembly code, allowing for better scheduling and optimization.
gcc/ChangeLog:
2021-02-18 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add
float_trunc_rodd builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_float_trunc_rodd_df):
Define.
(aarch64_float_trunc_rodd_lo_v2sf): Define.
(aarch64_float_trunc_rodd_hi_v4sf_le): Define.
(aarch64_float_trunc_rodd_hi_v4sf_be): Define.
(aarch64_float_trunc_rodd_hi_v4sf): Define.
* config/aarch64/arm_neon.h (vcvtx_f32_f64): Use RTL builtin
instead of inline asm.
(vcvtx_high_f32_f64): Likewise.
(vcvtxd_f32_f64): Likewise.
* config/aarch64/iterators.md: Add FCVTXN unspec.
Jonathan Wright [Fri, 12 Feb 2021 15:37:05 +0000 (15:37 +0000)]
aarch64: Use RTL builtins for v[q]tbx intrinsics
Rewrite v[q]tbx Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-02-12 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add tbx1 builtin
generator macros.
* config/aarch64/aarch64-simd.md (aarch64_tbx1<mode>):
Define.
* config/aarch64/arm_neon.h (vqtbx1_s8): USE RTL builtin
instead of inline asm.
(vqtbx1_u8): Likewise.
(vqtbx1_p8): Likewise.
(vqtbx1q_s8): Likewise.
(vqtbx1q_u8): Likewise.
(vqtbx1q_p8): Likewise.
(vtbx2_s8): Likewise.
(vtbx2_u8): Likewise.
(vtbx2_p8): Likewise.
Jonathan Wright [Fri, 12 Feb 2021 12:13:27 +0000 (12:13 +0000)]
aarch64: Use RTL builtins for v[q]tbl intrinsics
Rewrite v[q]tbl Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-02-12 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add tbl1 builtin
generator macros.
* config/aarch64/arm_neon.h (vqtbl1_p8): Use RTL builtin
instead of inline asm.
(vqtbl1_s8): Likewise.
(vqtbl1_u8): Likewise.
(vqtbl1q_p8): Likewise.
(vqtbl1q_s8): Likewise.
(vqtbl1q_u8): Likewise.
(vtbl1_s8): Likewise.
(vtbl1_u8): Likewise.
(vtbl1_p8): Likewise.
(vtbl2_s8): Likewise.
(vtbl2_u8): Likewise.
(vtbl2_p8): Likewise.
Jonathan Wright [Wed, 10 Feb 2021 13:02:24 +0000 (13:02 +0000)]
aarch64: Use RTL builtins for polynomial vsri[q]_n intrinsics
Rewrite vsri[q]_n_p* Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-02-10 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add polynomial
ssri_n buitin generator macro.
* config/aarch64/arm_neon.h (vsri_n_p8): Use RTL builtin
instead of inline asm.
(vsri_n_p16): Likewise.
(vsri_n_p64): Likewise.
(vsriq_n_p8): Likewise.
(vsriq_n_p16): Likewise.
(vsriq_n_p64): Likewise.
Jonathan Wright [Wed, 10 Feb 2021 11:39:39 +0000 (11:39 +0000)]
aarch64: Use RTL builtins for polynomial vsli[q]_n intrinsics
Rewrite vsli[q]_n_p* Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-02-10 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Use VALLP mode
iterator for polynomial ssli_n builtin generator macro.
* config/aarch64/arm_neon.h (vsli_n_p8): Use RTL builtin
instead of inline asm.
(vsli_n_p16): Likewise.
(vsliq_n_p8): Likewise.
(vsliq_n_p16): Likewise.
* config/aarch64/iterators.md: Define VALLP mode iterator.
Jonathan Wright [Tue, 9 Feb 2021 01:14:00 +0000 (01:14 +0000)]
aarch64: Use RTL builtins for vpadal_[su]32 intrinsics
Rewrite vpadal_[su]32 Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-02-09 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Use VDQV_L
iterator to generate [su]adalp RTL builtins.
* config/aarch64/aarch64-simd.md: Use VDQV_L iterator in
[su]adalp RTL pattern.
* config/aarch64/arm_neon.h (vpadal_s32): Use RTL builtin
instead of inline asm.
(vpadal_u32): Likewise.
Jonathan Wright [Mon, 8 Feb 2021 21:23:48 +0000 (21:23 +0000)]
aarch64: Use RTL builtins for [su]paddl[q] intrinsics
Rewrite [su]paddl[q] Neon intrinsics to use RTL builtins rather than
inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-02-08 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add [su]addlp
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_<su>addlp<mode>):
Define.
* config/aarch64/arm_neon.h (vpaddl_s8): Use RTL builtin
instead of inline asm.
(vpaddl_s16): Likewise.
(vpaddl_s32): Likewise.
(vpaddl_u8): Likewise.
(vpaddl_u16): Likewise.
(vpaddl_u32): Likewise.
(vpaddlq_s8): Likewise.
(vpaddlq_s16): Likewise.
(vpaddlq_s32): Likewise.
(vpaddlq_u8): Likewise.
(vpaddlq_u16): Likewise.
(vpaddlq_u32): Liwewise.
* config/aarch64/iterators.md: Define [SU]ADDLP unspecs with
appropriate attributes.
Jonathan Wright [Mon, 8 Feb 2021 16:50:30 +0000 (16:50 +0000)]
aarch64: Use RTL builtins for vpaddq intrinsics
Rewrite vpaddq Neon intrinsics to use RTL builtins rather than inline
assembly code, allowing for better scheduling and optimization.
gcc/ChangeLog:
2021-02-08 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Use VDQ_I iterator
for aarch64_addp<mode> builtin macro generator.
* config/aarch64/aarch64-simd.md: Use VDQ_I iterator in
aarch64_addp<mode> RTL pattern.
* config/aarch64/arm_neon.h (vpaddq_s8): Use RTL builtin
instead of inline asm.
(vpaddq_s16): Likewise.
(vpaddq_s32): Likewise.
(vpaddq_s64): Likewise.
(vpaddq_u8): Likewise.
(vpaddq_u16): Likewise.
(vpaddq_u32): Likewise.
(vpaddq_u64): Likewise.
Jonathan Wright [Mon, 8 Feb 2021 11:37:29 +0000 (11:37 +0000)]
aarch64: Use RTL builtins for vq[r]dmulh[q]_n intrinsics
Rewrite vq[r]dmulh[q]_n Neon intrinsics to use RTL builtins rather
than inline assembly code, allowing for better scheduling and
optimization.
gcc/ChangeLog:
2021-02-08 Jonathan Wright <jonathan.wright@arm.com>
* config/aarch64/aarch64-simd-builtins.def: Add sq[r]dmulh_n
builtin generator macros.
* config/aarch64/aarch64-simd.md (aarch64_sq<r>dmulh_n<mode>):
Define.
* config/aarch64/arm_neon.h (vqdmulh_n_s16): Use RTL builtin
instead of inline asm.
(vqdmulh_n_s32): Likewise.
(vqdmulhq_n_s16): Likewise.
(vqdmulhq_n_s32): Likewise.
(vqrdmulh_n_s16): Likewise.
(vqrdmulh_n_s32): Likewise.
(vqrdmulhq_n_s16): Likewise.
(vqrdmulhq_n_s32): Likewise.
Joseph Myers [Wed, 28 Apr 2021 19:56:03 +0000 (19:56 +0000)]
Update gcc .po files.
* be.po, da.po, de.po, el.po, es.po, fi.po, fr.po, hr.po, id.po,
ja.po, nl.po, ru.po, sr.po, sv.po, tr.po, uk.po, vi.po, zh_CN.po,
zh_TW.po: Update.
Patrick McGehearty [Wed, 28 Apr 2021 19:14:48 +0000 (19:14 +0000)]
Practical improvement to libgcc complex divide
Correctness and performance test programs used during development of
this project may be found in the attachment to:
https://www.mail-archive.com/gcc-patches@gcc.gnu.org/msg254210.html
Summary of Purpose
This patch to libgcc/libgcc2.c __divdc3 provides an
opportunity to gain important improvements to the quality of answers
for the default complex divide routine (half, float, double, extended,
long double precisions) when dealing with very large or very small exponents.
The current code correctly implements Smith's method (1962) [2]
further modified by c99's requirements for dealing with NaN (not a
number) results. When working with input values where the exponents
are greater than *_MAX_EXP/2 or less than -(*_MAX_EXP)/2, results are
substantially different from the answers provided by quad precision
more than 1% of the time. This error rate may be unacceptable for many
applications that cannot a priori restrict their computations to the
safe range. The proposed method reduces the frequency of
"substantially different" answers by more than 99% for double
precision at a modest cost of performance.
Differences between current gcc methods and the new method will be
described. Then accuracy and performance differences will be discussed.
Background
This project started with an investigation related to
https://gcc.gnu.org/bugzilla/show_bug.cgi?id=59714. Study of Beebe[1]
provided an overview of past and recent practice for computing complex
divide. The current glibc implementation is based on Robert Smith's
algorithm [2] from 1962. A google search found the paper by Baudin
and Smith [3] (same Robert Smith) published in 2012. Elen Kalda's
proposed patch [4] is based on that paper.
I developed two sets of test data by randomly distributing values over
a restricted range and the full range of input values. The current
complex divide handled the restricted range well enough, but failed on
the full range more than 1% of the time. Baudin and Smith's primary
test for "ratio" equals zero reduced the cases with 16 or more error
bits by a factor of 5, but still left too many flawed answers. Adding
debug print out to cases with substantial errors allowed me to see the
intermediate calculations for test values that failed. I noted that
for many of the failures, "ratio" was a subnormal. Changing the
"ratio" test from check for zero to check for subnormal reduced the 16
bit error rate by another factor of 12. This single modified test
provides the greatest benefit for the least cost, but the percentage
of cases with greater than 16 bit errors (double precision data) is
still greater than 0.027% (2.7 in 10,000).
Continued examination of remaining errors and their intermediate
computations led to the various tests of input value tests and scaling
to avoid under/overflow. The current patch does not handle some of the
rare and most extreme combinations of input values, but the random
test data is only showing 1 case in 10 million that has an error of
greater than 12 bits. That case has 18 bits of error and is due to
subtraction cancellation. These results are significantly better
than the results reported by Baudin and Smith.
Support for half, float, double, extended, and long double precision
is included as all are handled with suitable preprocessor symbols in a
single source routine. Since half precision is computed with float
precision as per current libgcc practice, the enhanced algorithm
provides no benefit for half precision and would cost performance.
Further investigation showed changing the half precision algorithm
to use the simple formula (real=a*c+b*d imag=b*c-a*d) caused no
loss of precision and modest improvement in performance.
The existing constants for each precision:
float: FLT_MAX, FLT_MIN;
double: DBL_MAX, DBL_MIN;
extended and/or long double: LDBL_MAX, LDBL_MIN
are used for avoiding the more common overflow/underflow cases. This
use is made generic by defining appropriate __LIBGCC2_* macros in
c-cppbuiltin.c.
Tests are added for when both parts of the denominator have exponents
small enough to allow shifting any subnormal values to normal values
all input values could be scaled up without risking overflow. That
gained a clear improvement in accuracy. Similarly, when either
numerator was subnormal and the other numerator and both denominator
values were not too large, scaling could be used to reduce risk of
computing with subnormals. The test and scaling values used all fit
within the allowed exponent range for each precision required by the C
standard.
Float precision has more difficulty with getting correct answers than
double precision. When hardware for double precision floating point
operations is available, float precision is now handled in double
precision intermediate calculations with the simple algorithm the same
as the half-precision method of using float precision for intermediate
calculations. Using the higher precision yields exact results for all
tested input values (64-bit double, 32-bit float) with the only
performance cost being the requirement to convert the four input
values from float to double. If double precision hardware is not
available, then float complex divide will use the same improved
algorithm as the other precisions with similar change in performance.
Further Improvement
The most common remaining substantial errors are due to accuracy loss
when subtracting nearly equal values. This patch makes no attempt to
improve that situation.
NOTATION
For all of the following, the notation is:
Input complex values:
a+bi (a= real part, b= imaginary part)
c+di
Output complex value:
e+fi = (a+bi)/(c+di)
For the result tables:
current = current method (SMITH)
b1div = method proposed by Elen Kalda
b2div = alternate method considered by Elen Kalda
new = new method proposed by this patch
DESCRIPTIONS of different complex divide methods:
NAIVE COMPUTATION (-fcx-limited-range):
e = (a*c + b*d)/(c*c + d*d)
f = (b*c - a*d)/(c*c + d*d)
Note that c*c and d*d will overflow or underflow if either
c or d is outside the range 2^-538 to 2^512.
This method is available in gcc when the switch -fcx-limited-range is
used. That switch is also enabled by -ffast-math. Only one who has a
clear understanding of the maximum range of all intermediate values
generated by an application should consider using this switch.
SMITH's METHOD (current libgcc):
if(fabs(c)<fabs(d) {
r = c/d;
denom = (c*r) + d;
e = (a*r + b) / denom;
f = (b*r - a) / denom;
} else {
r = d/c;
denom = c + (d*r);
e = (a + b*r) / denom;
f = (b - a*r) / denom;
}
Smith's method is the current default method available with __divdc3.
Elen Kalda's METHOD
Elen Kalda proposed a patch about a year ago, also based on Baudin and
Smith, but not including tests for subnormals:
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-08/msg01629.html [4]
It is compared here for accuracy with this patch.
This method applies the most significant part of the algorithm
proposed by Baudin&Smith (2012) in the paper "A Robust Complex
Division in Scilab" [3]. Elen's method also replaces two divides by
one divide and two multiplies due to the high cost of divide on
aarch64. In the comparison sections, this method will be labeled
b1div. A variation discussed in that patch which does not replace the
two divides will be labeled b2div.
inline void improved_internal (MTYPE a, MTYPE b, MTYPE c, MTYPE d)
{
r = d/c;
t = 1.0 / (c + (d * r));
if (r != 0) {
x = (a + (b * r)) * t;
y = (b - (a * r)) * t;
} else {
/* Changing the order of operations avoids the underflow of r impacting
the result. */
x = (a + (d * (b / c))) * t;
y = (b - (d * (a / c))) * t;
}
}
if (FABS (d) < FABS (c)) {
improved_internal (a, b, c, d);
} else {
improved_internal (b, a, d, c);
y = -y;
}
NEW METHOD (proposed by patch) to replace the current default method:
The proposed method starts with an algorithm proposed by Baudin&Smith
(2012) in the paper "A Robust Complex Division in Scilab" [3]. The
patch makes additional modifications to that method for further
reductions in the error rate. The following code shows the #define
values for double precision. See the patch for #define values used
for other precisions.
#define RBIG ((DBL_MAX)/2.0)
#define RMIN (DBL_MIN)
#define RMIN2 (0x1.0p-53)
#define RMINSCAL (0x1.0p+51)
#define RMAX2 ((RBIG)*(RMIN2))
if (FABS(c) < FABS(d)) {
/* prevent overflow when arguments are near max representable */
if ((FABS (d) > RBIG) || (FABS (a) > RBIG) || (FABS (b) > RBIG) ) {
a = a * 0.5;
b = b * 0.5;
c = c * 0.5;
d = d * 0.5;
}
/* minimize overflow/underflow issues when c and d are small */
else if (FABS (d) < RMIN2) {
a = a * RMINSCAL;
b = b * RMINSCAL;
c = c * RMINSCAL;
d = d * RMINSCAL;
}
else {
if(((FABS (a) < RMIN) && (FABS (b) < RMAX2) && (FABS (d) < RMAX2)) ||
((FABS (b) < RMIN) && (FABS (a) < RMAX2) && (FABS (d) < RMAX2))) {
a = a * RMINSCAL;
b = b * RMINSCAL;
c = c * RMINSCAL;
d = d * RMINSCAL;
}
}
r = c/d; denom = (c*r) + d;
if( r > RMIN ) {
e = (a*r + b) / denom ;
f = (b*r - a) / denom
} else {
e = (c * (a/d) + b) / denom;
f = (c * (b/d) - a) / denom;
}
}
[ only presenting the fabs(c) < fabs(d) case here, full code in patch. ]
Before any computation of the answer, the code checks for any input
values near maximum to allow down scaling to avoid overflow. These
scalings almost never harm the accuracy since they are by 2. Values that
are over RBIG are relatively rare but it is easy to test for them and
allow aviodance of overflows.
Testing for RMIN2 reveals when both c and d are less than [FLT|DBL]_EPSILON.
By scaling all values by 1/EPSILON, the code converts subnormals to normals,
avoids loss of accuracy and underflows in intermediate computations
that otherwise might occur. If scaling a and b by 1/EPSILON causes either
to overflow, then the computation will overflow whatever method is used.
Finally, we test for either a or b being subnormal (RMIN) and if so,
for the other three values being small enough to allow scaling. We
only need to test a single denominator value since we have already
determined which of c and d is larger.
Next, r (the ratio of c to d) is checked for being near zero. Baudin
and Smith checked r for zero. This code improves that approach by
checking for values less than DBL_MIN (subnormal) covers roughly 12
times as many cases and substantially improves overall accuracy. If r
is too small, then when it is used in a multiplication, there is a
high chance that the result will underflow to zero, losing significant
accuracy. That underflow is avoided by reordering the computation.
When r is subnormal, the code replaces a*r (= a*(c/d)) with ((a/d)*c)
which is mathematically the same but avoids the unnecessary underflow.
TEST Data
Two sets of data are presented to test these methods. Both sets
contain 10 million pairs of complex values. The exponents and
mantissas are generated using multiple calls to random() and then
combining the results. Only values which give results to complex
divide that are representable in the appropriate precision after
being computed in quad precision are used.
The first data set is labeled "moderate exponents".
The exponent range is limited to -DBL_MAX_EXP/2 to DBL_MAX_EXP/2
for Double Precision (use FLT_MAX_EXP or LDBL_MAX_EXP for the
appropriate precisions.
The second data set is labeled "full exponents".
The exponent range for these cases is the full exponent range
including subnormals for a given precision.
ACCURACY Test results:
Note: The following accuracy tests are based on IEEE-754 arithmetic.
Note: All results reporteed are based on use of fused multiply-add. If
fused multiply-add is not used, the error rate increases, giving more
1 and 2 bit errors for both current and new complex divide.
Differences between using fused multiply and not using it that are
greater than 2 bits are less than 1 in a million.
The complex divide methods are evaluated by determining the percentage
of values that exceed differences in low order bits. If a "2 bit"
test results show 1%, that would mean that 1% of 10,000,000 values
(100,000) have either a real or imaginary part that differs from the
quad precision result by more than the last 2 bits.
Results are reported for differences greater than or equal to 1 bit, 2
bits, 8 bits, 16 bits, 24 bits, and 52 bits for double precision. Even
when the patch avoids overflows and underflows, some input values are
expected to have errors due to the potential for catastrophic roundoff
from floating point subtraction. For example, when b*c and a*d are
nearly equal, the result of subtraction may lose several places of
accuracy. This patch does not attempt to detect or minimize this type
of error, but neither does it increase them.
I only show the results for Elen Kalda's method (with both 1 and
2 divides) and the new method for only 1 divide in the double
precision table.
In the following charts, lower values are better.
current - current complex divide in libgcc
b1div - Elen Kalda's method from Baudin & Smith with one divide
b2div - Elen Kalda's method from Baudin & Smith with two divides
new - This patch which uses 2 divides
===================================================
Errors Moderate Dataset
gtr eq current b1div b2div new
====== ======== ======== ======== ========
1 bit 0.24707% 0.92986% 0.24707% 0.24707%
2 bits 0.01762% 0.01770% 0.01762% 0.01762%
8 bits 0.00026% 0.00026% 0.00026% 0.00026%
16 bits 0.00000% 0.00000% 0.00000% 0.00000%
24 bits 0% 0% 0% 0%
52 bits 0% 0% 0% 0%
===================================================
Table 1: Errors with Moderate Dataset (Double Precision)
Note in Table 1 that both the old and new methods give identical error
rates for data with moderate exponents. Errors exceeding 16 bits are
exceedingly rare. There are substantial increases in the 1 bit error
rates for b1div (the 1 divide/2 multiplys method) as compared to b2div
(the 2 divides method). These differences are minimal for 2 bits and
larger error measurements.
===================================================
Errors Full Dataset
gtr eq current b1div b2div new
====== ======== ======== ======== ========
1 bit 2.05% 1.23842% 0.67130% 0.16664%
2 bits 1.88% 0.51615% 0.50354% 0.00900%
8 bits 1.77% 0.42856% 0.42168% 0.00011%
16 bits 1.63% 0.33840% 0.32879% 0.00001%
24 bits 1.51% 0.25583% 0.24405% 0.00000%
52 bits 1.13% 0.01886% 0.00350% 0.00000%
===================================================
Table 2: Errors with Full Dataset (Double Precision)
Table 2 shows significant differences in error rates. First, the
difference between b1div and b2div show a significantly higher error
rate for the b1div method both for single bit errros and well
beyond. Even for 52 bits, we see the b1div method gets completely
wrong answers more than 5 times as often as b2div. To retain
comparable accuracy with current complex divide results for small
exponents and due to the increase in errors for large exponents, I
choose to use the more accurate method of two divides.
The current method has more 1.6% of cases where it is getting results
where the low 24 bits of the mantissa differ from the correct
answer. More than 1.1% of cases where the answer is completely wrong.
The new method shows less than one case in 10,000 with greater than
two bits of error and only one case in 10 million with greater than
16 bits of errors. The new patch reduces 8 bit errors by
a factor of 16,000 and virtually eliminates completely wrong
answers.
As noted above, for architectures with double precision
hardware, the new method uses that hardware for the
intermediate calculations before returning the
result in float precision. Testing of the new patch
has shown zero errors found as seen in Tables 3 and 4.
Correctness for float
=============================
Errors Moderate Dataset
gtr eq current new
====== ======== ========
1 bit 28.68070% 0%
2 bits 0.64386% 0%
8 bits 0.00401% 0%
16 bits 0.00001% 0%
24 bits 0% 0%
=============================
Table 3: Errors with Moderate Dataset (float)
=============================
Errors Full Dataset
gtr eq current new
====== ======== ========
1 bit 19.98% 0%
2 bits 3.20% 0%
8 bits 1.97% 0%
16 bits 1.08% 0%
24 bits 0.55% 0%
=============================
Table 4: Errors with Full Dataset (float)
As before, the current method shows an troubling rate of extreme
errors.
There very minor changes in accuracy for half-precision since the code
changes from Smith's method to the simple method. 5 out of 1 million
test cases show correct answers instead of 1 or 2 bit errors.
libgcc computes half-precision functions in float precision
allowing the existing methods to avoid overflow/underflow issues
for the allowed range of exponents for half-precision.
Extended precision (using x87 80-bit format on x86) and Long double
(using IEEE-754 128-bit on x86 and aarch64) both have 15-bit exponents
as compared to 11-bit exponents in double precision. We note that the
C standard also allows Long Double to be implemented in the equivalent
range of Double. The RMIN2 and RMINSCAL constants are selected to work
within the Double range as well as with extended and 128-bit ranges.
We will limit our performance and accurancy discussions to the 80-bit
and 128-bit formats as seen on x86 here.
The extended and long double precision investigations were more
limited. Aarch64 does not support extended precision but does support
the software implementation of 128-bit long double precision. For x86,
long double defaults to the 80-bit precision but using the
-mlong-double-128 flag switches to using the software implementation
of 128-bit precision. Both 80-bit and 128-bit precisions have the same
exponent range, with the 128-bit precision has extended mantissas.
Since this change is only aimed at avoiding underflow/overflow for
extreme exponents, I studied the extended precision results on x86 for
100,000 values. The limited exponent dataset showed no differences.
For the dataset with full exponent range, the current and new values
showed major differences (greater than 32 bits) in 567 cases out of
100,000 (0.56%). In every one of these cases, the ratio of c/d or d/c
(as appropriate) was zero or subnormal, indicating the advantage of
the new method and its continued correctness where needed.
PERFORMANCE Test results
In order for a library change to be practical, it is necessary to show
the slowdown is tolerable. The slowdowns observed are much less than
would be seen by (for example) switching from hardware double precison
to a software quad precision, which on the tested machines causes a
slowdown of around 100x).
The actual slowdown depends on the machine architecture. It also
depends on the nature of the input data. If underflow/overflow is
rare, then implementations that have strong branch prediction will
only slowdown by a few cycles. If underflow/overflow is common, then
the branch predictors will be less accurate and the cost will be
higher.
Results from two machines are presented as examples of the overhead
for the new method. The one labeled x86 is a 5 year old Intel x86
processor and the one labeled aarch64 is a 3 year old arm64 processor.
In the following chart, the times are averaged over a one million
value data set. All values are scaled to set the time of the current
method to be 1.0. Lower values are better. A value of less than 1.0
would be faster than the current method and a value greater than 1.0
would be slower than the current method.
================================================
Moderate set full set
x86 aarch64 x86 aarch64
======== =============== ===============
float 0.59 0.79 0.45 0.81
double 1.04 1.24 1.38 1.56
long double 1.13 1.24 1.29 1.25
================================================
Table 5: Performance Comparisons (ratio new/current)
The above tables omit the timing for the 1 divide and 2 multiply
comparison with the 2 divide approach.
The float results show clear performance improvement due to using the
simple method with double precision for intermediate calculations.
The double results with the newer method show less overhead for the
moderate dataset than for the full dataset. That's because the moderate
dataset does not ever take the new branches which protect from
under/overflow. The better the branch predictor, the lower the cost
for these untaken branches. Both platforms are somewhat dated, with
the x86 having a better branch predictor which reduces the cost of the
additional branches in the new code. Of course, the relative slowdown
may be greater for some architectures, especially those with limited
branch prediction combined with a high cost of misprediction.
The long double results are fairly consistent in showing the moderate
additional cost of the extra branches and calculations for all cases.
The observed cost for all precisions is claimed to be tolerable on the
grounds that:
(a) the cost is worthwhile considering the accuracy improvement shown.
(b) most applications will only spend a small fraction of their time
calculating complex divide.
(c) it is much less than the cost of extended precision
(d) users are not forced to use it (as described below)
Those users who find this degree of slowdown unsatisfactory may use
the gcc switch -fcx-fortran-rules which does not use the library
routine, instead inlining Smith's method without the C99 requirement
for dealing with NaN results. The proposed patch for libgcc complex
divide does not affect the code generated by -fcx-fortran-rules.
SUMMARY
When input data to complex divide has exponents whose absolute value
is less than half of *_MAX_EXP, this patch makes no changes in
accuracy and has only a modest effect on performance. When input data
contains values outside those ranges, the patch eliminates more than
99.9% of major errors with a tolerable cost in performance.
In comparison to Elen Kalda's method, this patch introduces more
performance overhead but reduces major errors by a factor of
greater than 4000.
REFERENCES
[1] Nelson H.F. Beebe, "The Mathematical-Function Computation Handbook.
Springer International Publishing AG, 2017.
[2] Robert L. Smith. Algorithm 116: Complex division. Commun. ACM,
5(8):435, 1962.
[3] Michael Baudin and Robert L. Smith. "A robust complex division in
Scilab," October 2012, available at http://arxiv.org/abs/1210.4539.
[4] Elen Kalda: Complex division improvements in libgcc
https://gcc.gnu.org/legacy-ml/gcc-patches/2019-08/msg01629.html
2020-12-08 Patrick McGehearty <patrick.mcgehearty@oracle.com>
gcc/c-family/
* c-cppbuiltin.c (c_cpp_builtins): Add supporting macros for new
complex divide
libgcc/
* libgcc2.c (XMTYPE, XCTYPE, RBIG, RMIN, RMIN2, RMINSCAL, RMAX2):
Define.
(__divsc3, __divdc3, __divxc3, __divtc3): Improve complex divide.
* config/rs6000/_divkc3.c (RBIG, RMIN, RMIN2, RMINSCAL, RMAX2):
Define.
(__divkc3): Improve complex divide.
gcc/testsuite/
* gcc.c-torture/execute/ieee/cdivchkd.c: New test.
* gcc.c-torture/execute/ieee/cdivchkf.c: Likewise.
* gcc.c-torture/execute/ieee/cdivchkld.c: Likewise.
Tobias Burnus [Wed, 28 Apr 2021 19:15:16 +0000 (21:15 +0200)]
doc/install.texi: Document --enable-offload-defaulted config option
Document configure --enable-offload-defaulted option added in
commit r12-218-gfe5bfa6704179f8db7d1ae0b485439e9896df8eb
gcc/ChangeLog:
* doc/install.texi (--enable-offload-defaulted): Document.
Senthil Kumar Selvaraj [Wed, 28 Apr 2021 17:29:12 +0000 (17:29 +0000)]
AVR cc0 conversion
See https://gcc.gnu.org/pipermail/gcc-patches/2021-January/563638.html
for background.
This patch converts the avr backend to MODE_CC. It addresses some of
the comments made in the previous submission over here
(https://gcc.gnu.org/pipermail/gcc-patches/2020-December/561757.html).
Specifically, this patch has
1. Automatic clobber of REG_CC in inline asm statements, via
TARGET_MD_ASM_ADJUST hook.
2. Direct clobber of REG_CC in insns emitted after reload (pro and
epilogue).
3. Regression testing done on atmega8, atmega128, attiny40 and
atxmega128a3 devices (more details below).
4. Verification and fixes for casesi and avr_compare_pattern related
code that inspects insns, by looking at avr-casesi and mach RTL dumps.
5. Use length of parallel instead of passing in operand counts when
generating code for shift patterns.
6. Fixes for indentation glitches.
7. Removal of CC_xxx stuff in avr-protos.h. In the places where the
macros were still used (cond_string), I've replaced them with a bool
hardcoded to false. I expect this will go away/get fixed when I
eventually add specific CC modes.
Things still to do:
1. Adjustment of peepholes/define_splits to match against patterns
with REG_CC clobber.
2. Model effect of non-compare insns on REG_CC using additional CC
modes. I'm hoping to use of a modified version of the cc attribute
and define_subst (again inspired by the cris port), to do this.
3. RTX cost adjustment.
gcc/
* config/avr/avr-dimode.md: Turn existing patterns into
define_insn_and_split style patterns where the splitter
adds a clobber of the condition code register. Drop "cc"
attribute. Add new patterns to match output of
the splitters.
* config/avr/avr-fixed.md: Likewise.
* config/avr/avr.c (cc_reg_rtx): New.
(avr_parallel_insn_from_insns): Adjust insn count
for removal of set of cc0.
(avr_is_casesi_sequence): Likewise.
(avr_casei_sequence_check_operands): Likewise.
(avr_optimize_casesi): Likewise. Also insert
new insns after jump_insn.
(avr_pass_casesi::avr_rest_of_handle_casesi): Adjust
for removal of set of cc0.
(avr_init_expanders): Initialize cc_reg_rtx.
(avr_regno_reg_class): Handle REG_CC.
(cond_string): Remove usage of CC_OVERFLOW_UNUSABLE.
(avr_notice_update_cc): Remove function.
(ret_cond_branch): Remove usage of CC_OVERFLOW_UNUSABLE.
(compare_condition): Adjust for PARALLEL with
REG_CC clobber.
(out_shift_with_cnt): Likewise.
(ashlhi3_out): Likewise.
(ashrhi3_out): Likewise.
(lshrhi3_out): Likewise.
(avr_class_max_nregs): Return single reg for REG_CC.
(avr_compare_pattern): Check for REG_CC instead
of cc0_rtx.
(avr_reorg_remove_redundant_compare): Likewise.
(avr_reorg):Adjust for PARALLEL with REG_CC clobber.
(avr_hard_regno_nregs): Return single reg for REG_CC.
(avr_hard_regno_mode_ok): Allow only CCmode for REG_CC.
(avr_md_asm_adjust): Clobber REG_CC.
(TARGET_HARD_REGNO_NREGS): Define.
(TARGET_CLASS_MAX_NREGS): Define.
(TARGET_MD_ASM_ADJUST): Define.
* config/avr/avr.h (FIRST_PSEUDO_REGISTER): Adjust
for REG_CC.
(enum reg_class): Add CC_REG class.
(NOTICE_UPDATE_CC): Remove.
(CC_OVERFLOW_UNUSABLE): Remove.
(CC_NO_CARRY): Remove.
* config/avr/avr.md: Turn existing patterns into
define_insn_and_split style patterns where the splitter
adds a clobber of the condition code register. Drop "cc"
attribute. Add new patterns to match output of
the splitters.
(sez): Remove unused pattern.
Jonathan Wakely [Wed, 28 Apr 2021 17:14:05 +0000 (18:14 +0100)]
libstdc++: Add testcase for std::pair as a structural type [PR 97930]
This PR was fixed by r12-221-ge1543e694dadf1ea70eb72325219bc0cdc914a35
(for compilers that support C++20 Concepts) so this adds the testcase.
libstdc++-v3/ChangeLog:
PR libstdc++/97930
* testsuite/20_util/pair/requirements/structural.cc: New test.
Alexandre Oliva [Wed, 28 Apr 2021 17:07:43 +0000 (14:07 -0300)]
omit frame pointer in pr89676
This i386 test expects only two movl instructions.
In configurations that --enable-frame-pointer, -O2 won't implicitly
enable -fomit-frame-pointer, so we end up with a third movl to set up
the frame pointer.
This patch enables -fomit-frame-pointer explicitly, so that the result
no longer depends on that configuration option.
for gcc/testsuite/ChangeLog
* gcc.target/i386/pr89676.c: Add -fomit-frame-pointer.
Alexandre Oliva [Wed, 28 Apr 2021 17:07:41 +0000 (14:07 -0300)]
fix asm-not pattern in dwarf2/inline5.c
The test is supposed to check that the abstract lexical block of a
function that was inlined doesn't have attributes, and that the
concrete inlined lexical block does.
There are two patterns to verify the absence of attributes in the
abstract lexical block, one for the case in which the concrete block
appears after the abstract one, and another for the case in which it's
before.
The former has a problem that is not visible when asm comments start
with a single character, but that becomes apparent when they start
with "/ ".
The pattern starts by matching the abstract DW_TAG_lexical_block DIE
header, and checking that the next line has, after any of the
comment-starter characters (e.g. '/'), there are one or more blanks '
+', and then a character other than the '(' that would start another
DIE.
The problem is that '[.../...]+ +[^(].*' matches '/ (DIE...', because
'[^(]' may match the second blank, and after that anything goes. So
we end up recognizing the pattern, as if it was an abstract lexical
block with an attribute.
This could be minimally fixed by changing '[^(]' to '[^ (]', but the
pattern that matches concrete before abstract checks for an explicit
DW_AT after the abstract DIE, so I'm using that in the other pattern
as well.
For reference, the lines that start the unwanted match are:
.uleb128 0xc / (DIE (0xa4) DW_TAG_lexical_block)
.uleb128 0xd / (DIE (0xa5) DW_TAG_variable)
for gcc/testsuite/ChangeLog
* gcc.dg/debug/dwarf2/inline5.c: Adjust pattern to avoid
mismatch when asm comments start with "/ ".
Richard Earnshaw [Wed, 28 Apr 2021 16:56:38 +0000 (17:56 +0100)]
arm: fix UB due to missing mode check [PR100311]
Some places in the compiler iterate over all the fixed registers to
check if that register can be used in a particular mode. The idiom is
to iterate over the register and then for that register, if it
supports the current mode to check all that register and any
additional registers needed (HARD_REGNO_NREGS). If these two checks
are not fully aligned then it is possible to generate a buffer overrun
when testing data objects that are sized by the number of hard regs in
the machine.
The VPR register is a case where these checks were not consistent and
because this is the last HARD register the result was that we ended up
overflowing the fixed_regs array.
gcc:
PR target/100311
* config/arm/arm.c (arm_hard_regno_mode_ok): Only allow VPR to be
used in HImode.
Jonathan Wakely [Wed, 28 Apr 2021 16:46:01 +0000 (17:46 +0100)]
libstdc++: Simplify std::pair constraints using concepts
This re-implements the constraints on the std::pair constructors and
assignment operators in C++20 mode, to use concepts.
The non-standard constructors deprecated for PR 99957 are no longer
supported in C++20 mode, which requires some minor testsuite changes.
Otherwise all tests pass in C++20 mode.
libstdc++-v3/ChangeLog:
* include/bits/stl_pair.h (pair) [__cplusplus > 202002]: Add
new definitions for constructors and assignment operators using
concepts for constraints.
* testsuite/20_util/pair/cons/99957.cc: Disable for C++20 and
later.
* testsuite/20_util/pair/cons/explicit_construct.cc: Adjust
expected error messages to also match C++20 errors.
Jonathan Wakely [Wed, 28 Apr 2021 16:46:01 +0000 (17:46 +0100)]
libstdc++: Deprecate non-standard std::pair constructors [PR 99957]
This deprecates the non-standard std::pair constructors that support
construction from an rvalue and a literal zero used as a null pointer
constant. We can't just add the deprecated attribute to those
constructors, because they're currently used by correct code when they
are a better match than the constructors required by the standard e.g.
int i = 0;
const int j = 0;
std::pair<int, int> p(i, j); // uses pair(U1&&, const int&)
This patch adjusts the parameter types and constraints of those
constructors so that they only get used for literal zeros, and the
pair(U1&&, U2&&) constructor gets used otherwise. Once they're only used
for initializations that should be ill-formed we can add the deprecated
attribute.
The deprecated attribute is used to suggest that the user code uses
nullptr, which avoids the problem of 0 deducing as int instead of a null
pointer constant.
libstdc++-v3/ChangeLog:
PR libstdc++/99957
* include/bits/stl_pair.h (_PCC::_MoveCopyPair, _PCC::_CopyMovePair):
Combine and replace with ...
(_PCC::_DeprConsPair): New SFINAE helper function.
(pair): Merge preprocessor blocks so that all C++03 members
are defined together at the end.
(pair::pair(const _T1&, _U2&&), pair::pair(_U1&&, const _T2&)):
Replace _T1 and _T2 parameters with __null_ptr_constant and
adjust constraints.
* testsuite/20_util/pair/40925.cc: Use nullptr instead of 0.
* testsuite/20_util/pair/cons/explicit_construct.cc: Likewise.
* testsuite/20_util/pair/cons/99957.cc: New test.
Richard Sandiford [Wed, 28 Apr 2021 16:54:52 +0000 (17:54 +0100)]
aarch64: Fix address mode for vec_concat pattern [PR100305]
The load_pair_lanes<mode> patterns match a vec_concat of two
adjacent 64-bit memory locations as a single 128-bit load.
The Utq constraint made sure that the address was suitable
for a 128-bit vector, but this meant that it allowed some
addresses that aren't valid for the 64-bit element mode.
Two obvious fixes were:
(1) Continue to accept addresses that aren't valid for the element
modes. This would mean changing the mode of operands[1] before
printing it. It would also mean using a custom predicate instead
of the current memory_operand.
(2) Restrict addresses to the intersection of those that are valid
element and vector addresses.
The problem with (1) is that, as well as being more complicated,
it doesn't deal with the fact that we still have a memory_operand
for the second element. If we encourage the first operand to be
outside the range of a normal element memory_operand, we'll have
to reload the second operand to make it valid. This reload will
often be dead code, but will be kept around because the RTL
pattern makes it look as though the second element address
is still needed.
This patch therefore does (2) instead.
As mentioned in the PR notes, I think we have a general problem
with the way that the aarch64 port deals with paired addresses.
There's nothing to guarantee that the two addresses will be
reloaded in a way that keeps them “obviously” adjacent, so the
rtx_equal_p conditions could fail if something rechecked them
later.
For this particular pattern, I think it would be better to teach
simplify-rtx.c to fold the vec_concat to a normal vector memory
reference, to remove any suggestion that targets should try to
match the unsimplified form. That obviously wouldn't be suitable
for backports though.
gcc/
PR target/100305
* config/aarch64/constraints.md (Utq): Require the address to
be valid for both the element mode and for V2DImode.
gcc/testsuite/
PR target/100305
* gcc.c-torture/compile/pr100305.c: New test.
Tobias Burnus [Wed, 28 Apr 2021 16:46:47 +0000 (18:46 +0200)]
offload-defaulted: Config option to silently ignore uninstalled offload compilers
If configured with --enable-offload-defaulted, configured but not installed
offload compilers and libgomp plugins are silently ignored. Useful for
distribution compilers where those are in separate optional packages.
2021-04-28 Jakub Jelinek <jakub@redhat.com>
Tobias Burnus <tobias@codesourcery.com>
ChangeLog:
* configure.ac (--enable-offload-defaulted): New.
* configure: Regenerate.
gcc/ChangeLog:
* configure.ac (OFFLOAD_DEFAULTED): AC_DEFINE if offload-defaulted.
* gcc.c (process_command): New variable.
(driver::maybe_putenv_OFFLOAD_TARGETS): If OFFLOAD_DEFAULTED,
set it if -foffload is defaulted.
* lto-wrapper.c (OFFLOAD_TARGET_DEFAULT_ENV): Define.
(compile_offload_image): If OFFLOAD_DEFAULTED and
OFFLOAD_TARGET_DEFAULT is in the environment, don't fail
if corresponding mkoffload can't be found.
(compile_images_for_offload_targets): Likewise. Free and clear
offload_names if no valid offload is found.
* config.in: Regenerate.
* configure: Regenerate.
libgomp/ChangeLog:
* configure.ac (OFFLOAD_DEFAULTED): AC_DEFINE if offload-defaulted.
* target.c (gomp_load_plugin_for_device): If set and if a plugin
can't be dlopened, silently assume it has no devices.
* Makefile.in: Regenerate.
* config.h.in: Regenerate.
* configure: Regenerate.
Jonathan Wakely [Wed, 28 Apr 2021 14:56:04 +0000 (15:56 +0100)]
libstdc++: Define __cpp_lib_constexpr_string macro
As noted in r11-1339-gb6ab9ecd550227684643b41e9e33a4d3466724d8 we define
a non-standard __cpp_lib_constexpr_char_traits feature test macro to
indicate support for P0426R1 and P1032R1. At some point last year the
__cpp_lib_constexpr_string macro was retconned to indicate support for
those papers. This adds the new macro (which we didn't previously
define, because it referred to P0980R1 "Making std::string constexpr"
which we don't support).
libstdc++-v3/ChangeLog:
* include/bits/basic_string.h (__cpp_lib_constexpr_string): Define.
* include/std/version (__cpp_lib_constexpr_string): Define.
* testsuite/21_strings/char_traits/requirements/constexpr_functions_c++17.cc:
Check for __cpp_lib_constexpr_string.
* testsuite/21_strings/char_traits/requirements/constexpr_functions_c++20.cc:
Likewise.
* testsuite/21_strings/char_traits/requirements/version.cc: New test.
Jonathan Wakely [Wed, 28 Apr 2021 13:49:28 +0000 (14:49 +0100)]
libstdc++: Reduce output of 'make doc-pdf-doxygen'
Use '@' to prevent Make from echoing the recipe, so that users don't see
this every time:
if [ -f ${doxygen_pdf} ]; then
mv ${doxygen_pdf} ${api_pdf} ;
echo ":: PDF file is ${api_pdf}";
else
echo "... error";
grep -F 'LaTeX Error' ${doxygen_outdir}/latex/refman.log;
grep -F 'TeX capacity exceeded, sorry' ${doxygen_outdir}/latex/refman.log;
exit 12;
fi
The presence of the "error" strings in the output makes it look like an
error happened. By suppressing the echoing user's will only see "error"
if the 'else' branch is taken.
libstdc++-v3/ChangeLog:
* doc/Makefile.am (stamp-pdf-doxygen): Improve comment about
dealing with errors. Use '@' to prevent shell command being
echoed.
* doc/Makefile.in: Regenerate.
Jonathan Wakely [Wed, 28 Apr 2021 11:45:49 +0000 (12:45 +0100)]
libstdc++: Add missing noexcept on std::thread member function [PR 100298]
The new inline definition of std::thread::hardware_concurrency() for
non-gthreads targets is missing the noexcept-specifier that is on the
declaration.
libstdc++-v3/ChangeLog:
PR libstdc++/100298
* include/bits/std_thread.h (thread::hardware_concurrency): Add
missing noexcept to inline definition for non-gthreads targets.
José Rui Faustino de Sousa [Wed, 28 Apr 2021 11:20:25 +0000 (11:20 +0000)]
Fortran: Fix double function call with -fcheck=pointer [PR]
gcc/fortran/ChangeLog:
PR fortran/82376
* trans-expr.c (gfc_conv_procedure_call): Evaluate function result
and then pass a pointer.
gcc/testsuite/ChangeLog:
PR fortran/82376
* gfortran.dg/PR82376.f90: New test.
Jakub Jelinek [Tue, 27 Apr 2021 09:37:30 +0000 (11:37 +0200)]
c++: Remove #error for release builds
* module.cc: Remove #error that triggers if DEV-PHASE is empty.
Richard Biener [Wed, 28 Apr 2021 08:41:41 +0000 (10:41 +0200)]
tree-optimization/100292 - avoid invalid GIMPLE from vector lowering
We have to avoid folding the condition when building a COND_EXPR
since we no longer gimplify the whole thing. The folding done
at COND_EXPR build time will deal with possible simplifications.
2021-04-28 Richard Biener <rguenther@suse.de>
PR tree-optimization/100292
* tree-vect-generic.c (expand_vector_condition): Do not fold
the comparisons.
* gcc.dg/pr100292.c: New testcase.
Piotr Trojanek [Fri, 11 Dec 2020 09:41:20 +0000 (10:41 +0100)]
[Ada] Style fixes related to calls to List_Length
gcc/ada/
* sem_ch13.adb, sem_util.adb: Fix style.
Piotr Trojanek [Thu, 10 Dec 2020 23:42:22 +0000 (00:42 +0100)]
[Ada] Adjust List_Length description
gcc/ada/
* nlists.ads (List_Length): Adapt comment to match the
behaviour.
Arnaud Charlet [Thu, 10 Dec 2020 16:22:23 +0000 (11:22 -0500)]
[Ada] Fix recent optimization in evaluation of selected component for GNATprove
gcc/ada/
* sem_eval.adb (Eval_Selected_Component): Only consider compile
time known aggregates.
Eric Botcazou [Thu, 10 Dec 2020 20:02:07 +0000 (21:02 +0100)]
[Ada] Fix computation of Prec/Succ of zero without denormals
gcc/ada/
* libgnat/s-fatgen.adb: Add use clause for Interfaces.Unsigned_16
and Interfaces.Unsigned_32.
(Small16): New constant.
(Small32): Likewise.
(Small64): Likewise.
(Small80): Likewise.
(Pred): Declare a local overlay for Small and return it negated
for zero if the type does not support denormalized numbers.
(Succ): Likewise, but return it directly.
Piotr Trojanek [Thu, 10 Dec 2020 12:12:22 +0000 (13:12 +0100)]
[Ada] Remove redundant assignment in Formal_Is_Used_Once
gcc/ada/
* inline.adb (Formal_Is_Used_Once): Refine type of the counter
variable; remove redundant assignment.
Patrick Bernardi [Wed, 9 Dec 2020 21:48:20 +0000 (16:48 -0500)]
[Ada] Install_Restricted_Handlers: define Prio parameter as Interrupt_Priority
gcc/ada/
* libgnarl/s-interr.adb (Install_Restricted_Handlers): Change
Prio parameter to type Interrupt_Priority.
* libgnarl/s-interr.ads (Install_Restricted_Handlers): Likewise.
* libgnarl/s-interr__dummy.adb (Install_Restricted_Handlers):
Likewise.
* libgnarl/s-interr__hwint.adb (Install_Restricted_Handlers):
Likewise.
* libgnarl/s-interr__sigaction.adb (Install_Restricted_Handlers):
Likewise.
* libgnarl/s-interr__vxworks.adb (Install_Restricted_Handlers):
Likewise.
Piotr Trojanek [Tue, 8 Dec 2020 21:34:29 +0000 (22:34 +0100)]
[Ada] Simplify data structures for overloaded interpretations
gcc/ada/
* sem_type.ads (Write_Interp_Ref): Removed; no longer needed.
* sem_type.adb (Headers): Removed; now the hash table is
directly in the Interp_Map alone.
(Interp_Map): Now an instance of the GNAT.HTable.Simple_HTable.
(Last_Overloaded): New variable to emulate Interp_Map.Last.
(Add_One_Interp): Adapt to new data structure.
(Get_First_Interp): Likewise.
(Hash): Likewise.
(Init_Interp_Tables): Likewise.
(New_Interps): Likewise.
(Save_Interps): Likewise; handle O_N variable like in
Get_First_Interp.
(Write_Interp_Ref): Removed; no longer needed.