Tomasz Figa [Sat, 9 Nov 2013 02:17:34 +0000 (03:17 +0100)]
MAINTAINERS: Add entry for Samsung SoC clock drivers
This patch adds an entry for Samsung SoC clock drivers located under
drivers/clk/samsung/ directory, with me taking the maintainer role.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Tue, 31 Dec 2013 19:35:12 +0000 (11:35 -0800)]
Merge branch 'clk-next-unregister' into clk-next
Conflicts:
drivers/clk/clk.c
Mike Turquette [Mon, 30 Dec 2013 18:58:22 +0000 (10:58 -0800)]
Merge branch 'for_3.14/keystone-clk' of git://git./linux/kernel/git/ssantosh/linux-keystone into clk-next-keystone
Mike Turquette [Sun, 29 Dec 2013 21:37:56 +0000 (13:37 -0800)]
Merge tag 'sunxi-clk-3.14-for-mike' of https://bitbucket.org/emiliolopez/linux into clk-next-sunxi
Allwinner sunXi SoCs clock changes
This contains the clk driver parts of the "[PATCH v3 00/13] clk: sunxi:
add PLL5 and PLL6 support" series. It adds support for PLL4/5/6 and
mod0 clocks on most sunxi platforms. Additionally, it contains "[PATCH
1/4] clk: sunxi: Allwinner A20 output clock support" (v2) from Chen-Yu
Tsai, which adds support for output clocks present on A20.
Chen-Yu Tsai [Tue, 24 Dec 2013 13:26:17 +0000 (21:26 +0800)]
clk: sunxi: Allwinner A20 output clock support
This patch adds support for the external clock outputs on the
Allwinner A20 SoC. The clock outputs are similar to "module 0"
type clocks, with different offsets and widths for clock factors.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Emilio López [Mon, 23 Dec 2013 03:32:40 +0000 (00:32 -0300)]
clk: sunxi: support better factor DT nodes
The DT nodes should look like
abc_clk: clk@
deadbeef {
...
clock-output-names = "abc";
}
But our old DT nodes look like
abc: abc@
deadbeef {
...
}
So, let's support both formats, until we can transition everything
to the new, correct one.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:39 +0000 (00:32 -0300)]
clk: sunxi: mod0 support
This commit implements support for the "module 0" type of clocks, as
used by MMC, IR, NAND, SATA and other components.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:37 +0000 (00:32 -0300)]
clk: sunxi: add PLL5 and PLL6 support
This commit implements PLL5 and PLL6 support on the sunxi clock driver.
These PLLs use a similar factor clock, but differ on their outputs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:36 +0000 (00:32 -0300)]
clk: sunxi: make factors_clk_setup return the clock it registers
We will be needing this to register a factor clock as parent with leaf
divisors on a single call.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:34 +0000 (00:32 -0300)]
clk: sunxi: add gating support to PLL1
This commit adds gating support to PLL1 on the clock driver. This makes
the PLL1 implementation fully compatible with PLL4 as well.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:33 +0000 (00:32 -0300)]
clk: sunxi: clean the magic number of mux parents
This was pointed out during the review of the factor patches. Let's
indicate what does that magic 5 mean.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Mike Turquette <mturquette@linaro.org>
Emilio López [Mon, 23 Dec 2013 03:32:32 +0000 (00:32 -0300)]
clk: sunxi: register factors clocks behind composite
This commit reworks factors clock registration to be done behind a
composite clock. This allows us to additionally add a gate, mux or
divisors, as it will be needed by some future PLLs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Thu, 19 Dec 2013 05:38:52 +0000 (21:38 -0800)]
clk: remove CONFIG_COMMON_CLK_DEBUG
Populate ${DEBUGS_MOUNT_POINT}/clk if CONFIG_DEBUG_FS is set. This
eliminates the extra (annoying) step of enabling the config option
manually.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:48 +0000 (16:47 +0530)]
clk: max77686: Remove redundant break
'break' after 'goto' is redundant. Remove it.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Boris BREZILLON [Sat, 21 Dec 2013 09:34:48 +0000 (10:34 +0100)]
clk: add accuracy support for fixed clock
This patch adds support for accuracy retrieval on fixed clocks.
It also adds a new dt property called 'clock-accuracy' to define the clock
accuracy.
This can be usefull for oscillator (RC, crystal, ...) definitions which are
always given an accuracy characteristic.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Boris BREZILLON [Sat, 21 Dec 2013 09:34:47 +0000 (10:34 +0100)]
clk: add clk accuracy retrieval support
The clock accuracy is expressed in ppb (parts per billion) and represents
the possible clock drift.
Say you have a clock (e.g. an oscillator) which provides a fixed clock of
20MHz with an accuracy of +- 20Hz. This accuracy expressed in ppb is
20Hz/20MHz = 1000 ppb (or 1 ppm).
Clock users may need the clock accuracy information in order to choose
the best clock (the one with the best accuracy) across several available
clocks.
This patch adds clk accuracy retrieval support for common clk framework by
means of a new function called clk_get_accuracy.
This function returns the given clock accuracy expressed in ppb.
In order to get the clock accuracy, this implementation adds one callback
called recalc_accuracy to the clk_ops structure.
This callback is given the parent clock accuracy (if the clock is not a
root clock) and should recalculate the given clock accuracy.
This callback is optional and may be implemented if the clock is not
a perfect clock (accuracy != 0 ppb).
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Sat, 21 Dec 2013 10:15:27 +0000 (15:45 +0530)]
clk: si570: Remove redundant of_match_ptr helper
'clk_si570_of_match' is always compiled in. Hence the
helper macro is not needed.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Mon, 23 Dec 2013 05:55:22 +0000 (21:55 -0800)]
Merge tag 'renesas-clock-for-v3.14' of git://git./linux/kernel/git/horms/renesas into clk-next-shmobile2
Renesas ARM based SoC Clock updates for v3.14
Add support for using emev2 SMU clocks with DT
Mike Turquette [Fri, 20 Dec 2013 20:58:38 +0000 (12:58 -0800)]
Merge tag 'mvebu-clk-3.14' of git://git.infradead.org/linux-mvebu into clk-next
mvebu clock changes for v3.14
- mvebu: add the core divider clock driver
- sparse cleanup
Mike Turquette [Fri, 20 Dec 2013 20:53:02 +0000 (12:53 -0800)]
Merge tag 'zynq-clk-for-3.14-v2' of git://git.xilinx.com/linux-xlnx into clk-next
arm: Xilinx Zynq clk patches for v3.14
- Add support for fclk-enable feature
Soren Brinkmann [Wed, 27 Nov 2013 20:16:23 +0000 (12:16 -0800)]
clk/zynq/clkc: Add 'fclk-enable' feature
In some use cases Zynq's FPGA clocks are used as static clock
generators for IP in the FPGA part of the SOC for which no Linux driver
exists and would control those clocks. To avoid automatic
gating of these clocks in such cases a new property - fclk-enable - is
added to the clock controller's DT description to accomodate such use
cases. It's value is a bitmask, where a set bit results in enabling
the corresponding FCLK through the clkc.
FPGA clocks are handled following the rules below:
If an FCLK is not enabled by bootloaders, that FCLK will be disabled in
Linux. Drivers can enable and control it through the CCF as usual.
If an FCLK is enabled by bootloaders AND the corresponding bit in the
'fclk-enable' DT property is set, that FCLK will be enabled by the clkc,
resulting in an off by one reference count for that clock. Ensuring it
will always be running.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sachin Kamat [Tue, 8 Oct 2013 11:17:47 +0000 (16:47 +0530)]
clk: ux500: Remove extra semicolon
Extra semicolon is redundant. Remove it.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:46 +0000 (16:47 +0530)]
clk: vt8500: Staticize vtwm_pll_ops
'vtwm_pll_ops' is local to this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:45 +0000 (16:47 +0530)]
clk: mvebu: Staticize of_cpu_clk_setup
'of_cpu_clk_setup' is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:44 +0000 (16:47 +0530)]
clk: versatile: Staticize clk_sp810_timerclken_of_get
clk_sp810_timerclken_of_get is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:43 +0000 (16:47 +0530)]
clk: socfpga: Use NULL instead of 0
'div_reg' is a pointer. Assign NULL instead of 0.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:42 +0000 (16:47 +0530)]
clk: tegra: Staticize tegra_clk_periph_nodiv_ops
tegra_clk_periph_nodiv_ops is used only in this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:41 +0000 (16:47 +0530)]
clk: tegra: Staticize local variables in clk-pll.c
Local variables used only in this file are made static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sachin Kamat [Tue, 8 Oct 2013 11:17:40 +0000 (16:47 +0530)]
clk: SPEAr: Staticize clk_frac_ops
clk_frac_ops is local to this file. Make it static.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Soren Brinkmann [Sat, 21 Sep 2013 23:40:39 +0000 (16:40 -0700)]
clk: si570: Add a driver for SI570 oscillators
Add a driver for SILabs 570, 571, 598, 599 programmable oscillators.
The devices generate low-jitter clock signals and are reprogrammable via
an I2C interface.
Reviewed-by: Guenter Roeck <linux@roeck-us.net>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Stephen Boyd [Wed, 16 Oct 2013 07:40:03 +0000 (00:40 -0700)]
clk: Fix debugfs reparenting NULL pointer dereference
Adding clocks from a kernel module can cause a NULL pointer
dereference if the parent of a clock is added after the clock is
added. This happens because __clk_init() iterates over the list
of orphans and reparents the orphans to the clock being
registered before creating the debugfs entry for the clock.
Create the debugfs entry first before reparenting the orphans.
Unable to handle kernel NULL pointer dereference at virtual address
00000028
pgd =
ef3e4000
[
00000028] *pgd=
bf810831
Internal error: Oops: 17 [#1] PREEMPT SMP ARM
Modules linked in: mmcc_8960(+)
CPU: 0 PID: 52 Comm: modprobe Not tainted 3.12.0-rc2-00023-g1021a28-dirty #659
task:
ef319200 ti:
ef3a6000 task.ti:
ef3a6000
PC is at lock_rename+0x24/0xc4
LR is at debugfs_rename+0x34/0x208
pc : [<
c0317238>] lr : [<
c047dfe4>] psr:
00000013
sp :
ef3a7b88 ip :
ef3a7ba8 fp :
ef3a7ba4
r10:
ef3d51cc r9 :
ef3bc680 r8 :
ef3d5210
r7 :
ef3bc640 r6 :
eee287e0 r5 :
eee287e0 r4 :
00000000
r3 :
ef3bc640 r2 :
00000000 r1 :
eee287e0 r0 :
00000000
Flags: nzcv IRQs on FIQs on Mode SVC_32 ISA ARM Segment user
Control:
10c5787d Table:
af3e406a DAC:
00000015
Process modprobe (pid: 52, stack limit = 0xef3a6240)
Stack: (0xef3a7b88 to 0xef3a8000)
7b80:
ef3bc640 ee4047e0 00000000 eee287e0 ef3a7bec ef3a7ba8
7ba0:
c047dfe4 c0317220 ef3bc680 ef3d51cc ef3a7bdc ef3a7bc0 c06e29d0 c0268784
7bc0:
c08946e8 ef3d5210 00000000 ef3bc700 ef3d5290 ef3d5210 ef3bc680 ef3d51cc
7be0:
ef3a7c0c ef3a7bf0 c05b9e9c c047dfbc 00000000 00000000 ef3d5210 ef3d5290
7c00:
ef3a7c24 ef3a7c10 c05baebc c05b9e30 00000001 00000001 ef3a7c64 ef3a7c28
7c20:
c05bb124 c05bae9c bf000cd8 ef3bc7c0 000000d0 c0ff129c bf001774 00000002
7c40:
ef3bc740 ef3d5290 ef0f9a10 bf001774 bf00042c 00000061 ef3a7c8c ef3a7c68
7c60:
c05bb480 c05baed8 bf001774 ef3d5290 ef0f9a10 bf001774 ef38bc10 ef0f9a00
7c80:
ef3a7cac ef3a7c90 c05bb5a8 c05bb3a0 bf001774 00000062 ef0f9a10 ef38bc18
7ca0:
ef3a7cec ef3a7cb0 bf00010c c05bb56c 00000000 ef38ba00 00000000 ef3d60d0
7cc0:
ef3a7cdc c0fefc24 ef0f9a10 c0a091c0 bf000d24 00000000 bf0029f0 bf006000
7ce0:
ef3a7cfc ef3a7cf0 c05156c0 bf000040 ef3a7d2c ef3a7d00 c0513f5c c05156a8
7d00:
ef3a7d2c ef0f9a10 ef0f9a10 bf000d24 ef0f9a44 c09ca588 00000000 bf006000
7d20:
ef3a7d4c ef3a7d30 c05142b8 c0513ecc ef0fd25c 00000000 bf000d24 c0514214
7d40:
ef3a7d74 ef3a7d50 c0512030 c0514220 ef0050a8 ef0fd250 ef0050f8 bf000d24
7d60:
ef37c100 c09ed150 ef3a7d84 ef3a7d78 c05139c8 c0511fd8 ef3a7
7d80:
c051344c c05139a8 bf000864 c09ca588 ef3a7db4 bf000d24 bf002
7da0:
c09ca588 00000000 ef3a7dcc ef3a7db8 c05149dc c0513360 ef3a7
7dc0:
ef3a7ddc ef3a7dd0 c0515914 c0514960 ef3a7dec ef3a7de0 bf006
7de0:
ef3a7e74 ef3a7df0 c0208800 bf00600c ef3a7e1c ef3a7e00 c04c5
7e00:
ffffffff c09d46c4 00000000 bf0029a8 ef3a7e34 ef3a7e20 c024c
7e20:
ffffffff c09d46c4 ef3a7e5c ef3a7e38 c024e2fc c024ce40 00000
7e40:
ef3a7f48 bf0029b4 bf0029a8 271aeb1c ef3a7f48 bf0029a8 00000001 ef383c00
7e60:
bf0029f0 00000001 ef3a7f3c ef3a7e78 c028fac4 c0208718 bf0029b4 00007fff
7e80:
c028cd58 000000d2 f0065000 00000000 ef3a7ebc 00000000 00000000 bf0029b4
7ea0:
00000000 bf0029ac bf0029b4 ef3a6000 ef3a7efc c08bf128 00000000 00000000
7ec0:
00000000 00000000 00000000 00000000 6e72656b 00006c65 00000000 00000000
7ee0:
00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
7f00:
00000000 00000000 00000000 271aeb1c ef3a7f2c 00016376 b6f38008 001d3774
7f20:
00000080 c020f968 ef3a6000 00000000 ef3a7fa4 ef3a7f40 c02904dc c028e178
7f40:
c020f898 010ccfa8 f0065000 00016376 f0073f60 f0073d7d f007a1e8 00002b24
7f60:
000039e4 00000000 00000000 00000000 0000002f 00000030 00000019 00000016
7f80:
00000012 00000000 00000000 010de1b2 b6f38008 010ccfa8 00000000 ef3a7fa8
7fa0:
c020f6c0 c0290434 010de1b2 b6f38008 b6f38008 00016376 001d3774 00000000
7fc0:
010de1b2 b6f38008 010ccfa8 00000080 010de1b2 bedb6f90 010de1c9 0001d8dc
7fe0:
0000000c bedb674c 0001ce30 000094c4 60000010 b6f38008 00000008 0000001d
[<
c0317238>] (lock_rename+0x24/0xc4) from [<
c047dfe4>] (debugfs_rename+0x34/0x208)
[<
c047dfe4>] (debugfs_rename+0x34/0x208) from [<
c05b9e9c>] (clk_debug_reparent+0x78/0xc0)
[<
c05baebc>] (__clk_reparent+0x2c/0x3c) from [<
c05bb124>] (__clk_init+0x258/0x4c8)
[<
c05bb124>] (__clk_init+0x258/0x4c8) from [<
c05bb480>] (_clk_register+0xec/0x1cc)
[<
c05bb480>] (_clk_register+0xec/0x1cc) from [<
c05bb5a8>] (devm_clk_register+0x48/0x7c)
[<
c05bb5a8>] (devm_clk_register+0x48/0x7c) from [<
bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960])
[<
bf00010c>] (msm_mmcc_8960_probe+0xd8/0x190 [mmcc_8960]) from [<
c05156c0>] (platform_drv_probe+0x24/0x28)
[<
c05156c0>] (platform_drv_probe+0x24/0x28) from [<
c0513f5c>] (driver_probe_device+0x9c/0x354)
[<
c0513f5c>] (driver_probe_device+0x9c/0x354) from [<
c05142b8>] (__driver_attach+0xa4/0xa8)
[<
c05142b8>] (__driver_attach+0xa4/0xa8) from [<
c0512030>] (bus_for_each_dev+0x64/0x98)
[<
c0512030>] (bus_for_each_dev+0x64/0x98) from [<
c05139c8>] (driver_attach+0x2c/0x30)
[<
c05139c8>] (driver_attach+0x2c/0x30) from [<
c051344c>] (bus_add_driver+0xf8/0x2a8)
[<
c051344c>] (bus_add_driver+0xf8/0x2a8) from [<
c05149dc>] (driver_register+0x88/0x104)
[<
c05149dc>] (driver_register+0x88/0x104) from [<
c0515914>] (__platform_driver_register+0x58/0x6c)
[<
c0515914>] (__platform_driver_register+0x58/0x6c) from [<
bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960])
[<
bf006018>] (msm_mmcc_8960_driver_init+0x18/0x24 [mmcc_8960]) from [<
c0208800>] (do_one_initcall+0xf4/0x1b8)
[<
c0208800>] (do_one_initcall+0xf4/0x1b8) from [<
c028fac4>] (load_module+0x1958/0x22bc)
[<
c028fac4>] (load_module+0x1958/0x22bc) from [<
c02904dc>] (SyS_init_module+0xb4/0x120)
[<
c02904dc>] (SyS_init_module+0xb4/0x120) from [<
c020f6c0>] (ret_fast_syscall+0x0/0x48)
Code:
e1500001 e1a04000 e1a05001 0a000021 (
e5903028)
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Takashi Yoshii [Tue, 8 Oct 2013 05:32:17 +0000 (14:32 +0900)]
clk: emev2: Add support for emev2 SMU clocks with DT
Device tree clock binding document for EMMA Mobile EV2 SMU,
And Common clock framework based implementation of it.
Following nodes are defined to describe clock tree.
- renesas,emev2-smu
- renesas,emev2-smu-clkdiv
- renesas,emev2-smu-gclk
These bindings are designed manually based on
19UH0037EJ1000_SMU : System Management Unit User's Manual
So far, reparent is not implemented, and is fixed to index #0.
Clock tree description is not included, and should be provided
by device-tree.
Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Ulf Hansson [Tue, 12 Nov 2013 10:41:12 +0000 (11:41 +0100)]
MAINTAINERS: Add maintainer for the ARM Ux500 clock driver
Cc: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Mike Turquette [Fri, 13 Dec 2013 03:32:07 +0000 (19:32 -0800)]
Merge tag 'clk-hisilicon' of git://git./linux/kernel/git/hzhuang1/linux into clk-next-hisilicon
Mike Turquette [Fri, 13 Dec 2013 03:29:03 +0000 (19:29 -0800)]
Merge branch 'clk-next-shmobile' into clk-next
Laurent Pinchart [Thu, 17 Oct 2013 21:54:07 +0000 (23:54 +0200)]
clk: shmobile: Add MSTP clock support
MSTP clocks are gate clocks controlled through a register that handles
up to 32 clocks. The register is often sparsely populated.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Laurent Pinchart [Thu, 17 Oct 2013 21:54:07 +0000 (23:54 +0200)]
clk: shmobile: Add DIV6 clock support
DIV6 clocks are divider gate clocks controlled through a single
register. The divider is expressed on 6 bits, hence the name, and can
take values from 1/1 to 1/64.
Those clocks are found on Renesas ARM SoCs.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Laurent Pinchart [Wed, 6 Nov 2013 12:14:19 +0000 (13:14 +0100)]
clk: shmobile: Add R-Car Gen2 clocks support
The R-Car Gen2 SoCs (R8A7790 and R8A7791) have several clocks that are
too custom to be supported in a generic driver. Those clocks can be
divided in two categories:
- Fixed rate clocks with multiplier and divisor set according to boot
mode configuration
- Custom divider clocks with SoC-specific divider values
This driver supports both.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Haojian Zhuang [Wed, 11 Dec 2013 05:07:55 +0000 (13:07 +0800)]
clk: hi3620: add gate clock flag
Add missing CLK_SET_RATE_PARENT flag for gate clock.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Haojian Zhuang [Wed, 11 Dec 2013 02:30:29 +0000 (10:30 +0800)]
clk: hi3620: fix wrong flags on divider
The flags on dividers should be CLK_DIVIDER_HIWORD_MASK, not
CLK_MUX_HIWORD_MASK.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Grygorii Strashko [Sat, 23 Nov 2013 21:31:12 +0000 (16:31 -0500)]
clk: keystone: gate: fix error handling on init
This patch fixes Keystone gate control clock driver initialization path:
1) clk_register_psc() returns error code and not a pure pointer, hence
its return value need to be checked using IS_ERR(clk) macro.
2) Mapped IO memory isn't unmapped in case of errors, hence fix it.
Cc: Mike Turquette <mturquette@linaro.org
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Murali Karicheri [Sat, 23 Nov 2013 21:26:52 +0000 (16:26 -0500)]
clk: keystone: use clkod register bits for postdiv
DDR3A/B, ARM and PA PLL controllers have clkod register bits for
configuring postdiv values. So use it instead of using fixed
post dividers for these pll controllers. Assume that if fixed-postdiv
attribute is not present, use clkod register value for pistdiv.
Also update the Documentation of bindings to reflect the same.
Cc: Mike Turquette <mturquette@linaro.org
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Mike Turquette [Wed, 4 Dec 2013 20:14:59 +0000 (12:14 -0800)]
Merge branch 'clk/clk-unregister' of git://linuxtv.org/snawrocki/samsung into clk-next-unregister
Chander Kashyap [Thu, 26 Sep 2013 09:06:35 +0000 (14:36 +0530)]
clk: exynos5420: fix cpll clock register offsets
Fixes cpll control and lock register offset values for Exynos5420 SoC.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Sylwester Nawrocki [Sat, 24 Aug 2013 13:00:10 +0000 (15:00 +0200)]
clk: Implement clk_unregister
clk_unregister() is currently not implemented and it is required when
a clock provider module needs to be unloaded.
Normally the clock supplier module is prevented to be unloaded by
taking reference on the module in clk_get().
For cases when the clock supplier module deinitializes despite the
consumers of its clocks holding a reference on the module, e.g. when
the driver is unbound through "unbind" sysfs attribute, there are
empty clock ops added. These ops are assigned temporarily to struct
clk and used until all consumers release the clock, to avoid invoking
callbacks from the module which just got removed.
Signed-off-by: Jiada Wang <jiada_wang@mentor.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Sylwester Nawrocki [Sat, 24 Aug 2013 18:10:41 +0000 (20:10 +0200)]
clk: Add common __clk_get(), __clk_put() implementations
This patch adds common __clk_get(), __clk_put() clkdev helpers that
replace their platform specific counterparts when the common clock
API is used.
The owner module pointer field is added to struct clk so a reference
to the clock supplier module can be taken by the clock consumers.
The owner module is assigned while the clock is being registered,
in functions _clk_register() and __clk_register().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Fri, 23 Aug 2013 15:03:44 +0000 (17:03 +0200)]
clkdev: Fix race condition in clock lookup from device tree
There is currently a race condition in the device tree part of clk_get()
function, since the pointer returned from of_clk_get_by_name() may become
invalid before __clk_get() call. E.g. due to the clock provider driver
remove() callback being called in between of_clk_get_by_name() and
__clk_get().
Fix this by doing both the look up and __clk_get() operations with the
clock providers list mutex held. This ensures that the clock pointer
returned from __of_clk_get_from_provider() call and passed to __clk_get()
is valid, as long as the clock supplier module first removes its clock
provider instance and then does clk_unregister() on the corresponding
clocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Fri, 23 Aug 2013 15:03:43 +0000 (17:03 +0200)]
clk: Provide not locked variant of of_clk_get_from_provider()
Add helper functions for the of_clk_providers list locking and
an unlocked variant of of_clk_get_from_provider().
These functions are intended to be used in the clkdev to avoid
race condition in the device tree based clock look up in clk_get().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Russell King <rmk+kernel@arm.linux.org.uk>
Sylwester Nawrocki [Tue, 29 Oct 2013 19:51:04 +0000 (20:51 +0100)]
omap3isp: Modify clocks registration to avoid circular references
The clock core code is going to be modified so clk_get() takes
reference on the clock provider module. Until the potential circular
reference issue is properly addressed, we pass NULL as the first
argument to clk_register(), in order to disallow sub-devices taking
a reference on the ISP module back trough clk_get(). This should
prevent locking the modules in memory.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Haojian Zhuang [Wed, 13 Nov 2013 00:51:23 +0000 (08:51 +0800)]
clk: hisilicon: add common clock support
Enable common clock driver of Hi3620 SoC. clkgate-seperated driver is
used to support the clock gate that enable/disable/status registers
are seperated.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Mike Turquette [Tue, 3 Dec 2013 19:47:56 +0000 (11:47 -0800)]
Merge branch 'clk-tegra-next' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next-tegra
Mike Turquette [Sun, 1 Dec 2013 20:42:45 +0000 (12:42 -0800)]
Merge tag 'sunxi-clk-for-3.13' of https://github.com/mripard/linux into clk-next-sunxi-rebase
Allwinner sunXi SoCs clock changes
Those are mostly random fixes, except for one patch to the composite
clock that adds support for automatic reparenting.
Conflicts:
drivers/clk/sunxi/clk-sunxi.c
Wei Yongjun [Tue, 29 Oct 2013 02:07:57 +0000 (03:07 +0100)]
clk: tegra: fix __clk_lookup() return value checks
In case of error, the function __clk_lookup() returns NULL pointer
not ERR_PTR(). The IS_ERR() test in the return value check should
be replaced with NULL test.
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Thierry Reding [Wed, 27 Nov 2013 16:26:03 +0000 (17:26 +0100)]
clk: tegra: Do not print errors for clk_round_rate()
clk_round_rate() can be used by drivers to determine whether or not a
frequency is supported by the clock. The current Tegra clock driver
outputs an error message and a stacktrace when the requested rate isn't
supported. That's fine for clk_set_rate(), but it's confusing when all
the driver does is query whether or not a frequency is supported.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Dinh Nguyen [Thu, 24 Oct 2013 08:18:30 +0000 (03:18 -0500)]
clk: socfpga: Remove check for "reg" property in socfpga_clk_init
The function socfpga_clk_init() can support clocks that do not have a divider
register, but a fixed-divider that can be read from DTS. Therefore, the "reg"
property is not a failing condition for socfpga_clk_init().
Signed-off-by: Dinh Nguyen <dinguyen@altera.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Ezequiel Garcia [Wed, 25 Sep 2013 19:10:18 +0000 (16:10 -0300)]
clk: fixed-factor: Fix device-tree binding typo
The required properties are not named "div" and "mult",
but rather "clock-div" and "clock-mult".
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Alex Elder [Wed, 27 Nov 2013 15:39:49 +0000 (09:39 -0600)]
clk: clean up everything on debugfs error
[Maybe the third time will be the charm. -Alex]
If CONFIG_COMMON_CLK_DEBUG is defined, clk_debug_create_one() is
called to populate a debugfs directory with a few entries that are
common for all clock types.
If an error happens after creating the first one debugfs_remove() is
called on the clock's directory. The problem with this is that no
cleanup is done on the debugfs files already created in that
directory, so the directory never actually gets removed. This
problem is silently ignored.
Fix this by calling debugfs_remove_recursive() instead. Reset the
clk->dentry field to null afterward, to ensure it can't be mistaken
as a valid pointer.
Signed-off-by: Alex Elder <elder@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Thierry Reding [Mon, 18 Nov 2013 15:11:36 +0000 (16:11 +0100)]
clk: tegra: Initialize DSI low-power clocks
The low-power DSI clocks are used during host-driven transactions on the
DSI bus. Documentation recommends that they be children of PLLP and run
at a frequency of at least 52 MHz.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Alexandre Courbot [Thu, 21 Nov 2013 02:38:10 +0000 (03:38 +0100)]
clk: tegra: add FUSE clock device
This clock is needed to ensure the FUSE registers can be accessed
without freezing the system.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
Thierry Reding [Tue, 29 Oct 2013 15:51:12 +0000 (16:51 +0100)]
clk: tegra: Properly setup PWM clock on Tegra30
The clock for the PWM controller is slightly different from other
peripheral clocks on Tegra30. The clock source mux field start at
bit position 28 rather than 30.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Thierry Reding [Tue, 29 Oct 2013 15:51:11 +0000 (16:51 +0100)]
clk: tegra: Initialize secondary gr3d clock on Tegra30
There are two GPUs on Tegra30 and each of them uses a separate clock, so
the secondary clock needs to be initialized in order for the gr3d module
to work properly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Mikko Perttunen [Tue, 29 Oct 2013 15:51:10 +0000 (16:51 +0100)]
clk: tegra114: Initialize clocks needed for HDMI
Add disp1 and disp2 clocks to the clock initialization table. These
clocks are required for display and HDMI support.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Joseph Lo [Thu, 26 Sep 2013 09:46:23 +0000 (17:46 +0800)]
clk: tegra124: add suspend/resume function for tegra_cpu_car_ops
Adding suspend/resume function for tegra_cpu_car_ops. We only save and
restore the setting of the clock of CoreSight. Other clocks still need
to be taken care by clock driver.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Joseph Lo [Wed, 25 Sep 2013 09:27:51 +0000 (17:27 +0800)]
clk: tegra124: add wait_for_reset and disable_clock for tegra_cpu_car_ops
Hook the functions for CPU hotplug support. After the CPU is hot
unplugged, the flow controller will handle to clock gate the CPU clock.
But still need to implement an empty function to avoid warning message.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Peter De Schrijver [Mon, 9 Sep 2013 10:23:56 +0000 (13:23 +0300)]
clk: tegra124: Add support for Tegra124 clocks
Implement clock support for Tegra124.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 14 Oct 2013 15:53:10 +0000 (18:53 +0300)]
clk: tegra124: Add new peripheral clocks
Tegra124 introduces a number of new peripheral clocks. This patch adds those
to the common peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 14 Oct 2013 15:52:25 +0000 (18:52 +0300)]
clk: tegra124: Add common clk IDs to clk-id.h
Tegra124 introduces a number of a new clocks. Introduce the corresponding
the IDs for them.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 18 Nov 2013 15:11:38 +0000 (16:11 +0100)]
clk: tegra: add TEGRA_PERIPH_NO_GATE
Tegra124 has a clock which consists of a mux and a fractional divider.
Add support for this.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Peter De Schrijver [Mon, 18 Nov 2013 15:11:37 +0000 (16:11 +0100)]
clk: tegra: add locking to periph clks
Tegra124 has periph clocks which share the hw register. Hence locking is
required.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Peter De Schrijver [Wed, 11 Sep 2013 14:57:37 +0000 (17:57 +0300)]
clk: tegra: Add periph regs bank X
Tegra124 has an extra bank of peripheral clock registers. Add it to the
generic peripheral clock code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 9 Sep 2013 10:22:55 +0000 (13:22 +0300)]
clk: tegra: Add support for PLLSS
Tegra124 introduces a new PLL type, PLLSS. Add support for it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 7 Oct 2013 11:49:10 +0000 (14:49 +0300)]
clk: tegra: move tegra20 to common infra
Move tegra20 to common tegra clock infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 7 Oct 2013 11:49:04 +0000 (14:49 +0300)]
clk: tegra: move tegra30 to common infra
Move tegra30 to common tegra clock infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Tue, 3 Sep 2013 12:46:01 +0000 (15:46 +0300)]
clk: tegra: introduce common gen4 super clock
Introduce a common function which performs super clock initialization for
Tegra114 and beyond.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Tue, 15 Oct 2013 14:19:13 +0000 (17:19 +0300)]
clk: tegra: move PMC, fixed clocks to common files
Introduce new files for fixed and PMC clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Wed, 4 Sep 2013 14:04:19 +0000 (17:04 +0300)]
clk: tegra: move periph clocks to common file
Introduce a new file for peripheral clocks common between several Tegra
SoCs and move Tegra114 to this new infrastructure. Also PLLP and the PLLP_OUT
clocks will be initialized here.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Tue, 17 Sep 2013 12:42:24 +0000 (15:42 +0300)]
clk: tegra: move audio clk to common file
Move audio clocks and PLLA initialization to a common file so it can be used by
multiple Tegra SoCs. Also a new array tegra114_clks is introduced for Tegra114
which specifies which common clocks are available on Tegra114 and what their
DT IDs are.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Wed, 9 Oct 2013 11:47:57 +0000 (14:47 +0300)]
clk: tegra: add clkdev registration infra
Add a common infra for registering clkdev. This allows decoupling clk
registration from clkdev registration.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 14 Oct 2013 13:47:37 +0000 (16:47 +0300)]
clk: tegra: add common infra for DT clocks
Introduce a common infrastructure for sharing clock initialization between
SoCs.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 2 Sep 2013 12:09:08 +0000 (15:09 +0300)]
clk: tegra: add header for common tegra clock IDs
Many clocks are common between several Tegra SoCs. Define an enum to list
them so we can move them to separate files which can be shared between
SoCs. Each SoC specific file will provide an array with the common clocks
which are present on the SoC and their DT binding ID.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Fri, 4 Oct 2013 14:28:34 +0000 (17:28 +0300)]
clk: tegra: move fields to tegra_clk_pll_params
Move some fields related to the PLL HW description to the tegra_clk_pll_params.
This allows some PLL code to be moved to common files later.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 25 Nov 2013 12:44:13 +0000 (14:44 +0200)]
clk: tegra: use pll_ref as the pll_e parent
Use pll_ref instead of pll_re_vco as the pll_e parent on Tegra114. Also
add a 12Mhz pll_ref table entry for pll_e for Tegra114. This prevents
the system from crashing at bootup because of an unsupported pll_re_vco
rate.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Fri, 6 Sep 2013 11:37:37 +0000 (14:37 +0300)]
clk: tegra: move some PLLC and PLLXC init to clk-pll.c
VCO min clipping, dynamic ramp setup and IDDQ init can be done in the
respective PLL clk_register functions if the parent is already registered.
This is done for other some PLLs already.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 2 Sep 2013 15:43:56 +0000 (18:43 +0300)]
clk: tegra: Add TEGRA_PERIPH_NO_DIV flag
This flag indicates the peripheral clock does not have a divider. It will
simplify the initialization tables and avoids some very similar code.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Mon, 2 Sep 2013 12:22:02 +0000 (15:22 +0300)]
clk: tegra: common periph_clk_enb_refcnt and clks
This patch makes periph_clk_enb_refcnt a global array, dynamically allocated
at boottime. It simplifies the macros somewhat and allows clocks common to
several Tegra SoCs to be defined in a separate files. Also the clks array
becomes global and dynamically allocated which allows the DT registration to
be moved to a generic funcion.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Thu, 22 Aug 2013 15:44:06 +0000 (18:44 +0300)]
clk: tegra: simplify periph clock data
This patch determines the register bank for clock enable/disable and reset
based on the clock ID instead of hardcoding it in the tables describing the
clocks. This results in less data to be maintained in the tables, making the
code easier to understand. The full benefit of the change will be realized once
also other clocktypes will be table based.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Thierry Reding [Mon, 18 Nov 2013 15:11:35 +0000 (16:11 +0100)]
clk: tegra: Fix clock rate computation
The PLL output frequency is multiplied during the P-divider computation,
so it needs to be divided by the P-divider again before returning.
This fixes an issue where clk_round_rate() would return the multiplied
frequency instead of the real one after the P-divider.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Peter De Schrijver [Fri, 11 Oct 2013 13:52:14 +0000 (16:52 +0300)]
ARM: tegra30: add missing CLK IDs
The Tegra30 clock bindings lack few IDs for audio and clk_out muxes.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Thierry Reding [Wed, 2 Oct 2013 21:12:40 +0000 (23:12 +0200)]
clk: tegra114: Rename gr_2d/gr_3d to gr2d/gr3d
These clocks were named gr2d and gr3d on Tegra20 and Tegra30, so use the
same names on Tegra114 for consistency.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Peter De Schrijver [Thu, 26 Sep 2013 15:30:01 +0000 (18:30 +0300)]
clk: tegra: PLLE spread spectrum control
Add spread spectrum control for PLLE in Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Andrew Chew [Wed, 7 Aug 2013 11:25:09 +0000 (19:25 +0800)]
clk: tegra: Set the clk parent of host1x to pll_p
The power-on default parent for this clock is pll_m, which turns out to
be wrong. Previously, bootloader reparented this clock. We'll do it in
the kernel as well, so that there's one less thing that we depend on
bootloader to initialize.
Signed-off-by: Andrew Chew <achew@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
Peter De Schrijver [Tue, 26 Nov 2013 11:48:09 +0000 (13:48 +0200)]
clk: tegra: add TEGRA_DIVIDER_ROUND_UP for periph clks
Perform upwards rounding when calculating dividers for periph clks on Tegra30
and Tegra114.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Mark Zhang [Wed, 7 Aug 2013 11:25:08 +0000 (19:25 +0800)]
clk: tegra: Set the clock parent of gr2d/gr3d to pll_c2
pll_m will be the parent of gr2d/gr3d if we don't do this.
And because pll_m runs at a high rate so gr2d/gr3d will be
unstable. So change the parent of them to pll_c2.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Mark Zhang [Wed, 7 Aug 2013 11:25:07 +0000 (19:25 +0800)]
clk: tegra: Fix vde/2d/3d clock src offset
In Tegra114, vde/gr_2d/gr_3d have 3 bits for clock source selection.
So change the clock init macro for these clocks from
"TEGRA_INIT_DATA_INT" to "TEGRA_INIT_DATA_INT8".
Besides, no one uses "TEGRA_INIT_DATA_INT" after this change, so
remove this macro.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Mark Zhang [Thu, 8 Aug 2013 05:55:27 +0000 (13:55 +0800)]
clk: tegra: Correct sbc mux width & parent
Tegra114 sbc1-sbc6 have more possible parent clocks than Tegra30.
So correct the parents and mux width for them.
Signed-off-by: Mark Zhang <markz@nvidia.com>
Acked-by: Stephen Warren <swarren@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Thu, 22 Aug 2013 12:27:46 +0000 (15:27 +0300)]
clk: tegra: replace enum tegra114_clk by binding header
As the clock IDs are now specified in a header file, we can use those
definitions instead of maintaining an internal enum.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Peter De Schrijver [Thu, 22 Aug 2013 12:19:30 +0000 (15:19 +0300)]
ARM: tegra114: add missing clocks to binding
commit
992bb598f690542a2f539fd12a42b960b7692025 forgot to move dfll_soc and
dfll_ref to include/dt-bindings/clock/tegra114-car.h. Add them again in this
patch as TEGRA114_CLK_DFLL_SOC and TEGRA114_CLK_DFLL_REF.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Ezequiel Garcia [Thu, 26 Sep 2013 19:35:27 +0000 (16:35 -0300)]
clk: mvebu: Add Core Divider clock
This commit introduces a new group of clocks present in Armada 370/XP
SoCs (called "Core Divider" clocks) and add a provider for them.
The only clock supported for now is the NAND clock (ndclk), but the
infrastructure to add the rest is already set.
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Jisheng Zhang [Thu, 7 Nov 2013 08:59:33 +0000 (16:59 +0800)]
clk: mvebu: staticize of_cpu_clk_setup
This symbol is used only in this file. The patch fix the following
sparse warning:
warning: symbol 'of_cpu_clk_setup' was not declared. Should it be static?
Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Linus Torvalds [Fri, 22 Nov 2013 19:30:55 +0000 (11:30 -0800)]
Linux 3.13-rc1