panfrost: Set texel_interleave on Valhall

Instead of specifying the tiling on the texture descriptor, Valhall specifies it
on the plane descriptor. There is a new flag on the texture descriptor
specifying only whether the planes are interleaved or not.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Adapt estimate_texture_payload_size to Valhall

The plane descriptor is larger than earlier surface descriptors, so we need to
be somewhat careful here. This removes a memory micro-optimization in the
interest of simplifying the code.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Don't emit compression tags on Valhall

Unnecessary. To avoid even more #if/#endif soup, merge the v4, v5-v8, and v9
paths together -- by returning 0 as the compression tag on v4 or v9.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Allow uploading fragment SPDs

SPDs don't have the state dependence that fragment RSDs do.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Don't pack blend constants with blend shaders

It's probably harmless, but it is logically meaningless. The DDK doesn't do it,
I don't see a reason for us to, either. In theory this should be a small
overhead win.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Generalize some is_bifrost users

Valhall would want these too. Regretting the is_bifrost check at all..

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Add PAN_MESA_DEBUG=dump option

To dump all graphics memory via the new pandecode_dump_mappings function(),
since for Valhall I have to do this often enough to warrant a dynamic flag.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Rename prepare_rsd->prepare_shader

This hook will be repurposed on Valhall to prepare the Shader Program
Descriptor, which takes the role of the RSD. Rename to avoid confusion.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Add an enum for Valhall resource tables

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Make Divisor E an integer on v9

For consistency with previous architecture's XML files. Logically this is an
1-bit unsigned integer, not a boolean.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Clarify contains descriptor? bit

Influences cache prefetching. I don't see a good reason to put anything other
than descriptors inside shader resources, meaning always setting this bit is
appropriate (at least for GLES).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Remove Invalidate Cache from Valhall job header

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Add Tile Render Order enum to fragment jobs

Not sure what this is needed for yet.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

panfrost: Extend SPD size

There is software-defined state at the end we don't need. Model in the XML for
correct behaviour.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15204>

radeonsi: add check for graphics to si_try_normal_clear

Cc: mesa-stable
Signed-off-by: Thong Thai <thong.thai@amd.com>
Acked-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15177>

anv: fix fast clear type value with external images

Disable fast clear if not supported by the external modifier.

v2: Set fast_clear value to NONE in case of import/export from/to external

v3: Move logic next to existing acquire/release checks (Nanley)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6056
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15096>

venus: Implement guest vram blob type.

Add support of GUEST_VRAM type of blob. These are dedicated heap memory
allocations required for vk support on hypervisors that don't support
runtime injections of host memory into guest physical address space.

The flow of usage:
1) Host VM reserves dedicated heap memory
2) Device get info about memory reservations and report it to guest
using mmio registers
3) Guest virtio-gpu driver on starts checks mmio registers for
physical address and length of reserved region. Then it reserves it
in guest.
4) On each call of vkAllocateMemory() guest driver gets chunk of
required memory and send it to host using sg list. It uses one sg
entry for 1 blob call. Heap is managed on guest using drm memory
manager (drm_mm).

Signed-off-by: Oleksandr.Gabrylchuk <Oleksandr.Gabrylchuk@opensynergy.com>
Signed-off-by: Andrii Pauk <Andrii.Pauk@opensynergy.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14536>

amd: update addrlib

Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>

amd: add support for gfx1036 and gfx1037 chips

Both are identified as GFX1036 for simplicity.

Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>

ac: set correct cache size per TCC for Yellow Carp

Reviewed-by: Yifan Zhang <yifan1.zhang@amd.com>
Tested-by: Yifan Zhang <yifan1.zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15155>

radv: disable DCC for Fable Anniversary, Dragons Dogma, GTA IV and more

Also Starcraft 2 and The Force Unleashed II.

These games are known to be affected by the feedback loop issue. We will
fix this properly soon but as a hotfix disabling DCC should be enough.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4424
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15203>

iris: Do not apply SCANOUT allocation flags for SHARED-only requests

It provides similar solution as in [1].

This was workaround for the users of gbm_bo_create_with_modifiers(),
which were unable to specify the buffer usage (GPU / GPU+DISPLAY).

But after the commit [2] this become possible. And forcing usage to
GBM_BO_USE_SCANOUT migrated directly into gbm_bo_create_with_modifiers
[3], allowing us to remove such workarounds from the drivers.

[1]: ef3b31c9 ("v3d: Don't force SCANOUT for PIPE_BIND_SHARED requests")
[2]: 268e12c6 ("gbm: add gbm_{bo,surface}_create_with_modifiers2")
[3]: ad50b47a ("gbm: assume USE_SCANOUT in create_with_modifiers")

Suggested-by: Roman Stratiienko <roman.o.stratiienko@globallogic.com>
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5642
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14264>

ac/nir: Extract final mesh shader output counts to a separate function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>

aco: Remove superfluous code for mesh shader workgroup ID.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>

ac/nir: Properly invalidate mesh shader metadata.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>

ac/nir: Fix workgroup ID in mesh shader waves other than the first.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>

ac/nir: Store mesh shader API and HW workgroup size in lowering state.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>

ac/nir: Reuse existing nir_builder for emit_ms_finale.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>

ac/nir: Use vertex count minus 1 to determine max index in mesh shaders.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15199>

ci, valve: Add the dEQP runners for Valve CI

v2.

  - Build the runner image as part of the CI for the boot2container
  project, rather than as a manually step using the build instructions
  in valve-trigger.dockerfile.

  - Depend on a non-default kernel build hosted in the valve-infra
  package repository. This does reduce the current caching feature of
  local artifacts, but makes it easier to chop and change kernels on a
  per-project or even per-test basis.

v3.

  - Depend on a kernel built and stored in the valve-infra generic
  package repo.

  - Build the runner container using ci-templates as part of the CI in
  valve-infra.

  - Now that the runner container is built in the valve-infra CI, I
  dropped the source import of client.py and message.py. They are
  built in the runner container.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>

amd, ci: Categorize the sections of the CI file.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>

amd, ci: Drop log level in SPIRV -> NIR code generator.

See 786fa3435c for the rationale of this variable, but the point is to
avoid many error reports for conformance conformance issues within the
VK-CTS shaders.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>

amd, ci: Remove unused runners.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>

ci, valve: Add support scripts for the Valve bare-metal farm.

- Add the scripts to the prepared Mesa artifacts for use in later
runner stages.

- Add a template generator (generate_b2c.py) which reads and
validates (very lightly for now) the Gitlab job environment and then
spits out a YAML file describing the necessary test workload to be
sent to a Valve CI gateway.

Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14660>

radv: remove color exports in presence of holes

If there is holes, eg. if only MRT0 and MRT2 are exported, we have to
set MRT1 to SPI_SHADER_32_R to avoid a GPU hang but the export can
still be removed from the fragment shader.

fossils-db (Sienna Cichlid):
Totals from 565 (0.42% of 134913) affected shaders:
VGPRs: 13328 -> 11456 (-14.05%)
CodeSize: 613232 -> 548224 (-10.60%); split: -11.13%, +0.53%
LDS: 284672 -> 296960 (+4.32%)
MaxWaves: 17624 -> 17684 (+0.34%)
Instrs: 113056 -> 100445 (-11.15%); split: -11.68%, +0.53%
Latency: 684327 -> 639348 (-6.57%); split: -7.17%, +0.60%
InvThroughput: 122877 -> 104382 (-15.05%); split: -15.18%, +0.13%
VClause: 2601 -> 2323 (-10.69%); split: -10.77%, +0.08%
SClause: 5629 -> 5443 (-3.30%); split: -3.91%, +0.60%
Copies: 9393 -> 8720 (-7.16%); split: -8.22%, +1.05%
PreSGPRs: 14623 -> 13666 (-6.54%); split: -6.76%, +0.22%
PreVGPRs: 9847 -> 8503 (-13.65%)

fossils-db (Polaris10):
Totals from 565 (0.42% of 135960) affected shaders:
SGPRs: 28064 -> 27104 (-3.42%)
VGPRs: 12516 -> 10544 (-15.76%); split: -15.79%, +0.03%
CodeSize: 516920 -> 456536 (-11.68%); split: -11.68%, +0.00%
MaxWaves: 4369 -> 4418 (+1.12%)
Instrs: 97771 -> 85903 (-12.14%); split: -12.14%, +0.00%
Latency: 767482 -> 708545 (-7.68%); split: -7.97%, +0.29%
InvThroughput: 280017 -> 235744 (-15.81%)
VClause: 2270 -> 2090 (-7.93%); split: -8.50%, +0.57%
SClause: 5185 -> 5012 (-3.34%); split: -3.86%, +0.52%
Copies: 8328 -> 7555 (-9.28%); split: -9.35%, +0.07%
Branches: 1143 -> 1113 (-2.62%)
PreSGPRs: 13816 -> 12725 (-7.90%); split: -7.92%, +0.02%
PreVGPRs: 9707 -> 8270 (-14.80%)

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15108>

ac/nir: remove TCS nir_var_shader_out memory barrier

nir_var_shader_out writes are only used for later TES invocations, so I
don't think there's any need for the TCS workgroup to wait for them.

fossil-db (Sienna Cichlid):
Totals from 1691 (1.04% of 162293) affected shaders:
Instrs: 710699 -> 709008 (-0.24%)
CodeSize: 3830168 -> 3823404 (-0.18%)
Latency: 3396997 -> 3007934 (-11.45%)
InvThroughput: 1212094 -> 1082823 (-10.67%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15195>

intel/compiler: Lower Task/Mesh I/O before SIMD specific lowering

These are the same for all variants, so just lower it before cloning
the nir_shader for each of them.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15019>

turnip: Implement VK_EXT_physical_device_drm

Copied from ANV and V3DV.

v1. Fix a build error for clang "unannotated fall-through between switch labels"
( Hyunjun Ko <zzoon.ko@igalia.com> )

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6011

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14971>

radeonsi/drirc: use force_gl_vendor for Maya

Otherwise OpenCL initialization fails with "unknown vendor id 0".

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15151>

nouveau: add dEQP/GLCTS run failure info for GF108/GT215

I happened to have these plugged in. Ran them against mesa 21.3 and
recent VK-GL-CTS tree (shortly after vulkan-cts-1.2.8).

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Emma Anholt <emma@anholt.net>
Acked-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14797>

Revert "anv: Require the local heap for CCS on XeHP"

This reverts commit 382f6ccda8869f72134dbfa9c3cc68a229e01138.

The spec requires that all color images created with the same tiling
(and a few other properties) support the same memoryTypeBits. So this
wasn't a valid change. It also wasn't necessary - we already have a
mechanism in anv_BindImageMemory2 for disabling compression if the BO
doesn't support it.

With this, XeHP passes the tests in
dEQP-VK.memory.requirements.*tiling_optimal

Fixes: 382f6ccd ("anv: Require the local heap for CCS on XeHP")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>

anv: Add a perf warning in anv_BindImageMemory2

It reports: "BO lacks implicit CCS. Disabling the CCS aux usage."

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>

anv: Fall back to HiZ when disabling CCS on HiZ+CCS

When an image configured for HIZ_CCS/HIZ_CCS_WT is bound to a BO lacking
implicit CCS, we disable any compression it may have had. Such images
are still compatible with ISL_AUX_USAGE_HIZ however. Fall back to that
aux usage to retain the performance benefit.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>

anv: Don't disable HiZ/MCS in anv_BindImageMemory2

When an image is bound to a BO lacking implicit CCS, we disable any
compression it may have had. This is unnecessary in the cases where the
compression type doesn't depend on the BO having implicit CCS support.
Avoid this disabling for ISL_AUX_USAGE_MCS and ISL_AUX_USAGE_HIZ.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15068>

ir3: Use isam for bindless images

In the bindless case, we don't have to keep any shadow descriptors and
can just reuse the IBO descriptor as a texture descriptor. Now that
we're emitting the swizzle we can just flip this on.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>

tu: Call nir_opt_access

This adds some small optimizations, and enables lowering to isam in more
cases where the app didn't specify readonly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>

ir3/nir: Fix 1d array readonly images

ncoords includes the array index, and the NIR source has the array index
as its last component, so we have to insert the extra y coordinate in
the middle in this case.

Fixes: 0bb0cac ("freedreno/ir3: handle image buffer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>

ir3: Don't always set bindless_tex with readonly images

Fixes: 274f381 ("ir3: Plumb through bindless support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>

freedreno/fdl: Set swizzle on storage descriptor

It appears to be unused by ldib/stib, but it will let us use isam on IBO
descriptors for bindless images.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>

freedreno: Replace A6XX_IBO with A6XX_TEX_CONST

Since these were reverse-engineered, it's become clear that IBO
descriptors are just a subset of texture descriptors, and bindless reads
of readonly images actually use isam on the IBO descriptor, further
confirming that the two are always compatible, even if not all of the
texture fields exist for IBOs. It's pointless to have a separate type
for IBOs, and just leads to things getting out-of-sync unnecessarily
which has already happened. Just remove it and use TEX_CONST insted.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>

ir3: Use CAN_REORDER instead of NON_WRITEABLE

CAN_REORDER takes volatile into account, and is closer to what we
actually require to use texture instructions, which is that we can
arbitrarily reorder loads.

Fixes: aa93896 ("freedreno/ir3: adjust condition for when to use ldib")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15114>

turnip: Set drmFormatModifierTilingFeatures

From Vulkan spec for VkDrmFormatModifierProperties2EXT:

 "drmFormatModifierTilingFeatures is a bitmask of VkFormatFeatureFlagBits
  that are supported by any image created with format and drmFormatModifier."

 "The returned drmFormatModifierTilingFeatures must contain at least one bit."

 "Therefore, if the returned drmFormatModifier is DRM_FORMAT_MOD_LINEAR,
  then drmFormatModifierPlaneCount must equal the format planecount, and
  drmFormatModifierTilingFeatures must be identical to the
  VkFormatProperties2::linearTilingFeatures returned in the same pNext chain."

Relevant tests: dEQP-VK.drm_format_modifiers.*

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15032>

zink: add layer asserts for 3d imageview creation

make sure there's no other mishaps here in the future

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>

zink: more accurately clamp 3d fb surfaces to corresponding 2d target

if more than 1 layer is being bound, this is an array, otherwise it's just
regular 2d

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>

zink: clamp 3d/array shader images to lower dimensionality using layer counts

this creates the view type expected by the shader instead of doing weird stuff
like trying to create a 3D imageview with layers > 1

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>

zink: directly create surfaces for shader images

avoid the implicit clamping of fb surfaces in zink_create_surface()
in order to provide more granularity

no functional changes

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>

zink: restrict clear flushing on sampler/image bind to compute binds

this is otherwise going to be handled on the next renderpass start

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15172>

zink: use VK_EXT_depth_clip_control when available

this saves a few ALUs in vertex stages

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15174>

glx/drisw: handle GL_RESET_NOTIFICATION_STRATEGY

fixes (llvmpipe):
KHR-NoContext.gl45.robustness.lose_context_on_reset

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15061>

zink: update psiz handling to fix xfb output

now when gl_PointSize and gl_PointSizeMESA are both present, the former
will be used for xfb with a new location and the latter will be
exported by the shader

fixes (zink):
GTF-GL46.gtf30.GL3Tests.transform_feedback.transform_feedback_builtins

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15184>

nir/lower_psiz_mov: stop clobbering existing exports

for this pass to work with xfb, the original value in the shader must be
preserved when xfb is active, and the driver must export only the newly
created output

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15184>

nir/lower_psiz: create the store instruction more accurately

creating this at the start of the shader means it will get optimized out
when the pass is used to overwrite existing psiz values, and creating it
at the end means it will get optimized out in geometry shaders, so instead
just walk the instructions and create another store right after the existing one

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15184>

util: use correct type in sysctl argument

Fixes build on OpenBSD/macppc powerpc

error: incompatible pointer types passing 'int *' to parameter of type 'size_t *'
    (aka 'unsigned long *') [-Werror,-Wincompatible-pointer-types]

Fixes: 01bd21eef8f ("gallium: Import Dennis Smit cpu detection code.")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6511>

util: fix build with clang 10 on mips64

On mips64, the compiler does not allow use of non-zero argument with
__builtin_frame_address(). However, the returned frame address is only
used when PIPE_ARCH_X86 is defined. The compile error can be avoided
by making #ifdef PIPE_ARCH_X86 cover the getting of frame address too.

The argument checking of __builtin_frame_address() has been present
as a debug assert in clang 8. In clang 10, there is a proper runtime
check for the argument. This is why the build has not failed before.

Fixes: dc94a0506f1 ("gallium: Do not add -Wframe-address option for gcc <= 4.4.")
from Visa Hankala

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6511>

util/u_atomic: fix build on clang archs without 64-bit atomics

Make this build on clang architectures that don't have 64-bit atomic
instructions.  Clang doesn't allow redeclaration (and therefore
redefinition) of the __sync_* builtins.  Use #pragma redefine_extname
to work around that restriction.  Clang also turns __sync_add_and_fetch
into __sync_fetch_and_add (and __sync_sub_and_fetch into
__sync_fetch_and_sub) in certain cases, so provide these functions as
well.

Fixes: a6a38a038bd ("util/u_atomic: provide 64bit atomics where they're missing")
patch from Mark Kettenis

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6511>

Revert "CI: Disable Panfrost T720 jobs"

This reverts commit 35209b94a6c7d88fb67b6446fda8f8daf556c911.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15191>

Revert "CI: Disable panfrost-t760"

This reverts commit b9b444e0b8bc318cea2a93ec04b0a383c444180e.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15191>

panfrost: fix segfault in pandecode

The structure wrapped around the rb tree node was being freed, but not the node
itself, which caused a segmentation fault when accessing its parent node.

Add rb tree node remove call to fix it.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15188>

CI: Disable Panfrost T720 jobs

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15189>

CI: Disable panfrost-t760

The DUTs are extremely tempremental for some reason.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15186>

docs: update irc channel

According to the virglrenderer README.rst[1] file, #virgil3d has moved
from FreeNode to OFTC. Let's update our link as well.

While we're at it, use a proper link as well.

[1]: https://gitlab.freedesktop.org/virgl/virglrenderer/-/blob/master/README.rst

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: mark virgl gles2 renderer as done

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: update virgl description

Since this text was written, VirGL has become a shipping, production
quality solution. It's no longer a research project. Let's update the
text to reflect that.

While we're at it, let's drop the project from the page title, as this
is no longer the docs for the entire project.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: link to gitlab instead of cgit

While we're at it, let's update the releasing article as well.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: master -> main

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: Virgl -> VirGL

The name used for this project is usually stylized as VirGL instead of
"Virgil" or "Virgil 3D" these days. Let's be consistent.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: qemu -> QEMU

This is the official syling of the name, let's use that instead of
lower-case for consistensy.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: add missing get

This sentence doesn't make sense without a 'get' or something similar
here.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: remove a few repeated words

It doesn't make sense to repeat these, let's fix that.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

docs: import virgl docs

The docuentation has been imported verbatim from
https://virgil3d.github.io/.

Acked-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13836>

zink: don't free non-fbfetch dsl structs when switching to fbfetch

this triggers invalid access when recycling in-flight non-fbfetch sets

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

zink: free push descriptor pools on deinit

these are owned by the context, so destroy them when the context
requests destruction

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

zink: fix cached descriptor set invalidation for array bindings

need to iterate over the descriptors in the binding to invalidate the whole
thing here

=================================================================
==546534==ERROR: AddressSanitizer: heap-use-after-free on address 0x61a0000ae6c0 at pc 0x7fe20e26fd9d bp 0x7ffd92be6bc0 sp 0x7ffd92be6bb8
READ of size 8 at 0x61a0000ae6c0 thread T0
    #0 0x7fe20e26fd9c in zink_descriptor_set_refs_clear ../src/gallium/drivers/zink/zink_descriptors.c:950
    #1 0x7fe20e401304 in zink_destroy_surface ../src/gallium/drivers/zink/zink_surface.c:340
    #2 0x7fe20e21311b in zink_surface_reference ../src/gallium/drivers/zink/zink_surface.h:106
    #3 0x7fe20e21a5b9 in zink_sampler_view_destroy ../src/gallium/drivers/zink/zink_context.c:835
    #4 0x7fe20c41d35f in tc_sampler_view_destroy ../src/gallium/auxiliary/util/u_threaded_context.c:1848
    #5 0x7fe20e210ff7 in pipe_sampler_view_reference ../src/gallium/auxiliary/util/u_inlines.h:216
    #6 0x7fe20e22d592 in zink_set_sampler_views ../src/gallium/drivers/zink/zink_context.c:1532
    #7 0x7fe20c41a3d8 in tc_call_set_sampler_views ../src/gallium/auxiliary/util/u_threaded_context.c:1393
    #8 0x7fe20c411706 in tc_batch_execute ../src/gallium/auxiliary/util/u_threaded_context.c:211
    #9 0x7fe20c4124ba in _tc_sync ../src/gallium/auxiliary/util/u_threaded_context.c:362
    #10 0x7fe20c42b728 in tc_destroy ../src/gallium/auxiliary/util/u_threaded_context.c:4250
    #11 0x7fe20b65176a in st_destroy_context_priv ../src/mesa/state_tracker/st_context.c:387
    #12 0x7fe20b65669f in st_destroy_context ../src/mesa/state_tracker/st_context.c:1009
    #13 0x7fe20b7055ab in st_context_destroy ../src/mesa/state_tracker/st_manager.c:944
    #14 0x7fe20a9c75bd in dri_destroy_context ../src/gallium/frontends/dri/dri_context.c:256
    #15 0x7fe20a9d4bef in driDestroyContext ../src/gallium/frontends/dri/dri_util.c:534
    #16 0x7fe22361f25c in drisw_destroy_context ../src/glx/drisw_glx.c:429
    #17 0x7fe223625d95 in glXDestroyContext ../src/glx/glxcmds.c:523
    #18 0x7fe22636aaeb in glXDestroyContext /home/zmike/src/libglvnd-v1.3.2/src/GLX/libglx.c:332
    #19 0x7fe2269d9e7d in glXDestroyContext /home/zmike/src/libglvnd-v1.3.2/src/GL/g_libglglxwrapper.c:384
    #20 0x41b88a in tcu::lnx::x11::glx::GlxRenderContext::~GlxRenderContext() /home/zmike/src/VK-GL-CTS/framework/platform/lnx/X11/tcuLnxX11GlxPlatform.cpp:734
    #21 0x41b8e9 in tcu::lnx::x11::glx::GlxRenderContext::~GlxRenderContext() /home/zmike/src/VK-GL-CTS/framework/platform/lnx/X11/tcuLnxX11GlxPlatform.cpp:735
    #22 0x2323aa7 in deqp::gles31::Context::destroyRenderContext() /home/zmike/src/VK-GL-CTS/modules/gles31/tes31Context.cpp:77
    #23 0x2323969 in deqp::gles31::Context::~Context() /home/zmike/src/VK-GL-CTS/modules/gles31/tes31Context.cpp:55
    #24 0x232278e in deqp::gles31::TestPackage::deinit() /home/zmike/src/VK-GL-CTS/modules/gles31/tes31TestPackage.cpp:102
    #25 0x2c866c2 in tcu::DefaultHierarchyInflater::leaveTestPackage(tcu::TestPackage*) /home/zmike/src/VK-GL-CTS/framework/common/tcuTestHierarchyIterator.cpp:75
    #26 0x2c87058 in tcu::TestHierarchyIterator::next() /home/zmike/src/VK-GL-CTS/framework/common/tcuTestHierarchyIterator.cpp:252
    #27 0x2c365da in tcu::TestSessionExecutor::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuTestSessionExecutor.cpp:122
    #28 0x2c00b0c in tcu::App::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuApp.cpp:221
    #29 0x4141b7 in main /home/zmike/src/VK-GL-CTS/framework/platform/tcuMain.cpp:58
    #30 0x7fe2263e155f in __libc_start_call_main (/lib64/libc.so.6+0x2d55f)
    #31 0x7fe2263e160b in __libc_start_main_impl (/lib64/libc.so.6+0x2d60b)
    #32 0x413fa4 in _start (/home/zmike/src/VK-GL-CTS/build/external/openglcts/modules/glcts+0x413fa4)

0x61a0000ae6c0 is located 64 bytes inside of 1328-byte region [0x61a0000ae680,0x61a0000aebb0)
freed by thread T0 here:
    #0 0x7fe226cb6627 in free (/usr/lib64/libasan.so.6+0xae627)
    #1 0x7fe20aab1751 in unsafe_free ../src/util/ralloc.c:302
    #2 0x7fe20aab16c8 in unsafe_free ../src/util/ralloc.c:295
    #3 0x7fe20aab13c3 in ralloc_free ../src/util/ralloc.c:265
    #4 0x7fe20e269234 in descriptor_pool_free ../src/gallium/drivers/zink/zink_descriptors.c:286
    #5 0x7fe20e26937d in descriptor_pool_delete ../src/gallium/drivers/zink/zink_descriptors.c:296
    #6 0x7fe20e26ff53 in zink_descriptor_pool_reference ../src/gallium/drivers/zink/zink_descriptors.c:967
    #7 0x7fe20e270db2 in zink_descriptor_program_deinit ../src/gallium/drivers/zink/zink_descriptors.c:1071
    #8 0x7fe20e3b6536 in zink_destroy_gfx_program ../src/gallium/drivers/zink/zink_program.c:695
    #9 0x7fe20e1eaaf9 in zink_gfx_program_reference ../src/gallium/drivers/zink/zink_program.h:242
    #10 0x7fe20e20d386 in zink_shader_free ../src/gallium/drivers/zink/zink_compiler.c:2099
    #11 0x7fe20e3b9f0b in zink_delete_shader_state ../src/gallium/drivers/zink/zink_program.c:1074
    #12 0x7fe20c3e29ad in util_shader_reference ../src/gallium/auxiliary/util/u_live_shader_cache.c:188
    #13 0x7fe20e3ba11e in zink_delete_cached_shader_state ../src/gallium/drivers/zink/zink_program.c:1093
    #14 0x7fe20c41709e in tc_call_delete_fs_state ../src/gallium/auxiliary/util/u_threaded_context.c:998
    #15 0x7fe20c411706 in tc_batch_execute ../src/gallium/auxiliary/util/u_threaded_context.c:211
    #16 0x7fe20c4124ba in _tc_sync ../src/gallium/auxiliary/util/u_threaded_context.c:362
    #17 0x7fe20c423683 in tc_flush ../src/gallium/auxiliary/util/u_threaded_context.c:3003
    #18 0x7fe20b62d996 in st_flush ../src/mesa/state_tracker/st_cb_flush.c:60
    #19 0x7fe20b62dbe3 in st_glFlush ../src/mesa/state_tracker/st_cb_flush.c:94
    #20 0x7fe20ae4bded in _mesa_make_current ../src/mesa/main/context.c:1493
    #21 0x7fe20ae49702 in _mesa_free_context_data ../src/mesa/main/context.c:1187
    #22 0x7fe20b65668b in st_destroy_context ../src/mesa/state_tracker/st_context.c:1005
    #23 0x7fe20b7055ab in st_context_destroy ../src/mesa/state_tracker/st_manager.c:944
    #24 0x7fe20a9c75bd in dri_destroy_context ../src/gallium/frontends/dri/dri_context.c:256
    #25 0x7fe20a9d4bef in driDestroyContext ../src/gallium/frontends/dri/dri_util.c:534
    #26 0x7fe22361f25c in drisw_destroy_context ../src/glx/drisw_glx.c:429
    #27 0x7fe223625d95 in glXDestroyContext ../src/glx/glxcmds.c:523
    #28 0x7fe22636aaeb in glXDestroyContext /home/zmike/src/libglvnd-v1.3.2/src/GLX/libglx.c:332
    #29 0x7fe2269d9e7d in glXDestroyContext /home/zmike/src/libglvnd-v1.3.2/src/GL/g_libglglxwrapper.c:384

previously allocated by thread T0 here:
    #0 0x7fe226cb691f in __interceptor_malloc (/usr/lib64/libasan.so.6+0xae91f)
    #1 0x7fe20aab0c81 in ralloc_size ../src/util/ralloc.c:120
    #2 0x7fe20aab0e33 in rzalloc_size ../src/util/ralloc.c:153
    #3 0x7fe20aab12c8 in rzalloc_array_size ../src/util/ralloc.c:233
    #4 0x7fe20e26c76d in allocate_desc_set ../src/gallium/drivers/zink/zink_descriptors.c:657
    #5 0x7fe20e26e9cb in zink_descriptor_set_get ../src/gallium/drivers/zink/zink_descriptors.c:840
    #6 0x7fe20e2747aa in zink_descriptors_update ../src/gallium/drivers/zink/zink_descriptors.c:1424
    #7 0x7fe20e36fc48 in void zink_draw<(zink_multidraw)1, (zink_dynamic_state)2, true, false>(pipe_context*, pipe_draw_info const*, unsigned int, pipe_draw_indirect_info const*, pipe_draw_start_count_bias const*, unsigned int, pipe_vertex_state*, unsigned int) ../src/gallium/drivers/zink/zink_draw.cpp:788
    #8 0x7fe20e29166d in zink_draw_vbo<(zink_multidraw)1, (zink_dynamic_state)2, true> ../src/gallium/drivers/zink/zink_draw.cpp:907
    #9 0x7fe20c424982 in tc_call_draw_single ../src/gallium/auxiliary/util/u_threaded_context.c:3155
    #10 0x7fe20c411706 in tc_batch_execute ../src/gallium/auxiliary/util/u_threaded_context.c:211
    #11 0x7fe20c4124ba in _tc_sync ../src/gallium/auxiliary/util/u_threaded_context.c:362
    #12 0x7fe20c41f7a9 in tc_texture_map ../src/gallium/auxiliary/util/u_threaded_context.c:2279
    #13 0x7fe20b630757 in pipe_texture_map_3d ../src/gallium/auxiliary/util/u_inlines.h:572
    #14 0x7fe20b6341f6 in st_ReadPixels ../src/mesa/state_tracker/st_cb_readpixels.c:546
    #15 0x7fe20b42fea7 in read_pixels ../src/mesa/main/readpix.c:1178
    #16 0x7fe20b42fea7 in _mesa_ReadnPixelsARB ../src/mesa/main/readpix.c:1195
    #17 0x7fe20b42ffc0 in _mesa_ReadPixels ../src/mesa/main/readpix.c:1210
    #18 0x2a6d094 in glu::readPixels(glu::RenderContext const&, int, int, tcu::PixelBufferAccess const&) /home/zmike/src/VK-GL-CTS/framework/opengl/gluPixelTransfer.cpp:61
    #19 0x29eaa06 in deqp::gls::ShaderExecUtil::FragmentOutExecutor::execute(int, void const* const*, void* const*) /home/zmike/src/VK-GL-CTS/modules/glshared/glsShaderExecUtil.cpp:677
    #20 0x25a600b in iterate /home/zmike/src/VK-GL-CTS/modules/gles31/functional/es31fOpaqueTypeIndexingTests.cpp:585
    #21 0x2322b53 in deqp::gles31::TestCaseWrapper<deqp::gles31::TestPackage>::iterate(tcu::TestCase*) /home/zmike/src/VK-GL-CTS/modules/gles31/tes31TestCaseWrapper.hpp:86
    #22 0x2c376fd in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) /home/zmike/src/VK-GL-CTS/framework/common/tcuTestSessionExecutor.cpp:302
    #23 0x2c366e3 in tcu::TestSessionExecutor::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuTestSessionExecutor.cpp:139
    #24 0x2c00b0c in tcu::App::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuApp.cpp:221
    #25 0x4141b7 in main /home/zmike/src/VK-GL-CTS/framework/platform/tcuMain.cpp:58
    #26 0x7fe2263e155f in __libc_start_call_main (/lib64/libc.so.6+0x2d55f)

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

zink: set shader key size to 0 for non-generated tcs

Test case 'dEQP-GLES31.functional.shaders.builtin_functions.common.modf.vec2_mediump_tess_control'..
=================================================================
==539161==ERROR: AddressSanitizer: unknown-crash on address 0x60400008cfef at pc 0x7fffdb47b2d6 bp 0x7fffffffa490 sp 0x7fffffffa488
READ of size 4 at 0x60400008cfef thread T0
    #0 0x7fffdb47b2d5 in XXH_read32 ../src/util/xxhash.h:531
    #1 0x7fffdb47bfbf in XXH_readLE32 ../src/util/xxhash.h:608
    #2 0x7fffdb47bfbf in XXH_readLE32_align ../src/util/xxhash.h:620
    #3 0x7fffdb47bfbf in XXH32_endian_align ../src/util/xxhash.h:797
    #4 0x7fffdb47bfbf in XXH32 ../src/util/xxhash.h:831
    #5 0x7fffdb480b49 in _mesa_hash_data ../src/util/hash_table.c:631
    #6 0x7fffded8c10a in shader_module_hash ../src/gallium/drivers/zink/zink_program.c:82
    #7 0x7fffded8cad8 in get_shader_module_for_stage ../src/gallium/drivers/zink/zink_program.c:144
    #8 0x7fffded8cf64 in update_gfx_shader_modules ../src/gallium/drivers/zink/zink_program.c:182
    #9 0x7fffded8dcc2 in zink_update_gfx_program ../src/gallium/drivers/zink/zink_program.c:257
    #10 0x7fffdec63463 in update_gfx_program ../src/gallium/drivers/zink/zink_draw.cpp:223
    #11 0x7fffded7aab9 in update_gfx_pipeline<true> ../src/gallium/drivers/zink/zink_draw.cpp:445
    #12 0x7fffded4a88b in void zink_draw<(zink_multidraw)1, (zink_dynamic_state)2, true, false>(pipe_context*, pipe_draw_info const*, unsigned int, pipe_draw_indirect_info const*, pipe_draw_start_count_bias const*, unsigned int, pipe_vertex_state*, unsigned int) ../src/gallium/drivers/zink/zink_draw.cpp:777
    #13 0x7fffdec6c5b2 in zink_draw_vbo<(zink_multidraw)1, (zink_dynamic_state)2, true> ../src/gallium/drivers/zink/zink_draw.cpp:907
    #14 0x7fffdcdff982 in tc_call_draw_single ../src/gallium/auxiliary/util/u_threaded_context.c:3155
    #15 0x7fffdcdec706 in tc_batch_execute ../src/gallium/auxiliary/util/u_threaded_context.c:211
    #16 0x7fffdcded4ba in _tc_sync ../src/gallium/auxiliary/util/u_threaded_context.c:362
    #17 0x7fffdcdfa492 in tc_buffer_map ../src/gallium/auxiliary/util/u_threaded_context.c:2251
    #18 0x7fffdb7f2439 in pipe_buffer_map_range ../src/gallium/auxiliary/util/u_inlines.h:393
    #19 0x7fffdb7f56c2 in _mesa_bufferobj_map_range ../src/mesa/main/bufferobj.c:488
    #20 0x7fffdb803300 in map_buffer_range ../src/mesa/main/bufferobj.c:3734
    #21 0x7fffdb8036e7 in _mesa_MapBufferRange ../src/mesa/main/bufferobj.c:3817
    #22 0x29ecb02 in deqp::gls::ShaderExecUtil::BufferIoExecutor::readOutputBuffer(void* const*, int) /home/zmike/src/VK-GL-CTS/modules/glshared/glsShaderExecUtil.cpp:1069
    #23 0x29ee499 in deqp::gls::ShaderExecUtil::TessControlExecutor::execute(int, void const* const*, void* const*) /home/zmike/src/VK-GL-CTS/modules/glshared/glsShaderExecUtil.cpp:1390
    #24 0x246264c in deqp::gles31::Functional::CommonFunctionCase::iterate() /home/zmike/src/VK-GL-CTS/modules/gles31/functional/es31fShaderCommonFunctionTests.cpp:400
    #25 0x2322b53 in deqp::gles31::TestCaseWrapper<deqp::gles31::TestPackage>::iterate(tcu::TestCase*) /home/zmike/src/VK-GL-CTS/modules/gles31/tes31TestCaseWrapper.hpp:86
    #26 0x2c376fd in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) /home/zmike/src/VK-GL-CTS/framework/common/tcuTestSessionExecutor.cpp:302
    #27 0x2c366e3 in tcu::TestSessionExecutor::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuTestSessionExecutor.cpp:139
    #28 0x2c00b0c in tcu::App::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuApp.cpp:221
    #29 0x4141b7 in main /home/zmike/src/VK-GL-CTS/framework/platform/tcuMain.cpp:58
    #30 0x7ffff6dbc55f in __libc_start_call_main (/lib64/libc.so.6+0x2d55f)
    #31 0x7ffff6dbc60b in __libc_start_main_impl (/lib64/libc.so.6+0x2d60b)
    #32 0x413fa4 in _start (/home/zmike/src/VK-GL-CTS/build/external/openglcts/modules/glcts+0x413fa4)

0x60400008cff1 is located 0 bytes to the right of 33-byte region [0x60400008cfd0,0x60400008cff1)
allocated by thread T0 here:
    #0 0x7ffff769191f in __interceptor_malloc (/usr/lib64/libasan.so.6+0xae91f)
    #1 0x7fffded8c608 in get_shader_module_for_stage ../src/gallium/drivers/zink/zink_program.c:115
    #2 0x7fffded8cf64 in update_gfx_shader_modules ../src/gallium/drivers/zink/zink_program.c:182
    #3 0x7fffded8dcc2 in zink_update_gfx_program ../src/gallium/drivers/zink/zink_program.c:257
    #4 0x7fffdec63463 in update_gfx_program ../src/gallium/drivers/zink/zink_draw.cpp:223
    #5 0x7fffded7aab9 in update_gfx_pipeline<true> ../src/gallium/drivers/zink/zink_draw.cpp:445
    #6 0x7fffded4a88b in void zink_draw<(zink_multidraw)1, (zink_dynamic_state)2, true, false>(pipe_context*, pipe_draw_info const*, unsigned int, pipe_draw_indirect_info const*, pipe_draw_start_count_bias const*, unsigned int, pipe_vertex_state*, unsigned int) ../src/gallium/drivers/zink/zink_draw.cpp:777
    #7 0x7fffdec6c5b2 in zink_draw_vbo<(zink_multidraw)1, (zink_dynamic_state)2, true> ../src/gallium/drivers/zink/zink_draw.cpp:907
    #8 0x7fffdcdff982 in tc_call_draw_single ../src/gallium/auxiliary/util/u_threaded_context.c:3155
    #9 0x7fffdcdec706 in tc_batch_execute ../src/gallium/auxiliary/util/u_threaded_context.c:211
    #10 0x7fffdcded4ba in _tc_sync ../src/gallium/auxiliary/util/u_threaded_context.c:362
    #11 0x7fffdcdfa492 in tc_buffer_map ../src/gallium/auxiliary/util/u_threaded_context.c:2251
    #12 0x7fffdb7f2439 in pipe_buffer_map_range ../src/gallium/auxiliary/util/u_inlines.h:393
    #13 0x7fffdb7f56c2 in _mesa_bufferobj_map_range ../src/mesa/main/bufferobj.c:488
    #14 0x7fffdb803300 in map_buffer_range ../src/mesa/main/bufferobj.c:3734
    #15 0x7fffdb8036e7 in _mesa_MapBufferRange ../src/mesa/main/bufferobj.c:3817
    #16 0x29ecb02 in deqp::gls::ShaderExecUtil::BufferIoExecutor::readOutputBuffer(void* const*, int) /home/zmike/src/VK-GL-CTS/modules/glshared/glsShaderExecUtil.cpp:1069
    #17 0x29ee499 in deqp::gls::ShaderExecUtil::TessControlExecutor::execute(int, void const* const*, void* const*) /home/zmike/src/VK-GL-CTS/modules/glshared/glsShaderExecUtil.cpp:1390
    #18 0x246264c in deqp::gles31::Functional::CommonFunctionCase::iterate() /home/zmike/src/VK-GL-CTS/modules/gles31/functional/es31fShaderCommonFunctionTests.cpp:400
    #19 0x2322b53 in deqp::gles31::TestCaseWrapper<deqp::gles31::TestPackage>::iterate(tcu::TestCase*) /home/zmike/src/VK-GL-CTS/modules/gles31/tes31TestCaseWrapper.hpp:86
    #20 0x2c376fd in tcu::TestSessionExecutor::iterateTestCase(tcu::TestCase*) /home/zmike/src/VK-GL-CTS/framework/common/tcuTestSessionExecutor.cpp:302
    #21 0x2c366e3 in tcu::TestSessionExecutor::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuTestSessionExecutor.cpp:139
    #22 0x2c00b0c in tcu::App::iterate() /home/zmike/src/VK-GL-CTS/framework/common/tcuApp.cpp:221
    #23 0x4141b7 in main /home/zmike/src/VK-GL-CTS/framework/platform/tcuMain.cpp:58
    #24 0x7ffff6dbc55f in __libc_start_call_main (/lib64/libc.so.6+0x2d55f)

cc: mesa-stable

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

zink: skip extra descriptor lookups for images during barrier updates

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

zink: add layout to sampler descriptor hash

this can have more than one value, so avoid stale cache entries

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

zink: fix typo for image descriptor rebinds

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

zink: update descriptor refs after starting renderpass

this ensures that swapchain images will have been acquired before potentially
accessing swapchain images bound as descriptors

fixes caselist like:
dEQP-GLES31.functional.fbo.color.texcubearray.r8ui
dEQP-GLES31.functional.primitive_bounding_box.blit_fbo.blit_default_to_fbo

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15173>

radv: use MAJOR_IN_SYSMACROS for sysmacros.h include

fixes build on OpenBSD
../src/amd/vulkan/radv_device.c:35:10: fatal error: 'sys/sysmacros.h' file not found

Fixes: 7aaa54feb53 ("radv: implement VK_EXT_physical_device_drm")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13448>

util: fix util_cpu_detect_once() build on OpenBSD

Correct type for sysctl argument to fix the build.

../src/util/u_cpu_detect.c:631:29: error: incompatible pointer types passing 'int *' to parameter of type 'size_t *' (aka 'unsigned long *') [-Werror,-Wincompatible-pointer-types]
      sysctl(mib, 2, &ncpu, &len, NULL, 0);
                            ^~~~

Fixes: 5623c75e40b ("util: Fix setting nr_cpus on some BSD variants")
Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13448>

util: fix u_print.cpp build on OpenBSD

move include so va_list will be picked up via stdarg.h

In file included from ../src/util/u_printf.cpp:24:
../src/util/u_printf.h:43:41: error: unknown type name 'va_list'; did you mean '__va_list'?
size_t u_printf_length(const char *fmt, va_list untouched_args);
                                        ^~~~~~~
                                        __va_list
/usr/include/machine/_types.h:126:27: note: '__va_list' declared here
typedef __builtin_va_list       __va_list;
                                ^

and add includes to u_printf.h as suggested by Ilia Mirkin
stdarg.h for va_list and stddef.h for size_t

Signed-off-by: Jonathan Gray <jsg@jsg.id.au>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13448>

util: unbreak non-linux mips64 build

Put linux specific path inside an ifdef.  Unbreaks mips64 build on
OpenBSD and likely other systems without Elf64_auxv_t.

Fixes: 88b234d7a7c ("gallivm: add basic mips64 support and set mcpu to mips64r5 on ls3a4000")
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15166>

intel/compiler: optimize flat inputs mask calculation

Don't bother looking at urb if variable is not flat.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15169>

intel/compiler: ignore per-primitive attrs when calculating flat input mask

If we say that per-primitive attributes are flat (which is communicated by
3DSTATE_SBE.ConstantInterpolationEnable), GPU freaks out and applies it
to other (non-flat) attributes.

Fixes: be89ea3231c ("intel/compiler: Handle per-primitive inputs in FS")

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15169>

pan/va: Add TEX_FETCH assembler case

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15182>

pan/va: Handle sr_write_count in the disassembler

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15182>

pan/va: Fix definitions of TEX_SINGLE and TEX_FETCH

Fix the definitions of the basic texturing instructions. In particular, a
register format and a write mask were previously missing, as well as incorrect
handling of staging registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15182>

pan/va: Don't use staging index as a sideband

It would cause us to get incorrect disassembly when the syntax is flipped.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15182>

pan/va: Handle extended staging counts in assembler

Needed for texturing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15182>

pan/va: Allow forcing enums for 1-bit modifiers

Ocassionally the 0 value has a meaningful value that's not meaningfully default,
so we want an enum to encode both possible states.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15182>