Emma Anholt [Wed, 26 Jan 2022 05:19:05 +0000 (21:19 -0800)]
softpipe: Improve some local var naming in compute shaders.
These aren't dimensions, they're gl_LocalInvocationID.xyz.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14728>
Emma Anholt [Wed, 26 Jan 2022 05:48:44 +0000 (21:48 -0800)]
tgsi_exec: Fix shared var stores for >1 real invocation, and overflow checks.
The shared var store overflow checks left a lot of overflowing
opportunities available, while the buffer storage path did proper
checking. But, more importantly for this branch, it always used the first
invocation's offset for each invocation in the quad (which only worked so
far because softpipe only dispatched a single non-helper invocation
per quad).
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14728>
Hyunjun Ko [Wed, 26 Jan 2022 03:04:40 +0000 (03:04 +0000)]
turnip: fix leaks of submit requests.
Fixes:
479a1c40 ("turnip: Porting to common vulkan implementation for synchronization.")
Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14727>
Mike Blumenkrantz [Tue, 25 Jan 2022 18:47:12 +0000 (13:47 -0500)]
zink: return 256 for PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
this isn't the minimum allowed by the driver, but zink doesn't return
the minimum allowed by the driver anyway and hasn't in a very long time
instead, it suballocates using a minimum alignment of 256 bytes, so use
that instead
fixes (in caselists):
KHR-GL46.map_buffer_alignment.functional
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14720>
Michel Zou [Wed, 26 Jan 2022 19:54:28 +0000 (20:54 +0100)]
zink: fix unused variable warning
fixes:
4ed30be3
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14739>
Eric Engestrom [Wed, 26 Jan 2022 18:47:30 +0000 (18:47 +0000)]
docs/release-calendar: add another 21.3.x since 22.0 has been delayed a bit
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14737>
Eric Engestrom [Wed, 26 Jan 2022 18:39:08 +0000 (18:39 +0000)]
docs: update calendar and link releases notes for 21.3.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14737>
Eric Engestrom [Wed, 26 Jan 2022 18:36:17 +0000 (18:36 +0000)]
docs: add release notes for 21.3.5
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14737>
Jason Ekstrand [Mon, 17 Jan 2022 15:42:50 +0000 (09:42 -0600)]
.mailmap: Switch Jason Ekstrand to @collabora.com
Jason is starting at Collabora on the 24th. More details at
https://www.jlekstrand.net/jason/blog/2022/01/hello-collabora/
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14586>
Yiwei Zhang [Wed, 26 Jan 2022 07:53:59 +0000 (07:53 +0000)]
tu: VkExternalImageFormatProperties is optional
..even if external image info has valid external handles.
Fixes:
26380b3a9f8 ("turnip: Add driver skeleton (v2)")
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14730>
Ruijing Dong [Mon, 24 Jan 2022 18:00:32 +0000 (13:00 -0500)]
radeon/vcn: Updating render_pic_list for correction
In order to keep track of reference frame buffer address changing,
using past_ref to compare with render_pic_list, once the one in
past_ref is valid and if render_pic_list has that entry, it will
need to update it to the latest one in ref[i].
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5868
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14646>
Ruijing Dong [Mon, 24 Jan 2022 17:42:58 +0000 (12:42 -0500)]
frontend/va: Keep surface buf addr before reallocation
The reference buffer address is used as the indication in h264 DPB
Tier2, when reference buffer was reallocated, h264 DPB would lose
track of that reference picture. Adding a pointer obsolete_buf in
vlVaSurface data structure for tracking this released buffer, also
in h264_picture_desc adding a private field, which contains
past_ref[16] for tracking previously released buffer vs current
buffer for reference frames.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5868
Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14646>
Mike Blumenkrantz [Tue, 25 Jan 2022 16:25:24 +0000 (11:25 -0500)]
zink: reorder fbfetch flag-setting to avoid null deref
this avoids dereferencing pg->dd which is allocated a few lines later
Fixes:
417477f60ed ("zink: always use lazy (non-push) updating for fbfetch descriptors")
fixes (radv):
dEQP-GLES31.functional.blend_equation_advanced.basic.multiply
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14718>
Rhys Perry [Mon, 24 Jan 2022 20:05:37 +0000 (20:05 +0000)]
radv: fix optimized MSAA copies with suballocated images
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Fixes:
deb4685df39 ("radv: implement optimized MSAA copies using FMASK")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5829
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14705>
Mike Blumenkrantz [Tue, 18 Jan 2022 22:39:05 +0000 (17:39 -0500)]
zink: handle bogus xfb draws
drawing unpopulated xfb data is legal(?) and tested in cts, and the correct
operation is to just drop the draw, so do that here
fixes (nvidia):
GTF-GL46.gtf40.GL3Tests.transform_feedback2.transform_feedback2_api
Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14694>
Iván Briano [Thu, 4 Nov 2021 19:19:07 +0000 (12:19 -0700)]
anv: Enable VK_KHR_dynamic_rendering
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Thu, 4 Nov 2021 19:33:05 +0000 (12:33 -0700)]
anv: implement the meat of VK_KHR_dynamic_rendering
Includes a fake framebuffer allocation that's necessary for the code we
still use from the regular render passes.
v3: (Lionel)
- Reuse the attachment count from the faux render pass, remove now
unused function
- Add a cmd_buffer_end_rendering function to match begin_rendering,
making use of the split stuff from end_subpass
v4: (Lionel)
- Don't bother with mark_images_writen or resolves on suspend case
- Remove flush at the end of end_rendering, it's not needed
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Mon, 8 Nov 2021 21:10:00 +0000 (13:10 -0800)]
anv: split end_subpass into more discrete components
v3: Split cmd_buffer_end_subpass instead of doing parts conditionally (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Tue, 9 Nov 2021 00:32:31 +0000 (16:32 -0800)]
anv: Split attachment clearing code into their own functions
v3: Avoid recalculating parameters the caller already had (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Thu, 4 Nov 2021 19:30:20 +0000 (12:30 -0700)]
anv: allocate fake render pass for continuation command buffers
v4: Assert if there's no VkCommandBufferInheritanceRenderingInfoKHR (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Mon, 8 Nov 2021 19:32:37 +0000 (11:32 -0800)]
anv: Split out state attachments allocation
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Thu, 4 Nov 2021 19:29:09 +0000 (12:29 -0700)]
anv: allocate fake render pass on pipeline creation
v3: (Lionel)
- Handle VkPipelineRenderingCreateInfoKHR not being present
- Rename dynamic_pass and set it for regular render passes too
v4: C99 is good (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Thu, 4 Nov 2021 19:26:26 +0000 (12:26 -0700)]
anv: add functions to set up fake render passes
There's two of them because they can be created from three points in the
code that provide different details and this is the least ugly way I
could think of for now.
v2: Avoid allocations (Lionel)
v3: Move definition closer to its usage (Lionel)
v4: (Lionel)
- Simplify anv_dynamic_pass_init_full
- Zero out pass/subpass to avoid stall pointers
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Iván Briano [Tue, 9 Nov 2021 00:00:11 +0000 (16:00 -0800)]
anv: Remove unused struct member
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Jason Ekstrand [Tue, 26 Oct 2021 17:38:18 +0000 (12:38 -0500)]
anv/pass: Don't set first_subpass_layout for stencil-only attachments
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13980>
Alyssa Rosenzweig [Tue, 25 Jan 2022 23:10:10 +0000 (18:10 -0500)]
panfrost: Remove NO_BLEND_PACKS quirk
Now unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Alyssa Rosenzweig [Tue, 25 Jan 2022 23:08:55 +0000 (18:08 -0500)]
panfrost: Simplify format class selection
This was made way more complicated than it needs to be for a Midgard-only pass.
The only caller doesn't care about the class, only if it's native or not.
Simplify it appropriately.
It really isn't that hard.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Alyssa Rosenzweig [Tue, 25 Jan 2022 22:58:14 +0000 (17:58 -0500)]
panfrost: Don't set NO_BLEND_PACKS on Bifrost
It doesn't make sense on Bifrost -- the only consumer of the quirk is
pan_lower_framebuffer, a Midgard-only pass.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Alyssa Rosenzweig [Tue, 25 Jan 2022 22:56:33 +0000 (17:56 -0500)]
panfrost: Remove MIDGARD_{NO_TYPED_BLEND_STORES,MISSING_LOADS}
These "quirks" are common for Midgard, yet are only consumed by
pan_lower_framebuffer -- a Midgard-only pass. So the quirks should be removed
and inlined into their users. Thid removes MIDGARD_QUIRKS altogether.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Alyssa Rosenzweig [Tue, 25 Jan 2022 22:51:48 +0000 (17:51 -0500)]
panfrost: Remove NO_TILE_ENABLE_MAP quirk
Function of architecture. Add a comment to the sole consumer of the quirk bit
about why it's used.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Alyssa Rosenzweig [Tue, 25 Jan 2022 22:49:54 +0000 (17:49 -0500)]
panfrost: Remove MIDGARD_BROKEN_FP16 quirk
Unused.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Alyssa Rosenzweig [Tue, 25 Jan 2022 22:49:08 +0000 (17:49 -0500)]
panfrost: Remove MIDGARD_SFBD quirk
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Alyssa Rosenzweig [Tue, 25 Jan 2022 22:46:40 +0000 (17:46 -0500)]
panfrost: Remove HAS_SWIZZLES quirk
It's a function of the major arch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14724>
Jesse Natalie [Sat, 1 Jan 2022 22:49:40 +0000 (14:49 -0800)]
d3d12: Set caps for tesselation
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Thu, 6 Jan 2022 15:42:22 +0000 (07:42 -0800)]
d3d12: Handle input clip array size in the shader key
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Wed, 5 Jan 2022 15:38:38 +0000 (07:38 -0800)]
d3d12: Update varying creation logic to handle location_frac
When multiple variables are packed into the same location, we need
to re-construct variables that read/write the same components of that
register so that the DXIL signature is correct. We could try to
merge these variables, but getting the types right sounds harder than
just preserving the multiple individual variables.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Thu, 6 Jan 2022 00:07:51 +0000 (16:07 -0800)]
d3d12: Add a state variable for patch_vertices_in
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 20:49:28 +0000 (12:49 -0800)]
d3d12: Handle passthrough TCS in the case where eval is bound
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 23:21:55 +0000 (15:21 -0800)]
d3d12: Handle patch_vertices and patch topology
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 21:03:32 +0000 (13:03 -0800)]
d3d12: Link tesselation control and eval shaders
GLSL puts a bunch of tessellation info in the eval shaders, because
passthrough control shaders can exist. D3D12 puts it in the control
(hull) shader instead. So, when specializing, copy info from domain
to hull. For initial compiles (no domain shader), just make something
up.
D3D12 also requires the domain and hull shaders to have identical
patch constant signatures. Use the existing infrastructure and extend
it to also propagate patch constants. Notably, patch constant locations
are outside of the 64-bit range value so they require a separate pass
to avoid shifts larger than 64.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sat, 1 Jan 2022 22:49:28 +0000 (14:49 -0800)]
d3d12: Initial plumbing for tesselation
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Thu, 6 Jan 2022 17:03:18 +0000 (09:03 -0800)]
d3d12: Enable PIPE_CAP_TGSI_TEXCOORD
This is required to be able to use the necessary number of varyings,
otherwise we hit asserts because mesa/st starts assigning varyings
locations above 64 due to the +9 reserving these texcoords.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Thu, 6 Jan 2022 15:40:24 +0000 (07:40 -0800)]
microsoft/compiler: Handle clip/cull distance as an input to tess shaders
In order to get the semantics right, we need to know how many of the clip/
cull fields are designated for which purpose. In the case of a shader that
can receive these fields as both input and output, the shader_info property
is reserved to store the output info. We could add a dedicated input field
to shader_info, but since it'd probably only be useful for us, just send
it through a side channel during shader linking.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Wed, 5 Jan 2022 15:40:49 +0000 (07:40 -0800)]
microsoft/compiler: Location_frac needs to be included in sort order
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 22:47:35 +0000 (14:47 -0800)]
microsoft/compiler: Primitive ID should only be added as a sysval in geometry shaders
Docs say that its presence in signatures as a "shadow" element (meaning it's not
accessed via load/store, but with a dedicated opcode) is legacy. It seems it
wasn't carried forward when HS/DS were added in D3D11.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 17:04:03 +0000 (09:04 -0800)]
microsoft/compiler: Emit DS PSV validation and entrypoint metadata
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 23:23:06 +0000 (15:23 -0800)]
microsoft/compiler: Handle domain location intrinsic
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 4 Jan 2022 16:39:26 +0000 (08:39 -0800)]
microsoft/compiler: Handle load_output in the HS stage as reading a previously written patch constant
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 4 Jan 2022 00:15:12 +0000 (16:15 -0800)]
microsoft/compiler: Handle load_per_vertex_output as LoadOutputControlPoint
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 21:35:39 +0000 (13:35 -0800)]
microsoft/compiler: For load_input from DS, use loadPatchConstant
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 17:56:08 +0000 (09:56 -0800)]
microsoft/compiler: For store_output from HS, use storePatchConstant
In HS, store_per_vertex_output maps to storeOutput in DXIL. The data
that isn't per-vertex is patch constants.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:51:36 +0000 (05:51 -0800)]
microsoft/compiler: Add a pass for hull and domain shaders to shrink tess level vars
DXIL validation will complain if the tess factor signature entries have the
wrong number of components for the shader's domain. Make sure that both
hull and domain shaders have the right number, and drop loads and stores
from the removed components.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 14:08:35 +0000 (06:08 -0800)]
microsoft/compiler: Add patch constant signature into PSV and as container blob
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 14:01:14 +0000 (06:01 -0800)]
microsoft/compiler: Gather patch const signature and handle tess factor in it
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 21:33:53 +0000 (13:33 -0800)]
microsoft/compiler: When sorting patch varyings, adjust location to be in normal varying range
This way, patch varyings come before the patch sysvals (tess levels).
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 18:15:58 +0000 (10:15 -0800)]
microsoft/compiler: Overlap patch and non-patch varyings so both are separately 0-indexed
Also add tess factors to the list of sysvals that can cause vars to be sorted last.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:45:48 +0000 (05:45 -0800)]
microsoft/compiler: Fix I/O signatures for tess shaders
- Skip patch variables, those go into a separate patch constant signature
- Use nir_is_arrayed_io and only strip one level of array when it's true
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 14:20:25 +0000 (06:20 -0800)]
microsoft/compiler: Emit HS PSV validation and entrypoint metadata
Note that this requires the shader info "tess" data to be correct.
For GLSL tess control shaders, only the output primitive count is
automatically available. The rest will need to be either guessed
or filled in from a matching tess eval (domain) shader. This is handled
by the d3d12 driver in a later patch.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 19:56:09 +0000 (11:56 -0800)]
microsoft/compiler: Delete misleading TODO comments about semantic table
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
We've been writing a valid semantic table for a while now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sat, 1 Jan 2022 21:14:05 +0000 (13:14 -0800)]
microsoft/compiler: Split hull (tess ctrl) shaders into main and patch constant funcs
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:23:48 +0000 (05:23 -0800)]
microsoft/compiler: Handle store_per_vertex_output for HS outputs
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:17:25 +0000 (05:17 -0800)]
microsoft/compiler: Emit all NIR functions into the DXIL module
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 00:04:47 +0000 (16:04 -0800)]
microsoft/compiler: Emit functions with actual function names
Once we start writing multiple functions, we can't keep calling all
of them "main"
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:13:39 +0000 (05:13 -0800)]
microsoft/compiler: Support emitting multiple functions into a DXIL module
The instruction and block lists are moved into a new "function definition"
struct, and the DXIL module tracks one at a time for adding instructions
into. The NIR side still only emits the main function here though.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 25 Jan 2022 23:20:23 +0000 (15:20 -0800)]
microsoft/compiler: Emit statically-indexed resource handles and scratch later
The resource declarations are module-wide, but the resource handles
are function-local. A future change will add multi-function support,
but requires these handles to be potentially emitted multiple times.
The alloca used for scratch is also function-local.
This is the same pattern that the DXBC to DXIL converter uses.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 25 Jan 2022 23:20:31 +0000 (15:20 -0800)]
microsoft/compiler: Fix typo in enum entry
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 12:59:36 +0000 (04:59 -0800)]
microsoft/compiler: Add mapping from MESA_SHADER_* to DXIL_*_SHADER for tessellation
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 12:59:03 +0000 (04:59 -0800)]
microsoft/compiler: Getting a builtin function with an undeclared signature should be unreachable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 19:58:00 +0000 (11:58 -0800)]
microsoft/compiler: Multi-row output semantics need to write multiple never_writes_masks
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 19:57:34 +0000 (11:57 -0800)]
microsoft/compiler: Semantic table should be de-duped for multi-row semantics too
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 17:48:12 +0000 (09:48 -0800)]
microsoft/compiler: Use driver_location instead of location for inter-stage varying index in GL
In the case of two vars being packed into the same register / location,
they'll still get unique driver_location, which is what we need.
This does require some tweaks to stream output handling, which also needs to
produce the varying index.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 17:47:36 +0000 (09:47 -0800)]
microsoft/compiler: Force integer I/O vars to use flat/constant interpolation
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Dave Airlie [Tue, 25 Jan 2022 03:39:02 +0000 (13:39 +1000)]
mesa/st: refactor program translation into one file.
This moves the notify callback into the file where it's all called
from.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 06:20:48 +0000 (16:20 +1000)]
mesa/st: move program new/delete into mesa
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 06:15:22 +0000 (16:15 +1000)]
mesa/st: move st_vertex_program to gl_vertex_program in mesa
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 06:00:43 +0000 (16:00 +1000)]
mesa/st: move new ati fragment shader to mesa
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 05:54:08 +0000 (15:54 +1000)]
mesa/st: collapse st_program into gl_program object.
Remove the subclass for this.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Jordan Justen [Tue, 25 Jan 2022 07:40:07 +0000 (23:40 -0800)]
intel/genxml: Extend length of 3DSTATE_DEPTH_BUFFER for gfx12.5
The two added dwords are MBZ.
Ref: bspec 46935
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702>
Jordan Justen [Wed, 9 Oct 2019 10:59:16 +0000 (03:59 -0700)]
intel/genxml: Extend length of 3DSTATE_WM_HZ_OP for gfx12.5
The added dword is MBZ.
Ref: bspec 46981
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702>
Mike Blumenkrantz [Tue, 25 Jan 2022 21:48:22 +0000 (16:48 -0500)]
zink: add anv (icl) fails
mesa/mesa#5918
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14722>
Mike Blumenkrantz [Fri, 21 Jan 2022 14:39:22 +0000 (09:39 -0500)]
zink: never use SpvOpImageQuerySizeLod for texel buffers
this is illegal
cc: mesa-stable
affects KHR-GL46.texture_buffer.texture_buffer_texture_buffer_range
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14696>
Mike Blumenkrantz [Tue, 25 Jan 2022 21:29:57 +0000 (16:29 -0500)]
zink: update radv fails list
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14717>
Mike Blumenkrantz [Thu, 20 Jan 2022 20:14:23 +0000 (15:14 -0500)]
zink: update nv fails
more passes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14716>
Caio Oliveira [Sun, 23 Jan 2022 21:08:03 +0000 (13:08 -0800)]
intel/fs/xehp: Add unit test for handling of RaR deps across multiple pipelines.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Paulo Zanoni [Wed, 15 Dec 2021 23:53:29 +0000 (15:53 -0800)]
intel/fs: Assert the GPU supports 64bit ops if present at lower_scoreboard time.
On platforms where we don't support 64 bit instructions we shouldn't
pass such instructions for the code generator to lower into supported
instructions, because this makes their execution pipeline
unpredictable to the scoreboard lowering pass on XeHP+ platforms.
We really should be reducing all these 64 bit instructions before code
generation, so here we add an assert to help us catch and fix these
cases more easily.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[ Francisco Jerez: Also allow has_integer_dword_mul. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:34:13 +0000 (14:34 -0800)]
intel/fs: Perform 64-bit CLUSTER_BROADCAST lowering in the lower_regioning pass.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 08:20:38 +0000 (00:20 -0800)]
intel/fs: Honor strided source regions specified by the IR for CLUSTER_BROADCAST.
This fixes a bug in the CLUSTER_BROADCAST code generation that causes
the original IR region to be ignored, this will be a problem when we
start lowering 64-bit CLUSTER_BROADCAST instructions at the IR level,
since it will lead to instructions with non-trivial regioning.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:33:45 +0000 (14:33 -0800)]
intel/fs: Perform 64-bit SEL_EXEC lowering in the lower_regioning pass.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:52:16 +0000 (14:52 -0800)]
intel/fs: Perform 64-bit SHUFFLE lowering in the lower_regioning pass.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:49:02 +0000 (14:49 -0800)]
intel/fs: Fix destination suboffset calculations for non-trivial strides in SHUFFLE codegen.
One of the two SHUFFLE implementations wasn't taking into account the
destination stride at all, and the other (more commonly used) one was
taking it into account incorrectly since brw_reg::hstride represents
the stride logarithmically, so we need to use a left-shift operator
instead of product. Found by inspection.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 09:54:57 +0000 (01:54 -0800)]
intel/fs: Take into account region strides during SIMD lowering decision of SHUFFLE.
This fixes a bug in the handcrafted SIMD lowering done by the SHUFFLE
code generation, which wasn't taking into account the source and
destination region strides while deciding whether it needs to split an
instruction.
v2: Use new element_sz() helper instead of left shift. (Lionel)
Fixes:
90c9f29518d ("i965/fs: Add support for nir_intrinsic_shuffle")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:15:47 +0000 (14:15 -0800)]
intel/fs: Teach the lower_regioning pass how to split instructions of unsuported exec type.
This adds some generic infrastructure that allows splitting any
instruction into a number of instructions of a smaller legal execution
type. This is meant to replace several instances of handcrafted 64bit
type lowering done manually in the code generator, which is rather
error-prone, prevents scheduling of the lowered instructions, and
makes them invisible to the SWSB pass on Gfx12+ platforms, which will
become especially problematic on Gfx12.5+ since the EUs introduce
multiple asynchronous execution pipelines which the SWSB pass needs to
be able to synchronize to one another, so it's critical for the real
execution type of the instruction to be visible to the SWSB pass.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:01:50 +0000 (14:01 -0800)]
intel/fs: Move legal exec type calculation into helper function in lower_regioning pass.
Right now the execution type lowering functionality of this pass
assumes that an integer type of the original bit size is always
acceptable, however we'll want more complex behavior than that in
order to leverage this pass to automate the lowering of unsupported
64-bit operations into multiple 32-bit operations.
In order to do that calculate the closest legal execution type from a
new helper function, and take advantage of that function from the
has_invalid_exec_type() helper, along the lines of other
lower_regioning() helpers structured as a pair of has_invalid_foo() +
required_foo() functions.
This shouldn't have any functional changes.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Tue, 14 Dec 2021 07:48:29 +0000 (23:48 -0800)]
intel/fs/xehp: Merge repeated in-order read dependencies instead of replacement.
Previously the software scoreboard structure would drop previous
dependencies for a given register and replace them with the most
recent one for the same register when a new instruction (or set of
instructions) is processed. This worked correctly on the Gfx12LP
platforms this code was originally designed for, because a repeated
dependency on the same register would either require the second
instruction to synchronize against the first (so the first dependency
could be disregarded from that point on) *or* require the dependency
to be RaR and in-order, which allows the synchronization to be
optimized out (the first dependency could still be disregarded as
well, since the pipeline is in-order). However the latter assumption
will break on upcoming Gfx12HP platforms, because they have multiple
asynchronous FPU pipelines, so whenever we hit a RaR dependency we
need to propagate forward both dependencies, since the order in which
both reads will complete is not guaranteed by the hardware in cases
where they occur from different asynchronous pipelines.
Note that this dependency propagation change requires us to change the
definition of dependency::done as well, since that constant is defined
to discard any previous dependency information when used as argument
for shadow().
This has been reported to fix the following conformance failures on DG2:
KHR-GL46.shaders.uniform_block.random.all_per_block_buffers.19
dEQP-GLES3.functional.shaders.derivate.fwidth.*
Reported-by: Tapani Pälli <tapani.palli@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5670
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Alejandro Piñeiro [Tue, 25 Jan 2022 12:59:45 +0000 (13:59 +0100)]
vc4/nir_lower_blend: update write mask when we update num components
As explained at the header of the lowering:
"Once this pass is done, the color write will either have one
component (for single sample) with packed argb8888, or 4 components
with the per-sample argb8888 result."
So in several cases the lowering was updating the number of
components, so we need to update the writemask too.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14708>
Bas Nieuwenhuizen [Thu, 20 Jan 2022 23:57:52 +0000 (00:57 +0100)]
radv/amdgpu: Use aligned sizing for IB buffers.
Otherwise aligning might run over buffer size ...
Fixes:
1f36f6b83f2 ("radv/winsys: use same IBs padding as the kernel")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14644>
Bas Nieuwenhuizen [Thu, 20 Jan 2022 23:03:14 +0000 (00:03 +0100)]
radv/amdgpu: Fix handling of IB alignment > 4 words.
We reserved space for chaining by subtracting 4 words from max_dw, but
then the new alignment code in radv_amdgpu_cs_finalize ended up running
all over that. That resulted in going over buffer size when chaining.
When lucky you'd get a crash, and when unlucky other stuff might happen.
This always adds the 4 words at the end, but initializes with NOP by
default. That way we still adhere to the alignment rules.
Fixes:
1f36f6b83f2 ("radv/winsys: use same IBs padding as the kernel")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14644>
Dave Airlie [Tue, 25 Jan 2022 06:01:00 +0000 (16:01 +1000)]
mesa: consolidate setting no error state and checking suid.
This makes MESA_NO_ERROR and mesa_no_error via drirc do the same thing.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14701>
Samuel Pitoiset [Tue, 25 Jan 2022 14:40:18 +0000 (15:40 +0100)]
radv/ci: mark dEQP-VK.api.version_check.version as expected failure on Stoney
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Mon, 4 Oct 2021 14:47:58 +0000 (16:47 +0200)]
radv: advertise Vulkan 1.3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>