Hans de Goede [Tue, 23 Dec 2014 22:04:35 +0000 (23:04 +0100)]
sunxi: video: Enable video on sun8i, which supports LCD but not HDMI
The A23 (sun8i) only has lcd output support, so allow building the video code
without HDMI support for use with the A23.
Also the A23 has the same reset bits (and necessity to enable the DRC block)
as the sun6i, so enable those bits for sun8i too.
Note building without HDMI support is useful for the A13 (sun5i variant) too,
as that one does not have HDMI either.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 21 Dec 2014 15:28:32 +0000 (16:28 +0100)]
sunxi: video: Add lcd output support
Add lcd output support, see the new Kconfig entries and doc/README.video for
how to enable / configure this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 23 Dec 2014 17:39:52 +0000 (18:39 +0100)]
sunxi: video: Move sunxi_drc_init
Move sunxi_drc_init to directly above sunxi_engines_init, to avoid
unnecessary #ifdef-ery in later patches.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 21 Dec 2014 15:27:45 +0000 (16:27 +0100)]
sunxi: video: Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1
Modify sunxi_lcdc_pll_set to work with both tcon0 and tcon1, this is a
preparation patch for adding lcd support.
While at it also swap the divider search order, searching from low to
high, as the comment above the code says we should do. In cases where there
are multiple solutions this will result in picking a lower pll clock and
divider, which is more stable and saves power.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 21 Dec 2014 13:49:34 +0000 (14:49 +0100)]
sunxi: video: Prepare for lcd support
Refactor sunxi_mode_set into a bunch of helpers, and make it do a switch
case on sunxi_display.monitor to decide what to do.
Also rename sunxi_lcdc_mode_set to sunxi_lcdc_tcon1_mode_set, as it sets the
timings for tcon1, and for lcd support we need a similar function operating
on tcon0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 21 Dec 2014 13:37:45 +0000 (14:37 +0100)]
sunxi: video: Improve monitor video-mode option handling
Add a sunxi_monitor enum and parse the monitor option string into this enum
once, rather then doing strcmp-s on it in various places. This also adds
checking for it being a valid value.
This also adds new "none" and "lcd" values in preparation for lcd support.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Wed, 24 Dec 2014 18:34:38 +0000 (19:34 +0100)]
sunxi: gpio: Add support for gpio pins on the AXP209 pmic
Some boards use GPIO-s on the pmic, one example of this is the A13-OLinuXino
board, which uses gpio0 of the axp209 for the lcd-power signal.
This commit adds support for gpio pins on the AXP209 pmic, the sunxi_gpio.c
changes are universal, adding gpio support for the other AXP pmics (when
necessary) should be a matter of adding the necessary axp_gpio_foo functions
to their resp. drivers, and add "#define AXP_GPIO" to their header file.
Note this commit only adds support for the non device-model version of the
gpio code, patches for adding support to the device-model version are very
welcome.
The string representation for these gpio-s is AXP0-#, the 0 in the AXP0 prefix
is there in case we need to support gpio-s on more then 1 pmic in the future.
At least A80 boards have 2 pmics, and we may end up needing to support gpio-s
on both.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 22 Dec 2014 10:39:57 +0000 (11:39 +0100)]
sunxi: gpio: Properly sort mux defines by port number
Move a few mux defines around so that all the mux defines are properly sorted
by port number.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 20 Dec 2014 12:51:16 +0000 (13:51 +0100)]
sunxi: video: Set input sync enable
Add a write to the "unknown" (*) register to enable auto input sync, when
initially adding sunxi hdmi output support this magic write from the android
kernel code was missed, causing lcdc -> hdmi encoder sync problems.
With this write added, we can drop the modesetting retries and the extra
delays added to work around these sync problems.
With the retries dropped there also is no need to 0 all the enable flags at
the beginning of the modeset, as they are initialized to 0 already by
engines_init.
*) "unknown" is the actual name of this register in the android kernel sources
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Sat, 20 Dec 2014 14:15:23 +0000 (15:15 +0100)]
sunxi: video: Give hotplug-detect (hpd) signal some time to show up
When using a hdmi powered hdmi to vga dongle, and cold booting a sunxi
device, the hpd detect code would not see the dongle (until a warm reboot),
because the dongle needs some time to boot.
Testing has shown that this dongle needs 213ms to respond on a cold boot,
so wait up to 300ms for a hpd signal to show up before giving up.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Sat, 20 Dec 2014 13:31:45 +0000 (14:31 +0100)]
sunxi: video: When using edid use CEA681 extension blocks to select hdmi output
When using edid use CEA681 edid extension blocks to select between dvi and
hdmi output formats, so that u-boot will automatically do the right thing.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Sat, 20 Dec 2014 13:01:48 +0000 (14:01 +0100)]
sunxi: video: Add sunxi_hdmi_edid_get_block helper function
Add a sunxi_hdmi_edid_get_block helper function, this is a preparation patch
for adding support for parsing EDID extension blocks.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Sat, 20 Dec 2014 12:38:06 +0000 (13:38 +0100)]
sunxi: video: Add hdmi support
So far we've been programming the hdmi-encoder to send out dvi data over the
hdmi connector. This works well for most devices, including hdmi devices, but
not all devices accept dvi data on a hdmi input.
Add support for sending proper hdmi data over the hdmi output found on most
sunxi boards. This can be turned on by adding monitor=hdmi as option to the
video-mode env. variable.
A follow up patch will determine whether to send dvi or hdmi automatically when
EDID is used.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 15:05:12 +0000 (16:05 +0100)]
sunxi: video: Add DDC & EDID support
Add DDC & EDID support and use it to automatically select the native mode of
the attached monitor. This can be disabled by adding edid=0 as option
to the video-mode env. variable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 14:13:57 +0000 (15:13 +0100)]
sunxi: video: Add hpd option
Allow the user to specify hpd=0 as option in the video-mode env. variable,
if hpd is set to 0 then the hdmi output will be brought up even if no cable
is connected.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 13:03:40 +0000 (14:03 +0100)]
sunxi: video: Add support for video-mode environment variable
Add support for the standard video-mode environment variable using the
videomodes.c video_get_ctfb_res_modes() helper function.
This will allow users to specify the resolution e.g. :
setenv video-mode sunxi:video-mode=1280x1024-24@60
saveenv
Also make the reserved fb mem slightly larger to allow 1920x1200 to work.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 12:46:33 +0000 (13:46 +0100)]
sunxi: video: Use video-mode/-timing from videomodes
Switch from fb_videomode to ctfb_res_modes and use the predefined videotimings
from videomodes.c, rather then defining our own.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Sat, 20 Dec 2014 13:30:27 +0000 (14:30 +0100)]
edid: Add struct and defines for cea681 extension blocks
Add a struct describing the (fixed) bits of cea681 edid extension blocks,
and defines for accessing various bitfields.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Mon, 24 Nov 2014 12:47:13 +0000 (13:47 +0100)]
edid: Add an edid_check_checksum() helper function
Add a helper function to check the checksum of an EDID data block.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 14:47:37 +0000 (15:47 +0100)]
videomodes: Add video_edid_dtd_to_ctfb_res_modes helper function
Add a video_edid_dtd_to_ctfb_res_modes helper function to convert an EDID
detailed timing to a struct ctfb_res_modes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 13:27:46 +0000 (14:27 +0100)]
videomodes: Add helper functions to parse video-mode env-var extra options
Add 2 helper functions to get strings, respectively integers from the options
value returned by video_get_video_mode() / video_get_ctfb_res_modes().
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 12:22:47 +0000 (13:22 +0100)]
videomodes: Add video_get_ctfb_res_modes helper function
Add a video_get_ctfb_res_modes() helper function, which uses
video_get_video_mode() to parse the 'video-mode' environment variable and then
looks up the matching mode in res_mode_init and returns the matching mode.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 10:45:19 +0000 (11:45 +0100)]
videomodes: Add a bunch of high res modes
Add modes useful for hd-tvs and modern monitors.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 10:11:52 +0000 (11:11 +0100)]
videomodes: Add (vesa) standard timings
The timings for the modes defined in videomodes.c differ (significantly)
from vesa standard timings for these modes.
This commit adds a version with the proper std timings for these modes,
since I do not want to cause regressions, boards which want to use the standard
timings need to define CONFIG_VIDEO_STD_TIMINGS to get the new correct timings.
Since there is no std timing for 960x720 this commit uses the timing used
by the nvidia video drivers for 960x720, which uses a standard pixelclock
of 74.25 MHz rather then the weird 76.335... clock used by the old modes.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Fri, 19 Dec 2014 09:38:49 +0000 (10:38 +0100)]
videomodes: Add pixelclock_khz and refresh fields to ctfb_res_modes
Add pixelclock_khz and refresh fields to ctfb_res_modes:
1) pixelclocks are usually referred to in hz, not picoseconds, and e.g
pll-s are also typically programmed in hz, not ps. Converting between the
2 leads to rounding differences, add a pixelclock_khz field to directly
store the *exact* pixelclock for a mode, so that drivers do not need to
resort to rounding tricks to try and guess the exact pixelclock;
2) The video-mode environment variable, as parsed by video_get_video_mode
also contains the vertical refresh rate, add a refresh field, so that
the refresh-rate can be matched when parsing the video-mode environment
variable.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Anatolij Gustschin <agust@denx.de>
Hans de Goede [Wed, 31 Dec 2014 10:30:26 +0000 (11:30 +0100)]
sun7i: Add new Bananapro board / defconfig
Add support for the new Bananapro A20 development board from lemaker.org.
This board features 1G RAM, 2 USB A receptacles, 1 micro USB receptacle for
OTG, 1 micro USB receptacle for power, HDMI, sata, Gbit ethernet, ir receiver,
3.5 mm jack for a/v out, on board microphone, 40 gpio pins and sdio wifi.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 27 Dec 2014 16:56:59 +0000 (17:56 +0100)]
sunxi: Fix PLL1 running at half speed on sun8i
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Siarhei Siamashka [Wed, 24 Dec 2014 16:58:17 +0000 (18:58 +0200)]
sunxi: Fix buggy sun6i/sun8i DRAM size detection logic
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).
The current sun6i/sun8i DRAM size detection logic, which is
inherited from the Allwinner code, relies on using a large magic
signature with the hope that it is unique enough and unlikely to
ever accidentally match this leftover garbage data in RAM. But
this approach is inherently unsafe, as can be demonstrated using
the following test program:
/***** A testcase for reproducing the problem ******/
void main(int argc, char *argv[])
{
size_t size, i;
uint32_t *buf;
/* Allocate the buffer */
if (argc < 2 || !(size = (size_t)atoi(argv[1]) * 1048576) ||
!(buf = malloc(size))) {
printf("Need buffer size in MiB as a cmdline argument\n");
exit(1);
}
/* Fill it with the Allwinner DRAM "magic" values */
for (i = 0; i < size / 4; i++)
buf[i] = 0xaa55aa55 + ((uintptr_t)&buf[i] / 4) % 64;
/* Try to reboot */
system("reboot");
/* And wait */
for (;;) {}
}
/***************************************************/
If this test program is run on the device (giving it a large
chunk of memory), then the DRAM size detection logic in u-boot
gets confused after reboot and fails to initialize DRAM properly.
A better approach is not to rely on luck and abstain from making
any assumptions about the properties of the leftover garbage
data in RAM. Instead just use a more reliable code for testing
whether two different addresses refer to the same memory location.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Siarhei Siamashka [Sat, 27 Dec 2014 07:38:57 +0000 (09:38 +0200)]
sun7i: Add defconfig for MSI Primo73 tablet
This patch uses the same DRAM settings as in the pre-installed
Android firmware. The LCD display is supported too.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Siarhei Siamashka [Sat, 27 Dec 2014 07:38:56 +0000 (09:38 +0200)]
sun6i: Add defconfig for MSI Primo81 tablet
This patch uses the same ZQ and DRAM clock settings as in the
pre-installed Android firmware.
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Siarhei Siamashka [Thu, 25 Dec 2014 00:34:47 +0000 (02:34 +0200)]
sunxi: Fix CONFIG_UART0_PORT_F build and add it to menuconfig
The CONFIG_UART0_PORT_F option has been supported since
http://git.denx.de/?p=u-boot.git;a=commit;h=
ff2b47f6a9cc1025
This option is primarily useful only for low level u-boot debugging
on tablets, where normal UART0 is difficult to access and requires
device disassembly and/or soldering.
This patch now allows it to be selected from menuconfig. A dependency on
SPL_FEL is added because u-boot does not support booting from NAND yet
and also booting from SD card is impossible when a MicroSD breakout board
is plugged into the SD slot.
Additionally a compilation problem is fixed:
common/spl/built-in.o: In function `spl_mmc_load_image':
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:94: undefined reference to `mmc_initialize'
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:96: undefined reference to `find_mmc_device'
/tmp/u-boot-sunxi/common/spl/spl_mmc.c:104: undefined reference to `mmc_init'
scripts/Makefile.spl:206: recipe for target 'spl/u-boot-spl' failed
Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Mon, 8 Dec 2014 13:34:29 +0000 (14:34 +0100)]
sun8i: Add defconfig for Ippo_q8h v1.2
We need separate defconfigs for the v5 and v1.2 versions of this board, as
they use different DRAM parameters.
Note they also use different dtb files, as the wifi is different too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 20 Dec 2014 11:25:14 +0000 (12:25 +0100)]
sun8i: Ippo_q8h_v5_defconfig: Enable SPL support
Now that we've sun8i dram-init support we can enable the SPL for sun8i boards.
While at it also replace CONFIG_DEFAULT_DEVICE_TREE with CONFIG_FDTFILE,
the former is for u-boot's own fdt usage, which we do not use (yet), the later
specifies the fdt to pass to the kernel, which is the one we want.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 7 Dec 2014 13:34:27 +0000 (14:34 +0100)]
sun8i: Add dram initialization support
Based on the register / dram_para headers from the Allwinner u-boot / linux
sources + the init sequences from boot0.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 8 Dec 2014 13:17:08 +0000 (14:17 +0100)]
sunxi: Use memcmp for mctl_mem_matches
Use memcmp for mctl_mem_matches instead of DIY.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 8 Dec 2014 12:58:53 +0000 (13:58 +0100)]
sunxi: Fill memory before comparing it when doing dram init on sun6i
The sun8i boot0 code fills the DRAM with a "random" pattern before comparing
it at different offsets to do columns, etc. detection. The sun6i boot0 code
does not do it, instead relying on the memory contents being random enough
to begin with for the memcmp to properly detect the wrap-around address, iow
it is working purely by chance. Since our sun6i dram code was modelled after
the boot0 code it contained the same issue.
This commit fixes this by filling the memory with a unique, distinct pattern.
The new mctl_mem_fill function this introduces is added as an inline helper
in dram.h, so that it can be shared with the sun8i dram code.
While at it move mctl_mem_matches to dram.h for re-use in sun8i too.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Mon, 8 Dec 2014 12:38:21 +0000 (13:38 +0100)]
sunxi: Move await_completion dram helper to dram.h
The await_completion helper is already copy pasted between the sun4i and sun6i
dram code, and we need it for sun8i too, so lets make it an inline helper in
dram.h, rather then adding yet another copy.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 7 Dec 2014 20:09:31 +0000 (21:09 +0100)]
sun6i: clock_set_pll5: Calculate k and m rather then hardcoding them
Our old hardcoded k and m values are based on PLL5 being configured in steps
of 48 MHz, which is correct for sun6i where the DRAM PLL runs at twice the
DRAM CLK, which is usually configured in 24 MHz step. But on the A23 (sun8i)
the PLL5 runs at half the DRAM CLK, so we require 12 MHz steps.
This commit adjusts clock_set_pll5 to automatically select the best k and m
depending on the requested clk rate.
Suggested-by: Siarhei Siamashka <siarhei.siamashka@gmail.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 30 Nov 2014 10:58:17 +0000 (11:58 +0100)]
sun6i: Add a sigma_delta_enable paramter to clock_set_pll5()
The sun8i dram code sometimes wants to enable sigma delta mode,
add a parameter to allow this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 13:20:09 +0000 (14:20 +0100)]
sunxi: axp221: Disable dcdc4 on sun8i (A23)
dcdc4 is not used on sun8i, disable it.
While at it also add comments to the other fixed voltages to document what
they are used for.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 13:02:38 +0000 (14:02 +0100)]
sunxi: axp221: Explicitly turn off unused voltages
Explicitly turn off unused voltages, rather then leaving them as is. Likewise
explictly enabled the dcdc convertors, rather then assuming they are already
enabled at boot.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 13:12:06 +0000 (14:12 +0100)]
sunxi: axp221: Make dcdc1 voltage configurable
The dcdc1 voltage is typically used as generic 3.3V IO voltage for things like
GPIO-s, sdcard interfaces, etc. On most boards this is undervolted to 3.0V to
safe battery, but not on all, make it configurable so that we can use the
same settings as the original firmware on all boards.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 11:40:45 +0000 (12:40 +0100)]
sunxi: axp221: Add Kconfig help and sane defaults for typical ldo usage
Some of the ldo-s of the axp221 are used in the same way on most boards, add
comments to the Kconfig help text to reflect this, and give them defaults
matching their typical usage.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 29 Nov 2014 22:54:25 +0000 (23:54 +0100)]
sunxi: axp221: Add axp223 support
The axp223 appears to be the same as the axp221, except that it uses the
rsb to communicate rather then the p2wi. At least all the registers we use
are 100% the same.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 29 Nov 2014 12:38:35 +0000 (13:38 +0100)]
sunxi: Add support for the rsb (Reduced Serial Bus)
sun8i (A23) introduces a new bus for communicating with the pmic, the rsb,
the rsb is also used to communicate with the pmic on the A80, and is
documented in the A80 user manual.
This commit adds support for this based on the rsb driver from the allwinner
u-boot sources.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 13 Dec 2014 09:25:14 +0000 (10:25 +0100)]
sun6i: s/SUNXI_*P2WI*/SUN6I_*P2WI*/
The p2wi interface is only available on sun6i, adjust the gpio pinmux and
base address defines for it to reflect this.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Axel Lin [Sat, 20 Dec 2014 03:41:25 +0000 (11:41 +0800)]
mmc: sunxi: Fix misuse of gpio_direction_input()
It does not make sense to make gpio_direction_input() return the gpio input
status. The return value of gpio_direction_input() is inconsistent if
CONFIG_DM_GPIO is defined.
And we don't need to call gpio_direction_input() int sunxi_mmc_getcd().
Just init the gpio once in mmc_resource_init() is enough.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Jan Kiszka [Thu, 27 Nov 2014 08:38:50 +0000 (09:38 +0100)]
sunxi: Align PSCI stack calculation to comment
0x400 is true 1K.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ian Campbell <ijc@hellion.org.uk>
Chen-Yu Tsai [Tue, 9 Dec 2014 08:56:53 +0000 (16:56 +0800)]
sun6i: Add new board Merrii Hummingbird A31
The Merrii Hummingbird A31 is a A31 based development board with 1G
RAM, 8G NAND, AP6210 WiFi+BT, gigabit ethernet, USB OTG, 2 USB 2.0
ports connected to a USB hub chip, HDMI, VGA, TV and stereo in/out.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Hans de Goede [Tue, 25 Nov 2014 23:04:24 +0000 (00:04 +0100)]
sunxi: Add sunxi_get_sid helper function
On sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a helper function to abstract this away.
This makes our MAC address generation code also work on sun6i.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 25 Nov 2014 15:37:52 +0000 (16:37 +0100)]
sun6i: axp221: Add axp221_get_sid function
For sun6i the SID is stored in the pmic, rather then in the SoC itself,
add a function to retreive the sid.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 7 Dec 2014 19:55:10 +0000 (20:55 +0100)]
sunxi: mmc: Properly setup mod-clk and clock sampling phases
The sunxi mmc controller has both an internal clock divider, as well as
the divider in the mod0-clk for the mmc controller.
The internal divider cannot be used, as it conflicts with the setting of
clock sampling phases which is done in the mod0-clk, so it must be set to
0 (divide by 1).
For some reason while the kernel has had this correct from day one, the
u-boot sunxi mmc code has been using a fixed mod0-clk and setting its
internal divider depending on the desired speed. This is something which
we've inherited from the original Allwinner u-boot sources, but while this
has been fixed in Allwinner's own u-boot code at least for the A23 and later
upstream u-boot was still doing this wrong.
This commit fixes this, thereby also fixing mmc support not working reliable
on the A23 (which seems more sensitive to this) and possible also fixes some
other sunxi mmc issues.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Tue, 2 Dec 2014 09:29:42 +0000 (10:29 +0100)]
sun6i: Update Colombus defconfig settings
The Colombus defconfig settings are missing a number of settings for recently
added features, because we did not know exactly how things were hooked up.
Maxime Ripard has run various tests to get us the necessary details, this
commit updates the defconfig with this info.
This commit also updates the dram clk and zq values with values verified
by Maxime to be the ones used by the original firmware for this board.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sun, 16 Nov 2014 10:33:56 +0000 (11:33 +0100)]
sun6i: Add new CSQ_CS908 board
The CSQ CS908 is an A31s based top-set box, with 1G RAM, 8G NAND,
rtl8188etv usb wifi, 2 USB A receptacles (1 connected through the OTG
controller), ethernet, 3.5 mm jack with a/v out and hdmi out:
http://www.geekbuying.com/item/CS908-Allwinner-A31S-Quad-Core-1-2GHz-Android-4-4-Mini-TV-Box-HDMI-HDD-Player-1G-8G-WIFI-Miracast---Black-333395.html
Note it has no sdcard slot and therefore can only be fel booted.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 15 Nov 2014 22:18:18 +0000 (23:18 +0100)]
sun6i: dram: Do not try to initialize a second dram chan on A31s
The A31s only has one dram channel, so do not bother with trying to initialize
a second channel.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 15 Nov 2014 21:55:53 +0000 (22:55 +0100)]
sun6i: Add sunxi_get_ss_bonding_id() function
Add a sunxi_get_ss_bonding_id() function, and use it to differentiate between
the A31s and the A31.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Hans de Goede [Sat, 15 Nov 2014 18:46:39 +0000 (19:46 +0100)]
sun6i: Make dram clk and zq value Kconfig options
It turns out that there is a too large spread between boards to handle this
with a default value, turn this into Kconfig options, and set the values
the factory images are using for the Colombus and Mele_M9 boards.
Note this changes the ZQ default when not overriden through defconfig from
120 to 123, as that is what most boards seem to actually use.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Acked-by: Ian Campbell <ijc@hellion.org.uk>
Tom Rini [Tue, 13 Jan 2015 18:39:25 +0000 (13:39 -0500)]
Merge git://git.denx.de/u-boot-x86
Bin Meng [Tue, 6 Jan 2015 06:35:38 +0000 (14:35 +0800)]
x86: Remove CONFIG_DISPLAY_CPUINFO in chromebook_link.h
CONFIG_DISPLAY_CPUINFO is already defined in x86-common.h, so remove
it to avoid duplication.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:24 +0000 (22:14 +0800)]
x86: Update README.x86 for coreboot support
Update README.x86 to include new build instructions for U-Boot as
the coreboot payload and testing considerations with coreboot.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:23 +0000 (22:14 +0800)]
x86: coreboot: Configure pci memory regions
Configure coreboot pci memory regions so that pci device drivers
could work correctly.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:22 +0000 (22:14 +0800)]
x86: coreboot: Wrap cros_ec initialization
cros_ec_board_init() should be called only when CONFIG_CROS_EC is
enabled.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:21 +0000 (22:14 +0800)]
x86: Make chromebook_link the default board for coreboot
Change SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE to chromebook_link
which is currently the only real board officially supported to run
U-Boot loaded by coreboot.
Note the symbolic link file chromebook_link.dts is deleted and
link.dts is renamed to chromebook_link.dts.
To avoid multiple definition of video_hw_init, the CONFIG_VIDEO_X86
define needs to be moved to arch/x86/cpu/ivybridge/Kconfig.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:20 +0000 (22:14 +0800)]
x86: Remove include/configs/coreboot.h
Since we already swtiched to use the new mechanism for building
U-Boot for coreboot, coreboot.h is no longer needed so remove it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:19 +0000 (22:14 +0800)]
x86: Move CONFIG_SYS_CAR_xxx to Kconfig
Move CONFIG_SYS_CAR_ADDR and CONFIG_SYS_CAR_SIZE to Kconfig so that
we don't need them in the board configuration file thus the same
board configuratoin file can be used to build both coreboot version
and bare version.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:18 +0000 (22:14 +0800)]
x86: coreboot: Move coreboot-specific defines from coreboot.h to Kconfig
There are many places in the U-Boot source tree which refer to
CONFIG_SYS_COREBOOT, CONFIG_CBMEM_CONSOLE and CONFIG_VIDEO_COREBOOT
that is currently defined in coreboot.h.
Move them to arch/x86/cpu/coreboot/Kconfig so that we can switch
to board configuration file to build U-Boot later.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:17 +0000 (22:14 +0800)]
x86: coreboot: Make SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE configurable
In theory U-Boot built for coreboot is supposed to run as a payload
to be loaded by coreboot on every board that coreboot supports.
The U-Boot build process uses SYS_CONFIG_NAME and DEFAULT_DEVICE_TREE
which are hardcoded in board defconfig and Kconfig files. For better
support of coreboot, we want to make these two options configurable
so that we can easily change them during 'make menuconfig' so that
the generated U-Boot image for coreboot is board configuration aware.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:16 +0000 (22:14 +0800)]
x86: Hide ROM chip size when CONFIG_X86_RESET_VECTOR is not selected
When CONFIG_X86_RESET_VECTOR is not selected, specifying the ROM chip
size is meaningless, hence hide it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:15 +0000 (22:14 +0800)]
x86: Move CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
Convert CONFIG_X86_RESET_VECTOR and CONFIG_SYS_X86_START16 to Kconfig
options so that we can remove them from board configuration file.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:14 +0000 (22:14 +0800)]
x86: Allow a hardcoded TSC frequency provided by Kconfig
By default U-Boot automatically calibrates TSC running frequency via
MSR and PIT. The calibration may not work on every x86 processor, so
a new Kconfig option CONFIG_TSC_CALIBRATION_BYPASS is introduced to
allow bypassing the calibration and assign a hardcoded TSC frequency
CONFIG_TSC_FREQ_IN_MHZ.
Normally the bypass should be turned on in a simulation environment
like qemu.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 14:14:13 +0000 (22:14 +0800)]
x86: coreboot: Set up timer base correctly
If coreboot is built with CONFIG_COLLECT_TIMESTAMPS, use the value
of base_time in coreboot's timestamp table as our timer base,
otherwise TSC counter value will be used.
Sometimes even coreboot is built with CONFIG_COLLECT_TIMESTAMPS,
the value of base_time in the timestamp table is still zero, so
we must exclude this case too (this is currently seen on booting
coreboot in qemu).
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 6 Jan 2015 06:04:36 +0000 (14:04 +0800)]
x86: fsp: Drop get_hob_type() and get_hob_length()
These two are not worth having separate inline functions as they are
really simple, so drop them.
Also changed 'type' parameter of fsp_get_next_hob() from u16 to uint.
Suggested-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:15 +0000 (16:18 -0700)]
x86: Add an 'mtrr' command to list and adjust MTRRs
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.
Update the documentation to list some of the available commands.
This does not support fixed MTRRs as yet.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 1 Jan 2015 23:18:14 +0000 (16:18 -0700)]
x86: ivybridge: Update microcode early in boot
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now, do an update early on so that it definitely works. Also refuse to
continue unless the microcode update check (later in boot) is successful.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:13 +0000 (16:18 -0700)]
x86: Disable CAR before relocation on platforms that need it
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:12 +0000 (16:18 -0700)]
x86: ivybridge: Add a way to turn off the CAR
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:11 +0000 (16:18 -0700)]
x86: Commit the current MTRRs before relocation
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:10 +0000 (16:18 -0700)]
x86: ivybridge: Request MTRRs for DRAM regions
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.
We set RAM as cacheable (with write-back) and registers as non-cacheable.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:09 +0000 (16:18 -0700)]
x86: board_f: Adjust x86 boot order for performance
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:08 +0000 (16:18 -0700)]
x86: ivybridge: Set up an MTRR for the video frame buffer
Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:07 +0000 (16:18 -0700)]
x86: Add support for MTRRs
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up booting so should be supported. Add these to global_data
so they can be requested while booting. We will apply the changes during
relocation (in a later commit).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:06 +0000 (16:18 -0700)]
x86: ivybridge: Drop support for ROM caching
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:05 +0000 (16:18 -0700)]
x86: pci: Display vesa modes in hex
The hex value is more commonly understood, so use that instead of decimal.
Add a 0x prefix to avoid confusion.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 1 Jan 2015 23:18:04 +0000 (16:18 -0700)]
x86: Tidy up VESA mode numbers
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:03 +0000 (16:18 -0700)]
x86: Use cache, don't clear the display in video BIOS
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:18:02 +0000 (16:18 -0700)]
x86: ivybridge: Only run the Video BIOS when video is enabled
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.
We could add a command to run the video BIOS later when needed, but this is
not considered at present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 1 Jan 2015 23:18:01 +0000 (16:18 -0700)]
x86: video: Add debug option to time the BIOS copy
This can be very slow - typically 80ms even on a fast machine since it uses
the SPI flash to read the data. Add an option to display the time taken.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 1 Jan 2015 23:18:00 +0000 (16:18 -0700)]
x86: pci: Don't return a vesa mode when there is not video
If the video has not been set up, we should not return a success code. This
can be detected by seeing if any of the variables are non-zero.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:17:59 +0000 (16:17 -0700)]
x86: video: Add a debug() to display the frame buffer address
Provide a way to display this address when booting.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Thu, 1 Jan 2015 23:17:56 +0000 (16:17 -0700)]
x86: Correct ifdtool microcode calculation
This currently assumes that U-Boot resides at the start of ROM. Update
it to remove this assumption.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 1 Jan 2015 23:17:55 +0000 (16:17 -0700)]
x86: Drop RAMTOP Kconfig
We don't need this in U-Boot since we calculate it based on available memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 1 Jan 2015 23:17:54 +0000 (16:17 -0700)]
x86: Correct XIP_ROM_SIZE
This should default to the size of the ROM for faster execution before
relocation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:14 +0000 (16:05 +0800)]
x86: crownbay: Add pci devices in the dts file
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio serial
port (io addr 0x3f8) is still used on Crown Bay as the console port.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:13 +0000 (16:05 +0800)]
x86: Use ePAPR defined properties for x86-uart
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:12 +0000 (16:05 +0800)]
serial: ns16550: Support ns16550 compatible pci uart devices
There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.
Those pci uart devices can have their register be memory-mapped, or
i/o-mapped. The driver will try to use the memory-mapped register if
the reg property in the node has an entry to describe the memory-mapped
register, otherwise i/o-mapped register will be used.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Bin Meng [Wed, 31 Dec 2014 08:05:11 +0000 (16:05 +0800)]
fdt: Add several apis to decode pci device node
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pci device register bar
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Acked-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Simon Glass <sjg@chromium.org>
(Include <pci.h> in fdtdec.h and adjust tegra to fix build error)
Georgi Botev [Tue, 13 Jan 2015 10:30:17 +0000 (12:30 +0200)]
PM9G45 adding generic board support
Signed-off-by: Georgi Botev <botev@ronetix.at>
Georgi Botev [Tue, 13 Jan 2015 10:15:55 +0000 (12:15 +0200)]
PM9261 adding generic board support
Signed-off-by: Georgi Botev <botev@ronetix.at>
Georgi Botev [Tue, 13 Jan 2015 10:07:21 +0000 (12:07 +0200)]
PM9263 adding generic board support
Signed-off-by: Georgi Botev <botev@ronetix.at>
Matthias Fuchs [Mon, 12 Jan 2015 21:47:35 +0000 (22:47 +0100)]
ppc4xx: switch VOM405 to generic board
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu>