Shazad Hussain [Tue, 13 Dec 2022 09:59:21 +0000 (15:29 +0530)]
arm64: dts: qcom: sa8540p-ride: enable pcie2a node
Add the pcie2a, pcie2a_phy, and respective tlmm nodes that are needed to
get pcie 2a controller enabled on Qdrive3.
This patch enables 4GB 64bit memory space for PCIE_2A to have BAR
allocations of 64bit pref mem needed on this Qdrive3 platform with dual
SoCs for root port and switch NT-EP. Hence this ranges property is
overridden in sa8540p-ride.dts only.
Moved tlmm node at the end as it tends to become rahter long.
Link: https://lore.kernel.org/lkml/Y49k1k8ayI9%2FrK+R@hovoldconsulting.com/
Signed-off-by: Shazad Hussain <quic_shazhuss@quicinc.com>
Reviewed-by: Brian Masney <bmasney@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213095922.11649-1-quic_shazhuss@quicinc.com
Krzysztof Kozlowski [Mon, 12 Dec 2022 10:02:28 +0000 (11:02 +0100)]
arm64: dts: qcom: sdm845: order top-level nodes alphabetically
Order top-level nodes like memory, reserved-memory, opp-table-cpu
alphabetically for easier code maintenance. No functional change (same
dtx_diff, except phandle changes).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221212100232.138519-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 12 Dec 2022 10:02:27 +0000 (11:02 +0100)]
arm64: dts: qcom: sc7180: order top-level nodes alphabetically
Order top-level nodes like memory, reserved-memory, opp-table-cpu
alphabetically for easier code maintenance. No functional change (same
dtx_diff).
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Dmitry Baryshkov<dmitry.baryshkov@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221212100232.138519-1-krzysztof.kozlowski@linaro.org
Rob Herring [Wed, 7 Dec 2022 21:13:27 +0000 (15:13 -0600)]
arm64: dts: qcom: sc7280: Fix CPU nodes compatible string
'arm,kryo' is not documented and is not an Arm Ltd thing either as that
is Qualcomm branding. The correct compatible is 'qcom,kryo'.
Signed-off-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207211327.2848665-1-robh@kernel.org
Konrad Dybcio [Thu, 29 Dec 2022 10:32:12 +0000 (11:32 +0100)]
arm64: dts: qcom: sm8450-nagara: Configure SLG51000 PMIC
Nagara devices use the Dialog SLG51000 PMIC for powering some camera
sensors. Add the required nodes to support it.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-7-konrad.dybcio@linaro.org
Konrad Dybcio [Thu, 29 Dec 2022 10:32:11 +0000 (11:32 +0100)]
arm64: dts: qcom: sm8450-nagara: Enable PMIC RESIN+PON
Enable the power and volume up buttons, connected to PON and RESIN
respectively.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-6-konrad.dybcio@linaro.org
Konrad Dybcio [Thu, 29 Dec 2022 10:32:10 +0000 (11:32 +0100)]
arm64: dts: qcom: sm8450-nagara: Set up camera regulators
Set up gpio-controlled fixed regulators for camera on PDX223 and fix
up the existing ones in common and PDX224 trees.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-5-konrad.dybcio@linaro.org
Konrad Dybcio [Thu, 29 Dec 2022 10:32:09 +0000 (11:32 +0100)]
arm64: dts: qcom: sm8450-nagara: Add GPIO keys
With PMIC GPIOs now available, set up required pin settings and add
gpio-keys.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-4-konrad.dybcio@linaro.org
Konrad Dybcio [Thu, 29 Dec 2022 10:32:08 +0000 (11:32 +0100)]
arm64: dts: qcom: sm8450-nagara: Add GPIO line names for PMIC GPIOs
Sony ever so graciously provides GPIO line names in their downstream
kernel (though sometimes they are not 100% accurate and you can judge
that by simply looking at them and with what drivers they are used).
Add these to the PDX223&224 DTSIs to better document the hardware.
Diff between 223 and 224:
pm8350b
< "CAM_PWR_LD_EN",
> "NC",
pm8350c
< "RGBC_IR_PWR_EN",
> "NC",
Which is due to different camera power wiring on 223 and lack of a
ToF sensor on 224.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-3-konrad.dybcio@linaro.org
Konrad Dybcio [Thu, 29 Dec 2022 10:32:07 +0000 (11:32 +0100)]
arm64: dts: qcom: sm8450-nagara: Include PMIC DTSIs
Now that SPMI is finally in place, include the DTSIs of PMICs present
on Nagara.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-2-konrad.dybcio@linaro.org
Vinod Koul [Thu, 29 Dec 2022 10:32:06 +0000 (11:32 +0100)]
arm64: dts: qcom: sm8450: add spmi node
Add the spmi bus as found in the SM8450 SoC
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
[Konrad: 0x0 -> 0, move #cells down, make reg-names a vertical list]
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
[bjorn: Adjusted unit address]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229103212.984324-1-konrad.dybcio@linaro.org
Neil Armstrong [Wed, 16 Nov 2022 10:48:35 +0000 (11:48 +0100)]
arm64: dts: qcom: sm8550: add QCrypto nodes
Add the QCE and Crypto BAM DMA nodes.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-qce-v1-0-fe750dfa90f6@linaro.org
Neil Armstrong [Wed, 16 Nov 2022 10:45:50 +0000 (11:45 +0100)]
arm64: dts: qcom: sm8550: add I2C Master Hub nodes
Add the I2C Master Hub wrapper and I2C serial engines nodes.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221115-topic-sm8550-upstream-dts-gpi-qup-v1-0-86a60cf3e57d@linaro.org
Abel Vesa [Fri, 6 Jan 2023 20:10:47 +0000 (22:10 +0200)]
arm64: dts: qcom: Add base SM8550 MTP dts
Add dts file for Qualcomm MTP platform which uses SM8550 SoC.
Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-11-abel.vesa@linaro.org
Neil Armstrong [Fri, 6 Jan 2023 20:10:46 +0000 (22:10 +0200)]
arm64: dts: qcom: Add PMR735d pmic dtsi
Add nodes for PMR735d in separate dtsi file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-10-abel.vesa@linaro.org
Neil Armstrong [Fri, 6 Jan 2023 20:10:45 +0000 (22:10 +0200)]
arm64: dts: qcom: Add PMK8550 pmic dtsi
Add nodes for PMK8550 in separate dtsi file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-9-abel.vesa@linaro.org
Neil Armstrong [Fri, 6 Jan 2023 20:10:44 +0000 (22:10 +0200)]
arm64: dts: qcom: Add PM8550vs pmic dtsi
Add nodes for PM8550vs in separate dtsi file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-8-abel.vesa@linaro.org
Neil Armstrong [Fri, 6 Jan 2023 20:10:43 +0000 (22:10 +0200)]
arm64: dts: qcom: Add PM8550ve pmic dtsi
Add nodes for PM8550ve in separate dtsi file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-7-abel.vesa@linaro.org
Neil Armstrong [Fri, 6 Jan 2023 20:10:42 +0000 (22:10 +0200)]
arm64: dts: qcom: Add PM8550b pmic dtsi
Add nodes for PM8550b in separate dtsi file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-6-abel.vesa@linaro.org
Neil Armstrong [Fri, 6 Jan 2023 20:10:41 +0000 (22:10 +0200)]
arm64: dts: qcom: Add PM8550 pmic dtsi
Add nodes for PM8550 in separate dtsi file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-5-abel.vesa@linaro.org
Neil Armstrong [Fri, 6 Jan 2023 20:10:40 +0000 (22:10 +0200)]
arm64: dts: qcom: Add pm8010 pmic dtsi
Add nodes for pm8010 in separate dtsi file.
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-4-abel.vesa@linaro.org
Abel Vesa [Fri, 6 Jan 2023 20:10:39 +0000 (22:10 +0200)]
arm64: dts: qcom: Add base SM8550 dtsi
Add base dtsi for SM8550 SoC and includes base description of
CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
interconnect, thermal sensor, cpu cooling maps and SMMU nodes
which helps boot to shell with console on boards with this SoC.
Co-developed-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Sai Prakash Ranjan <quic_saipraka@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230106201047.337409-3-abel.vesa@linaro.org
Bjorn Andersson [Tue, 10 Jan 2023 18:25:33 +0000 (12:25 -0600)]
Merge branch '
20230104093450.3150578-2-abel.vesa@linaro.org' into arm64-for-6.3
Merge the TCSR clock binding, to gain the Devicetree include file.
Abel Vesa [Wed, 4 Jan 2023 09:34:47 +0000 (11:34 +0200)]
dt-bindings: clock: Add SM8550 TCSR CC clocks
Add bindings documentation for clock TCSR driver on SM8550.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230104093450.3150578-2-abel.vesa@linaro.org
Bjorn Andersson [Tue, 10 Jan 2023 18:21:20 +0000 (12:21 -0600)]
Merge branch 'icc-sm8550-immutable' of https://git./linux/kernel/git/djakov/icc into arm64-for-6.3
Merge the immutable SM8550 interconnect branch, to gain the include file
from the binding.
Dmitry Baryshkov [Tue, 10 Jan 2023 05:54:33 +0000 (07:54 +0200)]
arm64: dts: qcom: sm8450: Add compat qcom,sm8450-dsi-ctrl
Add silicon specific compatible qcom,sm8450-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sm8450 against the yaml documentation.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230110055433.734188-3-dmitry.baryshkov@linaro.org
Dmitry Baryshkov [Tue, 10 Jan 2023 05:54:32 +0000 (07:54 +0200)]
arm64: dts: qcom: sm8150: Add compat qcom,sm8150-dsi-ctrl
Add silicon specific compatible qcom,sm8150-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sm8150 against the yaml documentation.
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230110055433.734188-2-dmitry.baryshkov@linaro.org
Krzysztof Kozlowski [Thu, 22 Dec 2022 15:13:19 +0000 (16:13 +0100)]
arm64: dts: qcom: sdm845: do not customize SPI0 pin drive/bias
Each board should define pin drive/bias for used busses. All boards
using SPI0 (db845c and cheza) already do it, so drop the bias/drive
strength from SoC DTSI.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Thu, 22 Dec 2022 15:13:18 +0000 (16:13 +0100)]
arm64: dts: qcom: sdm845: align TLMM pin configuration with DT schema
DT schema expects TLMM pin configuration nodes to be named with
'-state' suffix and their optional children with '-pins' suffix.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-3-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Thu, 22 Dec 2022 15:13:17 +0000 (16:13 +0100)]
arm64: dts: qcom: sdm845-xiaomi-beryllium: fix audio codec interrupt pin name
The pin config entry should have a string, not number, for the GPIO used
as WCD9340 audio codec interrupt.
Fixes:
dd6459a0890a ("arm64: dts: qcom: split beryllium dts into common dtsi and tianma dts")
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Thu, 22 Dec 2022 15:13:16 +0000 (16:13 +0100)]
arm64: dts: qcom: sdm845-db845c: fix audio codec interrupt pin name
The pin config entry should have a string, not number, for the GPIO used
as WCD9340 audio codec interrupt.
Fixes:
89a32a4e769c ("arm64: dts: qcom: db845c: add analog audio support")
Reported-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222151319.122398-1-krzysztof.kozlowski@linaro.org
Quentin Schulz [Mon, 5 Dec 2022 13:40:37 +0000 (14:40 +0100)]
arm64: dts: qcom: msm8998-fxtec: fix touchscreen reset GPIO polarity
The reset line is active low for the Goodix touchscreen controller so
let's fix the polarity in the Device Tree node.
Signed-off-by: Quentin Schulz <quentin.schulz@theobroma-systems.com>
Tested-by: Hans de Goede <hdegoede@redhat.com>
Reviewed-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221103-upstream-goodix-reset-v3-8-0975809eb183@theobroma-systems.com
Krzysztof Kozlowski [Mon, 2 Jan 2023 08:54:52 +0000 (09:54 +0100)]
arm64: dts: qcom: sm8450: align PSCI domain names with DT schema
Bindings expect power domains to follow generic naming pattern:
sm8450-qrd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-6-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 2 Jan 2023 08:54:51 +0000 (09:54 +0100)]
arm64: dts: qcom: sm8350: align PSCI domain names with DT schema
Bindings expect power domains to follow generic naming pattern:
sm8350-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-5-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 2 Jan 2023 08:54:50 +0000 (09:54 +0100)]
arm64: dts: qcom: sm8250: align PSCI domain names with DT schema
Bindings expect power domains to follow generic naming pattern:
sm8250-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 2 Jan 2023 08:54:49 +0000 (09:54 +0100)]
arm64: dts: qcom: sm8150: align PSCI domain names with DT schema
Bindings expect power domains to follow generic naming pattern:
sm8150-hdk.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-3-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 2 Jan 2023 08:54:48 +0000 (09:54 +0100)]
arm64: dts: qcom: sm6375: align PSCI domain names with DT schema
Bindings expect power domains to follow generic naming pattern:
sm6375-sony-xperia-murray-pdx225.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-2-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 2 Jan 2023 08:54:47 +0000 (09:54 +0100)]
arm64: dts: qcom: sc8280xp: align PSCI domain names with DT schema
Bindings expect power domains to follow generic naming pattern:
sc8280xp-crd.dtb: psci: 'cpu-cluster0', 'cpu0', 'cpu1', 'cpu2', 'cpu3', 'cpu4', 'cpu5', 'cpu6',
'cpu7' do not match any of the regexes: '^power-domain-', 'pinctrl-[0-9]+'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102085452.10753-1-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Mon, 2 Jan 2023 12:37:34 +0000 (13:37 +0100)]
arm64: dts: qcom: sm8450: disable by default Soundwire and VA-macro
Soundwire is a bus and VA-macro requires a supply, thus both are
expected to be explicitly enabled and populated by board DTS. The
HDK8450 already enables Soundwire devices, except swr4 which as a result
of this commit will stay disabled.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230102123734.478433-1-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 24 Dec 2022 15:42:55 +0000 (16:42 +0100)]
arm64: dts: qcom: use generic node name for CS35L41 speaker
Node names should be generic so use consistently speaker-amp for CS35L41
speaker amplifier.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-5-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 24 Dec 2022 15:42:54 +0000 (16:42 +0100)]
arm64: dts: qcom: sm8450: re-order GCC clocks
Bindings expect GCC clocks in other order:
sm8450-hdk.dtb: clock-controller@100000: clock-names:1: 'sleep_clk' was expected
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-4-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 24 Dec 2022 15:42:53 +0000 (16:42 +0100)]
arm64: dts: qcom: sm8250: drop unused clock-frequency from va-macro
Neither qcom,sm8250-lpass-va-macro bindings nor the driver use
"clock-frequency" property.
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-3-krzysztof.kozlowski@linaro.org
Krzysztof Kozlowski [Sat, 24 Dec 2022 15:42:51 +0000 (16:42 +0100)]
arm64: dts: qcom: msm8996: align bus node names with DT schema
The node names should be generic and the bindings expect "bus" for
simple-bus nodes:
msm8996-mtp.dtb: agnoc@0: $nodename:0: 'agnoc@0' does not match '^bus(@[0-9a-f]+)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224154255.43499-1-krzysztof.kozlowski@linaro.org
Marijn Suijten [Fri, 16 Dec 2022 23:34:08 +0000 (00:34 +0100)]
arm64: dts: qcom: sm6125-seine: Enable GPI DMA 0, QUP 0 and I2C SEs
Enable I2C Serial Engines 1, 2 and 3 which are known to have hardware
connected to them, leaving the rest disabled to save on power. For
this, only GPI DMA 0 and QUP 0 need to be enabled, as nothing seems to
be connected to Serial Engines on GPU DMA 1 / QUP 1. Beyond this
downstream only defines a UART console available on Serial Engine 4
which also resides on QUP 0.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-4-marijn.suijten@somainline.org
Marijn Suijten [Fri, 16 Dec 2022 23:34:07 +0000 (00:34 +0100)]
arm64: dts: qcom: sm6125: Add QUPs with SPI and I2C Serial Engines
Add Qualcomm Universal Peripheral nodes with SPI and I2C Serial Engines.
QUP 0 only has two SPIs at index 0 and 2, QUP 1 has four SPIs with a gap
in the middle (ranging from 5-9 with SPI 7 missing). Both QUPs have 5
I2C Serial Engines.
[Marijn: Add iommus, reword patch description, reorder all properties,
sort based on address, use QCOM_GPI_ constants, drop dma cells from 5
to 3]
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-3-marijn.suijten@somainline.org
Martin Botka [Fri, 16 Dec 2022 23:34:06 +0000 (00:34 +0100)]
arm64: dts: qcom: sm6125: Add pin configs for QUP SPI/I2C Serial Engines
Add pin setup for SPI/I2C Serial Engines that are supported under the
Qualcomm Universal Peripheral found on SM6125.
[Un-nest pins, remove duplicate pins= properties, follow new node naming
conventions, fix qup_14 -> qup14 function typo]
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216233408.1283581-2-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 19:24:43 +0000 (20:24 +0100)]
arm64: dts: qcom: sm6125-seine: Clean up gpio-keys (volume down)
- Remove autorepeat (leave key repetition to userspace);
- Remove unneeded status = "okay" (this is the default);
- Remove unneeded linux,input-type <EV_KEY> (this is the default for
gpio-keys);
- Allow the interrupt line for this button to be disabled;
- Use a full, descriptive node name;
- Set proper bias on the GPIO via pinctrl;
- Sort properties;
- Replace deprecated gpio-key,wakeup property with wakeup-source.
Fixes:
82e1783890b7 ("arm64: dts: qcom: sm6125: Add support for Sony Xperia 10II")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222192443.119103-1-marijn.suijten@somainline.org
Martin Botka [Thu, 22 Dec 2022 19:46:00 +0000 (20:46 +0100)]
arm64: dts: qcom: sm6125: Add GPI DMA nodes
Add nodes for GPI DMA hosts on SM6125.
[Marijn: reorder properties, use sdm845 fallback compatible, disable by
default, use 3 instead of 5 dma cells]
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222194600.139854-3-marijn.suijten@somainline.org
AngeloGioacchino Del Regno [Thu, 22 Dec 2022 19:32:54 +0000 (20:32 +0100)]
arm64: dts: qcom: sm6125: Add IOMMU context to DWC3
Add an IOMMU context to the USB DWC3 controller, required to get USB
functionality upon enablement of apps_smmu.
Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-5-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 19:32:53 +0000 (20:32 +0100)]
arm64: dts: qcom: sm6125: Add apps_smmu with streamID to SDHCI 1/2 nodes
When enabling the APPS SMMU the mainline driver reconfigures the SMMU
from its bootloader configuration, losing the stream mapping for (among
which) the SDHCI hardware and breaking its ADMA feature. This feature
can be disabled with:
sdhci.debug_quirks=0x40
But it is of course desired to have this feature enabled and working
through the SMMU.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-4-marijn.suijten@somainline.org
Martin Botka [Thu, 22 Dec 2022 19:32:52 +0000 (20:32 +0100)]
arm64: dts: qcom: sm6125: Configure APPS SMMU
Add a node for the APPS SMMU, to which various devices such as USB and
storage nodes are connected.
[Marijn: add the new, generic, "qcom,smmu-500" compatible, add patch
description, reorder # properties]
Signed-off-by: Martin Botka <martin.botka@somainline.org>
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222193254.126925-3-marijn.suijten@somainline.org
Marijn Suijten [Fri, 16 Dec 2022 21:33:43 +0000 (22:33 +0100)]
arm64: dts: qcom: sm6125: Reorder HSUSB PHY clocks to match bindings
Reorder the clocks and corresponding names to match the QUSB2 phy
schema, fixing the following CHECK_DTBS errors:
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:0: 'cfg_ahb' was expected
From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
arch/arm64/boot/dts/qcom/sm6125-sony-xperia-seine-pdx201.dtb: phy@1613000: clock-names:1: 'ref' was expected
From schema: /newdata/aosp-r/kernel/mainline/kernel/Documentation/devicetree/bindings/phy/qcom,qusb2-phy.yaml
Fixes:
cff4bbaf2a2d ("arm64: dts: qcom: Add support for SM6125")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Martin Botka <martin.botka@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221216213343.1140143-1-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 20:36:36 +0000 (21:36 +0100)]
arm64: dts: qcom: sm6125-seine: Lock eMMC and SD Card IDs via aliases
Ensure the eMMC and SD Card always have a predictable slot index by
predetermining them via aliases.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-6-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 20:36:35 +0000 (21:36 +0100)]
arm64: dts: qcom: sm6125-seine: Configure SD Card slot on SDHCI 2
Sony's seine board features an SD Card slot on SDHCI 2, that is to be
powered by l5 and l22. The card detect pin is already biased via
updates on the generic sdc2_*_state pinctrl nodes.
As usual regulator voltages are decreased to the maximum voted by the
downstream driver for safety. SDHCI 2 is the only hardware block
feeding off of these.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-5-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 20:36:34 +0000 (21:36 +0100)]
arm64: dts: qcom: sm6125-seine: Provide regulators to SDHCI 1
While SDHCI 1 appears to work out of the box, we cannot rely on the
bootloader-enabled regulators nor expect them to remain enabled (e.g.
when finally dropping pd_ignore_unused). Provide it the necessary l24
and l11 regulators now that PM6125 regulators have been made available
on this board.
As usual regulator voltages are decreased to the maximum voted by the
downstream driver for safety. No other hardware feeds off of these
regulators anyway (except UFS, which isn't used on the seine board in
favour of a DV6DMB eMMC card connected to SDHCI 1).
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-4-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 20:36:33 +0000 (21:36 +0100)]
arm64: dts: qcom: sm6125-seine: Provide regulators to HS USB2 PHY
Document the use of l7, l10 and l15 in the High Speed Qualcomm USB2 PHY,
in order to keep the regulators voted on when USB is active.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-3-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 20:36:32 +0000 (21:36 +0100)]
arm64: dts: qcom: sm6125-seine: Configure PM6125 regulators
Configure PM6125 regulators based on availability and voltages defined
downstream, to allow powering up (and/or keeping powered) other hardware
blocks going forward.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222203636.250190-2-marijn.suijten@somainline.org
Marijn Suijten [Thu, 22 Dec 2022 21:59:06 +0000 (22:59 +0100)]
arm64: dts: qcom: sm6350-lena: Flatten gpio-keys pinctrl state
Pinctrl states typically collate multiple related pins. In the case of
gpio-keys there's no hardware-defined relation at all except all pins
representing a key; and especially on Sony's lena board there's only one
pin regardless. Flatten it similar to other boards [1].
As a drive-by fix, clean up the label string.
[1]: https://lore.kernel.org/linux-arm-msm/
11174eb6-0a9d-7df1-6f06-
da4010f76453@linaro.org/
Fixes:
2b8bbe985659 ("arm64: dts: qcom: sm6350-lena: Include pm6350 and configure buttons")
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221222215906.324092-1-marijn.suijten@somainline.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:25 +0000 (02:10 +0000)]
arm64: dts: qcom: sm8250: Add compat qcom,sm8250-dsi-ctrl
Add silicon specific compatible qcom,sm8250-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sm8250 against the yaml documentation.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-19-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:24 +0000 (02:10 +0000)]
arm64: dts: qcom: sdm845: Add compat qcom,sdm845-dsi-ctrl
Add silicon specific compatible qcom,sdm845-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sdm845 against the yaml documentation.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-18-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:23 +0000 (02:10 +0000)]
arm64: dts: qcom: sdm660: Add compat qcom,sdm660-dsi-ctrl
Add silicon specific compatible qcom,sdm660-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sdm660 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-17-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:22 +0000 (02:10 +0000)]
arm64: dts: qcom: sdm630: Add compat qcom,sdm660-dsi-ctrl
The sdm630 can use the sdm660 mdss-dsi-ctrl compat. Currently it has the
same set of binding dependencies as sdm660.
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-16-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:21 +0000 (02:10 +0000)]
arm64: dts: qcom: sc7280: Add compat qcom,sc7280-dsi-ctrl
Add silicon specific compatible qcom,sc7280-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7280 against the yaml documentation.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-15-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:20 +0000 (02:10 +0000)]
arm64: dts: qcom: sc7180: Add compat qcom,sc7180-dsi-ctrl
Add silicon specific compatible qcom,sc7180-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for sc7180 against the yaml documentation.
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-14-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:19 +0000 (02:10 +0000)]
arm64: dts: qcom: msm8996: Add compat qcom,msm8996-dsi-ctrl
Add silicon specific compatible qcom,msm8996-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8996 against the yaml documentation.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-13-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:18 +0000 (02:10 +0000)]
arm64: dts: qcom: msm8953: Add compat qcom,msm8953-dsi-ctrl
Add silicon specific compatible qcom,msm8953-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8953 against the yaml documentation.
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-12-bryan.odonoghue@linaro.org
Bryan O'Donoghue [Fri, 23 Dec 2022 02:10:17 +0000 (02:10 +0000)]
arm64: dts: qcom: msm8916: Add compat qcom,msm8916-dsi-ctrl
Add silicon specific compatible qcom,msm8916-dsi-ctrl to the
mdss-dsi-ctrl block. This allows us to differentiate the specific bindings
for msm8916 against the yaml documentation.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223021025.1646636-11-bryan.odonoghue@linaro.org
Krzysztof Kozlowski [Fri, 23 Dec 2022 16:18:35 +0000 (17:18 +0100)]
arm64: dts: qcom: sm8350: align MMC node names with DT schema
The bindings expect "mmc" for MMC/SDHCI nodes:
sm8350-sony-xperia-sagami-pdx214.dtb: sdhci@8804000: $nodename:0: 'sdhci@8804000' does not match '^mmc(@.*)?$'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221223161835.112079-4-krzysztof.kozlowski@linaro.org
Alex Elder [Sat, 24 Dec 2022 00:21:26 +0000 (18:21 -0600)]
arm64: dts: qcom: sc7280: only enable IPA for boards with a modem
IPA is only needed on a platform if it includes a modem, and not all
SC7280 SoC variants do. The file "sc7280-herobrine-lte-sku.dtsi" is
used to encapsulate definitions related to Chrome OS SC7280 devices
where a modem is present, and that's the proper place for the IPA
node to be enabled.
Currently IPA is enabled in "sc7280-idp.dtsi", which is included by
DTS files for Qualcomm reference platforms (all of which include the
modem). That also includes "sc7280-herobrine-lte-sku.dtsi", so
enabling IPA there would make it unnecessary for "sc7280-idp.dtsi"
to enable it.
The only other place IPA is enabled is "sc7280-qcard.dtsi".
That file is included only by "sc7280-herobrine.dtsi", which
is (eventually) included only by these top-level DTS files:
sc7280-herobrine-crd.dts
sc7280-herobrine-herobrine-r1.dts
sc7280-herobrine-evoker.dts
sc7280-herobrine-evoker-lte.dts
sc7280-herobrine-villager-r0.dts
sc7280-herobrine-villager-r1.dts
sc7280-herobrine-villager-r1-lte.dts
All of but two of these include "sc7280-herobrine-lte-sku.dtsi", and
for those cases, enabling IPA there means there is no need for it to
be enabled in "sc7280-qcard.dtsi".
The two remaining cases will no longer enable IPA as a result of
this change:
sc7280-herobrine-evoker.dts
sc7280-herobrine-villager-r1.dts
Both of these have "lte" counterparts, and are meant to represent
board variants that do *not* have a modem.
This is exactly the desired configuration.
Signed-off-by: Alex Elder <elder@linaro.org>
Reviewed-by: Sibi Sankar <quic_sibis@quicinc.com>
Tested-by: Sibi Sankar <quic_sibis@quicinc.com>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221224002126.1518552-1-elder@linaro.org
Krzysztof Kozlowski [Wed, 28 Dec 2022 11:24:56 +0000 (12:24 +0100)]
arm64: dts: qcom: sm8350-sony-xperia-sagami: specify which LDO modes are allowed
This board uses RPMH, specifies "regulator-allow-set-load" for LDOs,
but doesn't specify any modes with "regulator-allowed-modes":
sm8350-sony-xperia-sagami-pdx214.dtb: regulators-0: ldo5: 'regulator-allowed-modes' is a dependency of 'regulator-allow-set-load'
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228112456.31348-2-krzysztof.kozlowski@linaro.org
Konrad Dybcio [Thu, 29 Dec 2022 10:05:10 +0000 (11:05 +0100)]
arm64: dts: qcom: sm8150: Wire up MDSS
Add required nodes for MDSS and hook up provided clocks in DISPCC.
This setup is almost identical to 8[23]50.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229100511.979972-3-konrad.dybcio@linaro.org
Konrad Dybcio [Thu, 29 Dec 2022 10:05:09 +0000 (11:05 +0100)]
arm64: dts: qcom: sm8150: Add DISPCC node
Years after the SoC support has been added, it's high time for it to
get dispcc going. Add the node to ensure that.
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # Xperia 5
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229100511.979972-2-konrad.dybcio@linaro.org
Krzysztof Kozlowski [Thu, 29 Dec 2022 13:27:31 +0000 (14:27 +0100)]
arm64: dts: qcom: sm8250: add cache size
Add full cache description to DTS to avoid:
1. "Early cacheinfo failed" warnings,
2. Cache topology detection which leads to early memory allocations and
"BUG: sleeping function called from invalid context" on PREEMPT_RT
kernel:
smp: Bringing up secondary CPUs ...
Detected VIPT I-cache on CPU1
BUG: sleeping function called from invalid context at kernel/locking/spinlock_rt.c:46
in_atomic(): 1, irqs_disabled(): 128, non_block: 0, pid: 0, name: swapper/1
preempt_count: 1, expected: 0
RCU nest depth: 1, expected: 1
3 locks held by swapper/1/0:
#0:
ffff5e337eee5f18 (&pcp->lock){+.+.}-{3:3}, at: get_page_from_freelist+0x20c/0xffc
#1:
ffffa9e24a900b18 (rcu_read_lock){....}-{1:3}, at: rt_spin_trylock+0x40/0xe4
#2:
ffff5e337efc8918 (&zone->lock){+.+.}-{3:3}, at: rmqueue_bulk+0x54/0x720
irq event stamp: 0
Call trace:
__might_resched+0x17c/0x214
rt_spin_lock+0x5c/0x100
rmqueue_bulk+0x54/0x720
get_page_from_freelist+0xcfc/0xffc
__alloc_pages+0xec/0x1150
alloc_page_interleave+0x1c/0xd0
alloc_pages+0xec/0x160
new_slab+0x330/0x454
___slab_alloc+0x5b8/0xba0
__kmem_cache_alloc_node+0xf4/0x20c
__kmalloc+0x60/0x100
detect_cache_attributes+0x2a8/0x5a0
update_siblings_masks+0x28/0x300
store_cpu_topology+0x58/0x70
secondary_start_kernel+0xc8/0x154
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229132731.1193713-1-krzysztof.kozlowski@linaro.org
Pierre Gondois [Mon, 7 Nov 2022 15:57:09 +0000 (16:57 +0100)]
arm64: dts: qcom: Update cache properties
The DeviceTree Specification v0.3 specifies that the cache node
'compatible' and 'cache-level' properties are 'required'. Cf.
s3.8 Multi-level and Shared Cache Nodes
The 'cache-unified' property should be present if one of the
properties for unified cache is present ('cache-size', ...).
Update the Device Trees accordingly.
About msm8953.dtsi:
According to the Devicetree Specification v0.3,
s3.7.3 'Internal (L1) Cache Properties',
cache-unified:
If present, specifies the cache has a unified or-
ganization. If not present, specifies that the
cache has a Harvard architecture with separate
caches for instructions and data.
Plus, the 'cache-level' property seems to be reserved to higher
cache levels (cf s3.8).
To describe a l1 data/instruction cache couple, no cache
information should be described. Remove the l1 cache nodes.
Signed-off-by: Pierre Gondois <pierre.gondois@arm.com>
[bjorn: Moved "qcom" to $subject prefix]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221107155825.1644604-17-pierre.gondois@arm.com
Konrad Dybcio [Thu, 29 Dec 2022 10:27:12 +0000 (11:27 +0100)]
arm64: dts: qcom: sm8350-sagami: Rectify GPIO keys
With enough pins set properly, the hardware buttons now also work
like a charm.
Fixes:
c2721b0c23d9 ("arm64: dts: qcom: Add support for Xperia 1 III / 5 III")
Tested-by: Marijn Suijten <marijn.suijten@somainline.org> # On Xperia 1 III and Xperia 5 III
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221229102712.983306-1-konrad.dybcio@linaro.org
Abel Vesa [Fri, 2 Dec 2022 23:20:54 +0000 (01:20 +0200)]
interconnect: qcom: Add SM8550 interconnect provider driver
Add driver for the Qualcomm interconnect buses found in SM8550 based
platforms. The topology consists of several NoCs that are controlled by
a remote processor that collects the aggregated bandwidth for each
master-slave pairs.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Link: https://lore.kernel.org/r/20221202232054.2666830-3-abel.vesa@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
Abel Vesa [Fri, 2 Dec 2022 23:20:53 +0000 (01:20 +0200)]
dt-bindings: interconnect: Add Qualcomm SM8550
The Qualcomm SM8550 SoC has several bus fabrics that could be
controlled and tuned dynamically according to the bandwidth demand.
Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20221202232054.2666830-2-abel.vesa@linaro.org
Signed-off-by: Georgi Djakov <djakov@kernel.org>
Gabriela David [Wed, 7 Dec 2022 18:30:46 +0000 (19:30 +0100)]
arm64: dts: qcom: sdm632: Add device tree for Motorola G7 Power
Add device tree for the Motorola G7 Power (ocean) smartphone. This
device is based on Snapdragon 632 (sdm632) SoC which is a variant of
MSM8953.
Signed-off-by: Gabriela David <ultracoolguy@disroot.org>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-9-a64b3b0af0eb@z3ntu.xyz
Eugene Lepshy [Wed, 7 Dec 2022 18:30:45 +0000 (19:30 +0100)]
arm64: dts: qcom: msm8953: Add device tree for Xiaomi Redmi 5 Plus
Add device tree for the Xiaomi Redmi 5 Plus (vince) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.
Signed-off-by: Eugene Lepshy <fekz115@gmail.com>
Co-developed-by: Gianluca Boiano <morf3089@gmail.com>
Signed-off-by: Gianluca Boiano <morf3089@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-8-a64b3b0af0eb@z3ntu.xyz
Danila Tikhonov [Wed, 7 Dec 2022 18:30:44 +0000 (19:30 +0100)]
arm64: dts: qcom: msm8953: Add device tree for Xiaomi Mi A1
Add device tree for the Xiaomi Mi A1 (tissot) smartphone. This device is
based on Snapdragon 625 (msm8953) SoC.
Co-developed-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Anton Bambura <jenneron@protonmail.com>
Signed-off-by: Danila Tikhonov <JIaxyga@protonmail.com>
Signed-off-by: Vladimir Lypak <vladimir.lypak@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-7-a64b3b0af0eb@z3ntu.xyz
Adam Skladowski [Wed, 7 Dec 2022 18:30:43 +0000 (19:30 +0100)]
arm64: dts: qcom: msm8953: Add device tree for Xiaomi Redmi Note 4X
Add device tree for the Xiaomi Redmi Note 4X (mido) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.
Signed-off-by: Adam Skladowski <a39.skl@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-6-a64b3b0af0eb@z3ntu.xyz
Alejandro Tafalla [Wed, 7 Dec 2022 18:30:42 +0000 (19:30 +0100)]
arm64: dts: qcom: msm8953: Add device tree for Xiaomi Mi A2 Lite
Add device tree for the Xiaomi Mi A2 Lite (daisy) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.
Signed-off-by: Alejandro Tafalla <atafalla@dnyon.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-5-a64b3b0af0eb@z3ntu.xyz
Sireesh Kodali [Wed, 7 Dec 2022 18:30:41 +0000 (19:30 +0100)]
arm64: dts: qcom: msm8953: Add device tree for Motorola G5 Plus
Add device tree for the Motorola G5 Plus (potter) smartphone. This
device is based on Snapdragon 625 (msm8953) SoC.
Signed-off-by: Sireesh Kodali <sireeshkodali1@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-4-a64b3b0af0eb@z3ntu.xyz
Julian Braha [Wed, 7 Dec 2022 18:30:40 +0000 (19:30 +0100)]
arm64: dts: qcom: sdm450: Add device tree for Motorola Moto G6
Add device tree for the Motorola Moto G6 (ali) smartphone. This device
is based on Snapdragon 450 (sdm450) SoC which is a variant of MSM8953.
Signed-off-by: Julian Braha <julianbraha@gmail.com>
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-3-a64b3b0af0eb@z3ntu.xyz
Luca Weiss [Wed, 7 Dec 2022 18:30:39 +0000 (19:30 +0100)]
arm64: dts: qcom: msm8953: Adjust reserved-memory nodes
Adjust node names so they're not just memory@ but actually show what
they're used for. Also add labels to most nodes so we can easily
reference them from devices.
Signed-off-by: Luca Weiss <luca@z3ntu.xyz>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207-msm8953-6-1-next-dtbs-v3-v3-2-a64b3b0af0eb@z3ntu.xyz
Dzmitry Sankouski [Wed, 28 Dec 2022 11:52:43 +0000 (14:52 +0300)]
arm64: dts: qcom: Re-enable resin on MSM8998 and SDM845 boards
resin node declaration was moved to pm8998.dtsi file (in disabled state).
MSM8998 and SDM845 boards defining resin node did not previously have
status="okay" and ended up disabled.
Re-enable it by using resin node link from pm8998.dtsi with status="okay".
Fixes:
f86ae6f23a9e ("arm64: dts: qcom: sagit: add initial device tree for sagit")
Signed-off-by: Dzmitry Sankouski <dsankouski@gmail.com>
Reviewed-by: Marijn Suijten <marijn.suijten@somainline.org>
Reported-by: Marijn Suijten <marijn.suijten@somainline.org>
Link: https://lore.kernel.org/linux-arm-msm/20221222115922.jlachctn4lxopp7a@SoMainline.org/
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228115243.201038-1-dsankouski@gmail.com
Youghandhar Chintala [Wed, 28 Dec 2022 09:41:03 +0000 (15:11 +0530)]
arm64: dts: qcom: sc7280: Add wifi alias for SC7280-idp
Currently, depth-charge Chrome OS bootloader code used in the SC7280
SoC accesses the WiFi node using node names (wifi@<addr>). Since
depth-charge Chrome OS bootloader is a common code that is used in
SoCs having different WiFi chipsets, it is better if the depth-charge
Chrome OS bootloader code accesses the WiFi node using a WiFi alias.
The advantage of this method is that the depth-charge Chrome OS
bootloader code need not be changed for every new WiFi chip.
Therefore, add wifi alias entry for SC7280-idp device tree.
Signed-off-by: Youghandhar Chintala <quic_youghand@quicinc.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228094104.356-1-quic_youghand@quicinc.com
Johan Hovold [Wed, 28 Dec 2022 08:56:14 +0000 (09:56 +0100)]
arm64: dts: qcom: sc8280xp-x13s: move 'regulator-vph-pwr' node
Move the new 'regulator-vph-pwr' node before the wlan regulator node to
restore the root-node sort order (alphabetically by node name).
While at it, add a couple of newlines to separate the properties for
consistency with the other regulator nodes.
Signed-off-by: Johan Hovold <johan+linaro@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221228085614.15080-1-johan+linaro@kernel.org
Steev Klimaszewski [Mon, 26 Dec 2022 00:47:27 +0000 (18:47 -0600)]
arm64: dts: qcom: c630: Fix firmware paths
The firmware paths were pointing to qcom/manufacturer whereas other
devices have them under qcom/chipset/manufacturer, so fix this up on the
c630, so we follow the same standard setup.
Signed-off-by: Steev Klimaszewski <steev@kali.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221226004727.204986-1-steev@kali.org
Souradeep Chowdhury [Tue, 27 Dec 2022 15:22:51 +0000 (20:52 +0530)]
arm64: dts: qcom: sdm845: Add Data Capture and Compare(DCC) support node
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.
Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/4b4289063e1b3baf98b653274060f35a5c888609.1672148732.git.quic_schowdhu@quicinc.com
Souradeep Chowdhury [Tue, 27 Dec 2022 15:22:50 +0000 (20:52 +0530)]
arm64: dts: qcom: sc7180: Add Data Capture and Compare(DCC) support node
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.
Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/08e8dc0f58145915f19d953c487a0df20a1ced1f.1672148732.git.quic_schowdhu@quicinc.com
Souradeep Chowdhury [Tue, 27 Dec 2022 15:22:49 +0000 (20:52 +0530)]
arm64: dts: qcom: sc7280: Add Data Capture and Compare(DCC) support node
Add the DCC(Data Capture and Compare) device tree node entry along with
the address of the register region.
Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/88ef6053ee56eb0613040ea1fe33439934810330.1672148732.git.quic_schowdhu@quicinc.com
Souradeep Chowdhury [Tue, 27 Dec 2022 15:22:48 +0000 (20:52 +0530)]
arm64: dts: qcom: sm8150: Add Data Capture and Compare(DCC) support node
Add the DCC(Data Capture and Compare) device tree node entry along with
the addresses for register regions.
Signed-off-by: Souradeep Chowdhury <quic_schowdhu@quicinc.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/4737bcbce591e59b2f29d9141c1a5e41e64cc4f4.1672148732.git.quic_schowdhu@quicinc.com
Marijn Suijten [Tue, 13 Dec 2022 00:26:26 +0000 (01:26 +0100)]
arm64: dts: qcom: sm8150: Enable split pagetables for Adreno SMMU
Allow the Adreno GPU to access split pagetables specifically on the
dedicated Adreno SMMU via the qcom,adreno-smmu compatible.
Signed-off-by: Marijn Suijten <marijn.suijten@somainline.org>
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221213002626.260267-2-konrad.dybcio@linaro.org
Vinod Koul [Wed, 7 Dec 2022 01:28:03 +0000 (03:28 +0200)]
arm64: dts: qcom: sm8450-hdk: Enable HDMI Display
Add the HDMI display nodes and link it to DSI.
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-6-dmitry.baryshkov@linaro.org
Vinod Koul [Wed, 7 Dec 2022 01:28:02 +0000 (03:28 +0200)]
arm64: dts: qcom: sm8450-hdk: Add LT9611uxc HDMI bridge
Add the LT9611uxc DSI-HDMI bridge and supplies
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-5-dmitry.baryshkov@linaro.org
Dmitry Baryshkov [Wed, 7 Dec 2022 01:28:01 +0000 (03:28 +0200)]
arm64: dts: qcom: sm8450-hdk: enable display hardware
Enable MDSS/DPU/DSI0 on SM8450-HDK device.
Reviewed-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-4-dmitry.baryshkov@linaro.org
Dmitry Baryshkov [Wed, 7 Dec 2022 01:28:00 +0000 (03:28 +0200)]
arm64: dts: qcom: sm8450: add display hardware devices
Add devices tree nodes describing display hardware on SM8450:
- Display Clock Controller
- MDSS
- MDP
- two DSI controllers and DSI PHYs
This does not provide support for DP controllers present on SM8450.
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-3-dmitry.baryshkov@linaro.org
Dmitry Baryshkov [Wed, 7 Dec 2022 01:27:59 +0000 (03:27 +0200)]
arm64: dts: qcom: sm8450: add RPMH_REGULATOR_LEVEL_LOW_SVS_D1
Add another power saving state used on SM8450. Unfortunately adding it
in proper place causes renumbering of all the opp states in sm8450.dtsi
Reviewed-by: Konrad Dybcio <konrad.dybcio@somainline.org>
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221207012803.114959-2-dmitry.baryshkov@linaro.org
Richard Acayan [Mon, 5 Dec 2022 22:52:37 +0000 (17:52 -0500)]
arm64: dts: qcom: sdm670-google-sargo: keep pm660 ldo8 on
According to the downstream device tree, the regulator that powers the
I/O for eMMC should not be turned off. Keep it always on just in case
the eMMC driver fails and doesn't enable it, or unloads and disables it.
Fixes:
07c8ded6e373 ("arm64: dts: qcom: add sdm670 and pixel 3a device trees")
Link: https://android.googlesource.com/kernel/msm/+/9ed6ddbe955d3b84d1416a1cf77e83904d1e8421/arch/arm64/boot/dts/google/sdm670-bonito-common.dtsi#105
Signed-off-by: Richard Acayan <mailingradian@gmail.com>
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20221205225237.200564-1-mailingradian@gmail.com