Ioana Ciocoi Radulescu [Tue, 26 Feb 2019 15:50:07 +0000 (15:50 +0000)]
driver: net: fsl-mc: Fix DPC MAC address fixup
If node /board_info/ports does not exist in the DPC file,
function mc_fixup_dpc() will skip not only MAC address fixup,
but also the cache flush at the end. This may cause the other
fixup changes (e.g. ICID related ones) to be ignored by MC.
Fixes:
1161dbcc0a36 ("drivers: net: fsl-mc: Include MAC addr fixup to DPL")
Signed-off-by: Ioana Radulescu <ruxandra.radulescu@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Pankaj Bansal [Fri, 8 Feb 2019 08:59:24 +0000 (08:59 +0000)]
drivers: net: ldpaa_eth: check if the dpmac is enabled
some dpmacs in armv8a based freescale layerscape SOCs can be
configured via both serdes(sgmii, xfi, xlaui etc) bits and via
EC*_PMUX(rgmii) bits in RCW.
e.g. dpmac 17 and 18 in LX2160A can be configured as SGMII from
serdes bits and as RGMII via EC1_PMUX/EC2_PMUX bits
Now if a dpmac is enabled by serdes bits then it takes precedence
over EC*_PMUX bits. i.e. in LX2160A if we select serdes protocol
that configures dpmac17 as SGMII and set the EC1_PMUX as RGMII,
then the dpmac is SGMII and not RGMII.
Therefore, in fsl_rgmii_init function of SOC, we will check if the
dpmac is enabled or not? if it is (fsl_serdes_init has already enabled
the dpmac), then don't enable it.
Signed-off-by: Pankaj Bansal <pankaj.bansal@nxp.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
Heiko Schocher [Wed, 13 Mar 2019 11:15:45 +0000 (12:15 +0100)]
Revert "env: add spi_flash_read_env function"
This reverts commit
9a9d66f5eff0f443de4c2c6ca3e27771ed14b1b4.
because it breaks fw_setenv and U-Boot interworking, if
U-Boot environment is stored in a SPI-NOR.
Reproduce it with:
boot linux with empty Environment and store a variable
with fw_setenv into it, the Environment is now filled
with 0xff:
root@ckey5e:10:8e:~# hexdump -C /dev/mtd4
00000000 e9 e8 07 fa 01 62 6f 6f 74 63 6d 64 3d 72 75 6e |.....bootcmd=run|
[...]
00000f30 7d 00 75 62 69 62 6f 6f 74 76 6f 6c 3d 32 00 00 |}.ubibootvol=2..|
00000f40 00 ff ff ff ff ff ff ff ff ff ff ff ff ff ff ff |................|
Boot now U-Boot prints:
Loading Environment from SPI Flash... SF: Detected s25fl128l with page size 256 Bytes, erase size 4 KiB, total 16 MiB
*** Warning - bad CRC, using default environment
Reason is the above commit, as it only reads until \0\0
is found, and assumes the rest of the Environment
space is filled with 0x00, which is not the case when
saving an Environment under linux with fw_setenv.
Signed-off-by: Heiko Schocher <hs@denx.de>
Acked-by: Stefano Babic <sbabic@denx.de>
Tom Rini [Wed, 13 Mar 2019 20:07:41 +0000 (16:07 -0400)]
Merge tag 'u-boot-imx-
20190313' of git://git.denx.de/u-boot-imx
Small fixes in several i.MX boards
----------------------------------
- imx8: add pinctrl driveri (mx8m), fix documentation and
fix reported CPU frequency. Fabio is co-maintainer
- pico-imx6ul: switch to DM
- local fixes for ventana, mx6ul_14x14_evk, engicam,
imx6(q)_logic, liteboard
Hannes Schmelzer [Fri, 15 Feb 2019 09:30:18 +0000 (10:30 +0100)]
drivers/net/fec: phy_init: remove redundant logic
The phy_connect_dev(...) function from phy.c does all the handling
(inclusive catching fixed-link).
So we drop here the single steps and call just phy_connect_dev(...).
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Adam Ford [Mon, 18 Feb 2019 23:58:17 +0000 (17:58 -0600)]
MTD: mxs_nand_spl: Redo the way nand_init initializes
Currently the spl system calls nand_init which does nothing.
It isn't until an attempt to load from NAND that it gets initialized.
Subsequent attempts to load just skip the initialization because
NAND is already initialized.
This moves the contents of mxs_nand_init to nand_init. In the event
of an error, it clears the number of nand chips found. Any
attempts to use nand will check if there are nand chips available
instead of actually doing the initialization at that time. If there
are none, it will return an error to the higher level calls.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Wed, 20 Feb 2019 14:53:56 +0000 (08:53 -0600)]
arm: dts: imx6qdl-u-boot: Enable spba-bus@2000000 simple bus
spba-bus has a few nodes under it including the UART1 and
some ESPI buses. In order to use them in SPL, the
u-boot,dm-spl flag needs to be added to the spba-bus@2000000
container.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Wed, 20 Feb 2019 04:07:22 +0000 (22:07 -0600)]
imx: serial_mxc: use CONFIG_IS_ENABLED instead of ifdef
Kconfig allows boards to configured with DM_SERIAL and still
have SPL_DM_SERIAL disabled. This patch changes the ifdef's
to CONFIG_IS_ENABLED to allow the modes to differ between
SPL and U-Boot.
Signed-off-by: Adam Ford <aford173@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Adam Ford [Sun, 17 Feb 2019 14:56:00 +0000 (08:56 -0600)]
ARM: imx6q_logic: Enable MTD and NAND_MXS_DT
This patch supports enabling MTD, and the corresponding CMD_MTD
along with enabling the MXS NAND Controller with device tree
support.
Signed-off-by: Adam Ford <aford173@gmail.com>
Adam Ford [Sat, 16 Feb 2019 20:09:45 +0000 (14:09 -0600)]
ARM: imx6_logic: Fix typo in FDT address
A few scripts reference 'fdt_addr' when they should reference
'fdt_addr_r' so this patch fixes those broken references.
Signed-off-by: Adam Ford <aford173@gmail.com>
Shyam Saini [Wed, 6 Feb 2019 07:53:37 +0000 (13:23 +0530)]
include: configs: imx6-engicam: Add recovery boot option
Combined with watchdog board reset mechanism, this can be used as recovery
boot option after bootlimit exceeds the configured value.
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Shyam Saini [Wed, 6 Feb 2019 07:53:36 +0000 (13:23 +0530)]
configs: imx6qdl_icore_mmc: Enable watchdog and bootcounter
Enable watchdog and bootcounter support on imx6qdl board
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Shyam Saini [Wed, 6 Feb 2019 07:53:35 +0000 (13:23 +0530)]
board: engicam: Add watchdog support on Engicam
This patch adds watchdog support for engicam imx6 family
of boards.
Signed-off-by: Shyam Saini <shyam.saini@amarulasolutions.com>
Fabio Estevam [Tue, 5 Feb 2019 12:43:26 +0000 (10:43 -0200)]
imx8qxp: Fix the reported CPU frequency
Currently the CPU frequency is incorrectly reported:
CPU: NXP i.MX8QXP RevB A35 at 147228 MHz
Fix this problem by using a direct call to the SCU firmware to
retrieve the Cortex A35 CPU frequency.
With this change applied the CPU frequency is displayed correctly:
CPU: NXP i.MX8QXP RevB A35 at 1200 MHz
Tested-by: Marcelo Macedo <marcelo.macedo@nxp.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Tested-by: Andrejs Cainikovs <andrejs.cainikovs@netmodule.com>
Fabio Estevam [Thu, 28 Feb 2019 11:46:15 +0000 (08:46 -0300)]
imx8mq_evk: Add myself as a co-maintainer
I would like to help maintaining this board.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Thu, 28 Feb 2019 11:46:14 +0000 (08:46 -0300)]
imx8mq_evk: Move CONFIG_ENV_IS_IN_MMC to Kconfig
Currently the command "saveenv" is not available.
The CONFIG_ENV_IS_IN_MMC symbol has been converted to Kconfig,
so fix the problem by moving it to the defconfig.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Tue, 26 Feb 2019 12:36:07 +0000 (09:36 -0300)]
mx6sabreauto: README: Adjust the binary name after DM conversion
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Tue, 26 Feb 2019 12:36:06 +0000 (09:36 -0300)]
mx6sabresd: README: Adjust the binary name after DM conversion
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Martyn Welch [Fri, 22 Feb 2019 19:05:48 +0000 (19:05 +0000)]
imx: mx6qsabrelite: Update the SabreLite README
The information in the SabreLite README is inaccurate and sparse. The
upstream U-Boot can boot the SabreLite from SPI-NOR. Additionally, the
freely available imx_loader tool can be easily used to boot a board with a
corrupted SPI, the official Freescale/NXP manufacturing tools are not
required.
Reformat the document, adding a description of how to boot from SPI-NOR
and adding a brief description of how to recover the board should the
SPI-NOR be corrupted using imx_loader.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Acked-by: Troy Kisky <troy.kisky@boundarydevices.com>
Baruch Siach [Thu, 28 Feb 2019 11:51:05 +0000 (13:51 +0200)]
imx8mq_evk/README: fix DDR training firmware path
Remove a redundant directory level.
Reported-by: Ofer Heifetz <ofer.heifetz@valens.com>
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Baruch Siach [Thu, 28 Feb 2019 11:51:04 +0000 (13:51 +0200)]
imx8mq_evk/README: add missing firmware extract step
Tested-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Thu, 14 Feb 2019 13:37:51 +0000 (11:37 -0200)]
warp7: Fix the write to the LDOGCTL PMIC register
The third parameter of the pmic_clrsetbits() function is the mask
to the register and the correct mask is 1 not 0.
Since the LDOGCTL only contains a single valid bit (bit 0),
we can use pmic_reg_write() and write 1 directly, which fixes
the problem in a simpler way and use the original pmic function
that was used prior to the DM PMIC conversion.
Fixes:
8ba377321c86 ("arm: imx7s-warp: Convert to DM PMIC")
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Fabio Estevam [Thu, 14 Feb 2019 13:35:46 +0000 (11:35 -0200)]
mx6ul_14x14_evk: Simplify the PMIC register writes
There is no need to store the values written to the PMIC inside the
'reg' variable. Make it simpler by writing the values directly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Thu, 14 Feb 2019 12:36:27 +0000 (10:36 -0200)]
warp7: Remove unneeded headers after DM conversion
After DM conversion the I2C and MMC related board codes have been
removed, so remove the corresponding header files as well.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Fabio Estevam [Sat, 9 Feb 2019 14:01:59 +0000 (12:01 -0200)]
warp7: README: Adjust the binary name after DM conversion
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org>
Tim Harvey [Thu, 21 Feb 2019 16:51:16 +0000 (08:51 -0800)]
imx: ventana: added support for 16bit 8Gb density (1GiB) DRAM
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Tim Harvey [Thu, 21 Feb 2019 16:48:48 +0000 (08:48 -0800)]
imx: ventana: hexdump invalid EEPROM data
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Marcin Niestroj [Sat, 19 Jan 2019 16:06:47 +0000 (17:06 +0100)]
ARM: liteboard: use random ethaddr
There is no ethaddr assigned to each board, so we need to use random
value in order to use network.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Marcin Niestroj [Sat, 19 Jan 2019 16:06:46 +0000 (17:06 +0100)]
ARM: liteboard: move towards driver model and device-tree boot
This patch mostly enables DM drivers in board defconfig and all their
dependencies. Additionally we remove USB code that is on longer
executed after enabling CONFIG_DM_USB. Enable CONFIG_PINCTRL, so we
can get rid of ethernet pin configuration.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Fabio Estevam [Thu, 14 Feb 2019 12:01:51 +0000 (10:01 -0200)]
pico-imx6ul: README: Adjust the binary name after DM conversion
After the conversion to DM the U-Boot binary is called u-boot-dtb.imx,
so fix the README file accordingly.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam [Thu, 14 Feb 2019 12:01:50 +0000 (10:01 -0200)]
pico-imx6ul: Convert to DM_PMIC
Convert to use DM_PMIC for the PFUZE3000. Since this PMIC is
under an I2C bus, conver to DM_I2C as well.
Also, since I2C is not used in SPL, remove CONFIG_SPL_I2C_SUPPORT
to avoid build warnings.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam [Thu, 14 Feb 2019 12:01:49 +0000 (10:01 -0200)]
pico-imx6ul: Convert to CONFIG_DM_GPIO
Convert to CONFIG_DM_GPIO.
Also, DM GPIO requires gpio_request() to be called explicitly before
doing any gpio operation, so do as requested.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam [Thu, 14 Feb 2019 12:01:48 +0000 (10:01 -0200)]
pico-imx6ul: Convert to DM MMC
Select CONFIG_DM_MMC=y in order to support MMC driver model.
This allows the MMC board related code to be removed.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam [Thu, 14 Feb 2019 12:01:47 +0000 (10:01 -0200)]
pico-imx6ul: Select CONFIG_OF_CONTROL
Select CONFIG_OF_CONTROL and the appropriate device tree files
in preparation for converting to driver model.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Fabio Estevam [Thu, 14 Feb 2019 12:01:46 +0000 (10:01 -0200)]
pico-imx6ul: Import dts files from kernel
Import the device tree files from kernel 5.0-rc6 in preparation
for driver model conversion.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Otavio Salvador <otavio@ossystems.com.br>
Chris Spencer [Mon, 4 Feb 2019 10:05:34 +0000 (10:05 +0000)]
imx8mq_evk_defconfig: Enable pinctrl driver
The Ethernet controller is not able to initialise correctly without the
pinctrl driver.
This config setting was enabled in the initial version of this file,
but was removed by a savedefconfig resync because the parameter did not
actually exist at that point.
Fixes:
1bac199e8c87 ("configs: Resync with savedefconfig")
Signed-off-by: Chris Spencer <christopher.spencer@sea.co.uk>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Peng Fan [Mon, 28 Jan 2019 09:43:42 +0000 (09:43 +0000)]
pinctrl: add imx8m driver
Add i.mx8m pinctrl driver.
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tom Rini [Tue, 12 Mar 2019 14:56:02 +0000 (10:56 -0400)]
Merge tag 'efi-2019-04-rc4-2' of https://github.com/xypron2/u-boot
Pull request for UEFI system for v2019.04-rc4
Fix an error with the serial communication on boards with a very small
UART buffer which leads to a stalled system.
Provide an X86 reset driver for the UEFI runtime.
Tom Rini [Mon, 11 Mar 2019 19:48:57 +0000 (15:48 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sunxi
- axp818 fix
- fix warnings for ethernet clock code
Tom Rini [Mon, 11 Mar 2019 15:24:20 +0000 (11:24 -0400)]
Merge git://git.denx.de/u-boot-x86
- ACPI changes and fixes to Intel Tangier/Edison
- i8254 beeper fixes
Bin Meng [Tue, 26 Feb 2019 09:52:22 +0000 (01:52 -0800)]
x86: crownbay: Enable the beeper sound driver
Use the i8254 sound driver to support creating simple beeps.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 26 Feb 2019 09:52:21 +0000 (01:52 -0800)]
x86: coreboot: Add the missing pc speaker node in the device tree
This is currently missing and without it the i8254 beeper driver
won't work.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 26 Feb 2019 09:52:20 +0000 (01:52 -0800)]
x86: Add a dtsi file for the pc speaker
The pc speaker driven by the i8254 is generic enough to deserve
a single dtsi file to be included by boards that use it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Tue, 26 Feb 2019 09:52:19 +0000 (01:52 -0800)]
x86: Make sure i8254 is setup correctly before generating beeps
The i8254 timer control IO port (0x43) should be setup correctly
by using PIT counter 2 to generate beeps, however in U-Boot other
codes like TSC driver utilizes PIT for TSC frequency calibration
and configures the counter 2 to a different mode that does not
beep. Fix this by always ensuring the PIT counter 2 is correctly
initialized so that the i8254 beeper driver works as expected.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Alexander Graf [Wed, 30 Jan 2019 10:46:34 +0000 (11:46 +0100)]
x86: Add efi runtime reset
Our selftest will soon test the actual runtime reset function rather than
the boot time one. For this, we need to ensure that the runtime version
actually succeeds on x86 to keep our travis tests work.
So this patch implements an x86 runtime reset function. It is missing
shutdown functionality today, but OSs usually implement that via ACPI
and this function does more than the stub from before, so it's at least
an improvement.
Eventually we will want to have full DM functionality in runtime services.
But this fixes a travis failure and doesn't clutter the code too heavily, so
we should pull it in without the amazing new RTS DM framework.
Signed-off-by: Alexander Graf <agraf@suse.de>
Matthias Brugger [Tue, 5 Mar 2019 11:50:18 +0000 (12:50 +0100)]
efi_loader: Fix serial console size detection
Function term_read_reply tries to read from the serial console until
the end_char was read. This can hang forever if we are, for some reason,
not able to read the full response (e.g. serial buffer too small,
frame error). This patch moves the timeout detection into
term_read_reply() to assure we will make progress.
Fixes:
6bb591f704 ("efi_loader: query serial console size reliably")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Throw missing error when an incomplete reply for the cursor position is
received.
Change type of argument of term_get_char() *s32. This renders the function
reusable in efi_cin_read_key().
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Sun, 10 Mar 2019 14:16:07 +0000 (10:16 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga
- Arria10 DRAM fixes and Gen5 cache fixes
Tom Rini [Sun, 10 Mar 2019 14:15:50 +0000 (10:15 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
- More gen2/gen3 fixes
Andy Shevchenko [Thu, 28 Feb 2019 08:10:07 +0000 (10:10 +0200)]
x86: edison: Add the rest of UARTs present on board
Intel Edison has three UART ports, i.e.
port 0 - Bluetooth
port 1 - auxiliary, available for general purpose use
port 2 - debugging, usually console output is here
Enable all of them for future use.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 28 Feb 2019 08:10:06 +0000 (10:10 +0200)]
x86: edison: Use proper number of serial interface
The console is actually serial #2. When we would like to enable other ports,
this would be not okay to mess up with the ordering.
Thus, fix the number of default console interface to be 2.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Thu, 28 Feb 2019 15:19:54 +0000 (17:19 +0200)]
x86: acpi: Not every platform has serial console a first device
We may not do an assumption that current console device is always a first
of UCLASS_SERIAL one.
For example, on properly described Intel Edison board the console UART
is a third one.
Use current serial device as described in global data.
Fixes:
a61cbad78e67 ("dm: serial: Adjust serial_getinfo() to use proper API")
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Tue, 26 Feb 2019 11:43:15 +0000 (13:43 +0200)]
x86: acpi: Add DMA descriptors for I2C1 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.
Provide DMA descriptors to utilize this capability in the future.
Note, I2C6, which is available to user, has no DMA request lines connected.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Tue, 26 Feb 2019 11:43:14 +0000 (13:43 +0200)]
x86: acpi: Add DMA descriptors for SPI5 on Intel Tangier
Intel Tangier SoC has a general purpose DMA which can serve to speed up
communications on SPI and I2C serial buses.
Provide DMA descriptors to utilize this capability in the future.
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Marek Vasut [Sat, 9 Mar 2019 20:58:09 +0000 (21:58 +0100)]
ddr: socfpga: Clean up ddr_setup()
Replace the current rather convoluted code using ad-hoc polling
mechanism with a more straightforward code. Use wait_for_bit_le32()
to poll the DDRCALSTAT register instead of local reimplementation.
It makes no sense to pull for 5 seconds before giving up and trying
to restart the EMIF, so instead wait 500 mSec for the calibration to
complete and if this fails, restart the EMIF and try again. Perform
this 32 times instead of 3 times as the original code did.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Sat, 9 Mar 2019 20:57:58 +0000 (21:57 +0100)]
ddr: socfpga: Clean up EMIF reset
The EMIF reset code can well use wait_for_bit_le32() instead of all that
convoluted polling code. Reduce the timeout from 100 seconds to 1 second,
since if the EMIF fails to reset itself in 1 second, it's unlikely longer
wait would help. Make sure to clear the EMIF reset request even if the
SEQ2CORE_INT_RESP_BIT isn't asserted.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Fri, 8 Mar 2019 18:11:55 +0000 (19:11 +0100)]
ddr: socfpga: Fix EMIF clear timeout
The current EMIF clear timeout handling code was applying bitwise
operations to signed data types and as it was, was extremely hard
to read. Replace it with simple wait_for_bit(). Expand the error
handling to make it more readable too.
This patch also changes the timeout for emif_clear() from 14 hours
to 1 second.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Wed, 6 Mar 2019 19:07:55 +0000 (20:07 +0100)]
ARM: socfpga: Fix A10 SoCDK Kconfig
The Kconfig checked for SoCFPGA Arria10 as a platform, instead of
checking for specific board configuration, which works with one
single platform in tree, but not with multiple. Fix it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Tue, 8 May 2018 16:44:43 +0000 (18:44 +0200)]
ARM: socfpga: Fix Arria10 SPI and NAND U-Boot offset
The SPL size on Gen5 is 4*64kiB, but on A10 it is 4*256kiB.
Handle the difference.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Tue, 8 May 2018 16:44:00 +0000 (18:44 +0200)]
ARM: socfpga: Drop CONFIG_SYS_NAND_BAD_BLOCK_POS
This is not used anywhere, so drop it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Tue, 8 May 2018 18:32:01 +0000 (20:32 +0200)]
ARM: socfpga: Disable D cache in SPL
The bootrom seems to leave the D-cache in messed up state, make sure
the SPL disables it so it can not interfere with operation.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Wed, 6 Mar 2019 16:18:22 +0000 (17:18 +0100)]
ddr: socfpga: Fix newline in debug print on A10
The debug print is missing a newline, add it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Marek Vasut [Tue, 5 Mar 2019 17:37:02 +0000 (18:37 +0100)]
ddr: socfpga: Fix IO in Arria10 DDR driver
The Altera Arria10 DDR driver was using constants in a few places
instead of reading registers associated with those constants, fix
this.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Chin Liang See <chin.liang.see@intel.com>
Cc: Dinh Nguyen <dinguyen@kernel.org>
Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Cc: Tien Fong Chee <tien.fong.chee@intel.com>
Dinh Nguyen [Sun, 3 Mar 2019 17:02:10 +0000 (11:02 -0600)]
ARM: socfpga: fix data and tag latency values for pl310 cache controller
The values for the data and tag latency settings on the PL310 caches
controller is an (n-1). For example, the "arm,tag-latency" is specified
as <1 1 1>, so the values that should be written to register should be
0x000. And for the "arm,data-latency" specified as <2 1 1>, the register
value should be 0x010.
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Eugeniu Rosca [Sat, 9 Mar 2019 13:04:57 +0000 (14:04 +0100)]
ARM: dts: rmobile: Zap redundant USB/SDHI nodes on M3N
v2019.01 commit
cbff9f80cedd ("ARM: dts: rmobile: Sync Gen3 DTs with
Linux 4.19.6") made the sdhi/usb nodes available in r8a77965.dtsi.
Hence, remove the SDHI/USB nodes from r8a77965-u-boot.dtsi. This is
equivalent to partially reverting below v2019.01 commits:
-
f529bc551b6d ("ARM: dts: rmobile: Extract USB nodes on M3N")
-
830b94f76867 ("ARM: dts: rmobile: Extract SDHI nodes on M3N")
Duplicating the nodes from <soc>.dtsi to <soc>-u-boot.dtsi is obviously:
- not needed if no U-boot-specific changes are needed in those nodes.
- potentially dangerous/error-prone, since the duplicated properties
override the properties originally defined in <soc>.dtsi. One
possible consequence is that <soc>.dtsi is getting an update from
Linux, while <soc>-u-boot.dtsi stays unchanged. In this situation,
the obsolete property values from <soc>-u-boot.dtsi will take
precedence masking some of the <soc>.dtsi updates, potentially
leading to all kind of obscure issues.
Below is the dtdiff of r8a77965-salvator-x-u-boot.dtb (the only "user"
of r8a77965-u-boot.dtsi) before and after the patch (slightly
reformatted to avoid 'git am/apply' issues and to reduce the width).
What below output means is there is already a mismatch in some of
SDHI/USB nodes between r8a77965.dtsi and r8a77965-u-boot.dtsi. Since no
U-Boot customization is needed in SDHI/USB DT nodes, get rid of them in
r8a77965-u-boot.dtsi.
$> dtdiff before-r8a77965-salvator-x-u-boot.dtb \
after-r8a77965-salvator-x-u-boot.dtb
--- /dev/fd/63 2019-03-09 12:57:40.
877963983 +0100
+++ /dev/fd/62 2019-03-09 12:57:40.
877963983 +0100
@@ -1471,7 +1471,7 @@
bus-width = <0x4>;
cd-gpios = <0x51 0xc 0x1>;
clocks = <0x6 0x1 0x13a>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
interrupts = <0x0 0xa5 0x4>;
max-frequency = <0xc65d400>;
pinctrl-0 = <0x4d>;
@@ -1492,7 +1492,7 @@
sd@
ee120000 {
clocks = <0x6 0x1 0x139>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
interrupts = <0x0 0xa6 0x4>;
max-frequency = <0xbebc200>;
power-domains = <0x1 0x20>;
@@ -1504,7 +1504,7 @@
sd@
ee140000 {
bus-width = <0x8>;
clocks = <0x6 0x1 0x138>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
fixed-emmc-driver-type = <0x1>;
interrupts = <0x0 0xa7 0x4>;
max-frequency = <0xbebc200>;
@@ -1526,7 +1526,7 @@
bus-width = <0x4>;
cd-gpios = <0x5a 0xf 0x1>;
clocks = <0x6 0x1 0x137>;
- compatible = "renesas,sdhi-r8a77965";
+ compatible = "renesas,sdhi-r8a77965", "renesas,rcar-gen3-sdhi";
interrupts = <0x0 0xa8 0x4>;
max-frequency = <0xc65d400>;
pinctrl-0 = <0x56>;
@@ -1868,14 +1868,14 @@
usb-phy@
ee0a0200 {
#phy-cells = <0x0>;
- clocks = <0x6 0x1 0x2be>;
+ clocks = <0x6 0x1 0x2bf>;
compatible = "renesas,usb2-phy-r8a77965", "renesas,rcar-gen3-usb2-phy";
phandle = <0x47>;
pinctrl-0 = <0x4c>;
pinctrl-names = "default";
power-domains = <0x1 0x20>;
reg = <0x0 0xee0a0200 0x0 0x700>;
- resets = <0x6 0x2be>;
+ resets = <0x6 0x2bf>;
status = "okay";
};
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Eugeniu Rosca [Tue, 5 Mar 2019 22:13:37 +0000 (23:13 +0100)]
ARM: rmobile: rcar-gen3: Activate bootm_size
v2019.01 commit
07a8060a1277 ("ARM: rmobile: Convert to bootm_size")
attempted converting to bootm_size of 256 MiB below targets:
- include/configs/alt.h
- include/configs/gose.h
- include/configs/koelsch.h
- include/configs/lager.h
- include/configs/porter.h
- include/configs/rcar-gen3-common.h
- include/configs/silk.h
- include/configs/stout.h
The update didn't fully work on R-Car3 due to the
CONFIG_SYS_BOOTMAPSZ=8MiB definition left by v2016.09 commit
e525d34b476e ("ARM: rmobile: Add support salvator-x board"),
which is explained in below README excerpt:
----8<----
CONFIG_SYS_BOOTMAPSZ:
[..] If CONFIG_SYS_BOOTMAPSZ is undefined,
then the value in "bootm_size" will be used instead.
----8<----
Allow the original commit to accomplish its purpose on R-Car3 targets
by removing the CONFIG_SYS_BOOTMAPSZ definition.
Fixes:
07a8060a1277 ("ARM: rmobile: Convert to bootm_size")
Signed-off-by: Eugeniu Rosca <erosca@de.adit-jv.com>
Marek Vasut [Tue, 19 Feb 2019 04:07:13 +0000 (05:07 +0100)]
ARM: rmobile: Convert Gen2 Stout, Porter, Silk to DM_SPI{,_FLASH}
Enable DM_SPI and DM_SPI_FLASH in U-Boot on H2 Stout, M2W Porter and E3 Silk.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 19 Feb 2019 04:58:24 +0000 (05:58 +0100)]
ARM: dts: rmobile: Force 1-bit bus width on Gen2 QSPI
U-Boot currently uses Gen2 QSPI in 1-bit mode, enforce it until
we can do better using the new SPI NOR framework.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Jagan Teki [Wed, 27 Feb 2019 18:56:59 +0000 (00:26 +0530)]
clk: sunxi: h3: Implement EPHY CLK and RESET
EPHY CLK and RESET is available in Allwinner H3 EMAC
via mdio-mux node of internal PHY. Add the respective
clock and reset reg and bits.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Jagan Teki [Wed, 27 Feb 2019 18:56:57 +0000 (00:26 +0530)]
clk: sunxi: Implement EMAC, GMAC clocks, resets
- Implement EMAC, GMAC clocks via ccu_clk_gate for
all supported Allwinner SoCs.
- Implement EMAC, GMAC resets via ccu_reset for all
supported Allwinner SoCs.
Cc: Joe Hershberger <joe.hershberger@ni.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Jagan Teki [Wed, 27 Feb 2019 18:56:49 +0000 (00:26 +0530)]
clk: sunxi: Implement A10 EMAC clocks
Implement EMAC clocks via ccu_clk_gate for Allwinner A10 SoC.
Which would eventually used in sunxi_emac.c driver.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Fri, 8 Mar 2019 23:04:13 +0000 (18:04 -0500)]
Merge branch '2019-03-08-master-imports'
- Assorted minor fixes:
- ARM: qemu-arm: enable USB boot in distro boot with UEFI
- image: fdt: handle coalesced reserve region
- cmd: thordown: Fix spelling of download.
- fdt: Fix FIT header verification in mkimage and conduct same checks
as bootm
- test: Update test-imagetools.sh to match new syntax
AKASHI Takahiro [Fri, 14 Dec 2018 09:53:22 +0000 (18:53 +0900)]
ARM: qemu-arm: enable USB boot in distro boot with UEFI
With this patch which adds a removable USB mass storage to a list
of bootable devices, USB boot is supported in distro boot if UEFI is
configured.
Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
Patrick Delaunay [Wed, 6 Mar 2019 13:23:52 +0000 (14:23 +0100)]
image: fdt: handle coalesced reserve region
Handle in boot_fdt_reserve_region
any return value > 0 of lmb_reserve() function;
it occurs when coalesced region are found:
adjacent reserved region are merged.
This patch avoid the error trace:
ERROR: reserving fdt memory region failed..
when reserved region are merged (return value = 1).
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Vagrant Cascadian [Wed, 6 Mar 2019 06:52:14 +0000 (22:52 -0800)]
cmd: thordown: Fix spelling of download.
Signed-off-by: Vagrant Cascadian <vagrant@debian.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Jordan Hand [Tue, 5 Mar 2019 22:47:56 +0000 (14:47 -0800)]
fdt: Fix FIT header verification in mkimage and conduct same checks as bootm
FIT header verification in mkimage was treating a return code as a boolean,
which meant that failures in validating the fit were seen as successes.
Additionally, mkimage was checking all formats to find a header which
passes validation, rather than using the image type specified to
mkimage.
checkpatch.pl checks for lines ending with '(' and alignment matching
open parentheses are ignored to keep with existing coding style.
Signed-off-by: Jordan Hand <jorhand@microsoft.com>
Martyn Welch [Thu, 14 Feb 2019 13:11:35 +0000 (13:11 +0000)]
test: Update test-imagetools.sh to match new syntax
The syntax of dumpimage was simplified in commit
12b831879a76 ("tools:
dumpimage: Simplify arguments"), but the test
(test/image/test-imagetools.sh) was not updated and is now failing.
Update the test to use the new syntax.
Reported-by: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Martyn Welch <martyn.welch@collabora.com>
Tested-by: Vagrant Cascadian <vagrant@debian.org>
Tom Rini [Fri, 8 Mar 2019 12:26:29 +0000 (07:26 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-i2c
This pull request contains bugfixes for rcar_i2c, rcar_ii2c and
i2c_cdns driver.
Also the commit "i2c: rcar_i2c: Add Gen3 SoC support" from Marek
is a bugfix for arm64 builds, as discussed with Marek on list.
Ondrej Jirman [Wed, 13 Feb 2019 17:51:05 +0000 (18:51 +0100)]
power: axp818: Fix typo in axp_set_dldo
Fix typo in axp_set_dldo() so that it correctly uses AXP818_DLDO1_CTRL
register to configure the voltage instead of setting AXP818_ELDO1_CTRL
register which is obviously incorrect.
Signed-off-by: Ondřej Jirman <megous@megous.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
Ismael Luceno Cortes [Thu, 7 Mar 2019 18:00:55 +0000 (18:00 +0000)]
i2c: rcar_i2c: Move FSDA check to rcar_i2c_recover
Cosmetic change. Any call to the recover function would need to do the
same check afterwards, so it's sensible to make it part of the function.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Ismael Luceno Cortes [Thu, 7 Mar 2019 18:00:54 +0000 (18:00 +0000)]
i2c: rcar_i2c: Set the slave address from rcar_i2c_xfer
It needs to be done for both reads and writes, so do it at rcar_i2c_xfer
to avoid duplication.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Ismael Luceno Cortes [Thu, 7 Mar 2019 18:00:53 +0000 (18:00 +0000)]
i2c: rcar_i2c: Don't mask errors with EREMOTEIO at rcar_i2c_xfer
Fix rcar_i2c_xfer return value, previously it was always returning
-EREMOTEIO when dealing with errors from calls to the read/write
functions.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Ismael Luceno Cortes [Thu, 7 Mar 2019 18:00:52 +0000 (18:00 +0000)]
i2c: rcar_i2c: Fix sending of slave addresses
Do the reset before clearing the MSR, otherwise it may result in a read
or write operation instead if the start condition is repeated.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Ismael Luceno Cortes [Thu, 7 Mar 2019 18:00:51 +0000 (18:00 +0000)]
i2c: rcar_i2c: Add comments about registers & values
Document the meaning of macros related to registers and values to be
written to them.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Ismael Luceno Cortes [Thu, 7 Mar 2019 18:00:49 +0000 (18:00 +0000)]
i2c: rcar_i2c: Setup SCL/SDA delay at rcar_i2c_set_speed
Setting up the delay only needs to be done once; move it to
rcar_i2c_set_speed so it's done at initialization time.
Signed-off-by: Ismael Luceno <ismael.luceno@silicon-gears.com>
Reviewed-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Siva Durga Prasad Paladugu [Thu, 7 Mar 2019 10:52:49 +0000 (11:52 +0100)]
i2c: i2c_cdns: Add support for handling arbitration lost
This patch adds support for handling arbitration lost
in case of multi master mode. When an arbitration lost
is detected, it retries for 10 times before failing.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Siva Durga Prasad Paladugu [Thu, 7 Mar 2019 10:52:48 +0000 (11:52 +0100)]
i2c: i2c_cdns: Fix clearing of all interrupts
The arbitration lost interrupt was not getting cleared
while clearing interrupts. This patch fixes this by adding
arbitration lost interrupt as well during clear. This patch
also removes hardcoded value and defined a macro for it.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Marek Vasut [Sat, 2 Mar 2019 16:17:11 +0000 (17:17 +0100)]
i2c: rcar_i2c: Add Gen3 SoC support
Add support for R-Car Gen3 SoCs into the driver, which encompases
the Gen3 SoC extra timing register handling and 64bit build fixes.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Reviewed-by: Heiko Schocher <hs@denx.de>
Marek Vasut [Thu, 7 Mar 2019 02:41:08 +0000 (03:41 +0100)]
i2c: rcar_iic: Read ICSR only once
Read ICSR only once to avoid missing interrupts. This happens on R8A7791
Porter during reset, when reading the PMIC register 0x13, which may fail
sometimes because of the missed DTE interrupt.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Heiko Schocher <hs@denx.de>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tom Rini [Thu, 7 Mar 2019 01:25:09 +0000 (20:25 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-spi
- dw spi include file fix
- Allwinner A31 spi, been in ML in many releases.
Tom Rini [Tue, 5 Mar 2019 13:51:48 +0000 (08:51 -0500)]
Merge tag 'efi-2019-04-rc4' of https://github.com/xypron2/u-boot
Pull request for the UEFI subsystem for v2019.04-rc4
This pull request contains only bug fixes.
The most notable bug fixed was writing to random memory addresses when
trying to add a HII package of a yet unsupported package type.
Tom Rini [Tue, 5 Mar 2019 02:46:24 +0000 (21:46 -0500)]
Prepare v2019.04-rc4
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 4 Mar 2019 21:35:40 +0000 (16:35 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-sh
- Assorted PFC fixes
Tom Rini [Mon, 4 Mar 2019 18:06:22 +0000 (13:06 -0500)]
Merge tag 'u-boot-atmel-2019.04-a' of git://git.denx.de/u-boot-atmel
First set of u-boot-atmel fixes for 2019.04 cycle
Tom Rini [Mon, 4 Mar 2019 18:05:53 +0000 (13:05 -0500)]
Merge git://git.denx.de/u-boot-fsl-qoriq
- Enable DHCP as boot-source in distro boot for NXP layerscape
platforms
- fix register layout for SEC on Layerscape architectures
- fixes related to DPAA2 ethernet
Jagan Teki [Wed, 27 Feb 2019 14:32:13 +0000 (20:02 +0530)]
spi: Rename sun4i_spi.c into spi-sunxi.c
Now the same SPI controller driver is reusable in all Allwinner
SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c
which eventually look like a common sunxi driver.
Also update the function, variable, structure names in driver from
sun4i into sunxi.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:12 +0000 (20:02 +0530)]
spi: sun4i: Driver cleanup
- drop unused macros.
- use base instead of base_addr, for better code readability
- move .probe and .ofdata_to_platdata functions in required
places to add platdata support in future.
- use sentinel sun4i_spi_ids.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:11 +0000 (20:02 +0530)]
spi: sun4: Add A31 spi controller support
The usual SPI transmission protocol in Allwinner A10 and A31
controllers share similar context with minimal changes in register
offsets along with few additional register bits on A31.
So, add A31 spi controller support in existing sun4i_spi with A31
specific register offsets and bits.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:10 +0000 (20:02 +0530)]
spi: sun4i: Add CLK support
Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver.
Clock disablement could be done while releasing the bus transfer, but
the existing code doesn't disable the clocks it only taken care of clock
enablement globally in probe.
So to make a proper clock handling, the clocks should enable it in claim
and disable it in release.
This patch would also do that change, by enable and disable clock in
proper order.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:09 +0000 (20:02 +0530)]
spi: sun4i: Support fifo_depth via drvdata
Support fifo_depth via drvdata instead of macro definition, this would
eventually reduce another macro definition for new SPI controller fifo
depth support addition.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Andre Przywara <andre.przywara@arm.com>
Jagan Teki [Wed, 27 Feb 2019 14:32:08 +0000 (20:02 +0530)]
spi: sun4i: Access registers and bits via enum offsets
Allwinner support two different SPI controllers one for A10 and
another for A31 with minimal changes in register offsets and
respective register bits, but the logic for accessing the SPI
master via SPI slave remains nearly similar.
Add enum offsets for register set and register bits, so-that
it can access both classes of SPI controllers.
Assign same control register for global, transfer and fifo control
registers to make the same code compatible with A31 SPI controller.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204