platform/kernel/u-boot.git
7 years agoARM: rmobile: Add R8A7796 support
Marek Vasut [Sat, 13 May 2017 13:57:39 +0000 (15:57 +0200)]
ARM: rmobile: Add R8A7796 support

Add Kconfig entry for the R8A7796 RCar M3 SoC.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Handle R8A7796 r1.1 in the PRR code
Marek Vasut [Sat, 13 May 2017 13:57:38 +0000 (15:57 +0200)]
ARM: rmobile: Handle R8A7796 r1.1 in the PRR code

The R8A7796 r1.1 reports itself as r2.0 , add quirk into the
PRR code to fix this report.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Add R8A7796 into the CPU table
Marek Vasut [Sat, 13 May 2017 13:57:37 +0000 (15:57 +0200)]
ARM: rmobile: Add R8A7796 into the CPU table

Add entry for the R8A7796 RCar M3 SoC into the CPU info table.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Add R8A7795 into the CPU table
Marek Vasut [Sat, 13 May 2017 13:57:36 +0000 (15:57 +0200)]
ARM: rmobile: Add R8A7795 into the CPU table

Add entry for the R8A7795 RCar H3 SoC into the CPU info table.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Make the Gen3 SoC configurable
Marek Vasut [Sat, 13 May 2017 13:57:35 +0000 (15:57 +0200)]
ARM: rmobile: Make the Gen3 SoC configurable

Allow selecting the Gen3 SoC in preparation for RCar M3 .
No functional change.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Update link address to match latest BL2
Marek Vasut [Sat, 13 May 2017 13:57:34 +0000 (15:57 +0200)]
ARM: rmobile: Update link address to match latest BL2

Update the CONFIG_SYS_TEXT_BASE to match BL2 Rev.1.0.9 and newer,
which loads the U-Boot to 0x50000000 .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Zap RCAR_GEN3_EXTRAM_BOOT
Marek Vasut [Sat, 13 May 2017 13:57:33 +0000 (15:57 +0200)]
ARM: rmobile: Zap RCAR_GEN3_EXTRAM_BOOT

This Kconfig option is not used on any board, so drop it.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Import R8A7796 PFC and GPIO tables
Marek Vasut [Sat, 13 May 2017 13:57:32 +0000 (15:57 +0200)]
ARM: rmobile: Import R8A7796 PFC and GPIO tables

Import the R8A7796 PFC and GPIO tables from the latest 3.5.3 release
from Renesas .

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoARM: rmobile: Update R8A7795 PFC and GPIO tables
Marek Vasut [Sat, 13 May 2017 13:57:31 +0000 (15:57 +0200)]
ARM: rmobile: Update R8A7795 PFC and GPIO tables

Sync the PFC and GPIO tables with the latest 3.5.3 release from
Renesas . This adds ES2.0 support.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agoserial: sh: Add r8a7796 support
Hiroyuki Yokoyama [Sat, 13 May 2017 13:55:26 +0000 (15:55 +0200)]
serial: sh: Add r8a7796 support

Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
7 years agonet: ravb: Add Renesas Ethernet RAVB driver
Marek Vasut [Sat, 13 May 2017 13:54:28 +0000 (15:54 +0200)]
net: ravb: Add Renesas Ethernet RAVB driver

Add driver for the Renesas Ethernet AVB block found in RCar H3/M3.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Tom Rini <trini@konsulko.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Based on work of:
Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Takeshi Kihara <takeshi.kihara.df@renesas.com>
Kazuya Mizuguchi <kazuya.mizuguchi.ks@renesas.com>

7 years agogpio: rcar_gen3: Fix GPIO read support
Kouei Abe [Sat, 13 May 2017 13:48:04 +0000 (15:48 +0200)]
gpio: rcar_gen3: Fix GPIO read support

This patch fixes to read the GPIO status after confirming the
INOUT setting.

Signed-off-by: Kouei Abe <kouei.abe.cp@renesas.com>
Signed-off-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Cc: Tom Rini <trini@konsulko.com>
7 years agoMerge branch 'master' of git://www.denx.de/git/u-boot-imx
Tom Rini [Thu, 18 May 2017 21:17:45 +0000 (17:17 -0400)]
Merge branch 'master' of git://denx.de/git/u-boot-imx

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-socfpga
Tom Rini [Thu, 18 May 2017 21:17:42 +0000 (17:17 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-socfpga

7 years agoMerge branch 'master' of git://git.denx.de/u-boot-usb
Tom Rini [Thu, 18 May 2017 21:17:39 +0000 (17:17 -0400)]
Merge branch 'master' of git://git.denx.de/u-boot-usb

7 years agoARM: dts: am335x-evm: disable mmc3
Jean-Jacques Hiblot [Wed, 17 May 2017 19:22:55 +0000 (21:22 +0200)]
ARM: dts: am335x-evm: disable mmc3

SDIO is not supported in u-boot, there is no point in enabling mmc3.
For this purpose, add u-boot specific dtsi that this will be included
automatically while building the dtb.

Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
7 years agoscripts/Makefile.lib: Always have ...-u-boot.dtsi be able to override
Tom Rini [Wed, 17 May 2017 18:06:08 +0000 (14:06 -0400)]
scripts/Makefile.lib: Always have ...-u-boot.dtsi be able to override

The intention of having a -u-boot.dtsi file is to be able to make
changes to the provided upstream dts files as well as to be able to add
nodes.  Change the logic for adding the file from making it the last
included file at the top of the dts to being included at the end of the
file.

Cc: Jean-Jacques Hiblot <jjhiblot@ti.com>
Cc: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tested-by: Jean-Jacques Hiblot <jjhiblot@ti.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agoMerge branch 'master' of git://git.denx.de/u-boot-imx
Stefano Babic [Thu, 18 May 2017 09:53:27 +0000 (11:53 +0200)]
Merge branch 'master' of git://git.denx.de/u-boot-imx

Signed-off-by: Stefano Babic <sbabic@denx.de>
7 years agoarm: socfpga: Enable build for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:48 +0000 (02:44 +0800)]
arm: socfpga: Enable build for Arria 10

Update Kconfig and Makefile to enable Arria 10.
Clean up Makefile and sorting *.o alphanumerically.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add board files for the Arria10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:47 +0000 (02:44 +0800)]
arm: socfpga: Add board files for the Arria10

Add support for the Arria10 SoCDK.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add config and defconfig for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:46 +0000 (02:44 +0800)]
arm: socfpga: Add config and defconfig for Arria 10

Add config and defconfig for the Arria10 and update socfpga_common.h.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add SPL support for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:45 +0000 (02:44 +0800)]
arm: socfpga: Add SPL support for Arria 10

Add SPL support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: dts: Add dts and dtsi for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:44 +0000 (02:44 +0800)]
arm: dts: Add dts and dtsi for Arria 10

Device tree files for Arria 10

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add misc support for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:43 +0000 (02:44 +0800)]
arm: socfpga: Add misc support for Arria 10

Add misc support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add pinmux for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:42 +0000 (02:44 +0800)]
arm: socfpga: Add pinmux for Arria 10

Add pinmux support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add sdram header file for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:41 +0000 (02:44 +0800)]
arm: socfpga: Add sdram header file for Arria 10

Add sdram header file for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add system manager for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:40 +0000 (02:44 +0800)]
arm: socfpga: Add system manager for Arria 10

Add system manager register struct and macros for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add clock driver for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:39 +0000 (02:44 +0800)]
arm: socfpga: Add clock driver for Arria 10

Add clock driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add reset driver support for Arria 10
Ley Foon Tan [Tue, 25 Apr 2017 18:44:38 +0000 (02:44 +0800)]
arm: socfpga: Add reset driver support for Arria 10

Add reset driver support for Arria 10.

Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Add A10 macros
Ley Foon Tan [Tue, 25 Apr 2017 18:44:37 +0000 (02:44 +0800)]
arm: socfpga: Add A10 macros

Add i2c, timer and other A10 macros.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Restructure misc driver
Ley Foon Tan [Tue, 25 Apr 2017 18:44:36 +0000 (02:44 +0800)]
arm: socfpga: Restructure misc driver

Restructure misc driver in the preparation to support A10.
Move the Gen5 specific code to gen5 file.

Change all uint32_t_to u32.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Restructure system manager
Ley Foon Tan [Tue, 25 Apr 2017 18:44:35 +0000 (02:44 +0800)]
arm: socfpga: Restructure system manager

Restructure system manager in the preparation to support A10.
No functional change.

Change uint32_t to u32.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Restructure reset manager driver
Ley Foon Tan [Tue, 25 Apr 2017 18:44:34 +0000 (02:44 +0800)]
arm: socfpga: Restructure reset manager driver

Restructure reset manager driver in the preparation to support A10.
Move the Gen5 specific code to gen5 files.

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agoarm: socfpga: Restructure clock manager driver
Ley Foon Tan [Tue, 25 Apr 2017 18:44:33 +0000 (02:44 +0800)]
arm: socfpga: Restructure clock manager driver

Restructure clock manager driver in the preparation to support A10.
Move the Gen5 specific code to _gen5 files.

- Change all uint32_t to u32 and change to use macro BIT(n) for bit shift.
- Check return value from wait_for_bit(). So change return type to int for
  cm_write_with_phase() and cm_basic_init().

Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
7 years agousb: lpc32xx: add i2c DM support
Liam Beguin [Wed, 17 May 2017 17:01:15 +0000 (13:01 -0400)]
usb: lpc32xx: add i2c DM support

Add DM support for i2c functions.

Signed-off-by: Liam Beguin <lbeguin@tycoint.com>
Signed-off-by: Sylvain Lemieux <slemieux@tycoint.com>
Reviewed-by: Marek Vasut <marex@denx.de>
7 years agopinctrl: imx: fix memory leak
Peng Fan [Thu, 11 May 2017 09:34:14 +0000 (17:34 +0800)]
pinctrl: imx: fix memory leak

Each time set_state is called, a new piece memory will
be allocated for pin_data, but not freed, this will
incur memory leak.

When error, the devm API could not free memory automatically.
So need call devm_kfree when error.

Issue reported by Coverity

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoimx: mx7dsabresd: fix secure config after switching to DM
Stefano Babic [Thu, 18 May 2017 08:37:01 +0000 (10:37 +0200)]
imx: mx7dsabresd: fix secure config after switching to DM

mx7dsabresd_secure_defconfig was not updated after moving to DM.

Signed-off-by: Stefano Babic <sbabic@denx.de>
7 years agoimx: mx7dsabresd: switch to DM USB
Peng Fan [Thu, 13 Apr 2017 06:09:59 +0000 (14:09 +0800)]
imx: mx7dsabresd: switch to DM USB

Switch to use DM USB.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
7 years agoimx: mx7dsabresd: reset ENET_RST_B
Peng Fan [Thu, 13 Apr 2017 06:09:58 +0000 (14:09 +0800)]
imx: mx7dsabresd: reset ENET_RST_B

Reset ENET_RST_B to make ENET function stable.
Since DM_GPIO enabled, we use "gpio_spi@0_5" which corresponds
to ENET_RST_B.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoimx: mx7dsabresd: enable more DM drivers
Peng Fan [Thu, 13 Apr 2017 06:09:57 +0000 (14:09 +0800)]
imx: mx7dsabresd: enable more DM drivers

Enable more DM drivers. The imx I2C/MMC DM drivers needs DM_GPIO
enabled. The 74x164 drivers needs SOFT_SPI and DM_GPIO enabled.
So needs to enable them together.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agogpio: 74x164: make oe-pins optional
Peng Fan [Thu, 13 Apr 2017 06:09:56 +0000 (14:09 +0800)]
gpio: 74x164: make oe-pins optional

Make oe-pins optional because some boards have fixed it to enable.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agospi: kconfig: add soft spi Kconfig entry
Peng Fan [Thu, 13 Apr 2017 06:09:55 +0000 (14:09 +0800)]
spi: kconfig: add soft spi Kconfig entry

Add the Kconfig entry for SOFT_SPI which uses gpio to simulate the
SPI signals. We use it for accessing 74x164 on some i.MX boards.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Jagan Teki <jagan@openedev.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoarm: dts: imx7d-sdb: add usdhc support
Peng Fan [Thu, 13 Apr 2017 06:09:54 +0000 (14:09 +0800)]
arm: dts: imx7d-sdb: add usdhc support

Add usdhc support

Signed-off-by: Peng Fan <peng.fan@nxp.com>
7 years agoarm: dts: imx7d-sdb: add i2c support
Peng Fan [Thu, 13 Apr 2017 06:09:53 +0000 (14:09 +0800)]
arm: dts: imx7d-sdb: add i2c support

Add i2c support.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoarm: dts: imx7d-sdb: add regulator node for usb and mmc
Peng Fan [Thu, 13 Apr 2017 06:09:52 +0000 (14:09 +0800)]
arm: dts: imx7d-sdb: add regulator node for usb and mmc

Add regulator node for usb and mmc.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoarm: dts: imx7d-sdb: add spi gpio node
Peng Fan [Thu, 13 Apr 2017 06:09:51 +0000 (14:09 +0800)]
arm: dts: imx7d-sdb: add spi gpio node

Add spi gpio node for 74LV595.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoarm: dts: imx7d-sdb add basic dts
Peng Fan [Thu, 13 Apr 2017 06:09:50 +0000 (14:09 +0800)]
arm: dts: imx7d-sdb add basic dts

Add basic dts for i.MX7D-SDB board.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoarm: dts: imx7: sync with Linux
Peng Fan [Thu, 13 Apr 2017 06:09:49 +0000 (14:09 +0800)]
arm: dts: imx7: sync with Linux

Sync with Linux commit 308ac756("Merge tag 'gpio-v4.11-3'").

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefan Agner <stefan.agner@toradex.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
7 years agoimx: ventana: update imx wdog external reset dt property
Tim Harvey [Mon, 15 May 2017 17:05:07 +0000 (10:05 -0700)]
imx: ventana: update imx wdog external reset dt property

Early backports of the imx wdog external reset feature occured before the
property was accepted upstream and used 'ext-reset-output' instead of
'fsl,ext-reset-output'. In order to support older kernels remove both
properties.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
7 years agoimx: ventana: fix GW520x external watchdog dt update
Tim Harvey [Mon, 15 May 2017 17:05:06 +0000 (10:05 -0700)]
imx: ventana: fix GW520x external watchdog dt update

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
7 years agomx6sabresd: Remove non-SPL targets
Fabio Estevam [Sun, 14 May 2017 23:00:24 +0000 (20:00 -0300)]
mx6sabresd: Remove non-SPL targets

Now that mx6sabresd_spl_defconfig can be used to boot all
mx6sabresd variants, the non-SPL targets can be safely removed.

Signed-off-by: Fabio Estevam <fabio.estvam@nxp.com>
7 years agomx6sabresd: Add SPL support for the mx6dl variant
Fabio Estevam [Fri, 12 May 2017 15:45:24 +0000 (12:45 -0300)]
mx6sabresd: Add SPL support for the mx6dl variant

Add support for the mx6dlsabresd board in SPL.

Retrieved the DCD table from:
board/freescale/mx6sabresd/mx6dlsabresd.cfg
(NXP U-Boot branch imx_v2015.04_4.1.15_1.0.0_ga)

Flashed SPL and u-boot.img to an SD card and could successfully boot it
on mx6q, mx6qp and mx6dl sabresd boards.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agomx6sabresd: Prepare for supporting MX6DL
Fabio Estevam [Fri, 12 May 2017 15:45:23 +0000 (12:45 -0300)]
mx6sabresd: Prepare for supporting MX6DL

Currently only MX6Q/QP sabresd boards are supported in SPL.

In order to also support MX6DL we need to convert to using
IOMUX_PADS and SETUP_IOMUX_PADS macros.

Other than that move the <asm/arch/mx6-ddr.h> header inclusion to the
SPL code block in order to avoid build error.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Jagan Teki <jagan@openedev.com>
7 years agoengicam: common: Move board_late_init
Jagan Teki [Sat, 6 May 2017 21:13:15 +0000 (02:43 +0530)]
engicam: common: Move board_late_init

Move board_late_init into common area from supported boards.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoengicam: common: Move common board code
Jagan Teki [Sat, 6 May 2017 21:13:14 +0000 (02:43 +0530)]
engicam: common: Move common board code

Move possible common board code into common area
from supported boards.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agogeam6/isiot: Move the spl code common
Jagan Teki [Sat, 6 May 2017 21:13:13 +0000 (02:43 +0530)]
geam6/isiot: Move the spl code common

SPL code for geam6 and isiot are same, so
move them in common area.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoicorem6[_rqs]: Move the spl code common
Jagan Teki [Sat, 6 May 2017 21:13:12 +0000 (02:43 +0530)]
icorem6[_rqs]: Move the spl code common

SPL code for icorem6 and icorem6_rqs are same, so
move them in common area.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoi.MX6UL: isiot: Add SETUP_IOMUX_PADS
Jagan Teki [Sat, 6 May 2017 21:13:11 +0000 (02:43 +0530)]
i.MX6UL: isiot: Add SETUP_IOMUX_PADS

Add generic SETUP_IOMUX_PADS function, for imx6ul mux pads
and use them in Is.IoT board.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoisiot: Fix to use usdhc2_pads for mmc2
Jagan Teki [Sat, 6 May 2017 21:13:10 +0000 (02:43 +0530)]
isiot: Fix to use usdhc2_pads for mmc2

mmc2 in Is.IoT using usdhc1_pads instead usdhc2_pads,
so update the same.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoi.MX6UL: geam6ul: Add SETUP_IOMUX_PADS
Jagan Teki [Sat, 6 May 2017 21:13:09 +0000 (02:43 +0530)]
i.MX6UL: geam6ul: Add SETUP_IOMUX_PADS

Add generic SETUP_IOMUX_PADS function, for imx6ul mux pads.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoicorem6: Use drive strength macros
Jagan Teki [Sat, 6 May 2017 21:13:08 +0000 (02:43 +0530)]
icorem6: Use drive strength macros

Use driver strength macros instead of hex numbers.
- IMX6DQ_DRIVE_STRENGTH - 0x30
- IMX6SDL_DRIVE_STRENGTH - 0x28

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoicorem6: Use proper iomux_ddr_regs drive strength values
Jagan Teki [Sat, 6 May 2017 21:13:07 +0000 (02:43 +0530)]
icorem6: Use proper iomux_ddr_regs drive strength values

Usually the drive strength values for DQ and SDL are 0x30 and
0x28 respectively, update them accordingly.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoengicam: Move uart mux init to SPL
Jagan Teki [Sat, 6 May 2017 21:13:06 +0000 (02:43 +0530)]
engicam: Move uart mux init to SPL

Since, u-boot handle fdt through uart so move the UART code
to SPL instead make it to global area.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoicorem6: Make SPL to pick suitable fdt
Jagan Teki [Sat, 6 May 2017 21:13:05 +0000 (02:43 +0530)]
icorem6: Make SPL to pick suitable fdt

SPL FIT is able to pick the suitable fdt file for u-boot,
so add that function through board_fit_config_name_match.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoengicam: Set fdt_file env during run-time
Jagan Teki [Sat, 6 May 2017 21:13:04 +0000 (02:43 +0530)]
engicam: Set fdt_file env during run-time

Set fdt_file env variable during board_late_init

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agogeam6ul: Add mmc_late_init
Jagan Teki [Sat, 6 May 2017 21:13:03 +0000 (02:43 +0530)]
geam6ul: Add mmc_late_init

Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.

Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agogeam6ul: Add modeboot env via board_late_init
Jagan Teki [Sat, 6 May 2017 21:13:02 +0000 (02:43 +0530)]
geam6ul: Add modeboot env via board_late_init

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.

Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoicorem6: Add mmc_late_init
Jagan Teki [Sat, 6 May 2017 21:13:01 +0000 (02:43 +0530)]
icorem6: Add mmc_late_init

Let the runtime code can set the mmcdev and mmcroot based
on the devno using mmc_get_env_dev instead of defining
separately in build-time configs using mmc_late_init func.

Cc: Stefano Babic <sbabic@denx.de>
Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoicorem6: Add modeboot env via board_late_init
Jagan Teki [Sat, 6 May 2017 21:13:00 +0000 (02:43 +0530)]
icorem6: Add modeboot env via board_late_init

Add runtime, modeboot env which is setting mmcboot, or
nandboot based on the bootdevice so-that conditional
macros b/w MMC and NAND for CONFIG_BOOTCOMMAND should
be avoided in config files.

Cc: Matteo Lisi <matteo.lisi@engicam.com>
Cc: Michael Trimarchi <michael@amarulasolutions.com>
Cc: Stefano Babic <sbabic@denx.de>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
7 years agoimx-common: rdc-sema: correct return value
Peng Fan [Fri, 21 Apr 2017 08:56:50 +0000 (16:56 +0800)]
imx-common: rdc-sema: correct return value

When unlock, if caller is not the sema owner,
return -EACCES, not 1.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agothermal: imx: fix calculation
Peng Fan [Tue, 18 Apr 2017 12:41:53 +0000 (20:41 +0800)]
thermal: imx: fix calculation

Fix calculation. do_div can not handle negative values.
Use div_s64_rem to handle the calculation.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoimx: thermal: update imx6 thermal driver according new equation
Peng Fan [Tue, 18 Apr 2017 12:41:52 +0000 (20:41 +0800)]
imx: thermal: update imx6 thermal driver according new equation

>From IC guys:
"
After a thorough accuracy study of the Temp sense circuit,
we found that with our current equation, an average part can
read 7 degrees lower than a known forced temperature.
We also found out that the standard variance was around 2C;
which is the tightest distribution that we could create.
We need to change the temp sense equation to center the average
part around the target temperature.
"

New equation:
Tmeas = (Nmeas - n1) / slope + t1 + offset
n1= fused room count
t1= 25
offset=3.580661
slope= 0.4148468 – 0.0015423*n1

According the new equation, update the thermal driver.
c1 and c2 changed to u64 type and update comments.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
7 years agoimx-common: timer: clean up
Peng Fan [Wed, 19 Apr 2017 09:05:55 +0000 (17:05 +0800)]
imx-common: timer: clean up

Drop the unneeded code. lib/time.c use timebase_l/h.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Stefano Babic <sbabic@denx.de>
7 years agomx25pdk: Add fuse API support
Fabio Estevam [Mon, 17 Apr 2017 22:29:05 +0000 (19:29 -0300)]
mx25pdk: Add fuse API support

Select CONFIG_FSL_IIM and CONFIG_CMD_FUSE so that the fuse API can
be used.

Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
7 years agonet: fec_mxc: specify the registered eth index by dev_id
Andy Duan [Mon, 10 Apr 2017 11:44:35 +0000 (19:44 +0800)]
net: fec_mxc: specify the registered eth index by dev_id

Specify the registered eth index by dev_id.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
7 years agonet: fec_mxc: avoid transfer dev_id -1 to get mac address from fuse
Andy Duan [Mon, 10 Apr 2017 11:44:34 +0000 (19:44 +0800)]
net: fec_mxc: avoid transfer dev_id -1 to get mac address from fuse

Avoid transfer parameter dev_id value with "-1" to .fec_get_hwaddr(),
it should transfer fec->dev_id to get mac address from fuse.

Signed-off-by: Fugang Duan <fugang.duan@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Stefano Babic <sbabic@denx.de>
7 years agonet: fec: do not access reserved register for i.MX6ULL
Peng Fan [Mon, 10 Apr 2017 11:44:33 +0000 (19:44 +0800)]
net: fec: do not access reserved register for i.MX6ULL

The MIB RAM and FIFO receive start register does not exist on
i.MX6ULL. Accessing these register will cause enet not work well or
cause system report fault.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
7 years agoMerge git://git.denx.de/u-boot-uniphier
Tom Rini [Wed, 17 May 2017 18:13:58 +0000 (14:13 -0400)]
Merge git://git.denx.de/u-boot-uniphier

- Add workaround code to make LD20 SoC boot from ARM Trusted Firmware
- Sync DT with Linux to fix DTC warnings
- Add new SoC support code
- Misc fix, updates

7 years agoMerge git://git.denx.de/u-boot-x86
Tom Rini [Wed, 17 May 2017 18:13:16 +0000 (14:13 -0400)]
Merge git://git.denx.de/u-boot-x86

7 years agoARM: uniphier: add more init code for PXs3
Masahiro Yamada [Mon, 15 May 2017 05:26:33 +0000 (14:26 +0900)]
ARM: uniphier: add more init code for PXs3

Add the boot device table and reset deassertion for eMMC.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: move kernel physical base to 0x82080000
Masahiro Yamada [Tue, 16 May 2017 05:35:15 +0000 (14:35 +0900)]
ARM: uniphier: move kernel physical base to 0x82080000

Reserve enough space below the kernel base.
The assumed address map is:
  80000000 - 80ffffff : for IPP
  81000000 - 81ffffff : for ARM secure
  82000000 -          : for Linux

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: dts: uniphier: sync DT with Linux
Masahiro Yamada [Mon, 15 May 2017 05:23:46 +0000 (14:23 +0900)]
ARM: dts: uniphier: sync DT with Linux

Fix the following DTC warnings:
Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/ethernet@00000000 simple-bus unit address format error, expected "0"
Warning (simple_bus_reg): Node /soc/system-bus@58c00000/support_card@1,1f00000/uart@000b0000 simple-bus unit address format error, expected "b0000"
Warning (simple_bus_reg): Node /soc/smpctrl@59800000 simple-bus unit address format error, expected "59801000"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: add weird workaround code for LD20
Masahiro Yamada [Fri, 12 May 2017 13:49:02 +0000 (22:49 +0900)]
ARM: uniphier: add weird workaround code for LD20

When booting from ARM Trusted Firmware, U-Boot runs in EL1-NS.
The boot flow is as follows:
  BL1 -> BL2 -> BL31 -> BL33 (i.e. U-Boot)

This boot sequence works fine for LD11 SoC (Cortex-A53), but LD20
SoC (Cortex-A72) hangs in U-Boot.  The solution I found is to
read sctlr_el1 and write back the value as-is.  This should be
no effect, but surprisingly fixes the problem for LD20 to boot.
I do not know why.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: add usbupdate command
Masahiro Yamada [Wed, 10 May 2017 11:57:39 +0000 (20:57 +0900)]
ARM: uniphier: add usbupdate command

This script command will be useful to update boot images in the
USB storage.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agoARM: uniphier: fix MODEL field of REVISION register
Masahiro Yamada [Tue, 9 May 2017 08:14:55 +0000 (17:14 +0900)]
ARM: uniphier: fix MODEL field of REVISION register

The MODEL field is 3 bit wide.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
7 years agox86: minnowmax: Remove incorrect pad-offset of several pins
Bin Meng [Mon, 8 May 2017 02:52:30 +0000 (19:52 -0700)]
x86: minnowmax: Remove incorrect pad-offset of several pins

Remove 'pad-offset' of soc_gpio_s5_0, soc_gpio_s5_1, soc_gpio_s5_2,
pin_usb_host_en0 and pin_usb_host_en1. These offsets are actually
wrong. Correct value should be added by 0x2000, but since they
are supposed to be 'mode-gpio', 'pad-offset' is not needed at all.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agox86: ich6_gpio: Add use-lvl-write-cache for I/O access mode
Bin Meng [Mon, 8 May 2017 02:52:29 +0000 (19:52 -0700)]
x86: ich6_gpio: Add use-lvl-write-cache for I/O access mode

Add a device-tree property use-lvl-write-cache that will cause
writes to lvl to be cached instead of read from lvl before each
write. This is required on some platforms that have the register
implemented as dual read/write (such as Baytrail).

Prior to this fix the blue USB port on the Minnowboard Max was
unusable since USB_HOST_EN0 was set high then immediately set
low when USB_HOST_EN1 was written.

This also resolves the 'gpio clear | set' command warning like:
  "Warning: value of pin is still 0"

Signed-off-by: George McCollister <george.mccollister@gmail.com>
<rebased on latest origin/master, fixed all baytrail boards>
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agospi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exit
Stefan Roese [Mon, 24 Apr 2017 07:48:04 +0000 (09:48 +0200)]
spi: ich: Configure SPI BIOS parameters for Linux upon U-Boot exit

This patch adds a remove function to the Intel ICH SPI driver, that will
be called upon U-Boot exit, directly before the OS (Linux) is started.
This function takes care of configuring the BIOS registers in the SPI
controller (similar to what a "standard" BIOS or coreboot does), so that
the Linux MTD device driver is able to correctly read/write to the SPI
NOR chip. Without this, the chip is not detected at all.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Jagan Teki <jteki@openedev.com>
7 years agox86: bootm: Add dm_remove_devices_flags() call to bootm_announce_and_cleanup()
Stefan Roese [Mon, 24 Apr 2017 07:48:03 +0000 (09:48 +0200)]
x86: bootm: Add dm_remove_devices_flags() call to bootm_announce_and_cleanup()

This patch adds a call to dm_remove_devices_flags() to
bootm_announce_and_cleanup() so that drivers that have one of the removal
flags set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may
do some last-stage cleanup before the OS is started.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agodm: core: Add DM_FLAG_OS_PREPARE flag
Stefan Roese [Mon, 24 Apr 2017 07:48:02 +0000 (09:48 +0200)]
dm: core: Add DM_FLAG_OS_PREPARE flag

This new flag can be added to DM device drivers, which need to do some
final configuration before U-Boot exits and the OS (e.g. Linux) is
started. The remove functions of those drivers will get called at
this stage to do these last-stage configuration steps.

Signed-off-by: Stefan Roese <sr@denx.de>
Reviewed-by: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
7 years agoserial: serial-uclass: Use force parameter in stdio_deregister_dev()
Stefan Roese [Mon, 24 Apr 2017 07:48:01 +0000 (09:48 +0200)]
serial: serial-uclass: Use force parameter in stdio_deregister_dev()

On my x86 platform I've noticed, that calling dm_uninit() or the new
function dm_remove_devices_flags() does not remove the desired device at
all. Debugging showed, that the serial uclass returns -EPERM in
serial_pre_remove(). This patch sets the force parameter when calling
stdio_deregister_dev() resulting in a removal of the device.

Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Simon Glass <sjg@chromium.org>
Cc: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
7 years agox86: Convert MMC to driver model
Simon Glass [Mon, 10 Apr 2017 00:38:21 +0000 (18:38 -0600)]
x86: Convert MMC to driver model

Convert the pci_mmc driver over to driver model and migrate all x86 boards
that use it.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Bin Meng <bmeng.cn@gmail.com>
7 years agox86: Document ACPI S3 support
Bin Meng [Fri, 21 Apr 2017 14:24:49 +0000 (07:24 -0700)]
x86: Document ACPI S3 support

Now that we have ACPI S3 support on Intel MinnowMax board, document
some generic information of S3 and how to test it.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: minnowmax: Enable ACPI S3 resume
Bin Meng [Fri, 21 Apr 2017 14:24:48 +0000 (07:24 -0700)]
x86: minnowmax: Enable ACPI S3 resume

This turns on ACPI S3 resume for minnowmax board.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: acpi: Fix Windows S3 resume failure
Bin Meng [Fri, 21 Apr 2017 14:24:47 +0000 (07:24 -0700)]
x86: acpi: Fix Windows S3 resume failure

U-Boot sets up the real mode interrupt handler stubs starting from
address 0x1000. In most cases, the first 640K (0x00000 - 0x9ffff)
system memory is reported as system RAM in E820 table to the OS.
(see install_e820_map() implementation for each platform). So OS
can use these memories whatever it wants.

If U-Boot is in an S3 resume path, care must be taken not to corrupt
these memorie otherwise OS data gets lost. Testing shows that, on
Microsoft Windows 10 on Intel Baytrail its wake up vector happens to
be installed at the same address 0x1000. While on Linux its wake up
vector does not overlap this memory range, but after resume kernel
checks low memory range per config option CONFIG_X86_RESERVE_LOW
which is 64K by default to see whether a memory corruption occurs
during the suspend/resume (it's harmless, but warnings are shown
in the kernel dmesg logs).

We cannot simply mark the these memory as reserved in E820 table
because such configuration makes GRUB complain: unable to allocate
real mode page. Hence we choose to back up these memories to the
place where we reserved on our stack for our S3 resume work.
Before jumping to OS wake up vector, we need restore the original
content there.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: pci: Allow conditionally run VGA rom in S3
Bin Meng [Fri, 21 Apr 2017 14:24:46 +0000 (07:24 -0700)]
x86: pci: Allow conditionally run VGA rom in S3

Introduce a new CONFIG_S3_VGA_ROM_RUN option so that U-Boot can
bypass executing VGA roms in S3.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: acpi: Turn on ACPI mode for S3
Bin Meng [Fri, 21 Apr 2017 14:24:45 +0000 (07:24 -0700)]
x86: acpi: Turn on ACPI mode for S3

Before jumping to OS waking up vector, we need turn on ACPI mode
for S3, just like what we do for a normal boot.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: acpi: Refactor acpi_resume()
Bin Meng [Fri, 21 Apr 2017 14:24:44 +0000 (07:24 -0700)]
x86: acpi: Refactor acpi_resume()

To do something more in acpi_resume() like turning on ACPI mode,
we need locate ACPI FADT table pointer first. But currently this
is done in acpi_find_wakeup_vector().

This changes acpi_resume() signature to accept ACPI FADT pointer
as the parameter. A new API acpi_find_fadt() is introduced, and
acpi_find_wakeup_vector() is updated to use FADT pointer as the
parameter as well.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: acpi: Make enter_acpi_mode() public
Bin Meng [Fri, 21 Apr 2017 14:24:43 +0000 (07:24 -0700)]
x86: acpi: Make enter_acpi_mode() public

enter_acpi_mode() is useful on other boot path like S3 resume, so
make it public.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>
7 years agox86: apci: Change PM1_CNT register access to RMW
Bin Meng [Fri, 21 Apr 2017 14:24:42 +0000 (07:24 -0700)]
x86: apci: Change PM1_CNT register access to RMW

In enter_acpi_mode() PM1_CNT register is changed to PM1_CNT_SCI_EN
directly without preserving its previous value. Update to change
the register access to read-modify-write (RMW).

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: Stefan Roese <sr@denx.de>