dri_interface: remove gl header

Only gl typedefs are used. So just remove the header and update the
types to the underlying types.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13387>

dri_interface: remove obsolete interfaces

Below are removed:
__DRI_FRAME_TRACKING
__DRI_TEX_OFFSET
__DRI_GET_DRAWABLE_INFO

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13387>

nir/serialize: Pack deref modes better

With nir_var_image, we've now run out of bits in our packed blob for
deref instructions.  We could revert to an unpacked blob or we could be
a bit more clever about how we encode deref modes and pack them into 5
bits.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13386>

nir: Re-arrange the variable modes

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13386>

nir: s/nir_var_mem_image/nir_var_image/g

We typically use nir_var_mem_* for stuff that has an explicit byte-based
memory layout.  Images are opaque.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13386>

meson: use gtest protocol for gtest based tests when possible

With the `gtest` protocol meson will add some extra arguments to the
test to generate better junit results, which may be useful. This
protocol is only available in meson 0.55.0+, so keep using the default
`exitcode` protocol for meson older than that.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8484>

microsoft/compiler: Shadow tex instructions always use shadow samplers

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13321>

aux/pb: more correctly check number of reclaims

the increment needs to happen before the comparison here

Fixes: 3d6c8829f54 ("aux/pb: add a tolerance for reclaim failure")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13388>

nir: Drop our attempt at typed-based image mode validation

This is broken for bindless images declared as local variables.  It
turns out nir_variable::data::bindless is only used for uniforms and we
already assume anything in nir_var_function_temp or similar is bindless.
We could try to make a tricky assert but now that we have everything
else passing but now that we've got everyone converted the extra
validation probably isn't necessary.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13384>

intel: fix INTEL_DEBUG environment variable on 32-bit systems

INTEL_DEBUG is defined (since 4015e1876a77162e3444eeaa29a0dfbc47efe90e) as:

 #define INTEL_DEBUG __builtin_expect(intel_debug, 0)

which unfortunately chops off upper 32 bits from intel_debug
on platforms where sizeof(long) != sizeof(uint64_t) because
__builtin_expect is defined only for the long type.

Fix this by changing the definition of INTEL_DEBUG to be function-like
macro with "flags" argument. New definition returns 0 or 1 when
any of the flags match.

Most of the changes in this commit were generated using:
for c in `git grep INTEL_DEBUG | grep "&" | grep -v i915 | awk -F: '{print $1}' | sort | uniq`; do
    perl -pi -e "s/INTEL_DEBUG & ([A-Z0-9a-z_]+)/INTEL_DBG(\1)/" $c
    perl -pi -e "s/INTEL_DEBUG & (\([A-Z0-9_ |]+\))/INTEL_DBG\1/" $c
done
but it didn't handle all cases and required minor cleanups (like removal
of round brackets which were not needed anymore).

Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13334>

virgl: remove unused pipebuffer include

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13385>

aux/pb: add a tolerance for reclaim failure

originally, a slab attempts to reclaim a single bo. there are two outcomes
to this which can occur:
* the bo is reclaimed
* the bo is not reclaimed

if the bo is reclaimed, great.

if the bo is not reclaimed, it remains at the head of the list until it can
be reclaimed. this means that any bo with a "long" work queue which makes it
into a slab will effectively kill the entire slab. in a benchmarking scenario,
this can occur in rapid succession, and every slab will get 1-2 suballocations
before it reaches a bo that blocks long enough for a new slab to be needed.

the inevitable result of this scenario is that all memory is depleted almost instantly,
all because pb assumes that if the first bo in the reclaim list isn't ready, none of them
can be ready

for drivers like radeonsi, this happens to be a fine assumption

for drivers like zink, this is entirely not workable and explodes the gpu

Cc: mesa-stable
Reviewed-by: Witold Baryluk <witold.baryluk@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Witold Baryluk <witold.baryluk@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13345>

intel/compiler: Build all tests in a single binary

With gtest is possible to filter execution and run only a specific
test suite or individual test, so there's no particular reason here to
generate multiple binaries for the tests of a single module.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13303>

intel/compiler: Rename vec4 test fixtures

Include vec4 in their names to avoid same names as the fs
counterparts.  This will allow compiling all the tests together in the
future.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13303>

freedreno/isa: Add immed reg accessors

This way we can assert that a src that we expect to be an immediate
actually is.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

isaspec: Add bitfield size assertions

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

isaspec: Do not emit duplicate field encodes

If an <override> overrides the definition of a field, don't emit
encoding for both the override's definition and the fallback.  (See
"SAMP" in #cat5-src3).  It is harmless currently, because (in this
case) it will just re-encode the low bits of "SAMP".  But when we
start asserting on that the field being encoded fits in the allowed
number of bits, the re-encoding of the fallback field definition
will start triggering asserts.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

isaspec: Fix derived field width

The low/high bit positions should be integers.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

freedreno/ir3: Don't lower s2en if samp/tex is too large

We only have four bits to encode an immediate samp/tex.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

freedreno/ir3/tests: Add additional disasm test vectors

Add branch with negative offset, and a couple others to trigger issues I
found while adding pack_field() overflow asserts.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

freedreno/ir3/tests: Fix indentation

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

freedreno/isa: Fixes for validation

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

freedreno/ir3+isa: Cleanup bindless cat5 samp/tex encoding

Don't let the way they are encoded at the isa level leak thru to the
ir3 level.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13353>

ir3: Images are always nir_var_mem_image

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

microsoft/clc: Images use nir_var_mem_image

The only big change is that lower_vars_to_explicit no longer assigns
a driver_location for images. That means that the storage for the
format/order loads is no longer implicitly "allocated" in the middle
of the kernel args. Instead, manually add the storage for that to the end
of the input args buffer.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir/gl_nir_lower_images: Require nir_var_mem_image

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

intel/fs: Stop emitting TGM fences for nir_var_mem_ssbo

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

aco: Split var_mem_image barrier handling from global/ssbo

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir: Validate image variable modes

We can also significantly simplify the foreach_image_variable helper.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

st/pbo: Use nir_var_mem_image for images

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

radv: Use nir_var_mem_image in meta shaders

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

ttn: Use nir_var_mem_image

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

glsl: Use nir_var_mem_image for images

We don't use it for bindless images because the uniforms in that case
just contain a bindless handle and aren't an actual image.  Bound
images, on the other hand, go in the nir_var_mem_image class.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

spirv: Use nir_var_mem_image

Use the new nir_var_mem_image mode for images that are not known to be
used with a sampler (i.e. storage images).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

spirv: Assert that OpTypeForwardPointer only points to structs

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

ir3: Check for nir_var_mem_image in shared_barrier handling

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

zink: Images can live in nir_var_mem_image now

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

clover: Use nir_foreach_image_variable for images

This splits image and sampler handling into two separate loops.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

clover: Insert dummy uniform variables for images

Instead of making images have a well-defined size, insert a dummy
variable of the appropriate type which we can use for the parameter
block layout.  This will work much better when we switch over to
nir_var_mem_image.

Acked-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir/lower_readonly_images_to_tex: Also rewrite variable modes

Storage images will start using nir_var_mem_image but sampled images
still use nir_var_uniform.  If we're going to rewrite types, we need to
rewrite the modes as well.  Otherwise, nir_validate will get grumpy and
drivers might get confused.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

llvmpipe: Support image variables living in nir_var_mem_image

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

ntt: Separate image and sampler handling

Use nir_foreach_image_variable for images so we survive the coming
refactor where they get their own mode.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

st/nir: Assign uniform locations to nir_var_mem_image vars

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir/gl_nir_lower_images: Support nir_var_mem_image

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir/gl_nir_lower_samplers_as_deref: Support nir_var_mem_image

Contrary to the name of the pass, it also handles storage images so we
need to support nir_var_mem_image.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

glsl/nir_linker: nir_var_mem_image is also a GL uniform

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

aco: Add support for nir_var_mem_image

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

amd/llvm/nir: Add support for nir_var_mem_image

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

anv: Use nir_foreach_image_variable

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

i965/uniforms: Handle images as a separate pass

Instead of walking all uniforms and handling images as a special case,
walk "normal" uniforms first and images as a second pass.  This lets us
use nir_foreach_image_variable which will survive the upcoming refactor.
While we're at it, use nir_foreach_image_variable in
brw_nir_lower_gl_images too.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

intel/fs: Consider nir_var_mem_image for TGM fences

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir: Add a nir_foreach_image_variable() iterator

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir: Add nir_var_mem_image

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

nir/schedule: Handle nir_intrisic_scoped_barrier

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4743>

freedreno: Fix for large epilogues

Apparently Rocket League overflows the fixed size epilogue.  Switch it
to be growable.

Closes: #5493
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13365>

v3dv: enable VK_KHR_swapchain_mutable_format

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13297>

aco: do not return an empty string when disassembly is not supported

Fixes dEQP-VK.pipeline.executable_properties.* on GFX6-7 when
clrxdisasm isn't found. Other generations are also affected if RADV
is built without LLVM.

Cc: 21.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tony Wasserka <tony.wasserka@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13333>

iris: fix scratch address patching for TESS_EVAL stage

Scratch patching code in iris_upload_dirty_render_state (see MERGE_SCRATCH_ADDR
calls) assumes that in all shader stages derived_data field stores 3DSTATE_XS
packet first.

This is not true for TESS_EVAL (DS), so we end up patching 3DSTATE_TE
instead of 3DSTATE_DS leading to DWordLength becoming 11 instead of 9
(9 == 3DSTATE_DS.DWordLength, 2 == 3DSTATE_TE.DWordLength, and 9|2 == 11),
and hardware hanging on the next instruction.

Fix this by reversing the order of packets for TESS_EVAL stage.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5499

Fixes: 4256f7ed584 ("iris: Fill out scratch base address dynamically")
Signed-off-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13358>

crocus: Delete the MI_COPY_MEM_MEM resource_copy_region implementation.

(ported from iris - airlied)

The MI_COPY_MEM_MEM version of resource_copy_region has known bugs:

    It's failing to set valid_buffer_range correctly
    It's missing iris_emit_buffer_barrier_for() for the source/destination, so there may be missing flushes.
    There are some bad interactions with the tile cache and VF using L3.

Even with those fixed, if you expand the "no more than 16 bytes" restriction to allow copies up to 1024 bytes, then it starts failing Piglit tests on Icelake.

We could probably fix this. However, I had originally only measured a 0.689096% +/- 0.473968% (n=4) speedup in Shadow of Mordor's OpenGL port, which is already fairly small, especially before adding missing flushes. Further, some of that likely came from not switching between render and compute...which we'll soon be able to avoid thanks to BLOCS.

Folks were also worried that MI_COPY_MEM_MEM can't be pipelined, and that stalling the command streamer may actually slow things down, especially as the GPUs become more powerful. We aren't really sure about this, but it's another concern.

So, let's just get rid of this optimization. It seemed like a good idea at the time, but it's just causing issues for very little gain.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13374>

egl: set TSD as NULL after deinit

When eglReleaseThread() is called from application's
destructor (API with __attribute__((destructor))),
it crashes due to invalid memory access.

In this case, _egl_TLS is freed in the flow of
_eglAtExit() as below but _egl_TLS is not set to NULL.

    _eglDestroyThreadInfo
        _eglFiniTSD
            _eglAtExit
                _run_exit_handlers
                    exit

Later when the eglReleaseThread is called from
application's destructor, it ends-up accessing
the freed _egl_TLS pointer.

    eglReleaseThread -> in libEGL_mesa
        eglReleaseThread -> in libEGL(glvnd)
            destructor() -> App's destructor

To resolve the invalid access, setting the _egl_TLS
pointer as NULL after freeing it.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5466
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13302>

v3dv: implement VK_EXT_host_query_reset

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13319>

i965: Emit a NULL surface for buffer textures with no buffer

This is a preexisting bug but it was uncovered by 231653ea3506
("intel/isl: Add a max_buffer_size limit to isl_device") which added an
assert(num_elements > 0) for typed buffers.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13351>

zink: Do not access just freed zink_batch_state

Cc: mesa-stable
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13370>

anv: don't advertise vk conformance on GPUs that aren't conformant

This sets the conformance version to 0.0.0.0 for GPUs that have
incomplete support for vulkan, so that it's easier to check if vulkan is
fully supported by a GPU at runtime for applications/libraries.

    $ vulkaninfo|grep conf
    MESA-INTEL: warning: Ivy Bridge Vulkan support is incomplete
        conformanceVersion = 0.0.0.0

Signed-off-by: Clayton Craft <clayton@craftyguy.net>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13275>

docs: update calendar and link releases notes for 21.2.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13369>

docs: add sha256 sum for 21.2.4 release

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13369>

docs: add release notes for 21.2.4

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13369>

docs: update calendar for 21.3.0-rc1

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13368>

ir3/freedreno: account for component in build_tessfactor_base

The burden was put on the caller, which caused:
- Reading of tess levels back in TCS not accounting for component
- Reading patch outputs in TES account for component twice

Fixes vkd3d tests:
- test_tessellation_read_tesslevel
- test_tessellation_primitive_id
- test_line_tessellation_dxbc

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13338>

loader: Avoid enumerating drm devices just to get an fd's PCI ID.

Cuts 1/3 of the runtime of the VA-API unit tests (which do a separate
pipe-loader init per test) on radeonsi on my system by not faffing around
in sysfs so much.

Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13324>

vulkan/wsi/win32: Delete the wrapper entrypoints

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13352>

nir/print: print bindless info as applicable

this is useful to know

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13204>

vulkan/log: Don't assert on non-client-visible objects

We already have code to deal with non-client-visible objects but we were
asserting if it didn't fall into one of the clearly mappable error
cases.  However, we didn't have a mapping for VK_ERROR_NOT_PERMITTED
which can happen during object creation.  Let's just be sloppy and drop
the assert.  Worst case, the client gets an error with no object.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13341>

vulkan/log: Tweak our handling of a couple error enums

VK_ERROR_INITIALIZATION_FAILED can happen as part of device creation and
isn't really an instance error in that case.
VK_ERROR_EXTENSION_NOT_PRESENT, on the other hand, is always an instance
thing and we should handle it as such.

Fixes: 0cad3beb2a0d ("vulkan/log: Add common vk_error and vk_errorf helpers")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13341>

vulkan: Set unused entrypoints to vk_entrypoint_stub when compiling with MSVC

If we don't do that we hit the assert(entry[i] != NULL) added by commit
6d44b21d4fd ("vulkan: Fix weak symbol emulation when compiling with MSVC").

Fixes: 6d44b21d4fd ("vulkan: Fix weak symbol emulation when compiling with MSVC")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13355>

radv: Fix modifier property query.

radv_get_modifier_flags read the format properties, doesn't write any. Setting
the central format properties based on the drm format properties doesn't make
any sense.

Fixes: 5dee0d9da96 "radv: switch to VK_FORMAT_FEATURE_2_XXX/VkFormatProperties3KHR"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5498
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13357>

v3dv: fix TLB buffer to image copy path for 3D images

Another instance of not taking the Z offset from the right place. We had
not seen this one until now because we typically use the TFU path, where
we also fixed this same issue in commit df1d08533c4.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13356>

vulkan: Fix weak symbol emulation when compiling with MSVC

Mapping unimplemented entrypoints to a global function pointer variable
initialized to NULL is a bit cumbersome, and actually led to a bug
in the vk_xxx_dispatch_table_from_entrypoints() template: the !override
case didn't have the right check on the source table entries. Instead of
fixing that case, let's simplify the logic by creating a stub function
and making the alternatename pragma point to this stub. This way we get
rid of all those uneeded xxx_Null symbols/variables and simplify the
tests in vk_xxxx_dispatch_table_from_entrypoints().

Cc: mesa-stable
Fixes: 98c622a96e28 ("vulkan: Update dispatch table gen for Windows")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13348>

nir/loop_unroll: Always unroll loops that iterate at most once

Two carchase compute shaders (shader-db) and two Fallout 4 fragment
shaders (fossil-db) were helped.  Based on the NIR of the shaders, all
four had structures like

    for (i = 0; i < 1; i++) {
        ...

for (...) {
            ...
}
    }

All HSW+ platforms had similar results. (Ice Lake shown)
total loops in shared programs: 6033 -> 6031 (-0.03%)
loops in affected programs: 4 -> 2 (-50.00%)
helped: 2
HURT: 0

All Intel platforms had similar results. (Ice Lake shown)
Instructions in all programs: 143692018 -> 143692006 (-0.0%)
SENDs in all programs: 6947154 -> 6947154 (+0.0%)
Loops in all programs: 38285 -> 38283 (-0.0%)
Cycles in all programs: 8434822225 -> 8434476815 (-0.0%)
Spills in all programs: 191665 -> 191665 (+0.0%)
Fills in all programs: 298822 -> 298822 (+0.0%)

In the presense of loop unrolling like this, the change in cycles is not
accurate.

v2: Rearrange the logic in the if-condition to read a little better.
Suggested by Tim.

Closes: #5089
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13323>

brw/nir: remove unused function prototypes.

These got moved into common code a good while ago.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13328>

anv: Enable tessellation redistribution

This patch adds Tessellation Distribution on top of Geometry
Distribution. Using recommended values based on performance studies
across a range of workloads.

Rework:
- Add comment for new packet bits (Sagar)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>

iris: Enable tessellation redistribution

This patch adds Tessellation Distribution on top of Geometry
Distribution. Using recommended values based on performance studies
across a range of workloads.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>

anv: Enable geometry distribution

Using recommended values based on performance studies across a range
of workloads.

Rework:
 * Always enable geometry distribution
 * Set ListCutIndexEnable if primitive restart is enabled
 * Set distribution mode based on TEEnable
 * Add comment explaining the 3DSTATE_VFG bits (Sagar)

v2:
- Emit 3DSTATE_VFG dynamically based on primitive restart (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>

iris: Enable geometry distribution

Using recommended values based on performance studies across a range
of workloads.

Rework:
 * Always enable geometry distribution
 * Set ListCutIndexEnable if primitive restart is enabled
 * Set distribution mode based on TEEnable

v2:
- Flag missing IRIS_DIRTY_VFG bit (Ken)

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>

genxml/gen125: Update 3DSTATE_TE fields

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>

intel/genxml: Update genxml to support tessellation/geometry distribution

Rework:
- Fix 3DSTATE_VFG opcode (Lionel)
- Fix distribution mode values (Sagar)
- Update 3DSTATE_VFG fields (Anuj)

Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12091>

ci/lvp: Skip some slow tests under ASan.

depending on the runner's load, we might see timeouts.  The
subgroupbroadcast one has hit us a couple times this week.

Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13346>

v3d/clif: add support for dumping GS shader state

The basic vertex+fragment shader state uses the packet
GL_SHADER_STATE, but when geometry shader are involved, the packet
used is GL_SHADER_STATE_INCLUDING_GS.

Without this commit any program using a geometry shader would dump
their shader state (and their shader state record and attribues) as
binaries.

Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13269>

v3dv/pipeline: don't clone the nir shader at pipeline_state_create_binning

At that point we didn't call all the v3dv lowerings. So the reference
nir shader used to call the v3d compiler could be different.

Note that at that point the nir shader is only available for internal
shaders (like gs multiview).

This specifically affected multiview tests that wrote gl_PointSize, as
the nir shader for the geometry shader were wrongly exposing
per_vertex_point_size as false, as we were basing our check on the
nir_shader_info, and that was gathered calling nir_shader_gather_info
at pipeline_lower_nir.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13325>

VERSION: bump to 22.0

I mistakenly bumped it from 21.3 to 21.4, but there is no 4 (:

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13347>

docs: reset new_features.txt

Signed-off-by: Eric Engestrom <eric@engestrom.ch>

VERSION: bump to 21.4

Signed-off-by: Eric Engestrom <eric@engestrom.ch>

iris: Require a 4K alignment for extra clear color BOs.

Apparently, we've been requiring a 4K alignment for internally allocated
clear color addresses to work around some unknown issues.  There's a
comment to that effect in iris_resource_create_with_modifiers().

When importing a dmabuf and tacking on an additional clear color BO, we
only required an alignment of 1.  This wasn't a problem for a long time
because all BO allocations were naturally aligned to the 4K page size.

However, once we enabled suballocation, we were able to allocate "BOs"
at 256B granularity, making this no longer 4K aligned.  Increase the
alignment requirement to 4K to match the behavior of our normal
allocations and also our previous behavior.

Fixes Piglit's ext_image_dma_buf_import-intel-modifiers.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5482
Fixes: ce2e2296ab6 ("iris: Suballocate BO using the Gallium pb_slab mechanism")
Reviewed-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13326>

intel/compiler: Remove unused `ret` declaration

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>

intel/compiler: Convert test_eu_compact to use gtest

Be consistent with the other test suites in intel/compiler.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13340>

radv: move alpha_adjust into conditional during vertex input updating

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>

radv: add a mask of bound descriptor buffers for dynamic vertex input

unnecessarily dereferencing the vertex buffer info array here causes a
ton of cpu overhead due to bad cache locality, so just use a mask to
avoid loading X more cachelines into memory unnecessarily

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>

radv: pre-calc "simple" dynamic vertex input values

when the shader pipeline is known to not require any of the more complex
calculations, those calculations can be excluded from the dynamic update
code

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>

radv: dynamically calculate misaligned_mask for dynamic vertex input

this avoids incurring overhead at draw time, instead shifting it to vertex
binding commands

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>

radv: don't use invalid stride for triggering vertex state change

NULL here means this was regular CmdBindVertexBuffers, so the stride
cannot be used

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13320>