Dave Airlie [Fri, 25 Aug 2023 02:43:44 +0000 (12:43 +1000)]
clover/llvm: move to modern pass manager.
This seems like it should work, but I haven't tested it yet.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24879>
Erico Nunes [Sun, 3 Sep 2023 21:45:01 +0000 (23:45 +0200)]
lima: fix plbu block stride calculation
For some specific texture sizes, notably some texture sizes with width
4096, block stride calculation could end up calculating stride 256 which
is an invalid value.
In those specific cases, this could cause rendering artifacts or
application/driver crashes.
Cc: mesa-stable
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25084>
Konstantin Seurer [Fri, 8 Sep 2023 06:47:00 +0000 (08:47 +0200)]
radv/rt: Enable monolithic pipelines
Store can_inline inside the stages to avoid rerunning the analysis pass
for library stages.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>
Konstantin Seurer [Mon, 21 Aug 2023 11:32:53 +0000 (13:32 +0200)]
radv/rt: Add monolithic raygen lowering
Ray traversal is inlined to allow for constant folding and avoid
spilling.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>
Konstantin Seurer [Sat, 24 Jun 2023 13:46:51 +0000 (15:46 +0200)]
radv/rt: Store NIR shaders separately
In order to compile monolithic shaders with pipeline libraries, we need
to keep the NIR around for inlining recursive stages.
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21929>
Mike Blumenkrantz [Tue, 5 Sep 2023 16:37:29 +0000 (12:37 -0400)]
nir/inline_uniforms: fix oob access with nir_find_inlinable_uniforms
the array dimensionality needs to match nir_add_inlinable_uniforms even if
only the first member is used
Fixes:
0c0fb216dd6 ("nir/inline_uniforms: Allow possibility of more than one UBO")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25063>
Mike Blumenkrantz [Thu, 10 Aug 2023 14:05:36 +0000 (10:05 -0400)]
zink: delete all psiz=1.0 stores if maintenance5 is present
this frees up an output location woooo
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24782>
Mike Blumenkrantz [Thu, 10 Aug 2023 13:53:01 +0000 (09:53 -0400)]
zink: slightly refactor psiz deletion during linking
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24782>
Eric Engestrom [Fri, 8 Sep 2023 08:54:32 +0000 (09:54 +0100)]
Revert "ci: taking igalia farm offline"
This reverts commit
a69ffbd08a44032d0f12c5739382cefc8a5d7f50.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25136>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:09:47 +0000 (11:09 -0400)]
zink: use HIC for image subdata when possible
this has a lot of caveats:
* extension must be supported
* resource must have usage bit set
* resource must not have any pending batch usage
* resource must be in supported layout
if all of these conditionals pass, then HIC can be used for direct image subdata
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:08:59 +0000 (11:08 -0400)]
zink: check/use suboptimal HIC during ici init
this allows implicit use of HIC where possible while rejecting it when
it would cause performance loss
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Mon, 21 Aug 2023 13:30:17 +0000 (09:30 -0400)]
zink: use some return codes for check_ici errors
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Mon, 21 Aug 2023 13:24:27 +0000 (09:24 -0400)]
zink: fix some off-by-one indentation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:06:49 +0000 (11:06 -0400)]
zink: add a fixup method for extra driver props
some extensions have "extra" props which need the get_count -> get_prop_array
dance, and codegen is too stupid to figure this out (and probably always will be)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 25 Aug 2023 16:55:43 +0000 (12:55 -0400)]
zink: disable HIC without resizable BAR
this otherwise ooms the system
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 25 Aug 2023 16:54:19 +0000 (12:54 -0400)]
zink: move mem type detection up in file
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 15:04:30 +0000 (11:04 -0400)]
zink: hook up VK_EXT_host_image_copy
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Wed, 23 Aug 2023 20:02:08 +0000 (16:02 -0400)]
lavapipe: don't advertise UNDEFINED layout for HIC
this is illegal
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 14:07:37 +0000 (10:07 -0400)]
lavapipe: handle VkHostImageCopyDevicePerformanceQueryEXT
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Fri, 18 Aug 2023 13:39:58 +0000 (09:39 -0400)]
zink: use VkFormatProperties3
but wrap it in a smaller type to save some space
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Wed, 16 Aug 2023 10:58:22 +0000 (06:58 -0400)]
zink: simplify redundant is_buffer check
it's in the params
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24775>
Mike Blumenkrantz [Tue, 29 Aug 2023 11:23:21 +0000 (07:23 -0400)]
ci: bump VVL to 1.3.263
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24925>
Jordan Justen [Wed, 6 Sep 2023 06:26:22 +0000 (23:26 -0700)]
intel/dev: Update device string for MTL PCI ID 0x7d55
Ref: bspec 55420
Cc: mesa-stable
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Acked-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25073>
Faith Ekstrand [Fri, 8 Sep 2023 23:18:52 +0000 (18:18 -0500)]
nvk: Invalidate the texture cache in PipelineBarrier
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>
Faith Ekstrand [Fri, 8 Sep 2023 23:05:01 +0000 (18:05 -0500)]
nvk: Set the discard bit for Z/S self-deps
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>
Faith Ekstrand [Fri, 8 Sep 2023 22:29:47 +0000 (17:29 -0500)]
nvk: Don't add a dummy attachment when gl_SampleMask is written
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25135>
Ian Romanick [Thu, 18 May 2023 22:14:16 +0000 (15:14 -0700)]
intel/compiler: Don't evict for workgroup-scope fences
Flushing and invalidating caches isn't necessary for workgroup scope
fences. In fact, the DP_FLUSH_TYPE docs (BSpec 54041) say:
"If the fence scope is Local or Threadgroup, HW ignores the flush
type and operates as if it was set to None(no flush)"
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Ian Romanick [Tue, 16 May 2023 19:21:52 +0000 (12:21 -0700)]
intel/compiler: Combine control barriers with identical memory semantics
This prevents the second barrier generating a spurious, identical fence
message as the first barrier.
fossil-db stats on Alchemist:
Totals:
Instrs:
196513342 ->
196512777 (-0.00%); split: -0.00%, +0.00%
Cycles:
14271426028 ->
14271404569 (-0.00%); split: -0.00%, +0.00%
Send messages: 8021892 -> 8021770 (-0.00%)
Totals from 46 (0.01% of 653252) affected shaders:
Instrs: 76761 -> 76196 (-0.74%); split: -0.75%, +0.01%
Cycles: 2027946 -> 2006487 (-1.06%); split: -1.45%, +0.39%
Send messages: 7589 -> 7467 (-1.61%)
Nothing in shader-db was affected.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 17:40:40 +0000 (10:40 -0700)]
anv: Use nir_opt_barrier_modes() to drop unnecessary barriers
fossil-db stats on Alchemist:
Totals:
Instrs:
196514947 ->
196513342 (-0.00%); split: -0.00%, +0.00%
Cycles:
14271450761 ->
14271426028 (-0.00%); split: -0.00%, +0.00%
Send messages: 8022316 -> 8021892 (-0.01%)
Totals from 43 (0.01% of 653252) affected shaders:
Instrs: 98558 -> 96953 (-1.63%); split: -1.63%, +0.00%
Cycles:
15867801 ->
15843068 (-0.16%); split: -0.17%, +0.02%
Send messages: 8997 -> 8573 (-4.71%)
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 17:38:55 +0000 (10:38 -0700)]
glsl: Use nir_opt_barrier_modes() to drop unnecessary barriers
iris shader-db stats on Alchemist:
total instructions in shared programs:
23150249 ->
23142733 (-0.03%)
instructions in affected programs: 157322 -> 149806 (-4.78%)
helped: 105
HURT: 2
helped stats (abs) min: 2 max: 821 x̄: 71.61 x̃: 15
helped stats (rel) min: 0.13% max: 27.56% x̄: 6.21% x̃: 2.35%
HURT stats (abs) min: 1 max: 2 x̄: 1.50 x̃: 1
HURT stats (rel) min: 0.18% max: 0.23% x̄: 0.20% x̃: 0.20%
95% mean confidence interval for instructions value: -101.99 -38.50
95% mean confidence interval for instructions %-change: -7.59% -4.58%
Instructions are helped.
total sends in shared programs: 1036916 -> 1035366 (-0.15%)
sends in affected programs: 15274 -> 13724 (-10.15%)
helped: 108 / HURT: 0
helped stats (abs) min: 1 max: 162 x̄: 14.35 x̃: 3
helped stats (rel) min: 0.88% max: 33.83% x̄: 9.81% x̃: 5.05%
95% mean confidence interval for sends value: -20.79 -7.92
95% mean confidence interval for sends %-change: -11.66% -7.95%
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Fri, 8 Sep 2023 23:17:30 +0000 (16:17 -0700)]
dxil: Set UAV_FENCE_THREAD_GROUP any time global isn't required
With the new nir_opt_barrier_modes() pass, we may encounter control
barriers with no memory modes set, such as:
@barrier () (execution_scope=WORKGROUP, memory_scope=WORKGROUP, mem_semantics=ACQ|REL, mem_modes=0)
The DXIL validator documentation [1] mentions an
INSTR.BARRIERMODENOMEMORY validation rule:
"sync must include some form of memory barrier - _u (UAV) and/or
_g (Thread Group Shared Memory). Only _t (thread group sync) is
optional."
We were generating a dx.op.barrier instruction with only one flag,
DXIL_BARRIER_MODE_SYNC_THREAD_GROUP. This seems to run afoul of the
above validator rule. So, this patch adjusts the code generator to
set DXIL_BARRIER_MODE_UAV_FENCE_THREAD_GROUP too, whenever
UAV_FENCE_GLOBAL isn't required.
[1] https://github.com/microsoft/DirectXShaderCompiler/blob/main/docs/DXIL.rst
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Wed, 6 Sep 2023 22:38:58 +0000 (15:38 -0700)]
virgl, nir_to_tgsi: Add a hack for promoting partial memory barriers
Most drivers will want nir_opt_barrier_modes() to optimize out
unnecessary memory barrier modes. However, virgl has to translate
back to GLSL, which means it can really only handle partial memory
barriers in compute shaders today, because there isn't a proper
way to express them otherwise. Just ask nir_to_tgsi to promote
these back to full barriers as a workaround.
See KHR-GL43.shader_storage_buffer_object.advanced-readWrite-case1
on virpipe-on-gl as a case where this hack is needed.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Thu, 31 Aug 2023 22:29:54 +0000 (15:29 -0700)]
lavapipe: Don't delete control barriers
Control barriers still need to do synchronization even if there are no
associated memory barrier modes.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 01:55:13 +0000 (18:55 -0700)]
nir: Reduce the scope of shared memory barriers
Originally written by Ian Romanick for the Intel backend, but ported
to the new nir_opt_barrier_modes() common optimization pass. Ian's
original explanation and commit message follows:
Shared memory only exists within a workgroup, so synchronizing it beyond
workgroup scope is nonsense.
Basically every SPIR-V compiler generates operations like
OpMemoryBarrier(/*Memory*/Device,
/*Semantics*/AcquireRelease | WorkgroupMemory)
This is suggested in numerous places, including
https://github.com/KhronosGroup/GLSL/blob/master/extensions/khr/GL_KHR_vulkan_glsl.txt.
Even Mesa's glsl_to_nir pass does this. This advice, which has been
copy-and-pasted everywhere, is contrary to issue 13 in the original
GL_ARB_compute_shader spec:
"Since shared memory is only accessible to threads within a single
work group, memoryBarrierShared() also only requires synchronization
with other threads in the same work group."
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Tue, 22 Aug 2023 01:53:20 +0000 (18:53 -0700)]
nir: Add an optimization pass to reduce barrier modes
Many shaders issue full memory barriers, which may need to synchronize
access to images, SSBOs, shared local memory, or global memory.
However, many of them only use a subset of those memory types - say,
only SSBOs.
Shaders may also have patterns such as:
1. shared local memory access
2. barrier with full variable modes
3. more shared local memory access
4. image access
In this case, the barrier is needed to ensure synchronization between
the various shared memory operations. Image reads and writes do also
exist, but they are all on one side of the barrier, so it is a no-op for
image access. We can drop the image mode from the barrier here too.
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Kenneth Graunke [Mon, 21 Aug 2023 19:44:20 +0000 (12:44 -0700)]
nir: Fix function parameter indentation in nir_opt_barriers.c
The first parameter should be on the first line, and any subsequent
lines should line up.
Acked-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24842>
Mike Blumenkrantz [Tue, 29 Aug 2023 15:20:27 +0000 (11:20 -0400)]
zink: re-rework i/o variable handling to make having variables entirely optional
old variables are now only used for copying names if possible, which should
make it possible for zink to process shaders which have no variables at all
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Fri, 8 Sep 2023 17:12:26 +0000 (13:12 -0400)]
zink: use right function to get src_type in eliminate_io_wrmasks
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Thu, 7 Sep 2023 16:46:01 +0000 (12:46 -0400)]
zink: add a new linker pass to handle mismatched i/o components
this is the inverted version of rewrite_read_as_0 which tests for mismatched
component i/o on a given location and rewrites the inputs to zero if the
producer shader didn't write to the component
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 15:20:02 +0000 (11:20 -0400)]
zink: create new vars without copying existing ones
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Wed, 30 Aug 2023 15:55:05 +0000 (11:55 -0400)]
zink: use explicit sizing for builtins when creating variables
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 15:14:02 +0000 (11:14 -0400)]
zink: use MAX_PATCH_VERTICES directly for arrayed io var sizing
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 14:54:39 +0000 (10:54 -0400)]
zink: use explicit stride from types instead of copying old_var stride
should be no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 14:54:15 +0000 (10:54 -0400)]
zink: simplify an arrayed io check during variable creation
no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:52:40 +0000 (09:52 -0400)]
zink: use nir_io_semantics::num_slots for indirect var creation
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:49:58 +0000 (09:49 -0400)]
zink: delete some bindless io lowering code
now that variables are pre-converted this is no longer necessary
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:47:46 +0000 (09:47 -0400)]
zink: fix typing on bindless io lowering
with lowered io this should always be an ivec2
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:47:30 +0000 (09:47 -0400)]
zink: reorder bindless io lowering
should be no functional changes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Tue, 29 Aug 2023 13:41:36 +0000 (09:41 -0400)]
zink: set is_xfb=false for all i/o variables
this can affect streamout generation, even though it so far hasn't
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24950>
Mike Blumenkrantz [Fri, 8 Sep 2023 23:12:13 +0000 (19:12 -0400)]
zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 17:27:32 +0000 (13:27 -0400)]
zink: handle multi-plane implicit sync
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:55:30 +0000 (12:55 -0400)]
zink: handle implicit sync for dmabufs
this adds explicit queue transitions to FOREIGN at the end of the batch
for all written-to dmabufs, then also adds signal/wait semaphores
using the dmabuf fds
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:52:07 +0000 (12:52 -0400)]
zink: hook up cached fd semaphore usage for batch signal/waits
not yet used, matches handling of normal semaphores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:13:33 +0000 (16:13 -0400)]
zink: add a util for getting cached fd semaphores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:09:54 +0000 (16:09 -0400)]
zink: add a screen cache for fd semaphores
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:07:02 +0000 (16:07 -0400)]
zink: add another submitinfo for fd semaphore waits
these are semaphores created with VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
and can't be cached with the others
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 30 Aug 2023 20:05:31 +0000 (16:05 -0400)]
zink: make submitinfo handling easier to manage with enum
this was starting to get hard to read
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:54:39 +0000 (12:54 -0400)]
zink: add a third submitinfo (unused for now)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:53:32 +0000 (12:53 -0400)]
zink: make zink_resource_image_barrier2_init public
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Mike Blumenkrantz [Wed, 16 Aug 2023 16:52:55 +0000 (12:52 -0400)]
zink: use a pointer to simplify submit struct mechanics
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24962>
Yiwei Zhang [Fri, 8 Sep 2023 18:55:48 +0000 (11:55 -0700)]
venus: expose KHR_external_fence/sempahore_fd extensions
Re-purpose renderer has_external_sync to cover explicit sync emulation
in venus, so that we don't have to add a new flag to distinguish the
emulation path enablement for virtgpu and vtest.
This is to unblock zink implicit sync hanlding against venus for now,
and soon we should migrate to virtgpu fence passing.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25127>
Eric Engestrom [Tue, 11 Jul 2023 19:38:00 +0000 (20:38 +0100)]
ci: drop clover leftover
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24098>
Marek Olšák [Mon, 4 Sep 2023 17:27:09 +0000 (13:27 -0400)]
meson: use llvm-config instead of cmake to fix linking errors with meson 1.2.1
The cmake path picks a random LLVM in /usr, which happens to be 32-bit LLVM,
which fails to link with 64-bit Mesa. This is a meson, cmake, or LLVM bug.
Acked-by: Dylan Baker <dylan@pnwbakers.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25042>
Sagar Ghuge [Fri, 4 Aug 2023 21:09:40 +0000 (14:09 -0700)]
anv: Program and emit STATE_COMPUTE_MODE
Don't rely on the HW to set values correctly so just emit
STATE_COMPUTE_MODE with default values set to zero.
Also, this change includes workaround changes:-
-
14015808183 (Parent HSD
14015782607) - Need to emit pipe control
with HDC flush and untyped cache flush set to 1 when CCS has
non-pipelined state update with STATE_COMPUTE_MODE.
-
14014427904 (Parent HSD
22013045878) - We need additional
invalidate/flush when emitting non-pipelined state commands with
multiple CCS enabled.
v2: (Tapani)
- Use lineage HSD numbers for check
- Don't use poisoned WA directly
- Use intel_needs_workaround helper
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>
Sagar Ghuge [Fri, 4 Aug 2023 21:09:22 +0000 (14:09 -0700)]
intel/genxml: Add STATE_COMPUTE_MODE instruction
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24508>
Sagar Ghuge [Fri, 8 Sep 2023 06:42:31 +0000 (23:42 -0700)]
iris: Enable always flush cache with DEBUG_STALL option
With DEBUG_STALL option, enable always cache flush option for debugging
purpose that aligns with anv.
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25108>
Konstantin Seurer [Sat, 2 Sep 2023 20:33:58 +0000 (22:33 +0200)]
radv: Don't use the depth image view for depth bias emission
If the application records a secondary command buffer that inherits
a render pass without specifying a framebuffer, we should still be able
to emit the depth bias state properly.
Fixes: 266b2cf ("radv: implement VK_EXT_depth_bias_control")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9588
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25018>
Tatsuyuki Ishi [Mon, 21 Aug 2023 05:49:29 +0000 (14:49 +0900)]
radv/amdgpu: Use rwlock to protect access to virtual BOs.
Vulkan provides no external synchronization guarantees on sparse memory
objects. Use a per-BO rwlock to prevent reading data mid-update.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24806>
Lionel Landwerlin [Wed, 30 Aug 2023 10:37:33 +0000 (13:37 +0300)]
anv: bound image usages to the associated queue family
When applying barriers for image transitions, we're currently
considering all possible usages of an image. But when running on a
compute only queue for example, the usage of an image will never be
one of those :
- VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
- VK_IMAGE_USAGE_DEPTH_STENCIL_ATTACHMENT_BIT
- VK_IMAGE_USAGE_TRANSIENT_ATTACHMENT_BIT
- VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
- VK_IMAGE_USAGE_FRAGMENT_SHADING_RATE_ATTACHMENT_BIT_KHR
Removing unused usages for the compute queue allows us to reduce the
scope of the VK_IMAGE_LAYOUT_GENERAL for example. This a bunch of
transition operation that are completely useless when dealing with
barriers on the compute queue.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25092>
Eric Engestrom [Fri, 8 Sep 2023 08:58:30 +0000 (09:58 +0100)]
ci/b2c: drop logic to remove install.tar
It's still buggy, and it turns out `mcli` has some logic to check if
a file really needs to be re-uploaded, so this doesn't actually change
much to the time uploads take.
This effectively reverts https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24196
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25114>
Lionel Landwerlin [Thu, 7 Sep 2023 14:24:12 +0000 (17:24 +0300)]
anv: remove aux checking asserts
Zink is running into those asserts on CI. The problem is that with non
auxilary modifiers like I915_FORMAT_MOD_Y_TILED, we might still
allocate larger buffers with IMPLICIT_CCS.
This isn't a complete fix, the real fix with come with
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25003 where
we stop overallocating and those assert will match the private binding
allocation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
569f80f2df ("anv: Reduce accesses of isl_mod_info->aux_usage")
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25099>
Samuel Pitoiset [Fri, 8 Sep 2023 06:29:38 +0000 (08:29 +0200)]
radv: remove useless PIPELINE_CREATE_2_LIBRARY_BIT check for retained shaders
VK_PIPELINE_CREATE_2_RETAIN_LINK_TIME_OPTIMIZATION_INFO_BIT_EXT is only
allowed for pipeline libs, so VK_PIPELINE_CREATE_2_LIBRARY_BIT_KHR
should also be set.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25110>
David Rosca [Thu, 7 Sep 2023 19:11:47 +0000 (21:11 +0200)]
frontends/va: Flush after unmapping VAImageBufferType
If application changed image data we need to flush on unmap to make the
changes visible. This will also flush if the mapping was used only for
reading, but we can't know that as vaMapBuffer doesn't have a parameter
to specify if read or write is requested.
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9774
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25102>
Georg Lehmann [Sat, 2 Sep 2023 15:55:57 +0000 (17:55 +0200)]
nir/opt_algebraic: remove broken fddx/fddy patterns
These patterns are broken in the following scenario:
%1 = f2fmp %0
%2 = fddx %1
%3 = ... // non quad uniform
if %3 {
%4 = f2f32 %2
...
}
Which would turn into
%3 = ...
if %3 {
%4 = fddx %0
...
}
Yet another example that shows why derivative instructions should be
be intrinsics, not alu.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25014>
Dave Airlie [Fri, 8 Sep 2023 01:59:53 +0000 (11:59 +1000)]
llvmpipe: enable f16 paths on aarch64.
Karol noticed luxmark didn't work, and this seems to fix it.
Cc: mesa-stable
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25104>
Samuel Pitoiset [Fri, 8 Sep 2023 09:42:13 +0000 (11:42 +0200)]
radv: do not use pre-compiled prologs when VS is compiled separately
This wouldn't work for VS+TCS or VS+GS if they are compiled separately
on GFX9+.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>
Samuel Pitoiset [Fri, 8 Sep 2023 09:41:45 +0000 (11:41 +0200)]
radv: adjust emitted prolog regs for merged shaders compiled separately
It should also be the merged shader stage.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>
Samuel Pitoiset [Fri, 8 Sep 2023 09:41:18 +0000 (11:41 +0200)]
radv: adjust next stage for VS prologs and merged shaders compiled separately
It should be the merged shader stage.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24933>
Georg Lehmann [Sat, 5 Aug 2023 17:02:53 +0000 (19:02 +0200)]
aco/gfx11: don't use bfe for local_invocation_id if the others are always 0
Foz-DB GFX1100:
Totals from 4469 (3.37% of 132657) affected shaders:
Instrs: 3895053 -> 3893529 (-0.04%); split: -0.04%, +0.00%
CodeSize:
20244128 ->
20220952 (-0.11%); split: -0.11%, +0.00%
Latency:
37864147 ->
37862227 (-0.01%); split: -0.01%, +0.00%
InvThroughput: 5578100 -> 5576469 (-0.03%); split: -0.03%, +0.00%
SClause: 108336 -> 108343 (+0.01%); split: -0.00%, +0.01%
Copies: 275897 -> 275900 (+0.00%); split: -0.00%, +0.00%
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24514>
Danylo Piliaiev [Thu, 7 Sep 2023 14:34:29 +0000 (16:34 +0200)]
tu: Call tu_cs_dbg_stomp_regs with appropriate GPU gen
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25098>
Danylo Piliaiev [Thu, 7 Sep 2023 14:33:58 +0000 (16:33 +0200)]
tu: Exclude SP_UNKNOWN_AE73 from reg stomping
There is a guess that GPU may not be able to handle different values of
certain debug register between BR/BV. This one causes GPU to hang.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25098>
Pierre-Eric Pelloux-Prayer [Fri, 18 Aug 2023 09:58:27 +0000 (11:58 +0200)]
radv/sdma: use correct limits for gfx10.3
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>
Pierre-Eric Pelloux-Prayer [Fri, 18 Aug 2023 09:57:27 +0000 (11:57 +0200)]
radv/sdma: use multiple commands if required
Instead of failing the copy we can use multiple chunks.
This codepath shouldn't really be used since the source
image should usually be tiled but it still better to not
fail when possible.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>
Pierre-Eric Pelloux-Prayer [Fri, 18 Aug 2023 09:53:34 +0000 (11:53 +0200)]
radeonsi/sdma: use multiple commands if required
Instead of failing the copy we can use multiple chunks.
This codepath shouldn't really be used since the source
image should usually be tiled but it still better to not
fail when possible.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24771>
Eric Engestrom [Fri, 8 Sep 2023 08:37:52 +0000 (09:37 +0100)]
ci: taking igalia farm offline
We're having internet issues, everything is extremely slow.
Timothy Arceri [Wed, 6 Sep 2023 04:04:39 +0000 (14:04 +1000)]
nir: remove unused param from nir_alu_src_copy()
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>
Timothy Arceri [Wed, 6 Sep 2023 04:01:00 +0000 (14:01 +1000)]
nir: remove unused nir_src_copy()
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>
Timothy Arceri [Wed, 6 Sep 2023 03:56:09 +0000 (13:56 +1000)]
nir: replace use of nir_src_copy()
Since
03b2c34793b6 nir_src_copy() no longer does anything useful,
it will be removed in the following patch.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24986>
Mike Blumenkrantz [Wed, 6 Sep 2023 19:46:23 +0000 (15:46 -0400)]
zink: always add a per-prog ref for gpl libs
previously non-separable progs had their libs owned exclusively by
the shaders, which meant it was possible for a background compile job
to crash while the context was being destroyed when accessing libs
which no longer had active shaders
fixes #9234
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25088>
Bas Nieuwenhuizen [Tue, 5 Sep 2023 01:23:50 +0000 (03:23 +0200)]
radv: Use a double jump to limit nops in DGC for dynamic sequence count.
Some RGP data showing that a large amount of NOPs might be a performance
concern.
Some data from a Granite demo repurposed as benchmark:
- with max_count = 16, actual draw count 1-4, the new path is ~5% slower
- with max_count = 2048, actual draw count 1-4, the new path is >2x as fast.
- with max_count = 16384, actual draw count 1-4, the new path is >7x as fast.
Due to the new path being slower in e.g. small cmdbuffers I added a heuristic.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25046>
David Heidelberg [Thu, 7 Sep 2023 13:39:33 +0000 (19:09 +0530)]
ci/traces: extend no-output timeout by 5 minutes
This should help us handling possibly slower downloads of the traces,
which leads into piglit not printing anything on the output.
After Infra will get stabilized again, needs to be reverted.
Acked-by: Helen Koike <helen.koike@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25097>
Samuel Pitoiset [Tue, 5 Sep 2023 14:23:56 +0000 (16:23 +0200)]
radv: avoid emitting THREAD_TRACE_MARKER for predicated draws/dispatches
This confused RGP for example when DGC calls are skipped.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25060>
Samuel Pitoiset [Tue, 5 Sep 2023 13:03:06 +0000 (15:03 +0200)]
radv: skip DGC calls when the indirect sequence count is zero with a predicate
Starfield has a lot of empty ExecuteIndirect() calls. This optimizes
them by using the indirect sequence count as predicate.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25060>
Martin Roukala (né Peres) [Thu, 7 Sep 2023 10:27:56 +0000 (13:27 +0300)]
radv/ci: use the default kernel on vkcts-navi10
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7888
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25095>
Martin Roukala (né Peres) [Thu, 7 Sep 2023 10:53:39 +0000 (13:53 +0300)]
radv/ci: drop the auto-reboot-on-hang for vkcts-navi10
Anecdotal evidence seems to suggest this is not happening anymore, so
let's try dropping it and see how it fares!
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25095>
Danylo Piliaiev [Thu, 7 Sep 2023 11:33:30 +0000 (13:33 +0200)]
ir3/lower_tex_prefetch: Fix crash with lowered load_barycentric_at_offset
ir3_nir_lower_tex_prefetch expects src0 of load_interpolated_input to
be intrinsic, however this assumption broke when src0 is
load_barycentric_at_offset and is lowered in series of alu instructions.
32x2 %1121 = @load_barycentric_at_offset (%1120) (interp_mode=0)
32x4 %1118 = @load_interpolated_input (%1121, %1116 (0x0)) ...
32x2 %32 = vec2 %1118.x, %1118.y
32x4 %37 = (float32)tex %36 (texture_handle), %34 (sampler_handle), %32 (coord), 0 (texture), 0 (sampler)
is lowered into:
[...]
32 %54 = ffma %46.y, %52, %50
32 %55 = ffma %46.y, %53, %51
32x2 %56 = vec2 %54, %55
32x4 %57 = @load_interpolated_input (%56, %25 (0x0))
[...]
Crash backtrace:
#5 in __GI___assert_fail (assertion=0x7ff6692328 "parent && parent->type == nir_instr_type_intrinsic",
file=0x7ff66921c8 "nir.h", line=2536, function=0x7ff6692630 <__PRETTY_FUNCTION__.13> "nir_instr_as_intrinsic")
at assert.c:101
#6 in nir_instr_as_intrinsic (parent=0x7fd4b648e8) at nir.h:2536
#7 in coord_offset (ssa=0x7fd4b649d0) at ir3_nir_lower_tex_prefetch.c:77
#8 in coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:48
#9 in ir3_nir_coord_offset (ssa=0x7fd4b64a90) at ir3_nir_lower_tex_prefetch.c:104
#10 in lower_tex_prefetch_block (block=0x7fd482c100) at ir3_nir_lower_tex_prefetch.c:185
#11 in lower_tex_prefetch_func (impl=0x7fd4aa0890) at ir3_nir_lower_tex_prefetch.c:218
#12 in ir3_nir_lower_tex_prefetch (shader=0x7fd4942b10) at ir3_nir_lower_tex_prefetch.c:242
Cc: mesa-stable
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25096>
Iago Toral Quiroga [Thu, 7 Sep 2023 07:30:29 +0000 (09:30 +0200)]
v3dv: bump up MAX_UNIFORM_BUFFERS to 16
We currently expose 12 but that becomes 11 when running on Zink
since Mesa's state tracker is aware that the first one is reserved
for its own constant buffer, and the minimum number of UBOs required
by GL is 12, so Zink won't be able to expose UBO support.
Bump it up to 16 to meet Zink requirements, which is what we offer
on V3D.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9764
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25093>
Tatsuyuki Ishi [Wed, 6 Sep 2023 12:51:44 +0000 (21:51 +0900)]
radv: Fix dumping vertex descriptors with RADV_DEBUG=hang.
Adding 3 words should be done before the uint32_t ** cast. This is in
line with other places which uses pointer arithmetic on trace_id_ptr.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25081>
Vlad Schiller [Mon, 7 Aug 2023 14:06:15 +0000 (15:06 +0100)]
pvr: Add VK_KHR_driver_properties
This commit will implement the VK_KHR_driver_properties extension.
At the moment, the extension is disabled, because the current conformance
test version does not include the Imagination driver ID. The extension
can be enabled after conformance test version 1.3.6.0.
Co-Authored-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Matt Coster <matt.coster@imgtec.com>
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24927>
Lionel Landwerlin [Thu, 31 Aug 2023 06:23:38 +0000 (09:23 +0300)]
pps-producer: add ability to select device with DRI_PRIME
When running with multiple Intel cards in a system, having the ability
to select the device recording performance data is useful.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25051>