anv: Work around the spec question about pipeline feedback vs GPL.

This gives anv the same behavior as turnip in not asserting, and just not
filling out feedback for those stages.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: Refactor repeated pipeline creation feedback output code.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: Only enable GPL if ANV_GPL=true, or if zink or DXVK are the engine.

Since there are concerns that the VK_EXT_GPL implementation may have
issues with mesh shading, disable it by default but give users a knob to
turn it on to experiment.

This doesn't automatically enable GPL use in zink, because we lack
extendedDynamicState2PatchControlPoints, but it means that you only need
to set ZINK_DEBUG=gpl and not both env vars.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: implement VK_EXT_graphics_pipeline_library

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: add dynamic buffer offsets support with independent sets

With independent sets, we're not able to compute immediate values for
the index at which to read anv_push_constants::dynamic_offsets to get
the offset of a dynamic buffer. This is because the pipeline layout
may not have all the descriptor set layouts when we compile the
shader.

To solve that issue, we insert a layer of indirection.

This reworks the dynamic buffer offset storage with a 2D array in
anv_cmd_pipeline_state :

   dynamic_offsets[MAX_SETS][MAX_DYN_BUFFERS]

When the pipeline or the dynamic buffer offsets are updated, we
flatten that array into the
anv_push_constants::dynamic_offsets[MAX_DYN_BUFFERS] array.

For shaders compiled with independent sets, the bottom 6 bits of
element X in anv_push_constants::desc_sets[] is used to specify the
base offsets into the anv_push_constants::dynamic_offsets[] for the
set X.

The computation in the shader is now something like :

  base_dyn_buffer_set_idx = anv_push_constants::desc_sets[set_idx] & 0x3f
  dyn_buffer_offset = anv_push_constants::dynamic_offsets[base_dyn_buffer_set_idx + dynamic_buffer_idx]

It was suggested by Faith to use a different push constant buffer with
dynamic_offsets prepared for each stage when using independent sets
instead, but it feels easier to understand this way. And there is some
room for optimization if you are set X and that you know all the sets in
the range [0, X], then you can still avoid the indirection. Separate
push constant allocations per stage do have a CPU cost.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: move preprocessing of NIR right before compilation

For graphics pipelines, we'll need to load NIR for retained shaders.
We want to avoid as much processing as possible while doing that when
we're able to load ISA from cache.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: make input attachments available through bindless

With independent sets, we cannot bake into the shader the binding
table entry of input attachments anymore because that final location
is affected by multiple sets.

We can still access them by looking into the descriptor buffer. This
change enables the image handle to be stored in the descriptor buffer.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: move force shading rate writes checks

With variable fragment shading rate, the last pre-rasterization stage
is responsible to write the shading rate value.

The current checks is as follow :

   If the fragment shader can be dispatched at variable shading rate,
   look for the last pre-raster stage to force the write.

We change this to :

   If we're the last pre-raster stage, force the write.

That way this works for pre-rasterization shaders compiled without a
fragment shader.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

anv: introduce a base graphics pipeline object

Pipeline libraries and linked pipelines will inherit from this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

isl: don't set inconsistent fields for depth when using stencil only

Since Gfx12+ 3DSTATE_STENCIL_BUFFER gained its own
Width/Depth/Format/etc... fields. So don't set those fields but leave
the address/pitch to 0.

Issue found on simulation.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15637>

frontend/va: Add VAProfileH264High10

Acked-by: Ruijing Dong <ruijing.dong@amd.com>
Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22539>

d3d12: Support PIPE_VIDEO_CAP_ENC_QUALITY_LEVEL

Only return we support 1 quality level. The point of returning this
cap is that vlVaEndPicture will check for it and otherwise overwrite
some rate control parameters with defaults

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

d3d12: Support PIPE_VIDEO_CAP_MIN_WIDTH/HEIGHT caps

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

d3d12: Support QPMin/QPMax app params

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

d3d12: Support rate control HRD and MaxFrameSize app params

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

d3d12: Support QVBR rate control mode

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

frontend/va: Allow distinction for Min/MaxQP params sent from app and frontend defaults

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

frontend/va: Allow distinction for HRD params sent from app and frontend defaults

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

frontend/va: Support QVBR rate control mode

Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22530>

lima: fix refcnt imbalance related to framebuffer

Indeed, the current framebuffer hardcoded cleanup
is not sufficient.

For instance, this issue is triggered with:
"piglit/bin/fbo-depthstencil clear default_fb -samples=2 -auto"
while setting GALLIUM_REFCNT_LOG=refcnt.log.

cc: mesa-stable

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Reviewed-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22234>

build: Add Iris and ANV to ARM's auto-generated drivers

Xe KMD supports ARM CPUs, so we are now able to have Intel discrete
GPUs with ARM CPUs working.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22476>

iris: Fix vm bind of imported bos from other GPUs

The imported buffer may be created in a device with different
memory alignment and this can cause vm bind to fail because bo
size is smaller than vm bind range aligned.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22476>

iris: Implement batch_submit() in Xe kmd backend

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22476>

iris/bufmgr: Handle flat_ccs for BO_ALLOC_ZEROED

We can't map the CCS memory region. So, rely on the kernel's zeroing of
new allocations. This is helpful when creating dmabufs that use
compression.

Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22487>

iris/bufmgr: Add and use zero_bo

This simplifies the next patch.

Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22487>

iris: Allocate ZEROED BOs for shared resources

A port of cbee2d1102c ("i965/screen: Allocate ZEROED BOs for images").

Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22487>

lima/ci: temporarily disable deqp-egl tests due to timeouts

A regression causing these tests to become unstable was introduced while
lima CI was disabled in the last days. It seems to be caused by the
latest kernel bump, but still needs more investigation.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22531>

d3d12: Do not fail d3d12_screen creation if D3D12_FEATURE_D3D12_OPTIONS14 not available

Fixes: 52ee566bc550b4822c4a563e480e869b8228917b ("d3d12: Query device for D3D12_FEATURE_D3D12_OPTIONS14")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22534>

radeonsi: create a new context for transcode with multiple video engines

For CHIP_GFX1100, there are 2 VCN instances but using unified queue i.e.
decode and encode will go to HW via same ring type. With AMDGPU kernel
scheduler, since the trancode is sharing the same pipe context, so that
the gpu scheduler assign the decode and encode into the same VCN engine.
In order to use both engines with transcode case, the new pipe context will
be created when the case being detected, with that the transcode can be
load balanced with multiple VCN engines.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22471>

intel/common: Add gt_id to intel_engine_class

MTL and newer platforms on Xe kmd will have engines with gt_id != 0.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22477>

iris: Fix close of exported bos

On commit 910e659e31cb ("iris: Add function to close gem bos") I used
iris_bo_close() to close exported bos with the wrong drm_fd.
Causing piglit ext_image_dma_buf_import.ext_image_dma_buf_import*
tests to crash during tear-down.

So here adding iris_bufmgr_bo_close() that will close bos that belongs
to bufmgr->fd and changing the parameters of iris_bo_close() to close
the bo of given fd.

Fixes: 910e659e31cb ("iris: Add function to close gem bos")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8836
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22501>

vulkan/overlay: deal with unknown pNext structures

To implement some of the features of the layer, we need to enable some
of the feature bits at device/command_buffer creation. To do so, we
need to edit some of the structures coming from the application. Most
of those are const so we need to clone them before edition.

This change disables some of the layer features if we run into a
situation where one of the structure we need to clone is unknown such
that we can't make a copy of it (since we don't know its size).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7677
Cc: mesa-stable
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19897>

lima: fix stringop-overflow warning

New versions of gcc output a warning about this code, apparently
because of the mix of signed and unsigned operations in the loop
condition. Rework the types to fix the warning.

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22129>

r600: fix refcnt imbalance related to evergreen_set_shader_images()

Indeed, the reference was overwritten.

For instance, this issue is triggered with:
"piglit/bin/shader_runner tests/spec/arb_shader_image_load_store/execution/write-to-rendered-image.shader_test -auto -fbo"
while setting GALLIUM_REFCNT_LOG=refcnt.log.

Fixes: a6b379284365 ("r600: add core pieces of image support.")
Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22394>

r600: Report multi-plane formats as unsupported

This is the analogous of
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9490 but for
r600.

Discoloration of NV12 video frames was observed in Chrome/ChromeOS and
the problem was tracked down to the fact that Mesa was following the
PIPE_FORMAT_R8_G8B8_420_UNORM/lower_yuv_external() path. The symptom is
that (for an unknown reason) the YUV-to-RGB conversion is using the
value of Y as the value of Y, U, and V. So, for example, if the input
value is YUV = (50, 120, 130), then what actually gets converted to RGB
is YUV = (50, 50, 50).

Considering that PIPE_FORMAT_R8_G8B8_420_UNORM was introduced for
freedreno
(https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6693) and it
is already being reported as unsupported for radeonsi, it's reasonable
to assume that GPUs targeted by r600 don't support this path either.

Note: I tested this patch with an AMD Palm device which follows the
evergreen_is_format_supported() path. I did not have access to a device
to test the r600_is_format_supported() path.

v2: Changed >= 2 to > 1.

Fixes: 826a10255f5 ("st/mesa: Add NV12 lowering to PIPE_FORMAT_R8_G8B8_420_UNORM")
Tested-by: Andres Calderon Jaramillo <andrescj@chromium.org>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22511>

egl/wayland: fix oob buffer access during buffer_fds clean up

After iterating through the number of planes in the above for
loop i is more than the number of planes which corresponds to
the size of the buffer_fds array.

Fixes: 967b9ad084e ("egl/wayland: for prime, allocate linear_copy from display GPU VRAM")
Signed-off-by: David Redondo <kde@david-redondo.de>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22496>

radv: disable fast-clears with CMASK for 128-bit formats

This isn't supported according to RadeonSI.

This fixes a piglit test with Zink that uses a R32G32B32A32_SINT format
with MSAA 8x. This is because DCC fast-clears with MSAA require to
clear CMASK too.

Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7313
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22462>

radeonsi: remove separate_prolog parameter

si_get_ps_prolog_key is only called by part mode shader now.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

radeonsi: restructure mono merged shader build

No function change, just refine to share more code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

radeonsi: monolithic ps emit prolog in nir directly

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

radeonsi: handle lowered ps in scan_io_usage

si_update_shader_binary_info() will call into this function
to collect memory usage info after shader has been lowered
finally. To avoid assertion failure in nir_instr_as_intrinsic()
we have to check instruction type first.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

radeonsi: add si_nir_emit_polygon_stipple

Ported from si_llvm_emit_polygon_stipple().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

radeonsi: add si_nir_lower_ps_color_input

For lowering legacy color inputs in PS.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

ac/llvm,radeonsi: lower ps color load in nir

Remove the color0/1 in ac_shader_abi which is used by
radeonsi only.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

ac/nir/ps: lower sample mask input when needed

Ported from si_llvm_build_ps_prolog().

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

ac/nir/ps: add force lower barycentric load options

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

ac/nir/ps: lower barycentric load when bc_optimize

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

radeonsi: implement nir_load_barycentric_optimize_amd

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

nir: add nir_load_barycentric_optimize_amd intrinsic

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21683>

zink: make general bo allocation more robust by iterating

previously there was a fallback path here (broken by f6d3a5755f6)
which would attempt to demote BAR allocations to other heaps on failure
to avoid oom

this was great, but it's not the most robust solution, which is to iterate
all the memory types matching the given heap and try them in addition to having
a demotion fallback

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22479>

zink: restore BAR allocation failure demotion

this restores the fallback used when BAR allocation fails due to oom
by re-selecting memoryTypeIndex after the heap demotion

Fixes: f6d3a5755f6 ("zink: zink_heap isn't 1-to-1 with memoryTypeIndex")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22479>

zink: slightly rework memoryTypeIndex selection to pre-determine heap

should be no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22479>

zink: move memoryTypeIndex selection down in general bo allocation

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22479>

Revert "ci: disable lima farm, currently out-of-space, needs to be fixed"

This reverts commit 78644c9bb0d3b7920f7676c6388b472510a54f0b.

Fixes: 78644c9bb0d3b7920f76 ("ci: disable lima farm, currently out-of-space, needs to be fixed")

Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22513>

v3dv/ci: drop fixed failure from fails.txt

Fixes: 8976d8280ff45cd7f947 ("wsi: remove get_sorted_vk_formats duplication")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22514>

ci: uninstall libdrm from the GL and VK containers

Occasionally causing troubles on -valve jobs.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

ci: polish deqp-runner a bit

Plus cosmetics adjustments to pass more of shellcheck.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

ci/freedreno: fix the a530_piglit job and switch to Weston

If we count devices which running a530 with mainline kernel and Mesa,
it's probably mostly phones and tablets running on Wayland. Adapt to it.

Fixes: 83c2b26acf1e ("ci/freedreno: Switch the piglit job to using a deqp-runner suite.")

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

ci/freedreno: update a530 flakes, fails and skips

Add multiple skips for the:
 - KHR-GLES31.core.pixelstoragemodes.teximage2d
 - KHR-GLES31.core.pixelstoragemodes.teximage3d

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8837

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

ci/freedreno: a530 behaves stable in 6.3

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

ci: drop overriding new a530 firmware due to preemption issues with older kernel

Fixes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8825

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

ci/freedreno: do not restrict to 2 cpus on a530

Not needed for modern kernels (6.3+ for sure).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

ci: bump kernel to the 6.3, support HDK 888 based on sm8350

 - uprev to kernel 6.3-rc6
 - add sm8350 support (needed for HDK 888)
 - add missing patch for Asurada functionality
 - enable CONFIG_ARM_SMMU_QCOM, since we dropped specific patch
   worarounding need for it

Acked-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22255>

tu/perfetto: s/MRTs/attachment_count/ in traces.

MRTs usually means >1 color buffers, so seeing "2" is surprising when
you're expecing just color and depth.  Makes the output look more Vulkan.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22278>

tu/perfetto: Drop unused arg to send_descriptors().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22278>

tu/perfetto: Use tu_CmdBeginDebugUtilsLabelEXT as a stage event in perfetto.

This lets zink mark points of interest (particularly its barriers and
blits) with some useful data, for presenting in perfetto traces.

Closes: #8487
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22278>

tu/perfetto: Clean up an extra token paste to just use the arg being passed.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22278>

tu/perfetto: Refactor code out of the macro, to stage_end.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22278>

rusticl/event: drop work item before updating status

This fixes some CTS compiler tests where they relied on the cl_kernel
object to be released in time so it can recompile a program without
throwing CL_INVALID_OPERATION due to still having active kernel objects.

Fixes: 47a80d7ff4f ("rusticl/event: proper eventing support")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22510>

symbol_table: Prehash the key on insert, and reuse the entry on shadowing.

Mostly saves computing the hash twice, but while we're here there's no
need for shadowing to walk the table again.

Release Mesa build runtime of
KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive -4.19869%
+/- 3.20231%

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22451>

symbol_table: Don't bother resetting the key on popping scope.

If you made a same-name symbol, then its name was just the name from the
parent scope anyway.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22451>

symbol_table: Don't maintain the HT as we're destroying the table.

Release Mesa build runtime of
KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive -5.05801%
+/- 3.41206% (n=12)

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22451>

symbol_table: Store the symbol name in the same allocation as the symbol entry.

Saves an extra malloc.  Release Mesa build runtime of
KHR-Single-GL46.arrays_of_arrays_gl.SizedDeclarationsPrimitive (which is a
lot of GLSL 4.60 builtin vars symbol table setup) -5.15821% +/- 3.19636%
(n=13).

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22451>

ci/amd: update checksums after DXVK 2.1 update

Heaven got fixed with DXVK 2.1.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22447>

ci/dxvk: uprev to 2.1

Major uprev, requires VK 1.3 now.

Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22447>

ci/amd: 4/5 runners TPad-C13 runners are online, restore most of the tests

Partial revert of 590959057c2b ("ci/amd: raven is currently downgraded
to 2 machines only, adapt")

Test which remains disabled: radeonsi-raven-va:amd64 (VAAPI testing).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22447>

anv: enable blorp query reset for performance queries

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22480>

ci: Drop executable permissions from backend compiler wrapper script

Not needed anymore, since the frontend scripts just source the backend
script now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22438>

ci: Remove shebang from backend compiler wrapper script

Not needed anymore, since the frontend scripts just source the backend
script now.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22438>

ci: Use set -e in frontend compiler wrapper scripts.

I doubt the shebang line in the backend script has any effect now,
since the frontend scripts just source it directly.

v2:
* Use "set -e" instead of adding -e to shebang (Eric Engestrom)

v3:
* Apply to the clang wrapper scripts as well (Eric Engestrom)

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22438>

ci: Explicitly test for meson feature checks in compiler wrapper

The previous indirect method was more complicated and still error prone.

v2:
* Use "grep -E" (Eric Engestrom)
* Exclude spaces and slashes in the grep pattern, to avoid accidentally
  matching across unrelated compiler arguments.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22438>

util: Delete Offset() macro from u_memory.h

Reviewed-by: Giancarlo Devich <gdevich@microsoft.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22494>

spirv/tests: Add test for single-block loop

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22509>

dzn: Remove #if D3D12_SDK_VERSION blocks now that 610 is required

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22504>

microsoft/clc: Remove #if D3D12_SDK_VERSION blocks now that 610 is required

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22504>

d3d12: Remove #if D3D12_SDK_VERSION blocks now that 610 is required

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22504>

meson: keep Mako version checking in accord with build msg

Fixes: 52194ae4df1 ("meson: Ensure that mako is >= 0.8.0")
Signed-off-by: Luc Ma <luc@sietium.com>
Reported-by: Terry Zhang <terry@sietium.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22499>

radeonsi/vcn: engage all jpeg engines on gfx940 for mjpeg decode

engage all available jpeg engines to decode mjpeg video frames

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22388>

radeonsi/vcn: enable RGBP format on gfx940 jpeg

decode output format conversion to RGBP is supported on gfx940 jpeg.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22388>

frontends/va: add support for RGBP rt_format

check and enable RGBP rt_format and support VaImage creation for the RGBP/ARGB.

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22388>

util/format: add planar3 r8_g8_b8_unorm pipe format

add pipe format to represent three plane 8bit RGB format

Signed-off-by: Sathishkumar S <sathishkumar.sundararaju@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22388>

docs: add INTEL_MEASURE=cpu

Update documentation about INTEL_MEASURE=cpu

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

iris: Enable INTEL_MEASURE=cpu

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

anv: Enable INTEL_MEASURE=cpu

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

intel: INTEL_MEASURE cpu mode

INTEL_MEASURE normally measures timing of GPU events. However, it
is sometimes useful to instead measure when these gfx API calls
were requested of the driver. INTEL_MEASURE cpu can be used in
in conjunction with other driver debug capabilities, like
INTEL_DEBUG=pc for analyzing stalls/flushes or when debugger is
attached, to track which frame you're currently on or where in
the frame you're at.

Initial commit, without plumbing into anv/iris.

"INTEL_MEASURE=cpu" will collect a cpu timestamp for each
INTEL_MEASURE event instead of GPU timestamps.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

anv: split INTEL_MEASURE multi events

Measure performance of each draw separately in multi_draw event.
Previously, we measured duration of the sum of all draws launched
per multi_draw. This should provide more detailed data for
multi_draws.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

anv: Add flush reason to NEEDS_END_OF_PIPE_SYNC

cs_stall gets inserted if both flushes and invalidates are required.
This cs_stall reason was not called out explicitly, until now.

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

anv: Add flush reasons to raytracing flushes

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

anv: Add END_OF_PIPE_SYNC reporting to INTEL_DEBUG=pc

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21505>

radeonsi/vcn: add an exception of field case for h264 decoding

This is an error case where the I field has no reference, however
the reference list contains some reference, which resulting in
not be able to find its reference, and it is a correct behavior,
should not enter the correction code. Just add this exception to
prevent such a case, if more exceptions found, they will
be treated indiviually in the future.

Cc: mesa-stable
closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8740

Signed-off-by: Ruijing Dong <ruijing.dong@amd.com>
Signed-off-by: David (Ming Qiang) Wu <David.Wu3@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22485>