Rhys Perry [Mon, 7 Dec 2020 13:36:22 +0000 (13:36 +0000)]
nir: add sparse_residency_code_and
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Wed, 25 Nov 2020 17:07:20 +0000 (17:07 +0000)]
nir,spirv: implement SpvOpImageSparseTexelsResident
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Fri, 20 Nov 2020 16:14:26 +0000 (16:14 +0000)]
nir,spirv: add sparse image loads
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Fri, 20 Nov 2020 15:10:42 +0000 (15:10 +0000)]
nir,spirv: add sparse texture fetches
Like SPIR-V and GL_ARB_sparse_texture2, these return a residency code. It
is placed in the destination after the rest of the result. If it's zero,
then the texel is resident. Otherwise, it's not resident.
Besides the larger destination and the residency code, sparse fetches
work the same as normal fetches.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Mon, 23 Nov 2020 13:05:58 +0000 (13:05 +0000)]
nir: allow 5 component vectors
These will be useful for sparse texture instructions and image load
intrinsics.
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Rhys Perry [Fri, 13 Mar 2020 16:09:06 +0000 (16:09 +0000)]
nir/tests: fix callback for load/store vectorizer tests
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
Daniel Schürmann [Wed, 6 Jan 2021 18:06:51 +0000 (19:06 +0100)]
nir/opt_vectorize: fix call to filter function
Due to the typo, it could happen that instructions
got further vectorized than intended.
Fixes:
8eaf9c61d17370d3f272ca39256de58231c02127 ('nir/opt_vectorize: don't hash filtered instructions')
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8352>
Vinson Lee [Fri, 1 Jan 2021 02:29:04 +0000 (18:29 -0800)]
freedreno/afuc: Replace readfile with os_read_file.
Tested afuc-disasm produced same output.
$ ./builddir/src/freedreno/afuc/afuc-disasm -g 6 src/freedreno/.gitlab-ci/reference/afuc_test.fw > /tmp/afuc_test.asm
$ diff ./src/freedreno/.gitlab-ci/reference/afuc_test.asm /tmp/afuc_test.asm
$ echo $?
0
Suggested-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8290>
Dylan Baker [Tue, 1 Dec 2020 21:07:56 +0000 (13:07 -0800)]
bin/remove get-pick-list.sh files
These haven't been used for a long time, they've been supersceeded by
pick-ui
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7863>
Dylan Baker [Tue, 1 Dec 2020 21:06:04 +0000 (13:06 -0800)]
pick-ui: don't handle the mouse
It's annoying, since it prevents linux "midle click" copy-n-paste
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7863>
Erik Faye-Lund [Mon, 4 Jan 2021 09:35:36 +0000 (10:35 +0100)]
gallium/util: do not perform n^2 stencil blits
We already loop n times here, no point in doing n instances as well.
Fixes:
e8a40715a8b ("gallium/util: add blitter-support for stencil-fallback")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8301>
Rob Clark [Tue, 5 Jan 2021 20:38:02 +0000 (12:38 -0800)]
freedreno/ir3/parser: Fix pre-a6xx stib parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 5 Jan 2021 20:28:53 +0000 (12:28 -0800)]
freedreno/ir3/parser: a6xx ldib/stib parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 5 Jan 2021 19:39:26 +0000 (11:39 -0800)]
freedreno/ir3: Fix pre-a6xx ldgb/stib parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 5 Jan 2021 18:47:08 +0000 (10:47 -0800)]
freedreno/ir3: Explicitly flag disasm test vectors that don't parse
Mark the test cases which aren't supported by ir3_parser.y explicitly,
so we notice future regressions. And likewise, fail when we see an
unexpected pass, so we don't forget to update the test vectors in the
future as ir3_parser improves.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 4 Jan 2021 20:47:36 +0000 (12:47 -0800)]
freedreno/ir3: Fix ldg decoding/parsing
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 4 Jan 2021 19:30:32 +0000 (11:30 -0800)]
freedreno/ir3/parser: Fixup stg parsing and add more tests
The offset can also be a register, in which case we need to shuffle
around the src order. Add a few more test vectors to cover each
permutation (no offset, immed offset, gpr offset).
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 3 Jan 2021 18:08:21 +0000 (10:08 -0800)]
freedreno/ir3/parser: Add stgb support
Note that this conflicts with `stc` on a6xx+, so a good test that the
(new) disasm can handle both cases properly.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Thu, 31 Dec 2020 19:08:37 +0000 (11:08 -0800)]
freedreno/ir3/parser: Add ldgb support
Gives us at least better coverage of pre-a6xx-bindless-ibo instructions.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Thu, 31 Dec 2020 00:58:09 +0000 (16:58 -0800)]
freedreno/ir3/parser: Fix pre-a6xx resinfo
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Thu, 31 Dec 2020 00:04:55 +0000 (16:04 -0800)]
freedreno/ir3/parser: Fix atomic support
1) Handle a6xx bindless form
2) Fix shared vs global encoding
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Wed, 30 Dec 2020 23:18:16 +0000 (15:18 -0800)]
freedreno/ir3/parser: Add ldc support
Note that this shows up a slight encoding difference compared to test
vector extracted from blob deqp runs. We think these should be dontcare
bits. For now, add a note and replace the encoded value in the disasm
test.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Wed, 30 Dec 2020 23:00:44 +0000 (15:00 -0800)]
freedreno/ir3: Add cat5/cat6 nonuniform flag
Not yet used by the compiler, but needed so we don't loose information
between ir3 parser and instruction encoding.
Currently ignored for cat5, because the uniform vs non-uniform default
is swapped there.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Wed, 30 Dec 2020 21:23:18 +0000 (13:23 -0800)]
freedreno/ir3: Disambiguate a6xx+ "bindless" instructions
Add a `.b`.. for the atomic instructions it should be `atomic.b.op` but
for now put the `.b` at the end to simplify life for the existing disasm
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 28 Dec 2020 17:05:08 +0000 (09:05 -0800)]
freedreno/ir3: Don't leak disk_cache
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 20:35:08 +0000 (12:35 -0800)]
freedreno/ir3: Add parsing and assembler testing
In theory we should be able to round-trip from disasm->asm and get a
bitwise match.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 19:08:05 +0000 (11:08 -0800)]
freedreno/ir3: Tweak ldib/resinfo encoding
The blob is using '0' for the low bit in these (except for ldib where it
seems to randomly use either '0' or '1'). The upcoming xml based ISA
spec maps this bit to 'dontcare' in the ldib case.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 18:59:15 +0000 (10:59 -0800)]
freedreno/ir3/parser: Add initial cat6 IBO instructions
Well, really just resinfo.. dealing with the different ldib/stib syntax
for a6xx+ vs earlier seems a bit too painful to deal with. But resinfo
at least gives us some encoding test coverage of this group of instrs.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 17:34:13 +0000 (09:34 -0800)]
freedreno/ir3/parser: Relative gpr/const can have modifiers too
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 17:15:54 +0000 (09:15 -0800)]
freedreno/ir3/parser: Add missing (sat) modifier
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 17:05:05 +0000 (09:05 -0800)]
freedreno/ir3: Don't set bit for dest conversion for p0.c
This appears to be ignored when writing to predicate registers (which I
guess makes sense, since they are boolean). So no real harm in setting
it, other than it makes some of the ir3_parser test vectors not match
the expected result for encoding.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 21 Dec 2020 16:44:49 +0000 (08:44 -0800)]
freedreno/ir3/parser: Fixup cat5 s2en instructions
Currently ir3 (incl emit_cat5()) expects the samp/tex src register to be
first.. which requires some fixup for the parser to match.
TODO we might want to revisit the src reg order when adding new instr
packing/encoding. For now, lets just make the parser match the rest of
ir3.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 20:52:08 +0000 (12:52 -0800)]
freedreno/ir3/parser: Fix dsxpp/dsypp encoding
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 20:35:27 +0000 (12:35 -0800)]
freedreno/ir3/parser: Fix cat6 store encoding
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 19:05:57 +0000 (11:05 -0800)]
freedreno/ir3: Cleanup cat6 load instructions
There was some src2 vs src3 confusion, but since the syntax is like:
ldl.f32 rDst, l[rBase+off], ncomp
it makes more sense to call the offset src2 and ncomp src3, than the
way we had it. This is also easier to deal with for the ir3 assembly
parser.
Also, src_offset was only ever used by the assembly parser, and was
handled incorrectly in emit_cat6(), resulting that cat6 load instrs
would not work properly in (for ex) computerator. Since we are
cleaning things up, drop src_offset and make the asm parser work in
the same way as the nir->ir3 frontend.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sun, 20 Dec 2020 17:58:45 +0000 (09:58 -0800)]
freedreno/ir3: Clean up instruction creation
Convert everything remaining over to the version which takes # of
register (src + dst) and drop the ir3_instr_create2() version.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 23:36:24 +0000 (15:36 -0800)]
freedreno/ir3/parser: Handle half-immed
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 23:14:26 +0000 (15:14 -0800)]
freedreno/ir3/parser: cat1 updates (mova1, movmsk)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 22:15:13 +0000 (14:15 -0800)]
freedreno/ir3/parser: cat1 instructions can write relative GPR
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 22:05:58 +0000 (14:05 -0800)]
freedreno/ir3/parser: Add new cat0 instructions
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 21:46:59 +0000 (13:46 -0800)]
freedreno/ir3: Various cat0 updates
Update the IR and packer to handle the additional cat0 fields, in
prep for adding support in the assembler (in prep for adding round
trip parsing/packing test coverage).
We don't actually use these yet from the ir3 compiler, but at least
this is one less thing to worry about when we start trying to use
them.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 21:17:36 +0000 (13:17 -0800)]
freedreno/ir3/parser: Reset lexer when input changes
Otherwise, in case of parse errors, the lexer state can still contain
buffered input from the previous parse.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Sat, 19 Dec 2020 19:45:31 +0000 (11:45 -0800)]
freedreno/ir3: Move assembler error handling
Move out of ir3_parse_asm() so we can re-use it in disasm test for
round-tripping asm/disasm. We don't want failures to be fatal (yet)
as there are still some things missing from the assembler.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 15 Dec 2020 17:58:15 +0000 (09:58 -0800)]
freedreno/ir3: Add some more disasm test vectors
Various things that I noticed which were initially wrong with the xml
based disasm.
These were extracted from a collection of unique instructions extracted
from deqp traces, which unfortunately looses the link back to the
original test case.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Tue, 15 Dec 2020 18:50:28 +0000 (10:50 -0800)]
freedreno/ir3: Fix mova1 disasm
Yet another mnemonic for mov
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Rob Clark [Mon, 14 Dec 2020 18:56:04 +0000 (10:56 -0800)]
freedreno/ir3: Fix half-immed decoding issues
For mov, half-float immeds are packed in 16b. In other cases, the
syntax for a half-immed is a bit different (ie. `h(1)`)
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Connor Abbott [Mon, 14 Sep 2020 10:15:16 +0000 (12:15 +0200)]
ir3: Support MOVMSK
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Connor Abbott [Wed, 16 Sep 2020 14:44:08 +0000 (16:44 +0200)]
ir3: Better rules for shared src copy propagation
It turns out that the actual rule for when a source/dest can be shared
is that it has to be cat1, cat2, or cat3. Allow this and silence
warnings.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Connor Abbott [Thu, 10 Sep 2020 10:14:24 +0000 (12:14 +0200)]
ir3: Rename high registers to shared registers
This more accurately reflects what they are.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8175>
Danylo Piliaiev [Wed, 30 Dec 2020 13:59:46 +0000 (15:59 +0200)]
freedreno: Enable GLSL 3.30, updating us to GL 3.3 contexts
All necessary features are already supported.
GL33 CTS failures:
KHR-GL33.texture_swizzle.smoke - timeouts, passes otherwise
KHR-GL33.cull_distance.coverage - see
https://gitlab.khronos.org/Tracker/vk-gl-cts/-/issues/2673
fix is not in the public repo yet.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8270>
Christian Gmeiner [Sat, 2 Jan 2021 08:32:56 +0000 (09:32 +0100)]
pan: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:29:05 +0000 (09:29 +0100)]
microsoft/compiler: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:14:32 +0000 (09:14 +0100)]
anv: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:14:08 +0000 (09:14 +0100)]
intel/compiler: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 08:13:30 +0000 (09:13 +0100)]
intel/blorp: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:51:29 +0000 (08:51 +0100)]
vc4: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:43:52 +0000 (08:43 +0100)]
iris: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:40:37 +0000 (08:40 +0100)]
d3d12: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 07:31:11 +0000 (08:31 +0100)]
tu: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 06:42:52 +0000 (07:42 +0100)]
zink: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Sat, 2 Jan 2021 06:36:02 +0000 (07:36 +0100)]
st: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 20:33:35 +0000 (21:33 +0100)]
ir3: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:52:20 +0000 (20:52 +0100)]
v3dv: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:51:03 +0000 (20:51 +0100)]
v3d: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:37:53 +0000 (20:37 +0100)]
nir: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:53:51 +0000 (20:53 +0100)]
tgsi_to_nir: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Christian Gmeiner [Fri, 1 Jan 2021 19:33:32 +0000 (20:33 +0100)]
mesa/prog_to_nir: use intrinsic builders
Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8295>
Mike Blumenkrantz [Fri, 7 Aug 2020 20:19:19 +0000 (16:19 -0400)]
nir: preserve explicit_binding in lower_atomics_to_ssbo
it's important to be able to tell whether this is explicitly set by the
user
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7489>
Erik Faye-Lund [Wed, 6 Jan 2021 05:59:27 +0000 (06:59 +0100)]
zink: remove support for fcsel
fcsel is only emitted by bool -> float lowering. We used to do that a
long time ago, but no longer. So we don't need to support this opcode
any longer.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8347>
Erik Faye-Lund [Wed, 6 Jan 2021 06:38:41 +0000 (07:38 +0100)]
zink: also lower scmp for soft-fp
We recently added two versions of these options, due to soft-fp support.
So let's also add the lowering to the soft-fp version.
Fixes:
43302ead383 ("zink: use lower_scmp instead of open-coding")
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8347>
Boris Brezillon [Tue, 5 Jan 2021 13:02:07 +0000 (14:02 +0100)]
panfrost: Fix AFBC on Bifrost v6
The AFBC layout of RT/ZS-extension descriptors on Bifrost v6 matches the
v7 one except for the Block Format field. Update the set_buf() functions
accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8328>
Yogesh mohan marimuthu [Mon, 14 Dec 2020 15:56:27 +0000 (21:26 +0530)]
radeonsi: enable vrs2x2 coarse shading if flat shading (v9)
Enable vrs2x2 coarse shading if flat shading as per
idea and guidance given by Marek.
is_flat_shading variable in struct si_shader_info is set
based on the data from gather_intrinsic_info() function
and struct si_state_rasterizer. If is_flat_shading_variable
is set, then in function si_emit_db_render_state() vrs2x2
shading is enabled in hardware.
v2: Fix review comments from Pierre-Eric. Code optimizations.
v3: Fix indentation style issue.
v4: Fix review comments from Marek. Fixed logical issue pointed
by Marek where info->is_flat_shading variable can be corrupted
and other code cleanup.
v5: Make the code compact as suggested by Pierre-Eric.
v6: Fix new review comments from Marek.
v7: use info->uses_interp_color variable fix from Marek.
v8: Fix coding style comment from Marek.
v9: Add uses_fbfetch_output check as suggested by Marek.
Signed-off-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8161>
Eric Anholt [Mon, 21 Dec 2020 23:29:19 +0000 (15:29 -0800)]
gallium/ntt: Add support for PIPE_CAP_LOAD_CONSTBUF.
We needed to do this anyway to finish enabling NTT in general, but more
importantly: when we enabled sending NIR to the draw module, that broke
PIPE_CAP_LOAD_CONSTBUF drivers in the select/feedback paths if LLVM was
disabled.
Fixes:
44b7e1497f91 ("st/mesa: don't generate TGSI for the draw VS because it now supports NIR too")
(along with the rest of this MR)
Closes: #3996
Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 22 Dec 2020 00:22:03 +0000 (16:22 -0800)]
gallium/ntt: Fix load_ubo_vec4 buffer index setup.
I had a funny +1 in nir_to_tgsi's load_ubo lowering on the buffer index,
because I hadn't set lower_uniform_to_ubo for softpipe. This removes that
weirdness in favor of just using lower_uniform_to_ubo, regardless of
driver preference (which matters if a NIR-native driver had it set, and
then the gallium draw module triggered the non-LLVM TGSI fallback path
that hit NTT).
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 22 Dec 2020 01:12:02 +0000 (17:12 -0800)]
gallium/ntt: Fix dynamic indirect indexing of per_vertex_input.
It was off by one due to some copy and paste from UBO handling.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Fri, 11 Dec 2020 21:11:26 +0000 (13:11 -0800)]
gallium/ntt: Fix emitting UBO declarations.
Fixes:
d70fff99c5bc ("nir: Use a single list for all shader variables")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 5 Jan 2021 19:15:06 +0000 (11:15 -0800)]
gallium/tgsi_exec: Add support for PIPE_CAP_LOAD_CONSTBUF.
Now that we can end up in nir-to-tgsi in the draw fallback paths of
drivers with that flag set, we need to support it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Tue, 5 Jan 2021 19:12:11 +0000 (11:12 -0800)]
gallium/tgsi_exec: Refactor to fix CS local memory overflow checks.
It was OK because right now we only execute in the first channel of the
CS, but if you wanted to extend that then you'd need to check each
channel. We already had what we needed for SSBOs, so just reuse it.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Eric Anholt [Thu, 10 Dec 2020 19:34:48 +0000 (11:34 -0800)]
gallium/tgsi_exec: Fix assertion failure about missing constbufs.
GL by default gives you UB when you access a missing constbuf, and we were
crashing on debug builds in that case. More importantly, we were
assertion failing even under valid circumstances, when a !ExecMask channel
had a bad value for the indirect buffer index and we tried to load from it
anyway.
In removing the assertion, also sink the buf declaration to after we've
done the bounds check that determines that there's a constbuf actually
bound to this index.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8196>
Jesse Natalie [Mon, 14 Dec 2020 19:59:53 +0000 (11:59 -0800)]
d3d12: Don't allocate mappable textures
There's not really a reason to directly map textures. Doing so
requires the texture to be allocated in system RAM instead of
video RAM, which means all GPU access to it would be needlessly slow.
Notably, the one texture type that was allocated this way is the
display target texture for the software driver path. Instead, use
pipe_transfer_map to be able to copy the texture to system RAM.
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8095>
Jesse Natalie [Mon, 14 Dec 2020 19:53:39 +0000 (11:53 -0800)]
d3d12: Use an appropriate pipe resource usage for map intermediates
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8095>
Jesse Natalie [Mon, 14 Dec 2020 19:53:13 +0000 (11:53 -0800)]
d3d12: Use buffer pipe usage to inform allocation
For non-CPU-accessible pipe resource types (DEFAULT/IMMUTABLE),
allocate non-CPU-accessible buffers directly from the cache_bufmgr.
Update the d3d12_bo creation to handle nonmappable buffers.
For CPU-write-only (DYNAMIC/STREAM), use the upload slab_bufmgr.
Update this slab manager to use CPU_WRITE | GPU_READ PB usage.
For CPU-read-write (STAGING), use the readback_slab_bufmgr.
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8095>
Jesse Natalie [Mon, 14 Dec 2020 19:45:16 +0000 (11:45 -0800)]
d3d12: Add a slab bufmgr for readback buffers
Readback (GPU write, CPU read) should use different CPU page
properties compared to upload (write-back vs write-combined).
A future commit will start to respect these PB usage flags.
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8095>
Jesse Natalie [Mon, 14 Dec 2020 19:42:49 +0000 (11:42 -0800)]
d3d12: Add a path for mapping of not-directly-mappable buffers
Currently all buffers are allocated as mappable, but a future
commit will change that so that some buffers can be allocated
directly in non-CPU-accessible memory for improved performance.
Note that the returned pointer must be appropriately offset from
a 64-byte-aligned base pointer, so if offsets are used, the data
will be read/written to an offset region in the staging buffer.
Reviewed-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8095>
Jesse Natalie [Mon, 28 Dec 2020 23:45:58 +0000 (15:45 -0800)]
nir: Update saturated float->int/uint conversion algorithm
The mantissa for a float doesn't contain enough data to accurately represent
the min/max values for some destination types. Instead of clamping before
converting, clamp after converting when coming from floats. This improves
conformance of CL conversions, specifically for float -> long/ulong with
int64 emulation enabled.
Refactors the limit determination from the clamp, so we can determine
limits for the dest type (int/uint) in both the source (float) and dest
type. The limit as a float is used for comparison, while the limit as a
dest type is used for bcsel.
Important note is that the comparison is inverted to fge instead of flt,
so the bcsel chooses the direct int/uint over the converted float in the
case where the comparison comes up equal, but the conversion can't produce
the exact min/max value.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8256>
Eric Anholt [Mon, 4 Jan 2021 23:32:56 +0000 (15:32 -0800)]
freedreno/a5xx: Move link_stream_out after VPC_VAR_DISABLE like on a6xx.
Since we've got issues on a5xx xfb that we don't on a6xx, I've been
looking at making them line up a bit better. No change on tests.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8336>
Eric Anholt [Mon, 4 Jan 2021 23:25:17 +0000 (15:25 -0800)]
freedreno/a5xx: Drop redundant stream output linking check.
The link function just loops over the num_outputs. Brings us closer to
a6xx.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8336>
Eric Anholt [Mon, 4 Jan 2021 23:23:02 +0000 (15:23 -0800)]
freedreno/ir3: Deduplicate link_stream_out.
All 3 copies were the same other than style tweaks.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8336>
Erik Faye-Lund [Tue, 5 Jan 2021 17:36:09 +0000 (18:36 +0100)]
zink: use lower_scmp instead of open-coding
We already have the proper lowering in NIR for this, so there's no point
in doing our own implementations of these. The end result is the same
code anyway.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8335>
Danylo Piliaiev [Thu, 31 Dec 2020 13:54:10 +0000 (15:54 +0200)]
freedreno/a5xx: implement transform feedback resuming
Each transform feedback target should have a separate buffer
for an offset from which to resume, instead of just having
one buffer per binding point. Otherwise, if transform feedback
is paused and other tf object is bound - the offset of the
previous tf object would be lost.
Fixes CTS tests:
dEQP-GLES3.functional.transform_feedback.*triangles*
Fixes Piglit tests:
gl-3.1-primitive-restart-xfb flush
gles-3.0-transform-feedback-uniform-buffer-object
arb_transform_feedback2-change-objects-while-paused
arb_transform_feedback2-change-objects-while-paused_gles3
ext_transform_feedback-intervening-read
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8281>
Danylo Piliaiev [Thu, 31 Dec 2020 12:49:12 +0000 (14:49 +0200)]
freedreno/a6xx: fix transform feedback resuming
Each transform feedback target should have a separate buffer
for an offset from which to resume, instead of just having
one buffer per binding point. Otherwise, if transform feedback
is paused and other tf object is bound - the offset of the
previous tf object would be lost.
Fixes Piglit tests:
arb_transform_feedback2-change-objects-while-paused
arb_transform_feedback2-change-objects-while-paused_gles3
ext_transform_feedback-alignment 4
ext_transform_feedback-alignment 8
ext_transform_feedback-alignment 12
ext_transform_feedback-change-size offset-grow
ext_transform_feedback-change-size offset-shrink
ext_transform_feedback-change-size range-grow
ext_transform_feedback-change-size range-shrink
ext_transform_feedback-immediate-reuse-uniform-buffer
ext_transform_feedback-position *
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8281>
Mike Blumenkrantz [Tue, 5 Jan 2021 14:08:33 +0000 (09:08 -0500)]
zink: handle non-const offsets for txf/tg4 ops
required for gl_spirv handling and tg4
Fixes:
b77f43f2539 ("zink: use ConstOffset for nir_tex_src_offset")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8333>
James Jones [Thu, 15 Oct 2020 21:17:16 +0000 (14:17 -0700)]
gallium/dri: Use per-screen DRI extension list
Some DRI extension features are enabled/disabled
based on capabilities of the gallium pipe_screen
associated with the DRI screen. Additionally, the
list of extensions enabled also varied based on
features requested by the screen creator. However,
prior to this change the extension list and
extension definition structures within it were
global variables, meaning the last screen
initialized ended up defining the DRI capabilities
of all screens.
This change instead stores a copy of the
extensions which vary per screen, as well as a
copy of the extension list itself in the gallium
DRI screen structure, allowing them to vary per
screen.
Closes: https://gitlab.freedesktop.org/drm/nouveau/issues/9
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7175>
James Jones [Thu, 15 Oct 2020 21:30:32 +0000 (14:30 -0700)]
gallium/dri: Factor out DRI extension setup code
Share the DRI extension setup code between
dri2_init_screen and dri_kms_init_screen. There's
currently very little difference, and the sharing
will make a subsequent change to refactor this
code to use per-screen extension lists easier.
Signed-off-by: James Jones <jajones@nvidia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7175>
Erik Faye-Lund [Tue, 5 Jan 2021 10:58:28 +0000 (11:58 +0100)]
zink: use ConstOffset for nir_tex_src_offset
Quote from the OpenGL Shading Language spec, version 4.40, section 8.9.2
"Texel Lookup Functions":
> The offset value must be a constant expression.
So, until we start consuming SPIR-V shaders, it seems we don't need to
deal with non-constant offsets.
This means we can avoid lowering this away in some cases.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8327>
Erik Faye-Lund [Wed, 25 Nov 2020 11:43:46 +0000 (12:43 +0100)]
zink: do not reserve or pack fragment outputs
These are completely unrelated to other shader IO variables, so they
don't need this logic.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7986>
Erik Faye-Lund [Tue, 24 Nov 2020 18:08:47 +0000 (19:08 +0100)]
zink: do not use reservations for stream-out
reservations are accumulated for all shader-stages in a program without
resetting it. But stream-out is completely orthogonal to all other
inputs and outputs, so they don't matter for this stuff at all.
So let's drop considering reservations here, and simply count how many
generic outputs we have here instead.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7986>
Erik Faye-Lund [Tue, 15 Dec 2020 09:42:11 +0000 (10:42 +0100)]
zink: destroy device and instance
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8099>
Erik Faye-Lund [Tue, 15 Dec 2020 09:41:57 +0000 (10:41 +0100)]
zink: destroy transfer-helper
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8099>
Erik Faye-Lund [Tue, 15 Dec 2020 09:41:03 +0000 (10:41 +0100)]
zink: free sets and hash-tables in context
Up until now, we've simply leaked all of these. Let's try to do better.
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8099>
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