zink: add depth/stencil needs shader swizzle workaround field

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>

zink: extend shadow swizzle pass to all zs textures

if needs_zs_shader_swizzle is used, apply constant swizzles to all
depth/stencil textures and not just shadow samplers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>

zink: add needs_zs_shader_swizzle shader key

This will be used later, but for now it should always be disabled.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>

zink: minor formatting change

that line was becoming too long.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>

zink: track shadow swizzle for all shader stages

this will be used later on to enable the pass in all
shader stages.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>

zink: fix shadow mask change logic when binding sampler views

First make sure shadow mask change sets dirty state.
Second move shadow mask bit removal to unbind_samplerview which
is cleaner and correctly clears the shadow bit when binding buffer texture.

Fixes: 5193f4f712b ("zink: add a fs shader key member to indicate depth texturing mode")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21571>

zink: fix stale point sprite mode state

Fixes: cf8ca77be10 ("zink: handle point sprite")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21840>

zink: super reorder buffer copies

usually zink_get_cmdbuf() is enough for reordering operations, but
with new technology, it becomes possible to promote even the most stubborn
buffers to the unordered cmdbuf

first, check the src buffer to ensure that there's no pending writes in
the main cmdbuf that would prohibit reordering

second, apply a TRANSFER_DST to the dst buffer using the util function
to determine whether it can be reordered

if both the src and dst can be reordered for their respective regions
and read/write usage, then the entire op can be promoted regardless of
the unordered_read/unordered_write flags

this optimizes out patterns like
upload index buffer (offset=0)
draw
upload index buffer (offset=128)
draw
upload index buffer (offset=256)
draw
...

so that the uploads and draws can be separated and batched

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21802>

zink: rename zink_check_transfer_dst_barrier()

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21802>

zink: unify image TRANSFER_DST barrier checks

this should be consistent with buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21802>

zink: return the unordered state from zink_resource_buffer_transfer_dst_barrier()

convenience usage

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21802>

zink: rework zink_resource::valid_buffer_range

this is now the valid buffer region for the "main" command buffer,
and all transfer ops store their regions in the copy boxes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21802>

ci: fix LVP_POISON_MEMORY usage

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21847>

lavapipe: beef up LVP_POISON_MEMORY

this makes lavapipe behave more like a tiler and completely annihilate
any existing data for DONTCARE load/store ops

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21847>

vulkan/wsi: add a headless swapchain implementation/option

I wanted to find slow pieces of code in our Anv driver using our
drm-shim stub.

The last bit of code still talking to the compositor was the WSI
swapchain code and failing because none of the submissions are taking
place (because of the stub).

This change introduces a new variable MESA_VK_WSI_HEADLESS_SWAPCHAIN
which when set turns every swapchain creation into a headless
swapchain. This swapchain does not present anything, allowing the
application to spin as many frames as possible. Thus helping to
identify slow spots in command buffer building path.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6156>

anv: fix image height for field pictures.

Fixes: 98c58a16ef1ab2 ("anv: add initial video decode support for h264.)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21807>

intel/fs: fix subgroup invocation read bounds checking

nir->info.subgroup_size can be set to an enum :
  SUBGROUP_SIZE_VARYING = 0
  SUBGROUP_SIZE_UNIFORM = 1
  SUBGROUP_SIZE_API_CONSTANT = 2
  SUBGROUP_SIZE_FULL_SUBGROUPS = 3

So compute the API subgroup size value and compare it to the dispatch
size to determine whether we need some bound checking.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 9ac192d79d ("intel/fs: bound subgroup invocation read to dispatch size")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21856>

radv/rt: Fix any_hit scratch variables.

We have to make sure not to change call_data locations as well.

Fixes: 481f78ab93e2f2169c53a7c8494b488d45b60def ('radv/rt: place any-hit scratch vars after intersection scratch vars')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21876>

ci: Re-enable some swrast testing using fd.o's shared runners for now.

I'm not planning to stand mesa-swrast back up until we get Kata set up, so
turn the testing back on at a reduced fraction on so that
venus/llvmpipe/etc. dev can still get some coverage.

I haven't turned lavapipe back on, because it is now unstable in memory
model / atomics tests.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21880>

intel/fs: prevent large vector ops generated by peephole_ffma

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21782>

intel/fs: add MOV source count validation

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21782>

intel/fs: fixup sources number from opt_algebraic

Fixes issues with register_coalesce :

fossilize-replay: brw_fs_register_coalesce.cpp:297: bool fs_visitor::register_coalesce(): Assertion `mov[i]->sources == 1' failed.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21782>

intel/fs: fix nir_opt_peephole_ffma max vec assumption

There can be larger vec than vec4.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21782>

intel/fs: don't SEND messages as partial writes

For instance, to load uniform data with the LSC we usually rely on
tranpose messages which have to execute in SIMD1. Those end up being
considered as partial writes so within loops their life span spread to
the whole loop, increasing register pressure.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21867>

anv: more formats for acceleration structure vertices

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21821>

anv/video: disable picture id reampping.

This isn't needed at the hw level with vulkan

Fixes: 98c58a16ef1a ("anv: add initial video decode support for h264.")
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21433>

anv/video: fix chroma qp to be a integer value.

This is just a cleanup to the genxml

Fixes: 98c58a16ef1a ("anv: add initial video decode support for h264.")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21433>

lavapipe: add command debugging

I keep adding this in locally. it's great for debugging

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21814>

lavapipe: set render_condition_enabled=false for vkCmdClearDepthStencilImage

this command ignores conditional rendering

fixes:
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_host_memory_expect_noop
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_host_memory_secondary_buffer_expect_noop
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_host_memory_secondary_buffer_expect_noop_inverted
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_host_memory_secondary_buffer_inherited_expect_noop
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_local_memory_expect_noop_inverted
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_local_memory_secondary_buffer_expect_noop
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_local_memory_secondary_buffer_expect_noop_inverted
dEQP-VK.conditional_rendering.conditional_ignore.clear_condition_local_memory_secondary_buffer_inherited_expect_noop

Fixes: fe53c222949 ("lavapipe: fix only clearing depth or stencil paths.")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21814>

lavapipe: fix dynamic depth clamping

on pipeline bind with dynamic state, depth_clip_near needs to either be set by
* applying the dynamic state
* using the pipeline state

the previous code always used the pipeline state

fixes:
dEQP-VK.pipeline.*.extended_dynamic_state.between_pipelines.depth_clamp_enable

Fixes: 650880105e6 ("vulkan,lavapipe: Use a tri-state enum for depth clip enable")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21814>

ci: uprev virglrenderer and crosvm

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21794>

docs: update Anv features support

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21870>

anv: export EXT_pipeline_library_group_handles only with RT

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21870>

broadcom/ci: no need to skip the tests that swap buffers anymore

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21877>

ci: disable weston session timeout

    -iN, --idle-time=N
           Set  the idle timeout to N seconds. The default timeout is
           300 seconds. When there has not been any user input for the idle
           timeout, Weston enters an inactive mode. The screen fades to black,
           monitors may switch off, and the shell may lock the session.
           A value of 0 effectively disables the timeout.

We don't want the session to get locked and monitors to switch off while tests
are running, as many of them depend on swapping buffers.

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21877>

aux/tc: use renderpass tracking to optimize texture_subdata calls

if it's known that a renderpass is active and the driver wants to do
renderpass optimizing, help out by not forcing a sync and instead doing
what the driver would do: create a staging buffer and copy it to the
image

this requires that the driver already handles buffer -> image copies
with resource_copy_region

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21801>

radv/sqtt: Skip dumping pipeline libraries

They don't have any shaders which can lead to crashes when dumping
them.

Fixes: 2e04aeb ("radv: capture RT pipelines from the SQTT layer")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21852>

tu: fix tu_GetInstanceProcAddr not handling null instance

It is legal to pass in nullptr as an instance into
vkGetInstanceProcAddr when resolving any global addresses, this
wasn't handled correctly and an illegal access to a member of
a null struct was made.

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21827>

tu: KGSL backend rewrite

This commit rewrites the KGSL backend to utilize vk common wherever
possible to bring the codebase in line with DRM while implicitly
fixing minor API bugs that may have occurred as a result of manually
implementing VK functions.

As a part of moving to vk common, KGSL sync is now implemented
atop vk common sync and vastly expanded in terms of functionality
such as:
* Import/Export of sync FDs - A required capability for properly
  supporting the Android WSI and as these functions were stubbed
  when a presentation operation used semaphores, it would cause a
  leak of FDs that were imported due to the expectation that the
  driver would close them. As well as causing UB around due to
  ignoring the imported FD or not exporting a valid FD.
* Supporting pre-signalled fences - Vulkan allows fences to be
  created in a signalled state which was stubbed prior and can
  lead to UB.
* Timeline semaphore support - As a result of utilizing vk common
  as the backbone for synchronization, its timeline semaphore
  emulation has been utilized to provide support for them without
  needing kernel support. (Note: On newer versions of KGSL,
  timeline semaphores can be implemented natively rather than
  using emulation as they support wait-before-signal)

Fixes freezes due to semaphore usage with presentation on:
* Genshin Impact
* Skyline Emulator

Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21651>

Revert "driconf: add a workaround for plasmashell freezing"

This reverts commit 41eb491fb6460f401a4c845fc28a53de92e9075b.

The underlying issue was fixed by the previous commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20887>

yegl/wayland: fix glthread deadlocks

We need to make sure that glthread is idle before using wl_*
functions or they might be used from 2 threads at the same
time.

Thanks to @deltib for the investigation of this issue.

Fixes: 58f90fd03f4 ("egl/wayland: fix glthread crashes")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7624
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8136
Reviewed-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20887>

ci/panfrost: Add texturesize flake seen in the wild

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20887>

freedreno/a6xx: Simplify iova emit

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/register: Define chip enum values

Otherwise it cannot be used in templates

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Define rest of CP_REG_WRITE

Enough that we can use OUT_PKT() to emit it, which will be needed when
we use it to write regs that are different btwn a6xx and a7xx.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Fix nameless fields

Originally if we had an anonymous field (ie. field declared as part of
the register definition itself) the name in the generated field struct
would include the gen prefix (ie. .a6xx_rb_stencil_buffer_pitch), but
this doesn't work for variants because the variant regs would have
different gen prefixes.  Fix this by using reg name instead of the
full_name.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Add c++ magic for register variants

For regs with multiple variants, generate a template'ized function to
pack the reg value.  If the template param is known at compile time
(which is the expected usage) this will optimize to the same thing as
the "traditional" reg packing.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Split out regpair builder helper

We are going to want to re-use this in the next commit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Track varset

Track varset and assert that variants refer to a valid varset enum
value.  This adds a bit of extra sanity checking, but becomes more
useful in the next commit.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Start adding stuff for a7xx

Start adding the bits needed for userspace.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/decode: Start adding a7xx support

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Start adding a7xx pipe/control regs

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Merge a6xx and a7xx regs

They have more similarities than differences, so merge them and use
"variant" attribute as needed to manage differences.

Note initially using "variant" conservatively when it comes to regs
known on a7xx but not a6xx.  It could be that they exist also on later
versions of a6xx as well, for example.  For ex, LPAC related regs/bits
likely existed on later a6xx (eg. a660 family) but BV stuff is not.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Add prefix="variant"

To merge a7xx and a6xx regs, using variant property to manage the
differences, we'll want regs/etc to be named according to the first
generation it is use rather than the domain name.  Add a new prefix
type to accomplish this.  By default, if no variant property, things
will still be named based on domain (ie. REG_A6XX_...), and things
that have variant="A6XX" will also end up as they currently are
(since the chip enum matches domain name), but things that have
variant="A7XX" will end up as REG_A7XX_...

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Fix designator order

C++ is picky about order matching for some reason.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/a6xx: Convert to c++

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/a6xx: Fix designator initializer order

Clang seems more relaxed about this, allowing C99 style initializers
without requiring ordering.  But unfortunately g++ is more picky :-/

TODO this doesn't completely fix everything with g++, namely sparse
array initialization.. for ir3 driver-params, I think we can convert
these to structs.  But there are still one or two others to deal with.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/a6xx: Add missing "inline"

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/a6xx: Rework texture_clear fallback

C++ is more picky about a goto jumping over variable initialization,
even if unused after the goto label (presumably because of destructors
that can be called after a variable goes out of scope).  Since there is
only a single fallback path, get rid of the goto.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno: c++-proofing

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno: Un-inline buffer-mask enum

Also, fix obsolete comment.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/ir3: Add missing driver params

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/ir3+tu: Calculate subgroup size in ir3

TBD if the size changes for a7xx, but at least let's have it in one
place instead of duplicating in turnip and gallium.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/ir3: c++-proof the headers

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/ir3: Don't use negative opc for meta instructions

Stricter compilers complain about this, ie:

  error: left operand of shift expression ‘(-1 << 7)’ is negative [-fpermissive]

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/ir3: Un-inline enums

It seems to be a thing that c++ dislikes

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno: Quiet c++ warning about designated initializers

And various other things that c++ is more strict about.  Perhaps we
re-instate a few of the more reasonable warnings over time.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Add regs for a690

New regs needed on kernel side.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno/registers: Schema validation for gen_header.py

Lets catch issues at build time, and not relying on someone remembering
to run the unit tests.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

freedreno: Nerf strict-aliasing warning for all of gcc

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21846>

radv: allow to cache optimized (LTO) pipelines with GPL

This should be working now, except PS epilogs that are still not
added to the cache.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21834>

radv: keep track of the retained NIR shaders sha1 for LTO pipelines

Otherwise the per pipeline cache key doesn't consider shaders at all
when they are imported from libs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21834>

radv: determine if a graphics pipeline needs a noop FS earlier

Also introduce a helper.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21834>

radv: fix the error code when the driver fails to create a PS epilog

It would have been returned VK_SUCCESS.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21834>

radv/rt: place any-hit scratch vars after intersection scratch vars

If both, any-hit and intersection shader, use scratch vars,
it could happen that they end up in the same location and
overwrite each other.
Found by inspection.

Fixes: c3d82a962217def9b9f7e1f4c5ce0a450b97e9c7 ('radv: Add pass to lower anyhit shader into an intersection shader.')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21863>

intel/dev: Enable MTL PCI ids

Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/include/drm/i915_pciids.h?h=v6.0-rc4#n736
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18481>

radv: avoid a huge memset in radv_graphics_pipeline_compile()

this has a noticeable impact on pipeline creation

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20947>

radv: zero-initialize radv_shader_info earlier for graphics pipeline

This should allow us to remove a big memset when compiling a
graphics pipeline. This is mostly for imported NIR stages which
don't go through radv_pipeline_stage_init().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20947>

radv: zero-initialize radv_shader_args right before declaring them

This should allow us to remove a big memset when compiling a
graphics pipeline. This is mostly for imported NIR stages which
don't go through radv_pipeline_stage_init().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20947>

radv: delete radv_graphics_pipeline_compile() asserts

validation should catch these by now

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20947>

pps: Fix build errors.

In file included from ../src/tool/pps/pps_device.cc:10:
../src/tool/pps/pps_device.h:23:11: error: ‘uint32_t’ does not name a type
   23 |    static uint32_t device_count();
      |           ^~~~~~~~

In file included from ../src/tool/pps/pps_counter.cc:10:
../src/tool/pps/pps_counter.h:22:4: error: ‘uint32_t’ does not name a type
   22 |    uint32_t id;
      |    ^~~~~~~~

Fixes: 1cc72b2aef8 ("pps: Gfx-pps v0.3.0")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8186
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21714>

glthread: qualify the *cmd unmarshal parameter with restrict

This seems like a logical thing to do. Clearly the memory can't be
accessed with any other pointer.

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21777>

mesa: put dispatch table initialization into one place

We have 3 new/changed functions with this commit:
1. _mesa_alloc_dispatch_tables creates all dispatch tables that are not
   created on demand and sets them to nop. This operates on gl_dispatch,
   so it's reusable (e.g. glthread will want to use it)
2. _mesa_free_dispatch_tables frees everything
3. _mesa_initialize_dispatch_tables initializes gl_dispatch for GL
   (not glthread)

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21777>

mesa: rename CurrentClientDispatch to GLApi

I like this more. The name self-documents itself. It's always equal
to the dispatch set in glapi.

GLAPI is a definition, so can't use that.

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21777>

mesa: move ctx->Table -> ctx->Dispatch.Table except Client & MarshalExec

There is a new struct gl_dispatch, which I'd like to reuse in glthread.
This allows building code around gl_dispatch that can be shared between
mesa and glthread. This is only refactoring.

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21777>

glapi: inline the meson list files_mapi_util

so that people can easily tell where these files are used by searching
for the file names in the meson files.

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21777>

glapi: move files specific to shared-glapi into the shared-glapi subdirectory

Acked-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21777>

ci/clover: disable the jobs

Prepare for Clover removal; don't waste resources on Clover anymore.

Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21865>

aco/spill: allow for disconnected CFG

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20853>

aco/insert_exec_mask: allow for disconnected CFG

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20853>

aco/dead_code_analysis: don't add artificial uses to p_startpgm

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20853>

aco/value_numbering: clear hashmap between disconnected CFGs

There is no dominance-relationship between two disconnected CFGs,
thus no CSE is possible.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20853>

aco/dominance: set immediate dominator for any BB without predecessors

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20853>

CI: Disable mingw job

mingw just hangs somewhere in Meson, with a totally unclear cause, when
trying to run winepath:

Program winepath found: YES (/usr/bin/winepath)
Running command: /usr/bin/winepath -w /builds/mesa/mesa/_build/src/util/process_test.exe
[... hangs forever ...]

root          27  0.0  0.0   4044  3232 ?        S    17:10   0:00 bash .gitlab-ci/meson/build.sh
root          35  0.0  0.0 2811920 55800 ?       Sl   17:10   0:00 Xvfb :0 -screen 0 1024x768x16
root          40  0.1  0.0  45484 40740 ?        S    17:10   0:00 /usr/bin/python3 /usr/local/bin/meson setup _build --native-file=native.file --wrap-mode=nofallback --force-fallback-for perfetto -D prefix=/builds/mesa/mesa/install -D libdir=lib -D buildtype=debug -D build-tests=true -D c_args=-Wno-error=format -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=unused-but-set-variable -Wno-error=sign-compare -Wno-error=narrowing -D cpp_args=-Wno-error=format -Wno-error=unused-function -Wno-error=unused-variable -Wno-error=unused-but-set-variable -Wno-error=sign-compare -Wno-error=narrowing -D enable-glcpp-tests=false -D libunwind=disabled -D gallium-opencl=icd -D gallium-rusticl=false -D opencl-spirv=true -D microsoft-clc=enabled -D static-libclc=all -D llvm=enabled -D gallium-va=enabled -D video-codecs=h264dec,h264enc,h265dec,h265enc,vc1dec -D gallium-drivers=swrast,d3d12,zink -D vulkan-drivers=swrast,amd,microsoft-experimental -D video-codecs=h264dec,h264enc,h265dec,h265enc,vc1dec -D werror=true -D min-windows-version=7 -D spirv-to-dxil=true -D gles1=enabled -D gles2=enabled -D osmesa=true -D cpp_rtti=true -D shared-glapi=enabled -D zlib=enabled --cross-file=.gitlab-ci/x86_64-w64-mingw32
root        1366  0.0  0.0      0     0 ?        Z    17:10   0:00 [winepath.exe] <defunct>
root        1375  0.0  0.0   8544  7188 ?        Ss   17:10   0:00 /usr/lib/wine/wineserver64 -p0
root        1381  0.0  0.0 2018764 11080 ?       Ssl  17:10   0:00 C:\windows\system32\services.exe
root        1384  0.0  0.0 1821312 10044 ?       Sl   17:10   0:00 C:\windows\system32\plugplay.exe
root        1386  0.0  0.0 1856096 23016 ?       Sl   17:10   0:00 C:\windows\system32\explorer.exe /desktop
root        1393  0.0  0.0 1822712 11000 ?       Sl   17:10   0:00 C:\windows\system32\winedevice.exe
root        1402  0.0  0.0 1778832 21456 ?       S    17:10   0:00 winedbg --auto 26 80
root        1405  0.0  0.0 1891516 12192 ?       Sl   17:11   0:00 C:\windows\system32\winedevice.exe

Disable it until we can figure it out.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21864>

CI: Disable Windows runners

They are currently being rebuilt, with no firm ETA for their return.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21864>

Revert "ci: Disable Collabora LAVA farm"

This reverts commit c1aa876747a37d42b67ff1f53675890b05b40d1a.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21864>

fix: gallivm: fix LLVM #include of Host.h, moved to TargetParser

Upstream moved Host.h from Support to TargetParser in LLVM 17.

This shouldn't lead to a FTBFS, since there is a forwarding include left
behind. Sadly the added deprecation warning #pragma is invalid and thus
causes a build failure right away. But since we would have to follow the
move anyway in the future, just do it right away.

Reference: https://github.com/llvm/llvm-project/commit/d768bf994f508d7eaf9541a568be3d71096febf5
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Closes: #8275
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21263>

radv/rt: Properly handle pNext of pipeline library stages

Fixes
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.non_graphics.shader_module_info_rt_lib.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21707>

vulkan: Add vk_shader_module_init

This will be used for allocating shader modules using ralloc by RADV.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21707>

radv/rt: Use vk_pipeline_hash_shader_stage for RT stages

Fixes
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.non_graphics.shader_module_info_rt.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21707>