Andrzej Hajda [Thu, 28 Apr 2016 09:58:48 +0000 (11:58 +0200)]
drm/panel/s6e3ha2: fix frequency calibration on 1440p displays
The driver support 1440p and 1600p displays, to support both models correctly
it should send different frequency calibration sequence.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ic38d4eb357609be0d1a67c655c5c110559b08bd3
Andrzej Hajda [Wed, 27 Apr 2016 14:04:44 +0000 (16:04 +0200)]
drm/panel/s6e3ha2: fix calibration sequence
Panel TE interrupt was signaled with variable frequency 53-60 fps.
This patch fixes it to about 60 fps.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Icf88caae7eed9ea540158a17a6745a0265948265
Marek Szyprowski [Thu, 19 May 2016 11:12:37 +0000 (13:12 +0200)]
soc: exynos: pm_domains: restore old way of getting dt clocks
This restores support for asb clocks, which got lost during core rewrite.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Idc37a9814bd4825863960dc0e59486e07ddf9139
Marek Szyprowski [Thu, 19 May 2016 10:15:23 +0000 (12:15 +0200)]
drm/exynos: gsc: force to use zero buf_id for src and dst
Exynos DRM GSC IPP subdriver supports only processing a single src/dst
buffer pair, so don't use any other buf_id to avoid accessing
uninitialized buffers (IOMMU page fault).
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I488bb9ee60e0fe8e711b9c116b04483ac99a66e9
Marek Szyprowski [Thu, 19 May 2016 10:35:34 +0000 (12:35 +0200)]
media: s5p-mfc: fix build warning
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ib621db7813a80d0a775968c5fadef5f25d0a92f5
Marek Szyprowski [Thu, 19 May 2016 10:31:42 +0000 (12:31 +0200)]
media: s5p-mfc: exynos5422 doesn't provide sclk clock to MFC block
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Ibfe361bdff955eb446b472a5edcd0df9800c1221
Hyungwon Hwang [Mon, 24 Aug 2015 10:33:27 +0000 (19:33 +0900)]
drm/exynos: gsc: normalize invalid buf idx from userspace
At least in the one frame processing mode which is the only mode supported
by the current gsc driver, the buf idx is not meaningful for the driver.
Because only one address in the buffer is valid at a time, so it is OK to
convert the invalid buf idx from userspace to a valid idx, process the
frame, and return the result with original buf idx.
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I8257cd39e33382f214ce4573e4a79f15ea498aab
Marek Szyprowski [Thu, 19 May 2016 10:15:23 +0000 (12:15 +0200)]
Revert "drm/exynos: gsc: always use hw buffer 0 until queue management get fixed"
This reverts commit
937b633eebe825aad14181b168c5b79eccad833d.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I488bb9ee60e0fe8e711b9c116b04483ac99a66e8
Marek Szyprowski [Mon, 30 Nov 2015 13:53:24 +0000 (14:53 +0100)]
drm/exynos: mixer: enable video overlay plane only when VP is available
Video overlay plane should be registered only when suitable hardware
sub-block (Video Processor) is available.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Gustavo Padovan <gustavo.padovan@collabora.co.uk>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
[backport of mainline commit
ab14420125c3cd1111f57731f0f9359c4e64d76a
to let Enlightenment to use video/osd graphics plane]
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: Iea4dd02abb408aa188b46f6ed099b0231ef99b6d
Jaehoon Chung [Thu, 19 May 2016 03:56:34 +0000 (12:56 +0900)]
net: bcm4358: remove unused config for pci binding
This patch removes unused config for pci binding in bcm4358 driver.
Change-Id: Ib82010c667224a9ed323c52f604e3183f62f42a7
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Jaehoon Chung [Wed, 18 May 2016 04:28:41 +0000 (13:28 +0900)]
arm64: build: add tizen-tm2 its file to create kernel image for u-boot
This patch adds tizen-tm2 its file to create kernel image for u-boot.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Tue, 3 May 2016 06:07:50 +0000 (15:07 +0900)]
ARM: odroidxu3_defconfig: enable usb acm driver config
This patch enables usb cdc-acm driver config to support /dev/ttyACM#
nodes for ACM class devices.
Change-Id: I8531129aeabd504bb5f43a34379a1a2b6634a65c
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Wed, 20 Apr 2016 06:43:54 +0000 (15:43 +0900)]
ARM: odroidxu3_defconfig: enable dm_crypt
This patch enables dm_crypto config instead of building as a
module to manage encrypted disk.
Change-Id: Ic1639439a473cc2cd2e5206de282798d2e9f3973
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Wed, 6 Apr 2016 08:43:23 +0000 (17:43 +0900)]
ARM: odroidxu3_defconfig: enable cp210x usb serial driver
This patch enables cp210x usb serial driver. It is required to use
specific usb serial dongle.
Change-Id: I1e0a991ec4e467fd236a1806d672a42faa996081
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Kunhoon Baik [Wed, 30 Mar 2016 08:59:31 +0000 (17:59 +0900)]
avoid not-allowable mutex lock condition
Change-Id: Icd2c90535687558aa3f294471edb865ef178a5b4
Signed-off-by: Kazimierz Krosman <k.krosman@samsung.com>
Paul Osmialowski [Thu, 9 Jul 2015 16:27:32 +0000 (18:27 +0200)]
packaging: enable KDBUS for odroidxu3
CONFIG_KDBUS=y line added to odroidxu3_defconfig in the exact spot where it is
usually placed in .config file.
Change-Id: I019070af680aa8f1316cd2c2d069731d19f7c5b4
Signed-off-by: Paul Osmialowski <p.osmialowsk@samsung.com>
Lukasz Skalski [Mon, 24 Aug 2015 16:54:46 +0000 (18:54 +0200)]
kdbus: disable internal kdbus policy
Possibilities of connections to own, see and talk to well-known names
are already restricted by LSM hooks.
Change-Id: I62d86a506a85e6c48bdd3e0f8b11f1aa5a918c75
Signed-off-by: Lukasz Skalski <l.skalski@samsung.com>
Chanwoo Choi [Tue, 29 Dec 2015 01:42:39 +0000 (10:42 +0900)]
clk: samsung: exynos5420: Add pll_rate_table and clock id for EPLL
This patch add the clock id of EPLL to handle it on devicetree file
and the rate tables. EPLL is used as root clock of ASS (Audio Subsystem).
Change-Id: Iefcbd5ea4cb911a3b5d75888286926773a98af54
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Marek Szyprowski [Tue, 26 Jan 2016 08:45:13 +0000 (09:45 +0100)]
drm/exynos: mixer: add experimental support for 1024x600@43Hz mode
This patch adds experimental configuration data for HDMI PHY for 32MHz
pixel clock modes. This enables support for WaveShare 7inch HDMI LCD (C)
HDMI panel.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Change-Id: I2f711ef21ce21da58b8efaf6f6dd28c5e2d2e8fc
Seung-Woo Kim [Mon, 31 Aug 2015 03:59:17 +0000 (12:59 +0900)]
drm/exynos: rotator: remove unnecessary cur_buf_id
After commit
2af026584c81faa37f26b86713d6331ddf70e3f3,
'drm/exynos: ipp: introduce last_buf_id', each driver do not need
to handler buf_id for the event. So this patch removes unnecessary
cur_buf_id from rotator.
Change-Id: Idd80765c41260ae6ce4488e56b0d4beaea76229a
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Marek Szyprowski [Tue, 1 Sep 2015 09:23:09 +0000 (11:23 +0200)]
ARM: DTS: exynos5420: add GSCL block parent clock management to pm domain
Add support for restoring GSCALLER parent clocks configuration when GSCL
power domain is turned on.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Marek Szyprowski [Tue, 1 Sep 2015 09:22:18 +0000 (11:22 +0200)]
clk: samsung: exynos5422: add missing parent GSCL block clocks
This patch adds clocks, which are required for preserving parent clock
configuration on GSCALLER power domain on/off.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Marek Szyprowski [Mon, 31 Aug 2015 11:52:43 +0000 (13:52 +0200)]
clk: samsung: exynos5422: fix MFC clock hierarchy parent
Proper source for MFC block is mout_user_aclk333 (in datasheet named
USER_MUX_ACLK_333), not the output of CLKDIV_ACLK_333 MUX.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Junghak Sung [Wed, 16 Sep 2015 06:23:34 +0000 (15:23 +0900)]
ARM: odroidxu3_defconfig: enable UACCESS_WITH_MEMCPY
Enable CONFIG_UACCESS_WITH_MEMCPY for odroid-xu3.
Fix an issue that sometimes TS data is broken when DVB demux pass the data
to user-space by using copy_to_user.
Change-Id: I7994f193871e70afe31df9c7abdd75b8909b587d
Signed-off-by: Junghak Sung <jh1009.sung@samsung.com>
Seung-Woo Kim [Mon, 7 Dec 2015 09:45:35 +0000 (18:45 +0900)]
ARM: odroidxu3_defconfig: enable zram feature
This patch enables zram feature which is used by Tizen resourced.
Change-Id: I3f35f1c53ce60d64263064ed9b5b8221e1b63bb4
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Joonyoung Shim [Tue, 25 Aug 2015 09:17:16 +0000 (18:17 +0900)]
ARM: odroidxu3_defconfig: enable CONFIG_USB_RTL8152
Enable CONFIG_USB_RTL8152 for Odroid-XU4.
Change-Id: Iab87b058f01c0b8cd376d1fa4d84099ab412ba9a
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Seung-Woo Kim [Mon, 6 Jul 2015 07:39:25 +0000 (16:39 +0900)]
ARM: odroidxu3_defconfig: enable rt2x00 wifi usb drivers
This patch enables rt2x00 wifi usb drivers to support rt5572n.
Change-Id: I1d7f9c71e9cb60c83986f4e90cb1edd7557333df
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Joonyoung Shim [Tue, 25 Aug 2015 09:08:29 +0000 (18:08 +0900)]
ARM: dts: Add Odroid-XU4 support
The Odroid-XU4 is almost the same as XU3, except usb otg, DP, audio
codec and power monitoring sensors. This patch makes common dtsi file
and dts file for XU4.
We will add more features on dts for XU4 later.
Change-Id: I6536b9cfa4a4441e392bfe17011968be64c97b3e
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Joonyoung Shim [Mon, 24 Aug 2015 07:52:32 +0000 (16:52 +0900)]
ARM: odroidxu3_defconfig: disable CONFIG_RTC_DRV_S3C
Odroid-XU3 board has two rtc devices - SoC rtc(rtc-s3c) and pmic rtc
(rtc-s5m), so two device nodes for rtc like /dev/rtc0 and /dev/rtc1 will
be created.
The pmic rtc can keep time via rtc backup battery, so tizen platform
will want to use pmic rtc than SoC rtc but it can't know which device
node is for pmic rtc.
This patch disables CONFIG_RTC_DRV_S3C, then tizen platform can use only
pmic rtc.
Change-Id: Ie4256d547c9263c6bcb0302aacd7fbd3b47a4048
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Joonyoung Shim [Tue, 11 Aug 2015 10:29:11 +0000 (19:29 +0900)]
rtc: s3c: remove unnecessary NULL assignment
It's unnecessary the code that assigns info->rtc_clk to NULL in
s3c_rtc_remove.
Change-Id: I6a735e4fc010a208068305ee8ccd9c5f0cdaa6ad
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Joonyoung Shim [Tue, 11 Aug 2015 07:15:53 +0000 (16:15 +0900)]
rtc: s3c: add missing clk control
It's missed to call clk_unprepare() about info->rtc_src_clk in
s3c_rtc_remove and to call clk_disable_unprepare about info->rtc_clk in
error routine of s3c_rtc_probe.
Change-Id: Ia338db2dd1be2d9fc21d3455f91fba1dbff01a89
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Krzysztof Kozlowski [Sat, 30 May 2015 06:33:21 +0000 (15:33 +0900)]
ARM: dts: odroidxu3: Enable wake alarm of S2MPS11 RTC
The IRQB of S2MPS11 PMIC is wired to XEINT4 (GPX0-4) through pull-up
resistor.
Add interrupt properties and pinctrl configuration to enable RTC wake
alarm of rtc-s5m driver. This also removes a warning:
sec_pmic 4-0066: No interrupt specified, no interrupts
Change-Id: I3aa4d802ca9ff19f7b9cda2bbb178476aca19a9a
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Markus Reichl [Sun, 3 May 2015 16:34:29 +0000 (18:34 +0200)]
ARM: dts: add 'rtc_src' clock to rtc node for exynos5422-odroidxu3
The Exynos5422 SoC has a s3c6410 RTC where the source clock
is now a mandatory property.
This patch fixes probe failure of s3c-rtc on Odroid-XU3 boards.
Change-Id: Ie197965fb99f980deffddb96821f4c8a00bf69b8
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Tested-by: Anand Moon <linux.amoon@gmail.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Markus Reichl [Tue, 31 Mar 2015 11:57:20 +0000 (13:57 +0200)]
clk: samsung: Add bindings for 32kHz clocks from s2mps11
This creates include/dt-bindings/clock/samsung,s2mps11.h with
the three 32kHz clock outputs from the s2mps11 mfd.
Change-Id: I2e6de74e55b980d56f192344d712f1caca1a7ed9
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski.k@gmail.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Marek Szyprowski [Mon, 9 Feb 2015 07:25:41 +0000 (08:25 +0100)]
ARM: EXYNOS: use PS_HOLD based poweroff for all supported SoCs
PS_HOLD based power off procedure is common for all Exynos SoCs,
so use it for every Exynos SoCs.
Change-Id: I4c71a13430f088c9709fa6067b47a8da34f5da5e
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Chanwoo Choi [Fri, 17 Jul 2015 11:22:27 +0000 (20:22 +0900)]
ARM: dts: Add MSHC2 dt node for Exynos3250 SoC
This patch add the MSHC2 (Mobile Storage Host Controller) devicetree node for
Exynos3250 SoC.
Change-Id: Ia8850063ad90b986b1371952c879676a608fe3f1
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Chanwoo Choi [Fri, 17 Jul 2015 05:49:08 +0000 (14:49 +0900)]
ARM: dts: Add UART2 dt node for Exynos3250 SoC
This patch add the uart2 devicetree node for Exynos3250 SoC.
Change-Id: I28dd84bc645e26f14b7d0c7d630870cc812dccd8
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Chanwoo Choi [Fri, 17 Jul 2015 11:48:38 +0000 (20:48 +0900)]
clk: samsung: exynos3250: Add MMC2 clock
This patch add the MMC2 clocks (mux, divider, gate) of Exynos3250 SoC.
Change-Id: Ib0c194e09f6ed171ba1a84a35a96f651b615666f
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Chanwoo Choi [Fri, 17 Jul 2015 05:51:01 +0000 (14:51 +0900)]
clk: samsung: exynos3250: Add UART2 clock
This patch add the UART2 clocks (mux, divider, gate) of Exynos3250 SoC.
Change-Id: I5b013ed835a3985659f956b2bd3e64dbeeca7369
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Marek Szyprowski [Thu, 2 Jul 2015 08:57:15 +0000 (10:57 +0200)]
Revert "[media] s5p-mfc: set allow_zero_bytesused flag for vb2_queue_init"
This reverts commit
e6c9dec3e7d68c477768e2955c7f8ed78a09bfd6.
Joonyoung Shim [Wed, 1 Jul 2015 04:14:57 +0000 (13:14 +0900)]
drm/exynos: fix vsync interrupt clear rountine of mixer
INT_EN_VSYNC bit is not used when we clear vsync interrupt but
INT_STATUS_VSYNC bit should be related.
Also, if we want to enable vsync interrupt, we should write 1 in
INT_CLEAR_VSYNC bit before we set INT_EN_VSYNC bit. It will clear prior
vsync interrupt. You can check it from exynos mixer user manual.
Change-Id: Ide955d5cb966e49883c51d8fab0eba51897bac7a
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Joonyoung Shim [Mon, 8 Jun 2015 06:10:31 +0000 (15:10 +0900)]
drm/exynos: mixer: set the framebuffer source size by 0 when a layer is disabled
Repeately turning on and off a layer, sometimes page fault occurs. This
problem seems to happen, because of H/W malfunction during turning on
the layer. But it can be solved by setting the framebuffer source size
by 0.
Kernel dump:
[ 24.646472] PAGE FAULT occurred at 0x23000000 by
14650000.sysmmu(Page table base: 0x6d924000)
[ 24.653515] Lv1 entry: 0x6e3b1001
[ 24.656945] ------------[ cut here ]------------
[ 24.661485] kernel BUG at drivers/iommu/exynos-iommu.c:358!
[ 24.667030] Internal error: Oops - BUG: 0 [#1] PREEMPT SMP ARM
[ 24.672836] Modules linked in:
[ 24.675872] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 4.0.0-00007-g838e0df #136
[ 24.683145] Hardware name: SAMSUNG EXYNOS (Flattened Device Tree)
[ 24.689214] task:
c0e1aff0 ti:
c0e0c000 task.ti:
c0e0c000
[ 24.694597] PC is at exynos_sysmmu_irq+0x1b8/0x2c4
[ 24.699358] LR is at vprintk_emit+0x2a0/0x550
[ 24.703684] pc : [<
c036e530>] lr : [<
c00705d0>] psr:
60070193
[ 24.703684] sp :
c0e0dd90 ip :
00000000 fp :
c0e0ddcc
[ 24.715121] r10:
ee22e610 r9 :
00000000 r8 :
ee22e628
[ 24.720321] r7 :
ed875810 r6 :
23000000 r5 :
ed924000 r4 :
00000000
[ 24.726820] r3 :
c0e98098 r2 :
00000000 r1 :
00000000 r0 :
ed6819c0
[ 24.733321] Flags: nZCv IRQs off FIQs on Mode SVC_32 ISA ARM Segment kernel
[ 24.740685] Control:
10c5387d Table:
6cb8c06a DAC:
00000015
[ 24.746403] Process swapper/0 (pid: 0, stack limit = 0xc0e0c210)
[ 24.752383] Stack: (0xc0e0dd90 to 0xc0e0e000)
[ 24.756718] dd80:
c0e0dd9c c0932868 ffff28da 6d924000
[ 24.764864] dda0:
ffff2990 ee22d8c0 ee22f060 00000049 c0e34e34 c0e0c000 00000000 00000000
[ 24.773009] ddc0:
c0e0de14 c0e0ddd0 c0071fd8 c036e384 ffffffff 7fffffff c0e0ddf4 ee22f000
[ 24.781155] dde0:
c0e95dfc c0e95de8 c0e0de14 ee22f000 ee22f060 ee22d8c0 c0e34e34 ee004670
[ 24.789300] de00:
ee010800 c0e0df00 c0e0de34 c0e0de18 c007221c c0071f80 ee22f000 ee22f060
[ 24.797446] de20:
00000017 c0e34e34 c0e0de4c c0e0de38 c007520c c00721dc 00000049 ee0283c0
[ 24.805591] de40:
c0e0de64 c0e0de50 c0071540 c0075144 0000001c ee0283c0 c0e0de8c c0e0de68
[ 24.813737] de60:
c02fe7e8 c0071510 00000017 00000000 00000017 00000000 00000001 ee010800
[ 24.821882] de80:
c0e0dea4 c0e0de90 c0071540 c02fe750 c0e08a1c 00000000 c0e0ded4 c0e0dea8
[ 24.830028] dea0:
c0071880 c0071510 c0e0df00 f000200c 00000017 c0e140a8 c0e0df00 f0002000
[ 24.838173] dec0:
c0e96374 c0936d0c c0e0defc c0e0ded8 c0008734 c0071800 c0010d88 60070013
[ 24.846319] dee0:
ffffffff c0e0df34 00000001 c0e96374 c0e0df54 c0e0df00 c0014780 c0008700
[ 24.854464] df00:
00000001 00000000 00000000 c0020720 c0e0c000 c0e13530 00000000 00000000
[ 24.862610] df20:
00000001 c0e96374 c0936d0c c0e0df54 c0e0df58 c0e0df48 c0010d84 c0010d88
[ 24.870755] df40:
60070013 ffffffff c0e0df94 c0e0df58 c00626d8 c0010d4c 00000001 c0eb1f00
[ 24.878901] df60:
c0e95ab0 c0e0df70 c0e1353c c0e0a580 00000002 c0e13e84 c0e09b88 c0e0df58
[ 24.887046] df80:
c092e1b8 ffffffff c0e0dfac c0e0df98 c0928880 c00622fc c0e13e10 c0eb1f00
[ 24.895192] dfa0:
c0e0dff4 c0e0dfb0 c0d57d2c c09287f8 ffffffff ffffffff c0d576ec 00000000
[ 24.903337] dfc0:
00000000 c0dc1420 00000000 c0eb22d4 c0e134c0 c0dc141c c0e1c20c 4000406a
[ 24.911483] dfe0:
410fc073 00000000 00000000 c0e0dff8 40008074 c0d57968 00000000 00000000
[ 24.919641] [<
c036e530>] (exynos_sysmmu_irq) from [<
c0071fd8>] (handle_irq_event_percpu+0x64/0x25c)
[ 24.928644] [<
c0071fd8>] (handle_irq_event_percpu) from [<
c007221c>] (handle_irq_event+0x4c/0x6c)
[ 24.937483] [<
c007221c>] (handle_irq_event) from [<
c007520c>] (handle_level_irq+0xd4/0x14c)
[ 24.945802] [<
c007520c>] (handle_level_irq) from [<
c0071540>] (generic_handle_irq+0x3c/0x4c)
[ 24.954209] [<
c0071540>] (generic_handle_irq) from [<
c02fe7e8>] (combiner_handle_cascade_irq+0xa4/0x110)
[ 24.963653] [<
c02fe7e8>] (combiner_handle_cascade_irq) from [<
c0071540>] (generic_handle_irq+0x3c/0x4c)
[ 24.973009] [<
c0071540>] (generic_handle_irq) from [<
c0071880>] (__handle_domain_irq+0x8c/0xfc)
[ 24.981676] [<
c0071880>] (__handle_domain_irq) from [<
c0008734>] (gic_handle_irq+0x40/0x78)
[ 24.989994] [<
c0008734>] (gic_handle_irq) from [<
c0014780>] (__irq_svc+0x40/0x74)
[ 24.997440] Exception stack(0xc0e0df00 to 0xc0e0df48)
[ 25.002469] df00:
00000001 00000000 00000000 c0020720 c0e0c000 c0e13530 00000000 00000000
[ 25.010616] df20:
00000001 c0e96374 c0936d0c c0e0df54 c0e0df58 c0e0df48 c0010d84 c0010d88
[ 25.018757] df40:
60070013 ffffffff
[ 25.022234] [<
c0014780>] (__irq_svc) from [<
c0010d88>] (arch_cpu_idle+0x48/0x4c)
[ 25.029595] [<
c0010d88>] (arch_cpu_idle) from [<
c00626d8>] (cpu_startup_entry+0x3e8/0x4bc)
[ 25.037837] [<
c00626d8>] (cpu_startup_entry) from [<
c0928880>] (rest_init+0x94/0x98)
[ 25.045544] [<
c0928880>] (rest_init) from [<
c0d57d2c>] (start_kernel+0x3d0/0x3dc)
[ 25.052992] Code:
e34c30e9 e5932004 e3520000 ca000018 (
e7f001f2)
[ 25.059058] ---[ end trace
91806a51727d6586 ]---
Change-Id: Ic134f206721e33335962d7e941741331ec72672b
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Signed-off-by: Hyungwon Hwang <human.hwang@samsung.com>
Joonyoung Shim [Fri, 15 May 2015 07:29:00 +0000 (16:29 +0900)]
drm/exynos: workaround to change graphic layers priority
As cannot use video layer, need lower layer than default layer. So make
higher graphic layer 0 priority then graphic layer 1 priority. This is
just workaround, may need to make a interface to change layer priority
for user later.
Change-Id: If63a2f3eef6c164b5b3c3a5c801f9090a6a0a341
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Andrzej Pietrasiewicz [Mon, 18 May 2015 10:14:01 +0000 (12:14 +0200)]
media: s5p-jpeg: Adjust buffer size for Exynos 4412
Eliminate iommu fault during encoding by adjusting image size
used for buffer size computation and ensuring that the buffer is not
overrun.
Change-Id: I4837ef4cd518732af8110725b50e8f4e1bd313a9
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Joonyoung Shim [Thu, 14 May 2015 04:56:45 +0000 (13:56 +0900)]
ARM: odroidxu3_defconfig: enable cpufreq for arm bL
Also disable CONFIG_BL_SWITCHER as any error when does stress test.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Thomas Abraham [Tue, 21 Apr 2015 15:49:05 +0000 (17:49 +0200)]
ARM: Exynos: use generic cpufreq driver for Exynos5800
The new CPU clock type allows the use of generic arm_big_little_dt
cpufreq driver for Exynos5800.
Changes by Bartlomiej:
- split Exynos5800 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Tue, 21 Apr 2015 15:49:04 +0000 (17:49 +0200)]
ARM: dts: Exynos5800: fix CPU OPP
Fix CPU operating points for Exynos5800 (it uses different
voltages than Exynos5420 and supports additional frequencies).
However don't use 2000MHz & 1900MHz OPPs (for A15 cores) and
1400MHz OPP (for A7 cores) until there is a separate DTS for
ODROID-XU3 Lite board (which doesn't support these higher
OPPs).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Tue, 21 Apr 2015 15:49:03 +0000 (17:49 +0200)]
clk: samsung: exynos5800: fix cpu clock configuration data
Fix cpu clock configuration data for Exynos5800 (it uses
higher PCLK_DBG divider values than Exynos5420 and supports
additional frequencies).
Based on Hardkernel's kernel for ODROID-XU3 board.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Tue, 21 Apr 2015 15:49:02 +0000 (17:49 +0200)]
ARM: Exynos: use generic cpufreq driver for Exynos5420
The new CPU clock type allows the use of generic arm_big_little_dt
cpufreq driver for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
- disable cpufreq if big.LITTLE switcher support is enabled
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Tue, 21 Apr 2015 15:49:01 +0000 (17:49 +0200)]
ARM: dts: Exynos5420: add CPU OPP and regulator supply property
For Exynos5420 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5420 support from the original patch
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Tue, 21 Apr 2015 15:49:00 +0000 (17:49 +0200)]
clk: samsung: exynos5420: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5420.
Changes by Bartlomiej:
- split Exynos5420 support from the original patches
- moved E5420_[EGL,KFC]_DIV0() macros to clk-exynos5420.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Tue, 21 Apr 2015 15:48:59 +0000 (17:48 +0200)]
ARM: dts: Exynos5420/5800: add cluster regulator supply properties
Add cluster regulator supply properties as a preparation to
adding generic arm_big_little_dt cpufreq driver support for
Exynos5420 and Exynos5800 based boards.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Mon, 13 Apr 2015 17:47:02 +0000 (19:47 +0200)]
cpufreq: exynos: remove Exynos5250 specific cpufreq driver support
Exynos5250 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
The exynos-cpufreq driver itself is also removed as it is no
longer used/needed after Exynos5250 support removal.
Based on the earlier work by Thomas Abraham.
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Mon, 13 Apr 2015 17:47:01 +0000 (19:47 +0200)]
ARM: Exynos: switch to using generic cpufreq driver for Exynos5250
The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos5250 to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5250 support from the original patch
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Mon, 13 Apr 2015 17:47:00 +0000 (19:47 +0200)]
ARM: dts: Exynos5250: add CPU OPP and regulator supply property
For Exynos5250 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- split Exynos5250 support from the original patch
- added CPU regulator supply property for Google Spring board
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Andreas Farber <afaerber@suse.de>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Mon, 13 Apr 2015 17:46:59 +0000 (19:46 +0200)]
clk: samsung: exynos5250: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos5250.
Changes by Bartlomiej:
- split Exynos5250 support from the original patch
- moved E5250_CPU_DIV[0,1]() macros to clk-exynos5250.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 10 Apr 2015 17:59:02 +0000 (19:59 +0200)]
cpufreq: exynos: remove Exynos4x12 specific cpufreq driver support
Exynos4x12 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
Based on the earlier work by Thomas Abraham.
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 10 Apr 2015 17:59:01 +0000 (19:59 +0200)]
ARM: Exynos: switch to using generic cpufreq driver for Exynos4x12
The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4x12 to using generic cpufreq driver.
This patch also takes care of making ARM_EXYNOS_CPU_FREQ_BOOST_SW
config option depend on cpufreq-dt driver instead of exynos-cpufreq
one and fixes the minor issue present with the old code (support
for 'boost' mode in the exynos-cpufreq driver was enabled for all
supported SoCs even though 'boost' frequency was provided only for
Exynos4x12 ones).
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 10 Apr 2015 17:59:00 +0000 (19:59 +0200)]
ARM: dts: Exynos4x12: add CPU OPP and regulator supply property
For Exynos4x12 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Based on the earlier work by Thomas Abraham.
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Andreas Farber <afaerber@suse.de>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 10 Apr 2015 17:58:59 +0000 (19:58 +0200)]
clk: samsung: exynos4x12: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4x12.
Based on the earlier work by Thomas Abraham.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 10 Apr 2015 17:58:58 +0000 (19:58 +0200)]
cpufreq-dt: add 'boost' mode frequencies support
Add 'boost' mode frequencies support:
- add boost-opps binding to cpufreq-dt driver bindings
- make cpufreq_init() adjust freq_table accordingly
- fix set_target() to handle boost frequencies
- add boost_supported field to struct cpufreq_dt_platform_data
- set dt_cpufreq_driver.boost_supported in dt_cpufreq_probe()
This patch makes cpufreq-dt driver aware of 'boost' mode frequencies
and prepares it for adding support for Exynos4x12 'boost' support.
boost-opps binding is currently limited to cpufreq-dt but once there is
a need for cpufreq wide and/or generic Linux device support for 'boost'
mode cpufreq-dt can be updated to handle the new code without changing
the binding itself.
The decision to make 'boost' mode support limited to cpufreq-dt driver
for now was taken because 'boost' mode is currently a niche feature and
code needed for parsing boost-opps binding is minimal and simple. More
generic (i.e. separate 'boost' OPPs list in struct device and generic
cpufreq convertion of them to freq_table format) support would need far
more code and effort to make it work. Doing it without a demonstrated
real need would be on overengineering IMHO.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 10 Apr 2015 17:58:57 +0000 (19:58 +0200)]
cpufreq / OPP: allow allocation of extra table entries in freq_table
Prefix dev_pm_opp_init_cpufreq_table() with "__" and add a wrapper
for it to keep current users unchanged. Then add an extra_opps
parameter to __dev_pm_opp_init_cpufreq_table() to allow allocation of
extra table entries in freq_table.
This patch is a preparation for adding 'boost' mode frequencies
support to cpufreq-dt driver.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Fri, 3 Apr 2015 16:43:49 +0000 (18:43 +0200)]
cpufreq: exynos: remove Exynos4210 specific cpufreq driver support
Exynos4210 based platforms have switched over to use generic
cpufreq driver for cpufreq functionality. So the Exynos
specific cpufreq support for these platforms can be removed.
Changes by Bartlomiej:
- dropped Exynos5250 support removal for now
- updated exynos-cpufreq.[c,h]
Cc: Viresh Kumar <viresh.kumar@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Fri, 3 Apr 2015 16:43:48 +0000 (18:43 +0200)]
ARM: Exynos: switch to using generic cpufreq driver for Exynos4210
The new CPU clock type allows the use of generic CPUfreq driver.
Switch Exynos4210 to using generic cpufreq driver.
Changes by Bartlomiej:
- removed non-Exynos4210 support for now
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Fri, 3 Apr 2015 16:43:47 +0000 (18:43 +0200)]
ARM: dts: Exynos4210: add CPU OPP and regulator supply property
For Exynos4210 platforms, add CPU operating points and CPU
regulator supply properties for migrating from Exynos specific
cpufreq driver to using generic cpufreq driver.
Changes by Bartlomiej:
- removed Exynos5250 and Exynos5420 support for now
Cc: Kukjin Kim <kgene.kim@samsung.com>
Cc: Doug Anderson <dianders@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Andreas Faerber <afaerber@suse.de>
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Andreas Farber <afaerber@suse.de>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Fri, 3 Apr 2015 16:43:46 +0000 (18:43 +0200)]
clk: samsung: exynos4: add cpu clock configuration data and instantiate cpu clock
With the addition of the new Samsung specific cpu-clock type, the
arm clock can be represented as a cpu-clock type. Add the CPU clock
configuration data and instantiate the CPU clock type for Exynos4210.
Changes by Bartlomiej:
- fixed issue with wrong dividers being setup by Common Clock Framework
(by an addition of CLK_RECALC_NEW_RATES clock flag to mout_apll clock,
without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board), this
was probably meant to be workarounded by use of CLK_GET_RATE_NOCACHE
and CLK_DIVIDER_READ_ONLY clock flags in the original patchset (in
"[PATCH v12 6/6] clk: samsung: remove unused clock aliases and update
clock flags") but using these flags is not sufficient to fix the issue
observed
- removed Exynos5250 and Exynos5420 support for now
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Thomas Abraham [Fri, 3 Apr 2015 16:43:45 +0000 (18:43 +0200)]
clk: samsung: add infrastructure to register cpu clocks
The CPU clock provider supplies the clock to the CPU clock domain. The
composition and organization of the CPU clock provider could vary among
Exynos SoCs. A CPU clock provider can be composed of clock mux, dividers
and gates. This patch defines a new clock type for CPU clock provider and
adds infrastructure to register the CPU clock providers for Samsung
platforms.
Changes by Bartlomiej:
- fixed issue with setting lower dividers before the parent clock speed
was lowered (the issue resulted in lockup on Exynos4210 SoC based
Origen board when "ondemand" cpufreq governor was stress tested)
- fixed missing spin_unlock on error in exynos_cpuclk_post_rate_change()
problem by moving cfg_data search outside of the spin locked area
- removed leftover kfree() in exynos_register_cpu_clock() that could
result in dereferencing the NULL pointer on error
- moved spin_lock earlier in exynos_cpuclk_pre_rate_change() to cover
reading of E4210_SRC_CPU and E4210_DIV_CPU1 registers
- added missing "last chance" checks to wait_until_divider_stable() and
wait_until_mux_stable() (needed in case that IRQ handling took long
time to proceed and resulted in function printing incorrect error
message about timeout)
- moved E4210_CPU_DIV[0,1]() macros just before their only users,
this resulted in moving them from patch #2 to patch #3/6 ("clk:
samsung: exynos4: add cpu clock configuration data and instantiate
cpu clock")
- removed E5250_CPU_DIV[0,1](), E5420_EGL_DIV0() and E5420_KFC_DIV()
macros for now
- added my Copyrights to drivers/clk/samsung/clk-cpu.c
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 3 Apr 2015 16:43:44 +0000 (18:43 +0200)]
clk: add CLK_RECALC_NEW_RATES clock flag for Exynos cpu clock support
This flag is needed to fix the issue with wrong dividers being setup
by Common Clock Framework when using the new Exynos cpu clock support.
The issue happens because clk_core_set_rate_nolock() calls
clk_calc_new_rates(clk, rate) before both pre/post clock notifiers have
a chance to run. In case of Exynos cpu clock support pre/post clock
notifiers are registered for mout_apll clock which is a parent of armclk
cpu clock and dividers are modified in both pre and post clock notifier.
This results in wrong dividers values being later programmed by
clk_change_rate(top). To workaround the problem CLK_RECALC_NEW_RATES
flag is added and it is set for mout_apll clock later so the correct
divider values are re-calculated after both pre and post clock notifiers
had run.
For example when using "performance" governor on Exynos4210 Origen board
the cpufreq-dt driver requests to change the frequency from 1000MHz to
1200MHz and after the change state of the relevant clocks is following:
Without use of CLK_GET_RATE_NOCACHE flag:
fout_apll rate:
1200000000
fout_apll_div_2 rate:
600000000
mout_clkout_cpu rate:
600000000
div_clkout_cpu rate:
600000000
clkout_cpu rate:
600000000
mout_apll rate:
1200000000
armclk rate:
1200000000
mout_hpm rate:
1200000000
div_copy rate:
300000000
div_hpm rate:
300000000
mout_core rate:
1200000000
div_core rate:
1200000000
div_core2 rate:
1200000000
arm_clk_div_2 rate:
600000000
div_corem0 rate:
300000000
div_corem1 rate:
150000000
div_periph rate:
300000000
div_atb rate:
300000000
div_pclk_dbg rate:
150000000
sclk_apll rate:
1200000000
sclk_apll_div_2 rate:
600000000
With use of CLK_GET_RATE_NOCACHE flag:
fout_apll rate:
1200000000
fout_apll_div_2 rate:
600000000
mout_clkout_cpu rate:
600000000
div_clkout_cpu rate:
600000000
clkout_cpu rate:
600000000
mout_apll rate:
1200000000
armclk rate:
1200000000
mout_hpm rate:
1200000000
div_copy rate:
200000000
div_hpm rate:
200000000
mout_core rate:
1200000000
div_core rate:
1200000000
div_core2 rate:
1200000000
arm_clk_div_2 rate:
600000000
div_corem0 rate:
300000000
div_corem1 rate:
150000000
div_periph rate:
300000000
div_atb rate:
240000000
div_pclk_dbg rate:
120000000
sclk_apll rate:
150000000
sclk_apll_div_2 rate:
75000000
Without this change cpufreq-dt driver showed ~10 mA larger energy
consumption when compared to cpufreq-exynos one when "performance"
cpufreq governor was used on Exynos4210 SoC based Origen board.
This issue was probably meant to be workarounded by use of
CLK_GET_RATE_NOCACHE and CLK_DIVIDER_READ_ONLY clock flags in
the original Exynos cpu clock patchset (in "[PATCH v12 6/6] clk:
samsung: remove unused clock aliases and update clock flags" patch)
but usage of these flags is not sufficient to fix the issue observed.
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Bartlomiej Zolnierkiewicz [Fri, 27 Mar 2015 16:32:53 +0000 (17:32 +0100)]
cpufreq: exynos: remove dead ->need_apll_change method
Commit
26ab1c62b6e1 ("cpufreq: exynos5250: Set APLL rate
using CCF API") removed the last user of ->need_apll_change
method. Remove it and then cleanup exynos_cpufreq_scale()
accordingly.
This patch was tested on Exynos4412 SoC based Trats2 board.
There should be no functional changes caused by this patch.
Cc: Sachin Kamat <sachin.kamat@linaro.org>
Cc: Lukasz Majewski <l.majewski@samsung.com>
Cc: Kukjin Kim <kgene@kernel.org>
Signed-off-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Marek Szyprowski [Thu, 16 Apr 2015 09:52:33 +0000 (11:52 +0200)]
media: s5p-jpeg: add RGB565 format to Exynos4 buffer size workaround
JPEG HW can access buffer beyond the image data for images, which width
or height is not properly aligned. This patch adds RGB565 format to
workaround code to solve IOMMU page fault issue. The exact needed buffer
enlargement workaround need to be determined experimentally.
Reported-by: Inha Song <ideal.song@samsung.com>
Suggested-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Inha Song [Thu, 16 Apr 2015 07:59:40 +0000 (16:59 +0900)]
packaging: change version to 4.1
This patch change version to 4.1 from 4.0.0 because of upstream tag.
Change-Id: I6ef7dfedcf1decb07ca5ab6aaec5b5f462f084fa
Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Inha Song [Thu, 16 Apr 2015 07:56:39 +0000 (16:56 +0900)]
packaging: use upstream tags
Change-Id: Ib6eaf6e12ecc8f065b085253dbcc0c538caff511
Signed-off-by: Inha Song <ideal.song@samsung.com>
Inha Song [Tue, 17 Mar 2015 01:58:16 +0000 (10:58 +0900)]
packaging: add spec file to generate odroid-xu3 kernel by GBS
This patch add spec file to generate odroid-xu3 kernel-headers by GBS.
Signed-off-by: Inha Song <ideal.song@samsung.com>
Seung-Woo Kim [Tue, 9 Jun 2015 04:48:17 +0000 (13:48 +0900)]
ARM: odroidxu3_defconfig: enable fuse
This patch enables fuse config to support user file system.
Change-Id: I6543ace82673ab4108ea3154524cee5fb29a4760
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Thu, 14 May 2015 05:08:18 +0000 (14:08 +0900)]
ARM: odroidxu3_defconfig: enable trace and debug configs
This patch enables trace and debug configs to support user trace
request.
Change-Id: I7a63a7cf9d7bb5510434db8ff2fcc4ae8f7938bb
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Thu, 16 Apr 2015 04:29:52 +0000 (13:29 +0900)]
ARM: odroidxu3_defconfig: enable uinput config
This patch enables uinput config to support userland input driver.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Krzysztof Kozlowski [Wed, 11 Mar 2015 10:13:57 +0000 (11:13 +0100)]
ARM: EXYNOS: Fix failed second suspend on Exynos4
On Exynos4412 boards (Trats2, Odroid U3) after enabling L2 cache in
56b60b8bce4a ("ARM: 8265/1: dts: exynos4: Add nodes for L2 cache
controller") the second suspend to RAM failed. First suspend worked fine
but the next one hang just after powering down of secondary CPUs (system
consumed energy as it would be running but was not responsive).
The issue was caused by enabling delayed reset assertion for CPU0 just
after issuing power down of cores. This was introduced for Exynos4 in
13cfa6c4f7fa ("ARM: EXYNOS: Fix CPU idle clock down after CPU off").
The whole behavior is not well documented but after checking with vendor
code this should be done like this (on Exynos4):
1. Enable delayed reset assertion when system is running (for all CPUs).
2. Disable delayed reset assertion before suspending the system.
This can be done after powering off secondary CPUs.
3. Re-enable the delayed reset assertion when system is resumed.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Fixes:
13cfa6c4f7fa ("ARM: EXYNOS: Fix CPU idle clock down after CPU off")
Cc: <stable@vger.kernel.org>
Tested-by: Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com>
Tested-by: Chanwoo Choi <cw00.choi@samsung.com>
Inha Song [Mon, 9 Mar 2015 05:21:18 +0000 (14:21 +0900)]
ARM: odroidxu3_defconfig: update configs to Linux 4.1
This patch updates odroid configs to Linux 4.1 for tizen.
Change-Id: Iaf3770b31bdb38ec72bb844e4ea62e9373de877f
Signed-off-by: Inha Song <ideal.song@samsung.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Joonyoung Shim [Wed, 8 Apr 2015 07:23:52 +0000 (16:23 +0900)]
ARM: dts: exynos5420: fix clk of mali node
Need only CLK_G3D gate clock for mali and use clk_mali name to control
the clock from mali core codes.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Joonyoung Shim [Wed, 8 Apr 2015 07:22:16 +0000 (16:22 +0900)]
gpu: arm: midgard: remove clk and regulator control from exynos5422
Clk and regulator of mali will be controlled mali core codes.
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Marek Szyprowski [Thu, 2 Apr 2015 11:18:58 +0000 (13:18 +0200)]
arm: exynos5420.dts: add FIMC_3AA async bridge clock to GSC power domain
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Seung-Woo Kim [Tue, 6 Jan 2015 08:32:34 +0000 (17:32 +0900)]
ARM: dts: add lcd-wb flag to gsc dt nodes for Odroid XU3 board
This patch adds lcd-wb binding flag to gsc dt nodes to bind with
exynos drm gsc driver.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Mon, 23 Mar 2015 05:25:40 +0000 (14:25 +0900)]
ARM: dts: exynos5422-odroidxu3: add gpio key dt node
This patch adds gpio key dt node for power button. The dt nodes
are ported from https://github.com/hardkernel/linux.git
+refs/heads/odroidxu3-3.10.y.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Seung-Woo Kim [Mon, 23 Mar 2015 05:18:52 +0000 (14:18 +0900)]
ARM: dts: exynos5422-odroidxu3: add leds dt nodes
This patch adds leds dt nodes to support rgb led devices. The dt
nodes are ported from https://github.com/hardkernel/linux.git
+refs/heads/odroidxu3-3.10.y.
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Robert Baldyga [Mon, 4 Aug 2014 06:56:32 +0000 (08:56 +0200)]
ARM: dts: add odroid-usbotg extcon support for odroid platform
This patch adds odroid-usbotg extcon dt node for odroid-u3 and
odroid-x.
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
[Adjust gpio dt node name with the odroid-usbotg driver]
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Robert Baldyga [Mon, 23 Feb 2015 14:27:13 +0000 (15:27 +0100)]
ARM: dts: exynos5422-odroidxu3: make usbdrd3 extcon client
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Robert Baldyga [Wed, 4 Mar 2015 12:46:59 +0000 (13:46 +0100)]
ARM: dts: exynos5420: add snps,dis_u3_susphy_quirk to dwc3 controllers
It's needed for proper role switching in OTG mode.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Robert Baldyga [Mon, 9 Mar 2015 10:12:48 +0000 (11:12 +0100)]
ARM: dts: exynos5420: set usb3_lpm_capable in dwc3 controllers
These hardware has LPM and we want to use it.
This will be necessary for OTG role switching.
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Robert Baldyga [Mon, 9 Mar 2015 10:09:43 +0000 (11:09 +0100)]
ARM: dts: exynos5422-odroidxu3: add odroid-usbotg extcon support
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Robert Baldyga [Mon, 9 Mar 2015 10:00:47 +0000 (11:00 +0100)]
extcon: add extcon-odroid-usbotg driver
This patch adds extcon driver for Odroid U3, U3+ and X boards.
It recognizes type of USB cable connected to Odroid board basing on
two signal lines VBUS_DET and OTG_ID (the second one is present only
on Odroid U3+ board).
Following table of states presents relationship between this signals
and detected cable type:
state | VBUS_DET | OTG_ID
-------------------------------
USB | H | H
invalid | H | L
disconn. | L | H
USB-Host | L | L
This driver is based on extcon-gpio driver.
Signed-off-by: Łukasz Stelmach <l.stelmach@samsung.com>
Signed-off-by: Robert Baldyga <r.baldyga@samsung.com>
Marek Szyprowski [Mon, 9 Mar 2015 09:27:57 +0000 (10:27 +0100)]
ARM: dts: exynos5420: add iommu support to jpeg devices
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Andrzej Pietrasiewicz [Fri, 6 Mar 2015 10:32:39 +0000 (11:32 +0100)]
ARM: dts: exynos5420: add nodes for jpeg codec
Signed-off-by: Andrzej Pietrasiewicz <andrzej.p@samsung.com>
Inha Song [Fri, 13 Feb 2015 01:12:37 +0000 (10:12 +0900)]
ARM: dts: Support audio on Exynos5422-odroidxu3 using simple-audio-card
Add MAX98090 audio codec, I2S interface and the sound nodes to support
audio on Exynos5422 SoC Based Odroid-XU3 board. Now we can support audio
in Odroid-XU3 board using simple-audio-card DT binding.
Signed-off-by: Inha Song <ideal.song@samsung.com>
Marek Szyprowski [Thu, 31 Jul 2014 11:43:17 +0000 (13:43 +0200)]
ARM: dts: exynos4412-odroid*: enable MFC device
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Jaehoon Chung [Thu, 26 Feb 2015 08:16:30 +0000 (17:16 +0900)]
ARM: dts: exynos5422-odroidxu3: use cd-gpio method to detect sd-card
To detect sd-card use the cd-gpio method.
It can decrease the interrupt for detecting sd-card.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Thu, 26 Feb 2015 07:17:48 +0000 (16:17 +0900)]
ARM: dts: exynos5422-odroidxu3: support HS400 mode for eMMC
Add "mmc_hs400_1_8v" property to use HS400 mode.
(HS400 mode is supported since eMMC5.0.)
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Jaehoon Chung [Thu, 26 Feb 2015 06:39:03 +0000 (15:39 +0900)]
ARM: dts: exynos5422-odroidxu3: support HS200 mode for eMMC
Add "mmc-hs200_1_8v" property to use HS200 mode.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Marek Szyprowski [Wed, 18 Feb 2015 11:11:00 +0000 (12:11 +0100)]
ARM: dts: exynos4: add nodes for jpeg codec
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Joonyoung Shim [Tue, 27 Jan 2015 06:13:51 +0000 (15:13 +0900)]
ARM: dts: exynos5422-odroidxu3: add pwm-fan node
Usage:
echo [0 - 255] > /sys/devices/platform/pwm-fan/hwmon/hwmon0/pwm1
Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com>
Jaehoon Chung [Fri, 23 Jan 2015 09:16:54 +0000 (18:16 +0900)]
regulator: s2mps11: add shutdown function
This needs for poweroff on odroid xu3 board.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
projects / platform / kernel / linux-exynos.git / log