Vang Thao [Wed, 2 Feb 2022 23:33:40 +0000 (15:33 -0800)]
[AMDGPU] Fix scheduler live-ins with debug inst at start of block
GCNDownwardRPTracker RPTracker.reset() skips debug instructions for NextMI so RPTracker.getNext() will never give the beginning of a sched region if it is a debug value. In this case we will never set the live-ins for that block.
Add check to see if getNext also equals the MI after skipping debug instructions.
Reviewed By: rampitec
Differential Revision: https://reviews.llvm.org/D118853
Mircea Trofin [Thu, 3 Feb 2022 17:07:42 +0000 (09:07 -0800)]
[nfc][regalloc] const LiveIntervals within the allocator
Once built, LiveIntervals are immutable. This patch captures that.
Differential Revision: https://reviews.llvm.org/D118918
Philip Reames [Thu, 3 Feb 2022 20:22:25 +0000 (12:22 -0800)]
[tests] Add coverage for SLP reschedule event
This is slightly reduced from the crash reported against D117951.
Kazu Hirata [Thu, 3 Feb 2022 20:22:23 +0000 (12:22 -0800)]
[SampleProfile] Reduce indentation with an early return (NFC)
Bjorn Pettersson [Mon, 31 Jan 2022 12:49:35 +0000 (13:49 +0100)]
[CodeGenPrepare] Avoid out-of-bounds shift
AddressingModeMatcher::matchOperationAddr may attempt to shift a
variable by the same amount of steps as found in the IR in a SHL
instruction. This was done without considering that there could be
undefined behavior in the IR, so the shift performed when compiling
could end up having undefined behavior as well.
This patch avoid UB in the codegenprepare by making sure that we
limit the shift amount used, in a similar way as already being done
in CodeGenPrepare::optimizeLoadExt.
Differential Revision: https://reviews.llvm.org/D118602
Stanislav Mekhanoshin [Thu, 3 Feb 2022 19:44:45 +0000 (11:44 -0800)]
[AMDGPU] Fix windows build warning with IMMBitSelConst. NFC.
VS gives this warning for an integer constant:
AMDGPUGenDAGISel.inc(214687): warning C4334: '<<': result of 32-bit
shift implicitly converted to 64 bits (was 64-bit shift intended?)
John Ericson [Wed, 2 Feb 2022 15:37:13 +0000 (15:37 +0000)]
[lld][clang][cmake] Clean up a few things
- If not using `llvm-config`, `LLVM_MAIN_SRC_DIR` now has a sane default
- `LLVM_CONFIG_PATH` will continue to work for LLD for back compat.
- More quoting of paths in an abundance of caution.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D118792
River Riddle [Thu, 3 Feb 2022 19:45:39 +0000 (11:45 -0800)]
[mlir:Vector][NFC] Remove unnecessary dependency on Affine
Zequan Wu [Thu, 3 Feb 2022 01:12:40 +0000 (17:12 -0800)]
[LLDB] Fix window bot failure
This attempts to fix this bot failure: https://lab.llvm.org/buildbot/#/builders/83/builds/14736 caused by D118750 by un-xfail those expected failed tests.
Differential Revision: https://reviews.llvm.org/D118866
Caroline Concatto [Thu, 13 Jan 2022 16:52:41 +0000 (16:52 +0000)]
[AArch64][SVE] Add more folds to make use of gather/scatter with 32-bit indices
In AArch64ISelLowering.cpp this patch implements this fold:
1) GEP (%ptr, SHL ((stepvector(A) + splat(%offset))) << splat(B)))
into GEP (%ptr + (%offset << B), step_vector (A << B))
The above transform simplifies the index operand so that it can be expressed
as i32 elements.
This allows using only one gather/scatter assembly instruction instead of two.
Patch by Paul Walker (@paulwalker-arm).
Depends on D117900
Differential Revision: https://reviews.llvm.org/D118345
Florian Mayer [Thu, 3 Feb 2022 01:07:19 +0000 (17:07 -0800)]
[NFC] [hwasan] use InstIterator
Differential Revision: https://reviews.llvm.org/D118865
Keith Smiley [Thu, 3 Feb 2022 19:05:18 +0000 (19:05 +0000)]
[llvm-libtool-darwin] Remove var to fix use
This seems to have been moved so the second use is invalid on Linux but
not macOS
Florian Mayer [Thu, 3 Feb 2022 18:19:26 +0000 (10:19 -0800)]
[nfc] [mte] use InstrIter.
this improves code clarity.
Caroline Concatto [Thu, 13 Jan 2022 16:52:41 +0000 (16:52 +0000)]
[AArch64][SVE] Fold gather/scatter with 32bits when possible
In AArch64ISelLowering.cpp this patch implements this fold:
GEP (%ptr, (splat(%offset) + stepvector(A)))
into GEP ((%ptr + %offset), stepvector(A))
The above transform simplifies the index operand so that it can be expressed
as i32 elements.
This allows using only one gather/scatter assembly instruction instead of two.
Patch by Paul Walker (@paulwalker-arm).
Depends on D118459
Differential Revision: https://reviews.llvm.org/D117900
River Riddle [Thu, 3 Feb 2022 18:41:14 +0000 (10:41 -0800)]
[mlir][NFC] Split MlirQuant into proper IR/Utils/Transforms libraries
This matches the structure of other dialects, and also removes
unnecessary dependencies from the core dialect lib.
Mahesh Ravishankar [Thu, 3 Feb 2022 18:40:26 +0000 (18:40 +0000)]
[mli][Linalg] NFC: Refactor methods in `ElementwiseOpFusion`.
Reorder the methods and patterns to move related patterns/methods
closer (textually).
Reviewed By: gysit
Differential Revision: https://reviews.llvm.org/D118870
Dmitry Vyukov [Thu, 3 Feb 2022 15:04:34 +0000 (16:04 +0100)]
sanitizer_common: fix __sanitizer_get_module_and_offset_for_pc signature mismatch
This fixes the following error:
sanitizer_interface_internal.h:77:7: error: conflicting types for
'__sanitizer_get_module_and_offset_for_pc'
int __sanitizer_get_module_and_offset_for_pc(
common_interface_defs.h:349:5: note: previous declaration is here
int __sanitizer_get_module_and_offset_for_pc(void *pc, char *module_path,
I am getting it on a code that uses sanitizer_common (includes internal headers),
but also transitively gets includes of the public headers in tests
via an internal version of gtest.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D118910
mydeveloperday [Thu, 3 Feb 2022 18:36:56 +0000 (18:36 +0000)]
[clang-format] regression from clang-format v13
https://github.com/llvm/llvm-project/issues/53567
The following source
```
namespace A {
template <int N> struct Foo<char[N]> {
void foo() { std::cout << "Bar"; }
}; // namespace A
```
is incorrectly formatted as:
```
namespace A {
template <int N> struct Foo<char[N]>{void foo(){std::cout << "Bar";
}
}
; // namespace A
```
This looks to be caused by https://github.com/llvm/llvm-project/commit/
5c2e7c9ca043d92bed75b08e653fb47c384edd13
Reviewed By: curdeius
Differential Revision: https://reviews.llvm.org/D118911
Keith Smiley [Thu, 3 Feb 2022 01:19:58 +0000 (17:19 -0800)]
[llvm-libtool-darwin] Improve warning message for no symbols
This more closely mirrors apple's libtool, and also potentially makes it
clearer for multi-arch archives where the issue lies.
Differential Revision: https://reviews.llvm.org/D118867
Joseph Huber [Wed, 2 Feb 2022 18:06:55 +0000 (13:06 -0500)]
[Clang][Docs] Add documention for new OpenMP offloading driver
This patch adds more documentation for the OpenMP offloading driver.
This includes a new file that describes the overall pipeline becuase
that was not previously explained in full elsewhere.
Reviewed By: ABataev
Differential Revision: https://reviews.llvm.org/D118815
Amir Ayupov [Wed, 2 Feb 2022 23:37:32 +0000 (15:37 -0800)]
[Support][NFC] Don’t duplicate class or function name in comment
Refactor comments in CommandLine.h to follow the Coding Style rule
Reviewed By: MaskRay, serge-sans-paille
Differential Revision: https://reviews.llvm.org/D118859
Marek Kurdej [Thu, 3 Feb 2022 17:46:35 +0000 (18:46 +0100)]
[clang-format] Avoid merging macro definitions.
Fixes https://github.com/llvm/llvm-project/issues/42087.
Reviewed By: HazardyKnusperkeks, owenpan
Differential Revision: https://reviews.llvm.org/D118879
Marek Kurdej [Thu, 3 Feb 2022 17:29:53 +0000 (18:29 +0100)]
[clang-format] Avoid adding space after the name of a function-like macro when the name is a keyword.
Fixes https://github.com/llvm/llvm-project/issues/31086.
Before the code:
```
#define if(x)
```
was erroneously formatted to:
```
#define if (x)
```
Reviewed By: HazardyKnusperkeks, owenpan
Differential Revision: https://reviews.llvm.org/D118844
Craig Topper [Thu, 3 Feb 2022 17:26:34 +0000 (09:26 -0800)]
[RISCV] Add FMV_X_W and FMV_X_H to RISCVSExtWRemoval.
Add -target-abi to sextw-removal.ll RUN lines to show benefit on
new test case.
Stanislav Mekhanoshin [Wed, 2 Feb 2022 23:51:11 +0000 (15:51 -0800)]
[AMDGPU] HWRegs TMA and TBA also supported on gfx9
Differential Revision: https://reviews.llvm.org/D118860
Sanjay Patel [Thu, 3 Feb 2022 17:05:40 +0000 (12:05 -0500)]
[x86] add minimal test for sbb idiom and CPU capabilities; NFC
D116804 proposes to alter codegen on this example based on
CPU tuning, so check a variety of models to confirm it works
as expected. We already have this test mixed in with several
others in another test file, but it seems wasteful to add so
many RUN lines to check this difference over and over again.
Sanjay Patel [Thu, 3 Feb 2022 16:56:04 +0000 (11:56 -0500)]
[x86] remove CPU requirement for RUN line in test file; NFC
A proposed change ( D118843 ) that would affect this test
will not require a specific CPU model to show a difference.
Florian Mayer [Wed, 2 Feb 2022 23:44:41 +0000 (15:44 -0800)]
[hwasan] add musttail IR test.
we currently only have a test at the clang level
Reviewed By: morehouse
Differential Revision: https://reviews.llvm.org/D118856
Mircea Trofin [Thu, 3 Feb 2022 17:10:06 +0000 (09:10 -0800)]
Revert "[nfc][mlgo] De-const a parameter"
This reverts commit
bc3b372161716a4c4845d47a877e4892df0d08da.
The planned change that would have needed non-const MachineFunction refs
isn't needed after all.
Philip Reames [Thu, 3 Feb 2022 17:10:42 +0000 (09:10 -0800)]
[SLP] Fix a typo in comment
Pavel Labath [Thu, 3 Feb 2022 17:06:19 +0000 (18:06 +0100)]
[lldb] Fix windows&mac builds for
c34698a811b13
Thomas Symalla [Fri, 28 Jan 2022 11:27:54 +0000 (12:27 +0100)]
[AMDGPU] Introduce new ISel combine for trunc-slr patterns
In some cases, when selecting a (trunc (slr)) pattern, the slr gets translated
to a v_lshrrev_b3e2_e64 instruction whereas the truncation gets selected to
a sequence of v_and_b32_e64 and v_cmp_eq_u32_e64. In the final ISA, this appears
as selecting the nth-bit:
v_lshrrev_b32_e32 v0, 2, v1
v_and_b32_e32 v0, 1, v0
v_cmp_eq_u32_e32 vcc_lo, 1, v0
However, when the value used in the right shift is known at compilation time, the
whole sequence can be reduced to two VALUs when the constant operand in the v_and is adjusted to (1 << lshrrev_operand):
v_and_b32_e32 v0, (1 << 2), v1
v_cmp_ne_u32_e32 vcc_lo, 0, v0
In the example above, the following pseudo-code:
v0 = (v1 >> 2)
v0 = v0 & 1
vcc_lo = (v0 == 1)
would be translated to:
v0 = v1 & 0b100
vcc_lo = (v0 == 0b100)
which should yield an equivalent result.
This is a little bit hard to test as one needs to force the SelectionDAG to
contain the nodes before instruction selection, but the test sequence was
roughly derived from a production shader.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D118461
Chris Lattner [Thu, 3 Feb 2022 05:40:41 +0000 (21:40 -0800)]
[mlir-translate] Teach these tools about --allow-unregistered-dialect
Some translations do work with unregistered dialects, this allows one
to write testcases against them. It works the same way as it does for
mlir-opt.
Differential Revision: https://reviews.llvm.org/D118872
Sunho Kim [Thu, 3 Feb 2022 16:46:49 +0000 (16:46 +0000)]
[AARCH64][NEON] Allow to sink operands for aarch64_neon_pmull
This teaches AArch64TargetLowering::shouldSinkOperands to sink the
operands of aarch64_neon_pmull intrinsic.
Differential Revision: https://reviews.llvm.org/D117944
Augie Fackler [Thu, 3 Feb 2022 16:39:15 +0000 (08:39 -0800)]
[test] check strictest attributes possible for InferFunctionAttrs test
This appears to have all the same attributes as many other functions
in this file, and I think the use of INACCESSIBLEMEMONLY_NOFREE_NOUNWIND
instead of INACCESSIBLEMEMONLY_NOFREE_NOUNWIND_WILLRETURN was an
oversight that meant aligned_alloc's attributes were just going
unchecked. This patch corrects the test defect and now the attributes
inferred on aligned_alloc are actually validated, and the test still
passes.
Differential Revision: https://reviews.llvm.org/D117922
Augie Fackler [Thu, 3 Feb 2022 16:31:44 +0000 (08:31 -0800)]
add IR compatability test for (upcoming) allocsize attribute
Augie Fackler [Thu, 3 Feb 2022 16:30:37 +0000 (08:30 -0800)]
[NFC] MemoryBuiltins: tease out a getFreeFunctionDataForFunction helper
Craig Topper [Thu, 3 Feb 2022 16:30:39 +0000 (08:30 -0800)]
[RISCV] Remove createVirtualRegister from RISCVInstrInfo::movImm.
Based on the discussion in D61884, this was done to enable compressed
instructions by giving freedom to pick a compressible register.
Integer materializing can generate LUI, ADDI, ADDIW, SLLI and some
Zb* instructions. C.LI, C.LUI, C.ADDI, C.ADDIW, and C.SLLI all have a 5-bit
register encoding. The Zb* instructions aren't compressible. Based on
that I don't think compressibility of the register is a concern.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D118741
Kadir Cetinkaya [Thu, 3 Feb 2022 16:26:41 +0000 (17:26 +0100)]
[clang-tidy] Fix LLVM include order check policy
Clang-format LLVM style has a custom include category for gtest/ and
gmock/ headers between regular includes and angled includes. Do the same here.
Fixes https://github.com/llvm/llvm-project/issues/53525.
Differential Revision: https://reviews.llvm.org/D118913
Craig Topper [Thu, 3 Feb 2022 16:23:34 +0000 (08:23 -0800)]
[RISCV] Remove RISCVISD::SPLAT_VECTOR_I64 in favor of RISCVISD::VMV_V_X_VL.
SPLAT_VECTOR_I64 has the same semantics as RISCVISD::VMV_V_X_VL, it
just assumed VLMax instead of carrying a VL operand.
Include order of RISCVInstrInfoVSDPatterns.td and RISCVInstrInfoVVLPatterns.td
has been swapped to avoid moving riscv_vmv_v_x_vl into
RISCVInstrInfoVSDPatterns.td and to allow moving other "_vl" SDNodes back to
RISCVInstrInfoVVLPatterns.td
Reviewed By: frasercrmck
Differential Revision: https://reviews.llvm.org/D118841
Augie Fackler [Thu, 3 Feb 2022 16:21:09 +0000 (08:21 -0800)]
MemoryBuiltins: simplify isLibFreeFunction [NFC]
This is in anticipation of my next patch, where I need to store more information about free functions than just their argument count. It felt invasive enough on this function that it seemed worthwhile to just extract this as its own commit that makes no functional changes.
Differential Revision: https://reviews.llvm.org/D117350
Jay Foad [Thu, 3 Feb 2022 15:27:12 +0000 (15:27 +0000)]
[AMDGPU] Simplify AMDGPUAnnotateUniformValues::visitLoadInst
Always set uniform metadata on the pointer if it is an instruction, but
otherwise do not bother to create a trivial getelementptr instruction,
because AMDGPUInstrInfo::isUniformMMO can already detect that various
non-instruction pointers are uniform.
Most of the test case churn is from tests that used undef as a pointer,
which AMDGPUInstrInfo::isUniformMMO treats as uniform.
Differential Revision: https://reviews.llvm.org/D118909
Bixia Zheng [Wed, 2 Feb 2022 16:40:33 +0000 (08:40 -0800)]
[mlir][taco] Uses sparse_tensor.new to read tensor input data from files.
Replace the Python implementation for reading tensor input data from files with
create_sparse_tensor that uses sparse_tensor.new.
The MLIR TNS format has two extra meta data lines. Add the extra meta data to a
test data file.
Implement TACO tensor methods evaluate and unpack.
Add unit tests.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D118803
Abhishek Varma [Thu, 3 Feb 2022 16:09:51 +0000 (17:09 +0100)]
[MLIR][SCF] Remove loop invariant arguments of scf.while
-- This commit adds a canonicalization pattern on scf.while to remove
the loop invariant arguments.
-- An argument is considered loop invariant if the iteration argument value is
the same as the corresponding one being yielded (at the same position) in both
the before/after block of scf.while.
-- For the arguments removed, their use within scf.while and their corresponding
scf.while's result are replaced with their corresponding initial value.
Signed-off-by: Abhishek Varma <abhishek.varma@polymagelabs.com>
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D116923
Jay Foad [Thu, 3 Feb 2022 16:02:39 +0000 (16:02 +0000)]
[AMDGPU] Tweak tests in noclobber-barrier.ll
Tweak some of the tests to demonstrate
AMDGPUAnnotateUniformValues::visitLoadInst inserting a trivial
getelementptr instruction, just to have somewhere to put amdgpu.uniform
metadata. NFC.
LLVM GN Syncbot [Thu, 3 Feb 2022 16:04:30 +0000 (16:04 +0000)]
[gn build] Port
c34698a811b1
Simon Pilgrim [Thu, 3 Feb 2022 15:57:12 +0000 (15:57 +0000)]
MipsABIFlagsSection.h - replace unnecessary StringRef include with forward declaration
Simon Pilgrim [Thu, 3 Feb 2022 15:55:55 +0000 (15:55 +0000)]
[X86] simplifyX86varShift - use KnownBits.getMaxValue().ult() to check for out of bounds shift amounts
This is easier to grok than MaskedValueIsZero for high bits.
Nico Weber [Thu, 3 Feb 2022 15:55:40 +0000 (10:55 -0500)]
[gn build] (manually) port
20e05b9f0ebe (ClangPseudoTests)
Timm Bäder [Thu, 3 Feb 2022 15:52:07 +0000 (16:52 +0100)]
[clang][driver][wasm] Remove unneeded default labels
Fix build fallout from
b5787a0c6cc4da47b7d7b218e23f780076ad2f5f
Sander de Smalen [Thu, 3 Feb 2022 09:36:03 +0000 (09:36 +0000)]
[LV] Use VScaleForTuning to allow wider epilogue VFs.
When the main loop is e.g. VF=vscale x 1 and the epilogue VF cannot
be any smaller, the vectorizer should try to estimate how many lanes are
executed at runtime and allow a suitable fixed-width VF to be chosen. It
can use VScaleForTuning to figure out what a suitable fixed-width VF could
be. For the case where the main loop VF is VF=vscale x 1, and VScaleForTuning=8,
it could still choose an epilogue VF upto VF=4.
This was a bit tricky to test, so this patch also introduces a wrapper
function to get 'VScaleForTuning' by also considering vscale_range.
If min and max are equal, then that will be the vscale we compile for.
It makes little sense to tune for a different width if the code
will not be portable for other widths.
Reviewed By: david-arm
Differential Revision: https://reviews.llvm.org/D118709
Timm Bäder [Fri, 21 Jan 2022 10:15:23 +0000 (11:15 +0100)]
[clang][driver][wasm] Support -stdlib=libstdc++ for WebAssembly
The WebAssembly toolchain currently supports only -stdlib=libc++
and implicitly assumes the c++ stdlib to be libc++. Change this to also
support libstdc++.
Differential Revision: https://reviews.llvm.org/D117888#3290628
Andrzej Warzynski [Thu, 3 Feb 2022 15:15:53 +0000 (15:15 +0000)]
Revert "[flang] Debugging of ACCESS='STREAM' I/O"
This reverts commit
be9946b877add0db906090d22840b213c3f41dd2.
This change has caused Flang's Windows buildbot to start failing:
* https://lab.llvm.org/buildbot/#/builders/172/builds/7664
Simon Pilgrim [Thu, 3 Feb 2022 14:48:38 +0000 (14:48 +0000)]
[Lanai] Remove orphan LanaiInstPrinter::printAluOperand declaration. NFCI.
Simon Pilgrim [Thu, 3 Feb 2022 14:33:30 +0000 (14:33 +0000)]
LanaiInstPrinter.h - replace unnecessary StringRef include with forward declaration
Alexey Bataev [Fri, 31 Dec 2021 17:31:24 +0000 (09:31 -0800)]
[SLP]Excluded external uses from the reordering estimation.
Compiler adds the estimation for the external uses during operands
reordering analysis, which makes it tend to prefer duplicates in the
lanes rather than diamond/shuffled match in the graph. It changes the sizes of
the vector operands and may prevent some vectorization. We don't need
this kind of estimation for the analysis phase, because we just need to
choose the most compatible instruction and it does not matter if it has
external user or used in the non-matching lane. Instead, we count the number
of unique instruction in the lane and see if the reassociation changes
the number of unique scalars to be power of 2 or not. If we have power
of 2 unique scalars in the lane, it is considered more profitable rather
than having non-power-of-2 number of unique scalars.
Metric: SLP.NumVectorInstructions
test-suite :: MultiSource/Benchmarks/FreeBench/distray/distray.test 70.00 86.00 22.9%
test-suite :: External/SPEC/CFP2017rate/544.nab_r/544.nab_r.test 346.00 353.00 2.0%
test-suite :: External/SPEC/CFP2017speed/644.nab_s/644.nab_s.test 346.00 353.00 2.0%
test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test 235.00 239.00 1.7%
test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test 235.00 239.00 1.7%
test-suite :: External/SPEC/CFP2017rate/526.blender_r/526.blender_r.test 8723.00 8834.00 1.3%
test-suite :: MultiSource/Applications/JM/ldecod/ldecod.test 1051.00 1064.00 1.2%
test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 1628.00 1646.00 1.1%
test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 1628.00 1646.00 1.1%
test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test 9100.00 9184.00 0.9%
test-suite :: External/SPEC/CFP2017rate/538.imagick_r/538.imagick_r.test 3565.00 3577.00 0.3%
test-suite :: External/SPEC/CFP2017speed/638.imagick_s/638.imagick_s.test 3565.00 3577.00 0.3%
test-suite :: External/SPEC/CFP2017rate/511.povray_r/511.povray_r.test 4235.00 4245.00 0.2%
test-suite :: MultiSource/Benchmarks/tramp3d-v4/tramp3d-v4.test 1996.00 1998.00 0.1%
test-suite :: MultiSource/Applications/JM/lencod/lencod.test 1671.00 1672.00 0.1%
test-suite :: MultiSource/Benchmarks/Prolangs-C/TimberWolfMC/timberwolfmc.test 783.00 782.00 -0.1%
test-suite :: SingleSource/Benchmarks/Misc/oourafft.test 69.00 68.00 -1.4%
test-suite :: External/SPEC/CINT2017speed/641.leela_s/641.leela_s.test 207.00 192.00 -7.2%
test-suite :: External/SPEC/CINT2017rate/541.leela_r/541.leela_r.test 207.00 192.00 -7.2%
test-suite :: External/SPEC/CINT2017rate/531.deepsjeng_r/531.deepsjeng_r.test 89.00 80.00 -10.1%
test-suite :: External/SPEC/CINT2017speed/631.deepsjeng_s/631.deepsjeng_s.test 89.00 80.00 -10.1%
test-suite :: MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a/cjpeg.test 260.00 215.00 -17.3%
test-suite :: MultiSource/Benchmarks/MiBench/consumer-jpeg/consumer-jpeg.test 256.00 211.00 -17.6%
MultiSource/Benchmarks/Prolangs-C/TimberWolfMC - pretty the same.
SingleSource/Benchmarks/Misc/oourafft.test - 2 <2 x > loads replaced by
one <4 x> load.
External/SPEC/CINT2017speed/641.leela_s - function gets vectorized and
not inlined anymore.
External/SPEC/CINT2017rate/541.leela_r - same
xternal/SPEC/CINT2017rate/531.deepsjeng_r - changed the order in
multi-block tree, the result is pretty the same.
External/SPEC/CINT2017speed/631.deepsjeng_s - same.
MultiSource/Benchmarks/mediabench/jpeg/jpeg-6a - the result is the same
as before.
MultiSource/Benchmarks/MiBench/consumer-jpeg - same.
Differential Revision: https://reviews.llvm.org/D116688
Dawid Jurczak [Mon, 31 Jan 2022 14:51:13 +0000 (15:51 +0100)]
[NFC] Move FoldingSetNodeID::AddInteger and FoldingSetNodeID::AddPointer definitions to header
Lack of AddInteger/AddPointer inlining slows down NodeEquals/Profile/:operator== calls.
Inlining makes FunctionProtoTypes/PointerTypes/ElaboratedTypes/ParenTypes Profile functions faster
but since NodeEquals is still called indirectly through function pointer from FindNodeOrInsertPos
there is room for further inlining improvements.
Extracted from: https://reviews.llvm.org/D118385
Differential Revision: https://reviews.llvm.org/D118610
Simon Pilgrim [Thu, 3 Feb 2022 14:21:22 +0000 (14:21 +0000)]
XCoreTargetMachine.h - replace unnecessary StringRef include with forward declaration
Simon Pilgrim [Thu, 3 Feb 2022 14:05:53 +0000 (14:05 +0000)]
XCoreInstPrinter.h - replace unnecessary StringRef include with forward declaration
Simon Pilgrim [Thu, 3 Feb 2022 13:55:15 +0000 (13:55 +0000)]
[XCore] Remove orphan XCoreInstPrinter::printMemOperand declaration. NFCI.
Alexey Bataev [Thu, 16 Dec 2021 16:55:52 +0000 (08:55 -0800)]
[SLP]Alternate vectorization for cmp instructions.
Added support for alternate ops vectorization of the cmp instructions.
It allows to vectorize either cmp instructions with same/swapped
predicate but different (swapped) operands kinds or cmp instructions
with different predicates and compatible operands kinds.
Differential Revision: https://reviews.llvm.org/D115955
Nathan James [Thu, 3 Feb 2022 14:11:30 +0000 (14:11 +0000)]
[clang][docs] Regenerate ASTMatchers documentation
Markus Böck [Thu, 3 Feb 2022 14:07:46 +0000 (15:07 +0100)]
[mlir][Rewrite] Add support for using an operation with no results as location
Prior to this patch, using an operation without any results as the location would result in the generation of invalid C++ code. It'd try to format using the result values, which would would end up being an empty string for an operation without any.
This patch fixes that issue by instead using getValueAndRangeUse which handles both ranges as well as the case for an op without any results.
Differential Revision: https://reviews.llvm.org/D118885
Valentin Clement [Thu, 3 Feb 2022 14:03:58 +0000 (15:03 +0100)]
[fir] Add fir.array_amend operation definition
This patch adds the fir.array_amend operation. this op
is used later in upstreaming patches for the F95 compliance.
The `array_amend` operation marks an array value as having been changed via
a reference obtain by an `array_access`. It acts as a logical transaction
log that is used to merge the final result back with an `array_merge_store`
operation.
```mlir
// fetch the value of one of the array value's elements
%1 = fir.array_access %v, %i, %j : (!fir.array<?x?xT>, index, index) -> !fir.ref<T>
// modify the element by storing data using %1 as a reference
%2 = ... %1 ...
// mark the array value
%new_v = fir.array_amend %v, %2 : (!fir.array<?x?xT>, !fir.ref<T>) -> !fir.array<?x?xT>
```
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, schweitz
Differential Revision: https://reviews.llvm.org/D112448
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Valentin Clement [Thu, 3 Feb 2022 14:01:37 +0000 (06:01 -0800)]
[flang] Remove ununsed variable in ScalarExprLowering
Fix buildbot failure https://lab.llvm.org/buildbot/#/builders/180/builds/3066
Sam Parker [Thu, 3 Feb 2022 13:44:52 +0000 (13:44 +0000)]
[NFC] TypePromotion test for AArch64
Pavel Labath [Thu, 3 Feb 2022 12:26:10 +0000 (13:26 +0100)]
[lldb] Rename Logging.h to LLDBLog.h and clean up includes
Most of our code was including Log.h even though that is not where the
"lldb" log channel is defined (Log.h defines the generic logging
infrastructure). This worked because Log.h included Logging.h, even
though it should.
After the recent refactor, it became impossible the two files include
each other in this direction (the opposite inclusion is needed), so this
patch removes the workaround that was put in place and cleans up all
files to include the right thing. It also renames the file to LLDBLog to
better reflect its purpose.
Matt Devereau [Wed, 19 Jan 2022 16:30:29 +0000 (16:30 +0000)]
[AArch64][SVE] Fold vselect into predicated fmul, fsub and fadd
Fold vselect with an unpredicated fmul/fsub/fadd
operand into a predicated fmul/fsub/fadd:
(vselect (p) (op (a) (b)) (a)) => (op -> (p) (a) (b))
Differential Revision: https://reviews.llvm.org/D117689
Kirill Bobyrev [Thu, 3 Feb 2022 13:40:42 +0000 (14:40 +0100)]
[clangd] IncludeCleaner: Decrease API dependency on clangd
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D118882
Shao-Ce SUN [Thu, 20 Jan 2022 15:49:55 +0000 (23:49 +0800)]
[RISCV] Add support for Zihintpause extention
Add support for the 'pause' hint instruction as an alias for
'fence w, 0'. To do this allow the 'fence' operands pred and succ
to be set to 0 (the empty set). This will also allow future hints
to be encoded as 'fence 0, <x>' and 'fence <x>, 0'.
This patch revised from @mundaym's D93019.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D117789
John Brawn [Thu, 3 Feb 2022 12:38:54 +0000 (12:38 +0000)]
[AArch64] Adjust machine-combiner-reassociate.mir test
Use regular expressions for instruction numbers, as these can vary.
Sven van Haastregt [Thu, 3 Feb 2022 12:12:29 +0000 (12:12 +0000)]
[clang-format] Add missing newline in -style help
Simon Pilgrim [Thu, 3 Feb 2022 12:09:44 +0000 (12:09 +0000)]
ModuleUtils - VFABI::setVectorVariantNames - use ArrayRef<> instead of const SmallVector to pass argument
Christian Kühnel [Tue, 1 Feb 2022 13:45:59 +0000 (13:45 +0000)]
[clangd][nfc] cleanup of remaining clang-tidy findings
There were some left-overs (or new things) from the previous patches.
This will get us down to 0 open findings except:
clang-tidy is complaining in some files about
`warning: #includes are not sorted properly [llvm-include-order]`
however, clang-format does revert these changes.
It looks like clang-tidy and clang-format disagree there.
Not sure how we can fix that...
Reviewed By: sammccall
Differential Revision: https://reviews.llvm.org/D118698
John Brawn [Mon, 31 Jan 2022 15:13:34 +0000 (15:13 +0000)]
[AArch64] Make machine combiner patterns preserve MIFlags
This is mainly done so that we don't lose the nofpexcept flag once we
start emitting it.
Differential Revision: https://reviews.llvm.org/D118621
Haojian Wu [Thu, 3 Feb 2022 11:42:52 +0000 (12:42 +0100)]
[clangd] NFC, remove an unused local varaiable.
gbreynoo [Thu, 3 Feb 2022 11:33:49 +0000 (11:33 +0000)]
[llvm-ar] Prevent automatic conversion from thin to full archive
llvm-ar silently converts a thin archive to a regular archive when you
specify a modification operation (e.g. 'r') without the 'T' modifier.
This change stops this from occuring. If a user is trying to convert
between thin and full archives then they can explicitly use the 'L'
command to createa new archive.
Differential Revision: https://reviews.llvm.org/D118693
Benjamin Kramer [Thu, 3 Feb 2022 11:34:07 +0000 (12:34 +0100)]
[mlir][vector] Sink StandardOps include to its user in VectorUtils
Nikita Popov [Thu, 3 Feb 2022 11:25:05 +0000 (12:25 +0100)]
[RS4GC] Regenerate test checks (NFC)
Sven van Haastregt [Thu, 3 Feb 2022 11:09:41 +0000 (11:09 +0000)]
[OpenCL] Move most _explicit atomics into multiclass; NFC
This will simplify future conditionalization for OpenCL 3.0
optionality of atomic features.
The only set of atomic functions not using the multiclass is
atomic_compare_exchange_strong/weak, as these don't fit the common
pattern due to having 2 MemoryOrder arguments.
Florian Hahn [Thu, 3 Feb 2022 11:09:14 +0000 (11:09 +0000)]
[ConstraintElimination] Handle degenerate case with branch to same dest.
When a conditional branch has the same block as both true and false
successor it is not safe to add the condition.
Fixes PR49819.
Florian Hahn [Thu, 3 Feb 2022 11:09:10 +0000 (11:09 +0000)]
[ConstraintElimination] Add test cases from PR49819.
David Green [Thu, 3 Feb 2022 11:05:48 +0000 (11:05 +0000)]
[AArch64] Reassociate integer extending reductions to pairwise addition.
Given an (integer) vecreduce, we know the order of the inputs does not matter.
We can convert UADDV(add(zext(extract_lo(x)), zext(extract_hi(x)))) into
UADDV(UADDLP(x)). This can also happen through an extra add, where we transform
UADDV(add(y, add(zext(extract_lo(x)), zext(extract_hi(x))))).
This makes sure the same thing happens signed cases too, which requires adding
a new SADDLP node.
Differential Revision: https://reviews.llvm.org/D118107
Owen Pan [Thu, 3 Feb 2022 05:52:14 +0000 (21:52 -0800)]
[clang-format] Revert a feature in RemoveBracesLLVM
Revert the handling of a single-statement block that gets wrapped.
See issue #53543.
Differential Revision: https://reviews.llvm.org/D118873
David Spickett [Thu, 3 Feb 2022 10:52:02 +0000 (10:52 +0000)]
[compiler-rt][lsan] Increase libdl_deadlock test timeout
We (Linaro) still have the occasional failure here due
to high load on a shared buildbot machine.
We are looking into general soloutions but perhaps this
will help in the meantime.
Markus Böck [Thu, 3 Feb 2022 10:50:26 +0000 (11:50 +0100)]
[mlir][NFC] Fully qualify a default C++ string in Pattern.cpp
Valentin Clement [Thu, 3 Feb 2022 10:41:04 +0000 (11:41 +0100)]
[fir] Add fir.array_access op
The `array_access` provides a reference to a single element from an array
value. This is *not* a view in the immutable array, otherwise it couldn't
be stored to. It can be see as a logical copy of the element and its
position in the array. This reference can be written to and modified without
changing the original array.
The `array_access` operation is used to fetch the memory reference of an
element in an array value.
```fortran
real :: a(n,m)
...
... a ...
... a(r,s+1) ...
```
One can use `fir.array_access` to recover the implied memory reference to
the element `a(i,j)` in an array expression `a` as shown above. It can also
be used to recover the reference element `a(r,s+1)` in the second
expression.
```mlir
%s = fir.shape %n, %m : (index, index) -> !fir.shape<2>
// load the entire array 'a'
%v = fir.array_load %a(%s) : (!fir.ref<!fir.array<?x?xf32>>, !fir.shape<2>) -> !fir.array<?x?xf32>
// fetch the value of one of the array value's elements
%1 = fir.array_access %v, %i, %j : (!fir.array<?x?xf32>, index, index) -> !fir.ref<f32>
```
More information about `array_access` and other array operations can be
found in flang/docs/FIRArrayOperations.md.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: kiranchandramohan, schweitz
Differential Revision: https://reviews.llvm.org/D112445
Co-authored-by: Eric Schweitz <eschweitz@nvidia.com>
Valentin Clement [Thu, 3 Feb 2022 10:30:50 +0000 (11:30 +0100)]
[flang] Lower integer constant code for STOP stmt
This patch lower the integer constant code in the STOP statement.
The code is lowered to `arith.constant`.
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: schweitz, kiranchandramohan
Differential Revision: https://reviews.llvm.org/D118787
Haojian Wu [Wed, 19 Jan 2022 12:14:57 +0000 (13:14 +0100)]
[syntax][pseudo] Add Grammar for the clang pseudo-parser
This patch introduces the Grammar class, which is a critial piece for constructing
a tabled-based parser.
As the first patch, the scope is limited to:
- define base types (symbol, rules) of modeling the grammar
- construct Grammar by parsing the BNF file (annotations are excluded for now)
Differential Revision: https://reviews.llvm.org/D114790
Valentin Clement [Thu, 3 Feb 2022 09:40:19 +0000 (10:40 +0100)]
[flang] Add lowering for integer constant
This patch enables the lowering of integer constant.
The `ScalarExprLowering` class is introduced in `ConvertExpr.cpp` to help
the lowering of expression. This patch adds all the placeholder as well for future
expression lowering with the appropriate TODOs.
Integer constant expression are lowered to `arith.constant` with an integer type corresponding to the kind value.
This patch is in support of D118787
This patch is part of the upstreaming effort from fir-dev branch.
Reviewed By: schweitz, kiranchandramohan
Differential Revision: https://reviews.llvm.org/D118786
David Spickett [Thu, 3 Feb 2022 09:56:17 +0000 (09:56 +0000)]
[clang][Hexagon] Match -lc option more specifically in toolchain test
In https://lab.llvm.org/buildbot/#/builders/185/builds/1341
our bot happened to generate a temporary file path with -lc in
it.
Match with "" around the options so this doesn't happen again.
Simon Moll [Thu, 3 Feb 2022 10:01:42 +0000 (11:01 +0100)]
[VE] Packed v512i32 isel and tests
Reviewed By: kaz7
Differential Revision: https://reviews.llvm.org/D118332
Serge Pavlov [Thu, 3 Feb 2022 07:10:51 +0000 (14:10 +0700)]
[ConstantFolding] Fold constrained compare intrinsics
The change implements constant folding of ‘llvm.experimental.constrained.fcmp’
and ‘llvm.experimental.constrained.fcmps’ intrinsics.
Differential Revision: https://reviews.llvm.org/D110322
Tim Northover [Thu, 3 Feb 2022 09:41:50 +0000 (09:41 +0000)]
Revert "[compiler-rt][Darwin] Add arm64 to simulator platforms"
This reverts commit
a8e5ce76b475a22546090a73c22fa4f83529aa4e.
It looks like older Xcodes' headers don't allow arm64 builds so it was causing
CI failures.
Marek Kurdej [Thu, 3 Feb 2022 09:37:58 +0000 (10:37 +0100)]
[clang-format] Reserve vectors when the number of items is known beforehand. NFC.
Roman Lebedev [Thu, 3 Feb 2022 09:22:43 +0000 (12:22 +0300)]
Revert "[SimplifyCFG] Start redesigning `FoldTwoEntryPHINode()`."
Unfortunately, it seems we really do need to take the long route;
start from the "merge" block, find (all the) "dispatch" blocks,
and deal with each "dispatch" block separately, instead of simply
starting from each "dispatch" block like it would logically make sense,
otherwise we run into a number of other missing folds around
`switch` formation, missing sinking/hoisting and phase ordering.
This reverts commit
85628ce75b3084dc0f185a320152baf85b59aba7.
This reverts commit
c5fff9095342a792bf4b9a077fe3c3a83c4e566c.
This reverts commit
34a98e1046e3aa55e5f26ab20a15e96b4034d25a.
This reverts commit
1e353f092288309d74d380367aa50bbd383780ed.
Sander de Smalen [Thu, 3 Feb 2022 08:59:49 +0000 (08:59 +0000)]
[ISEL] Canonicalize STEP_VECTOR to LHS if RHS is a splat.
This helps recognise patterns where we're trying to match STEP_VECTOR
patterns to INDEX instructions that take a GPR for the Start/Step.
The reason for canonicalising this operation to the LHS is
because it will already be canonicalised to the LHS if the RHS
is a constant splat vector.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D118459
Thomas Symalla [Thu, 3 Feb 2022 09:25:55 +0000 (10:25 +0100)]
[AMDGPU] Update two Codegen tests. (NFC)
This change adds a new Codegen test with auto-generated checks and
updates divergence-driven-trunc-to-i1.ll with auto-generated checks.
This is in preparation to D118461 to visualize the Codegen changes.
Hans Wennborg [Wed, 2 Feb 2022 09:57:39 +0000 (10:57 +0100)]
Remove -Wweak-template-vtables
as it was planned for removal in clang 15 and we're now past the branch point
See https://github.com/llvm/llvm-project/issues/19107
Differential revision: https://reviews.llvm.org/D118762
Jean Perier [Thu, 3 Feb 2022 09:13:39 +0000 (10:13 +0100)]
[flang] add ExtendedValue type helpers and factory::genZeroValue
Add some helpers to get the base type and element type of
fir::ExtendedValue and to test if a fir::ExtendedValue is
a derived type with length parameters.
Add a new helper factory::genZeroValue to generate zero scalar value for
all the numerical types and false for logicals.
These helpers are used only in lowering for now, so add unit tests.
Differential Revision: https://reviews.llvm.org/D118795