Vitaly Buka [Tue, 13 Jul 2021 17:44:53 +0000 (10:44 -0700)]
[sanitizer] Fix VSNPrintf %V on Windows
Louis Dionne [Mon, 12 Jul 2021 21:50:21 +0000 (17:50 -0400)]
[libc++] Add a CI job for macOS on arm64 hardware 🥳
Differential Revision: https://reviews.llvm.org/D105848
Tom Stellard [Tue, 13 Jul 2021 17:47:29 +0000 (10:47 -0700)]
Fix utils/update_cc_test_checks/check-globals.test on stand-alone builds
We want to use LLVM_EXTERNAL_LIT if defined for the %lit substitution.
Reviewed By: jdenny
Differential Revision: https://reviews.llvm.org/D105873
Peyton, Jonathan L [Tue, 13 Jul 2021 17:33:01 +0000 (12:33 -0500)]
[OpenMP] Fix one sign-compare warning from GCC
Louis Dionne [Tue, 13 Jul 2021 17:07:45 +0000 (13:07 -0400)]
[libc++] NFC: Add comment for running macOS CI setup script remotely
Craig Topper [Tue, 13 Jul 2021 17:27:29 +0000 (10:27 -0700)]
[RISCV] Use DIVUW/REMUW/DIVW instructions for i8/i16/i32 udiv/urem/sdiv when LHS is constant.
We don't really have optimizations for division with a constant
LHS. If we don't use a W instruction we end up needing to sign
or zero extend the RHS to use the 64-bit instruction.
I had to sign_extend i32 constants on the LHS instead of using
any_extend which becomes zero_extend. If we don't do this, constants
that were originally negative become harder to materialize. I think
this problem exists for more of our W instruction cases. For example
(i32 (shl -1, X)), but we don't have lit tests. I'll work on that
as a follow up.
I also left a FIXME for enabling W instruction for RHS constants
under -Oz.
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D105769
Amy Kwan [Mon, 12 Jul 2021 21:35:50 +0000 (16:35 -0500)]
[PowerPC] Add FI alignment check if the addressing mode is DS/DQ-Form, emit X-Form if necessary.
This patch adds a function that checks whether or not the frame index
is aligned when the computed addressing mode is an aligned D-Form (DS, or DQ-Form).
If the frame index appears to be unaligned, within these two modes, reset
the mode to X-Form in order to fall back to selection X-Form loads.
A test case is added to ensure that the test emits X-Form loads and not DQ-Form
loads since the frame index is not aligned within the test case.
Differential Revision: https://reviews.llvm.org/D105661
Peyton, Jonathan L [Tue, 13 Jul 2021 17:23:49 +0000 (12:23 -0500)]
[OpenMP][NFC] Change comment style to eliminate warnings from GCC
Standalone build for OpenMP runtime using GCC is giving -Wcomment
warnings where a backslash newline is encountered in the // style
comment. This switches the // style for /* style to silence the
warnings.
Matheus Izvekov [Sat, 10 Jul 2021 00:34:17 +0000 (02:34 +0200)]
[clang] C++98 implicit moves are back with a vengeance
After taking C++98 implicit moves out in D104500,
we put it back in, but now in a new form which preserves
compatibility with pure C++98 programs, while at the same time
giving almost all the goodies from P1825.
* We use the exact same rules as C++20 with regards to which
id-expressions are move eligible. The previous
incarnation would only benefit from the proper subset which is
copy ellidable. This means we can implicit move, in addition:
* Parameters.
* RValue references.
* Exception variables.
* Variables with higher-than-natural required alignment.
* Objects with different type from the function return type.
* We preserve the two-overload resolution, with one small tweak to the
first one: If we either pick a (possibly converting) constructor which
does not take an rvalue reference, or a user conversion operator which
is not ref-qualified, we abort into the second overload resolution.
This gives C++98 almost all the implicit move patterns which we had created test
cases for, while at the same time preserving the meaning of these
three patterns, which are found in pure C++98 programs:
* Classes with both const and non-const copy constructors, but no move
constructors, continue to have their non-const copy constructor
selected.
* We continue to reject as ambiguous the following pattern:
```
struct A { A(B &); };
struct B { operator A(); };
A foo(B x) { return x; }
```
* We continue to pick the copy constructor in the following pattern:
```
class AutoPtrRef { };
struct AutoPtr {
AutoPtr(AutoPtr &);
AutoPtr();
AutoPtr(AutoPtrRef);
operator AutoPtrRef();
};
AutoPtr test_auto_ptr() {
AutoPtr p;
return p;
}
```
Signed-off-by: Matheus Izvekov <mizvekov@gmail.com>
Reviewed By: Quuxplusone
Differential Revision: https://reviews.llvm.org/D105756
Marcos Horro [Tue, 13 Jul 2021 17:07:03 +0000 (19:07 +0200)]
[llvm-mca] [NFC] Formatting code
Applied clang-format to all files. Discarded BottleneckAnalysis.h
80-column width violation since it contains an example of report.
Caught some typos and minor style details.
Reviewed By: andreadb
Differential Revision: https://reviews.llvm.org/D105900
Saleem Abdulrasool [Fri, 19 Mar 2021 15:26:27 +0000 (08:26 -0700)]
AST: correct name decoration for swift async functions on Windows
The name decoration scheme on Windows does not have a vendor namespace,
and the decoration scheme is not shared ownership - it is controlled by
Microsoft. `T` is a reserved identifier for an unknown calling
convention. The `W` identifier has been discussed with Microsoft
offline and is reserved as `Swift_3` as the identifier for the swift
async calling convention. Adjust the name decoration accordingly.
Philip Reames [Tue, 13 Jul 2021 16:58:19 +0000 (09:58 -0700)]
[ScalarEvolution] Fix overflow when computing max trip counts
This is split from D105216 to reduce patch complexity. Original code by Eli with very minor modification by me.
The primary point of this patch is to add the getUDivCeilSCEV routine. I included the two callers with constant arguments as we know those must constant fold even without any of the fancy inference logic.
Arthur Eubanks [Tue, 13 Jul 2021 16:57:37 +0000 (09:57 -0700)]
[NFC] Inline variable to prevent unused variable warning
thomasraoux [Tue, 13 Jul 2021 16:34:48 +0000 (09:34 -0700)]
[mlir] Add support for tensor.extract to comprehensive bufferization
Differential Revision: https://reviews.llvm.org/D105870
Craig Topper [Tue, 13 Jul 2021 06:53:40 +0000 (23:53 -0700)]
[RISCV] Prevent use of t0(aka x5) as rs1 for jalr instructions.
Some microarchitectures treat rs1=x1/x5 on jalr as a hint to pop
the return-address stack. We should avoid using x5 on jalr
instructions since we aren't using x5 as an alternate link register.
Differential Revision: https://reviews.llvm.org/D105875
Guillaume Chatelet [Tue, 13 Jul 2021 16:44:42 +0000 (16:44 +0000)]
Revert "[llvm] Add enum iteration to Sequence"
This reverts commit
a006af5d6ec6280034ae4249f6d2266d726ccef4.
Arthur Eubanks [Tue, 13 Jul 2021 16:29:53 +0000 (09:29 -0700)]
[OpaquePtr] Use byval type more
Arthur Eubanks [Tue, 13 Jul 2021 16:27:09 +0000 (09:27 -0700)]
[OpaquePtr] Get load/store type without PointerType::getElementType()
Arthur Eubanks [Tue, 13 Jul 2021 16:26:39 +0000 (09:26 -0700)]
[OpaquePtr] Use GlobalValue::getValueType() more
Arthur Eubanks [Tue, 13 Jul 2021 16:25:28 +0000 (09:25 -0700)]
[OpaquePtr] Use AllocaInst::getAllocatedType()
Julian Lettner [Mon, 12 Jul 2021 21:00:45 +0000 (14:00 -0700)]
Avoid triggering assert when program calls OSAtomicCompareAndSwapLong
A previous change brought the new, relaxed implementation of "on failure
memory ordering" for synchronization primitives in LLVM over to TSan
land [1]. It included the following assert:
```
// 31.7.2.18: "The failure argument shall not be memory_order_release
// nor memory_order_acq_rel". LLVM (2021-05) fallbacks to Monotonic
// (mo_relaxed) when those are used.
CHECK(IsLoadOrder(fmo));
static bool IsLoadOrder(morder mo) {
return mo == mo_relaxed || mo == mo_consume
|| mo == mo_acquire || mo == mo_seq_cst;
}
```
A previous workaround for a false positive when using an old Darwin
synchronization API assumed this failure mode to be unused and passed a
dummy value [2]. We update this value to `mo_relaxed` which is also the
value used by the actual implementation to avoid triggering the assert.
[1] https://reviews.llvm.org/D99434
[2] https://reviews.llvm.org/D21733
rdar://
78122243
Differential Revision: https://reviews.llvm.org/D105844
Nicolas Vasilache [Tue, 13 Jul 2021 15:32:40 +0000 (15:32 +0000)]
[mlir][Linalg] Properly specify Linalg attribute.
This fixes undefined reference introduced by https://reviews.llvm.org/D105859
Differential Revision: https://reviews.llvm.org/D105897
Fangrui Song [Tue, 13 Jul 2021 16:30:09 +0000 (09:30 -0700)]
[RISCV] Support machine constraint "S"
Similar to D46745, "S" represents an absolute symbolic operand, which
can be used to specify the access models, e.g.
extern int var;
void *addr_via_asm() {
void *ret;
asm("lui %0, %%hi(%1)\naddi %0,%0,%%lo(%1)" : "=r"(ret) : "S"(&var));
return ret;
}
'S' is documented in trunk GCC: https://gcc.gnu.org/bugzilla/show_bug.cgi?id=101275
Reviewed By: luismarques
Differential Revision: https://reviews.llvm.org/D105254
Guillaume Chatelet [Tue, 13 Jul 2021 16:22:19 +0000 (16:22 +0000)]
[llvm] Add enum iteration to Sequence
This patch allows iterating typed enum via the ADT/Sequence utility.
Differential Revision: https://reviews.llvm.org/D103900
Aart Bik [Mon, 12 Jul 2021 22:50:47 +0000 (15:50 -0700)]
[mlir][memref] adjust integration tests to new lowering passes
these tests run under the emulator and thus were overlooked
Reviewed By: ftynse
Differential Revision: https://reviews.llvm.org/D105855
Albion Fung [Tue, 13 Jul 2021 16:01:53 +0000 (11:01 -0500)]
[PowerPC] Fix L[D|W]ARX Implementation
LDARX and LWARX sometimes gets optimized out by the compiler
when it is critical to the correctness of the code. This inline asm generation
ensures that it preserved.
Differential Revision: https://reviews.llvm.org/D105754
Simon Pilgrim [Tue, 13 Jul 2021 15:57:40 +0000 (16:57 +0100)]
[InstCombine] Add basic (select C, (gep Ptr, Idx), Ptr) tests from PR50183
Simon Pilgrim [Tue, 13 Jul 2021 15:54:07 +0000 (16:54 +0100)]
[InstCombine] Regenerate select-gep.ll tests
Victor Huang [Tue, 13 Jul 2021 15:46:13 +0000 (10:46 -0500)]
[PowerPC][NFC] Power ISA features for Semachecking
[NFC] This patch adds features for pwr7, pwr8, and pwr9 that can be
used for semachecking builtin functions that are only valid for certain
versions of ppc.
Reviewed By: nemanjai, #powerpc
Authored By: Quinn Pham <Quinn.Pham@ibm.com>
Differential revision: https://reviews.llvm.org/D105501
Anton Zabaznov [Tue, 13 Jul 2021 13:41:21 +0000 (16:41 +0300)]
[OpenCL] Add verbosity when checking support of read_write images
Parenthesis were fixed incorrectly by D105890
Reviewed By: Anastasia
Differential Revision: https://reviews.llvm.org/D105892
Tres Popp [Tue, 13 Jul 2021 15:30:53 +0000 (17:30 +0200)]
[mlir] Handle unused variable when assertions are disabled.
John Ericson [Wed, 28 Apr 2021 22:36:47 +0000 (22:36 +0000)]
Prepare Compiler-RT for GnuInstallDirs, matching libcxx, document all
This is a second attempt at D101497, which landed as
9a9bc76c0eb72f0f2732c729a460abbd5239c2e3 but had to be reverted in
8cf7ddbdd4e5af966a369e170c73250f2e3920e7.
This issue was that in the case that `COMPILER_RT_INSTALL_PATH` is
empty, expressions like "${COMPILER_RT_INSTALL_PATH}/bin" evaluated to
"/bin" not "bin" as intended and as was originally.
One solution is to make `COMPILER_RT_INSTALL_PATH` always non-empty,
defaulting it to `CMAKE_INSTALL_PREFIX`. D99636 adopted that approach.
But, I think it is more ergonomic to allow those project-specific paths
to be relative the global ones. Also, making install paths absolute by
default inhibits the proper behavior of functions like
`GNUInstallDirs_get_absolute_install_dir` which make relative install
paths absolute in a more complicated way.
Given all this, I will define a function like the one asked for in
https://gitlab.kitware.com/cmake/cmake/-/issues/19568 (and needed for a
similar use-case).
---
Original message:
Instead of using `COMPILER_RT_INSTALL_PATH` through the CMake for
complier-rt, just use it to define variables for the subdirs which
themselves are used.
This preserves compatibility, but later on we might consider getting rid
of `COMPILER_RT_INSTALL_PATH` and just changing the defaults for the
subdir variables directly.
---
There was a seaming bug where the (non-Apple) per-target libdir was
`${target}` not `lib/${target}`. I suspect that has to do with the docs
on `COMPILER_RT_INSTALL_PATH` saying was the library dir when that's no
longer true, so I just went ahead and fixed it, allowing me to define
fewer and more sensible variables.
That last part should be the only behavior changes; everything else
should be a pure refactoring.
---
I added some documentation of these variables too. In particular, I
wanted to highlight the gotcha where `-DSomeCachePath=...` without the
`:PATH` will lead CMake to make the path absolute. See [1] for
discussion of the problem, and [2] for the brief official documentation
they added as a result.
[1]: https://cmake.org/pipermail/cmake/2015-March/060204.html
[2]: https://cmake.org/cmake/help/latest/manual/cmake.1.html#options
In
38b2dec37ee735d5409148e71ecba278caf0f969 the problem was somewhat
misidentified and so `:STRING` was used, but `:PATH` is better as it
sets the correct type from the get-go.
---
D99484 is the main thrust of the `GnuInstallDirs` work. Once this lands,
it should be feasible to follow both of these up with a simple patch for
compiler-rt analogous to the one for libcxx.
Reviewed By: phosek, #libc_abi, #libunwind
Differential Revision: https://reviews.llvm.org/D105765
Matt Arsenault [Mon, 12 Jul 2021 16:58:56 +0000 (12:58 -0400)]
AMDGPU: Promote signext/zeroext i16 shader returns
This makes them consistent with all the other return convention
handling. If we don't do this, we lose the sext/zext flag if treated
as a full assignment, which complicates a future GlobalISel patch.
Matt Arsenault [Sun, 11 Jul 2021 13:00:14 +0000 (09:00 -0400)]
GlobalISel: Use extension instead of merge with undef in common case
This fixes not respecting signext/zeroext in these cases. In the
anyext case, this avoids a larger merge with undef and should be a
better canonical form.
This should also handle this if a merge is needed, but I'm not aware
of a case where that can happen. In a future change this will also
allow AMDGPU to drop some custom code without introducing regressions.
Matt Arsenault [Sun, 11 Jul 2021 13:58:02 +0000 (09:58 -0400)]
GlobalISel: Remove getIntrinsicID utility function
This is redundant with a method directly on MachineInstr
Matt Arsenault [Tue, 6 Jul 2021 16:02:07 +0000 (12:02 -0400)]
Mips/GlobalISel: Use more standard call lowering infrastructure
This also fixes some missing implicit uses on call instructions, adds
missing G_ASSERT_SEXT/ZEXT annotations, and some missing outgoing
sext/zexts. This also fixes not respecting tablegen requested type
promotions.
This starts treating f64 passed in i32 GPRs as a type of custom
assignment, which restores some previously XFAILed tests. This is due
to getNumRegistersForCallingConv returns a static value, but in this
case it is context dependent on other arguments.
Most of the ugliness is reproducing a hack CC_MipsO32 uses in
SelectionDAG. CC_MipsO32 depends on a bunch of vectors populated from
the original IR argument types in MipsCCState. The way this ends up
working in GlobalISel is it only ends up inspecting the most recently
added vector element. I'm pretty sure there are cleaner ways to do
this, but this seemed easier than fixing up the current DAG
handling. This is another case where it would be easier of the
CCAssignFns were passed the original type instead of only the
pre-legalized ones.
There's still a lot of junk here that shouldn't be necessary. This
also likely breaks big endian handling, but it wasn't complete/tested
anyway since the IRTranslator gives up on big endian targets.
Matt Arsenault [Thu, 8 Jul 2021 23:35:45 +0000 (19:35 -0400)]
Mips: Mark special case calling convention handling as custom
The number of registers used for passing f64 in some cases is context
dependent, and thus getNumRegistersForCallingConv is sometimes
inaccurate. For f64, it reports 1 but is sometimes split into 2 32-bit
registers.
For GlobalISel, the generic argument assignment code expects
getNumRegistersForCallingConv to return an accurate answer. Switch to
marking these arguments as custom so we can deal with this case as a
custom assignment rather.
This temporarily breaks a few globalisel tests which are fixed by a
future change to use more of the generic infrastructure.
Louis Dionne [Tue, 13 Jul 2021 14:48:54 +0000 (10:48 -0400)]
[libc++] Workaround non-constexpr std::exchange pre C++20
std::exchange is only constexpr in C++20 and later. We were using it
in a constructor marked unconditionally constexpr, which caused issues
when building with -std=c++17.
The weird part is that the issue only showed up when building on the
arm64 macs, but that must be caused by the specific version of Clang
used on those. Since the code is clearly wrong and the fix is obvious,
I'm not going to investigate this further.
Louis Dionne [Mon, 12 Jul 2021 21:34:44 +0000 (17:34 -0400)]
[libc++] Target x86_64 only for the backdeployment jobs
Differential Revision: https://reviews.llvm.org/D105846
Louis Dionne [Tue, 13 Jul 2021 14:16:50 +0000 (10:16 -0400)]
[libc++] Generate ABI list for macOS arm64
Hansang Bae [Mon, 12 Jul 2021 15:57:15 +0000 (10:57 -0500)]
[OpenMP] Minor improvement in task allocation
This patch includes a few changes to improve task allocation
performance slightly. These changes are enough to restore performance
drop observed after introducing hidden helper.
Differential Revision: https://reviews.llvm.org/D105715
Bogdan Graur [Tue, 13 Jul 2021 13:38:20 +0000 (15:38 +0200)]
[NFC] Add paranthesis around logical expression to silence -Wlogical-op-parentheses warning.
Reviewed By: alexfh
Differential Revision: https://reviews.llvm.org/D105890
Simon Pilgrim [Tue, 13 Jul 2021 13:26:03 +0000 (14:26 +0100)]
[InstCombine] Fold lshr/ashr(or(neg(x),x),bw-1) --> zext/sext(icmp_ne(x,0)) (PR50816)
Handle the missing fold reported in PR50816, which is a variant of the existing ashr(sub_nsw(X,Y),bw-1) --> sext(icmp_sgt(X,Y)) fold.
We also handle the lshr(or(neg(x),x),bw-1) --> zext(icmp_ne(x,0)) equivalent - https://alive2.llvm.org/ce/z/SnZmSj
We still allow multi uses of the neg(x) - as this is likely to let us further simplify other uses of the neg - but not multi uses of the or() which would increase instruction count.
Differential Revision: https://reviews.llvm.org/D105764
Dave MacLachlan [Tue, 13 Jul 2021 13:21:25 +0000 (09:21 -0400)]
[clang/objc] Optimize getters for non-atomic, copied properties
Properties that were declared `@property(copy, nonatomic) id foo` make an
unnecessary call to objc_get_property(). This call can be replaced with a
direct access to the backing variable identical to how a `@property(nonatomic)
id foo` would do it.
This reduces codegen by 4 bytes (x86_64/arm64) and removes a cross linkage unit
function call per property declared as copy/nonatomic.
Differential Revision: https://reviews.llvm.org/D105311
Simon Pilgrim [Tue, 13 Jul 2021 12:48:04 +0000 (13:48 +0100)]
[InstCombine] Pre-commit ashr(or(neg(x),x),bw-1) --> sext(icmp_ne(x,0)) tests from D105764
Added 'thwart complexity-based canonicalization' hacks and the lshr(or(neg(x),x),bw-1) --> zext(icmp_ne(x,0)) variants suggested by Sanjay.
Anton Zabaznov [Tue, 13 Jul 2021 12:09:14 +0000 (15:09 +0300)]
[OpenCL] Add support of __opencl_c_read_write_images feature macro
This feature requires support of __opencl_c_images, so diagnostics for that is provided as well
Reviewed By: Anastasia
Differential Revision: https://reviews.llvm.org/D104915
Roman Lebedev [Tue, 13 Jul 2021 12:36:46 +0000 (15:36 +0300)]
[libomp] ompd_init(): fix heap-buffer-overflow when constructing libompd.so path
There is no guarantee that the space allocated in `libname`
is enough to accomodate the whole `dl_info.dli_fname`,
because it could e.g. have an suffix - `.5`,
and that highlights another problem - what it should do about suffxies,
and should it do anything to resolve the symlinks before changing the filename?
```
$ LD_LIBRARY_PATH="$LD_LIBRARY_PATH:/usr/local/lib" ./src/utilities/rstest/rstest -c /tmp/
f49137920.NEF
dl_info.dli_fname "/usr/local/lib/libomp.so.5"
strlen(dl_info.dli_fname) 26
lib_path_length 14
lib_path_length + 12 26
=================================================================
==30949==ERROR: AddressSanitizer: heap-buffer-overflow on address 0x60300000002a at pc 0x000000548648 bp 0x7ffdfa0aa780 sp 0x7ffdfa0a9f40
WRITE of size 27 at 0x60300000002a thread T0
#0 0x548647 in strcpy (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x548647)
#1 0x7fb9e3e3d234 in ompd_init() /repositories/llvm-project/openmp/runtime/src/ompd-specific.cpp:102:5
#2 0x7fb9e3dcb446 in __kmp_do_serial_initialize() /repositories/llvm-project/openmp/runtime/src/kmp_runtime.cpp:6742:3
#3 0x7fb9e3dcb40b in __kmp_get_global_thread_id_reg /repositories/llvm-project/openmp/runtime/src/kmp_runtime.cpp:251:7
#4 0x59e035 in main /home/lebedevri/rawspeed/build-Clang-SANITIZE/../src/utilities/rstest/rstest.cpp:491
#5 0x7fb9e3762d09 in __libc_start_main csu/../csu/libc-start.c:308:16
#6 0x4df449 in _start (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x4df449)
0x60300000002a is located 0 bytes to the right of 26-byte region [0x603000000010,0x60300000002a)
allocated by thread T0 here:
#0 0x55cc5d in malloc (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x55cc5d)
#1 0x7fb9e3e3d224 in ompd_init() /repositories/llvm-project/openmp/runtime/src/ompd-specific.cpp:101:17
#2 0x7fb9e3762d09 in __libc_start_main csu/../csu/libc-start.c:308:16
SUMMARY: AddressSanitizer: heap-buffer-overflow (/home/lebedevri/rawspeed/build-Clang-SANITIZE/src/utilities/rstest/rstest+0x548647) in strcpy
Shadow bytes around the buggy address:
0x0c067fff7fb0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c067fff7fc0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c067fff7fd0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c067fff7fe0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
0x0c067fff7ff0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
=>0x0c067fff8000: fa fa 00 00 00[02]fa fa fa fa fa fa fa fa fa fa
0x0c067fff8010: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c067fff8020: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c067fff8030: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c067fff8040: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
0x0c067fff8050: fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa fa
Shadow byte legend (one shadow byte represents 8 application bytes):
Addressable: 00
Partially addressable: 01 02 03 04 05 06 07
Heap left redzone: fa
Freed heap region: fd
Stack left redzone: f1
Stack mid redzone: f2
Stack right redzone: f3
Stack after return: f5
Stack use after scope: f8
Global redzone: f9
Global init order: f6
Poisoned by user: f7
Container overflow: fc
Array cookie: ac
Intra object redzone: bb
ASan internal: fe
Left alloca redzone: ca
Right alloca redzone: cb
==30949==ABORTING
Aborted
```
Simon Pilgrim [Tue, 13 Jul 2021 11:30:55 +0000 (12:30 +0100)]
[X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result (REAPPLIED)
Annoyingly, i686 cmpsd handling still fails to remove the unnecessary neg(and(x,1))
Reapplied rGe4aa6ad13216 with fix for intrinsic variants of the opcode which uses a vector return type
Frederik Gossen [Mon, 12 Jul 2021 13:38:25 +0000 (15:38 +0200)]
[MLIR] Fix documentation of the `ExecutionEngine` in the toy tutorial example
Differential Revision: https://reviews.llvm.org/D105813
George Rokos [Sat, 10 Jul 2021 11:14:44 +0000 (04:14 -0700)]
[libomptarget] Update device pointer only if needed
Currently, libomptarget will always perform a host-to-device memory transfer in
order to update the device pointer of a PTR_AND_OBJ entry. This is not always
necessary because the device pointer may have been set to the correct pointee
address already, so we can eliminate the redundant memory transfer.
Hafiz Abid Qadeer [Tue, 13 Jul 2021 10:17:04 +0000 (11:17 +0100)]
[AMDGPU] Handle s_branch to another section.
Currently, if target of s_branch instruction is in another section, it will fail with the error of undefined label. Although in this case, the label is not undefined but present in another section. This patch tries to handle this issue. So while handling fixup_si_sopp_br fixup in getRelocType, if the target label is undefined we issue an error as before. If it is defined, a new relocation type R_AMDGPU_REL16 is returned.
This issue has been reported in https://gcc.gnu.org/bugzilla/show_bug.cgi?id=100181 and https://bugs.llvm.org/show_bug.cgi?id=45887. Before https://reviews.llvm.org/D79943, we used to get an crash for this scenario. The crash is fixed now but the we still get an undefined label error. Jumps to other section can arise with hold/cold splitting.
A patch to handle the relocation in lld will follow shortly.
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D105760
Jon Chesterfield [Tue, 13 Jul 2021 11:06:55 +0000 (12:06 +0100)]
[libomptarget][devicertl] Remove branches around setting parallelLevel
Simplifies control flow to allow store/load forwarding
This change folds two basic blocks into one, leaving a single store to parallelLevel.
This is a step towards spmd kernels with sufficiently aggressive inlining folding
the loads from parallelLevel and thus discarding the nested parallel handling
when it is unused.
Transform:
```
int threadId = GetThreadIdInBlock();
if (threadId == 0) {
parallelLevel[0] = expr;
} else if (GetLaneId() == 0) {
parallelLevel[GetWarpId()] = expr;
}
// =>
if (GetLaneId() == 0) {
parallelLevel[GetWarpId()] = expr;
}
// because
unsigned GetLaneId() { return GetThreadIdInBlock() & (WARPSIZE - 1);}
// so whenever threadId == 0, GetLaneId() is also 0.
```
That replaces a store in two distinct basic blocks with as single store.
A more aggressive follow up is possible if the threads in the warp/wave
race to write the same value to the same address. This is not done as
part of this change.
```
if (GetLaneId() == 0) {
parallelLevel[GetWarpId()] = expr;
}
// =>
parallelLevel[GetWarpId()] = expr;
// because
unsigned GetWarpId() { return GetThreadIdInBlock() / WARPSIZE; }
// so GetWarpId will index the same element for every thread in the warp
// and, because expr is lane-invariant in this case, every lane stores the
// same value to this unique address
```
Reviewed By: tianshilei1992
Differential Revision: https://reviews.llvm.org/D105699
Jan Kratochvil [Tue, 13 Jul 2021 10:37:53 +0000 (12:37 +0200)]
[lldb] Fix editline unicode on Linux
Based on:
[lldb-dev] proposed change to remove conditional WCHAR support in libedit wrapper
https://lists.llvm.org/pipermail/lldb-dev/2021-July/016961.html
There is already setlocale in lldb/source/Core/IOHandlerCursesGUI.cpp
but that does not apply for Editline GUI editing.
Unaware how to make automated test for this, it requires pty.
Reviewed By: teemperor
Differential Revision: https://reviews.llvm.org/D105779
Nicolas Vasilache [Tue, 13 Jul 2021 10:22:51 +0000 (10:22 +0000)]
[mlir][Linalg] Better support for bufferizing non-tensor results.
Clean up corner cases related to elemental tensor / buffer type return values that would previously fail.
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D105857
Simon Pilgrim [Tue, 13 Jul 2021 10:25:35 +0000 (11:25 +0100)]
[X86][SSE] Add signbit tests to show cmpss/cmpsd intrinsics not recognised as 'allbits' results.
This adds test coverage for the crash reported on rGe4aa6ad13216
Tim Northover [Tue, 13 Jul 2021 10:23:03 +0000 (11:23 +0100)]
Support: reduce stack used in default size test.
When the sanitizers aren't enabled they can use more than 1KB of stack, causing
an overflow where there shouldn't be.
Should fix Green Dragon test.
Nicolas Vasilache [Tue, 13 Jul 2021 10:20:10 +0000 (10:20 +0000)]
[mlir][Linalg] Add layout specification support to bufferization.
Previously, linalg bufferization always had to be conservative at function boundaries and assume the most dynamic strided memref layout.
This revision introduce the mechanism to specify a linalg.buffer_layout function argument attribute that carries an affine map used to set a less pessimistic layout.
Reviewed By: ThomasRaoux
Differential Revision: https://reviews.llvm.org/D105859
Sebastian Neubauer [Tue, 6 Jul 2021 09:24:42 +0000 (11:24 +0200)]
[AMDGPU] Optimize VGPR LiveRange in waterfall loops
The loops are run exactly once per lane, so VGPRs do not need to be
saved. Use the SIOptimizeVGPRLiveRange pass to add phi nodes that take
undef when coming from the loop.
There is still a shortcoming:
Return values from a function call in the loop are copied because their
live range conflicts with the live range of arguments, even if arguments
are only IMPLICIT_DEF after the phi insertion.
Differential Revision: https://reviews.llvm.org/D105192
Sebastian Neubauer [Tue, 6 Jul 2021 09:23:06 +0000 (11:23 +0200)]
[AMDGPU] Mark waterfall loops as SI_WATERFALL_LOOP
This way, they can be detected later, e.g. by the
SIOptimizeVGPRLiveRange pass.
Differential Revision: https://reviews.llvm.org/D105467
Anton Zabaznov [Tue, 13 Jul 2021 09:45:38 +0000 (12:45 +0300)]
[OpenCL] Add support of __opencl_c_generic_address_space feature macro
Reviewed By: Anastasia
Differential Revision: https://reviews.llvm.org/D103401
Tim Northover [Mon, 28 Jun 2021 13:28:40 +0000 (14:28 +0100)]
AArch64: use 4-byte slots for arm64_32 pointers in a tail call
Guillaume Chatelet [Tue, 13 Jul 2021 09:59:11 +0000 (09:59 +0000)]
[libc] update benchmark distributions
All distributions (expect D) have been updated using 7 days worth of data.
Distributions are smoother.
This patch also moves data from header file to individual csv file. It
helps the editor and allows easier export/plotting of the data.
Differential Revision: https://reviews.llvm.org/D105766
Fraser Cormack [Wed, 23 Jun 2021 14:14:50 +0000 (15:14 +0100)]
[RISCV] Pass undef VECTOR_SHUFFLE indices on to BUILD_VECTOR
Often when lowering vector shuffles, we split the shuffle into two
LHS/RHS shuffles which are then blended together. To do so we split the
original indices into two, indexed into each respective vector. These
two index vectors are then separately lowered as BUILD_VECTORs.
This patch forwards on any undef indices to the BUILD_VECTOR, rather
than having the VECTOR_SHUFFLE lowering decide on an optimal concrete
index. The motiviation for ths change is so that we don't duplicate
optimization logic between the two lowering methods and let BUILD_VECTOR
do what it does best.
Propagating undef in this way allows us, for example, to generate
`vid.v` to produce the LHS indices of commonly-used interleave-type
shuffles. I have designs on further optimizing interleave-type and other
common shuffle patterns in the near future.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D104789
Jeroen Dobbelaere [Tue, 13 Jul 2021 08:37:45 +0000 (10:37 +0200)]
[remangleIntrinsicFunction] Detect and resolve name clash
It is possible that the remangled name for an intrinsic already exists with a different (and wrong) prototype within the module.
As the bitcode reader keeps both versions of all remangled intrinsics around for a longer time, this can result in a
crash, as can be seen in https://bugs.llvm.org/show_bug.cgi?id=50923
This patch makes 'remangleIntrinsicFunction' aware of this situation. When it is detected, it moves the version with the wrong prototype to a different name. That version will be removed anyway once the module is completely loaded.
With thanks to @asbirlea for reporting this issue when trying out an lto build with the full restrict patches, and @efriedma for suggesting a sane resolution mechanism.
Reviewed By: apilipenko
Differential Revision: https://reviews.llvm.org/D105118
Rainer Orth [Tue, 13 Jul 2021 09:15:03 +0000 (11:15 +0200)]
[sanitizer_common] Define internal_usleep on Solaris
The Solaris/amd64 buildbot
<https://lab.llvm.org/staging/#/builders/101/builds/2845> has recently been
broken several times, at least one of those remains unfixed:
[63/446] Generating Sanitizer-x86_64-Test
[...]
Undefined first referenced
symbol in file
_ZN11__sanitizer15internal_usleepEy /opt/llvm-buildbot/home/solaris11-amd64/clang-solaris11-amd64/stage1/projects/compiler-rt/lib/sanitizer_common/tests/libRTSanitizerCommon.test.x86_64.a(sanitizer_common.cpp.o)
ld: fatal: symbol referencing errors
Thist patch fixes it by defining the missing `internal_usleep`.
Tested on `amd64-pc-solaris2.11.`
Differential Revision: https://reviews.llvm.org/D105878
Jeroen Dobbelaere [Tue, 13 Jul 2021 08:16:41 +0000 (10:16 +0200)]
[NFC] Do not track calls to inlined intrinsics in IFI.
Just like intrinsics are not tracked for IFI.InlinedCalls, they should not be tracked for IFI.InlinedCallSites.
In the current top-of-tree this change is a NFC, but the full restrict patches (D68484) potentially trigger an read-after-free
if intrinsics are also added to the InlindeCallSites, due to a late optimization potentially removing some of the inlined intrinsics.
Also see https://lists.llvm.org/pipermail/llvm-dev/2021-July/151722.html for a discussion about the problem.
Reviewed By: aeubanks
Differential Revision: https://reviews.llvm.org/D105805
Dmitry Vyukov [Sun, 11 Jul 2021 13:12:24 +0000 (15:12 +0200)]
sanitizer_common: optimize memory drain
Currently we allocate MemoryMapper per size class.
MemoryMapper mmap's and munmap's internal buffer.
This results in 50 mmap/munmap calls under the global
allocator mutex. Reuse MemoryMapper and the buffer
for all size classes. This radically reduces number of
mmap/munmap calls. Smaller size classes tend to have
more objects allocated, so it's highly likely that
the buffer allocated for the first size class will
be enough for all subsequent size classes.
Reviewed By: melver
Differential Revision: https://reviews.llvm.org/D105778
Qiu Chaofan [Tue, 13 Jul 2021 06:50:26 +0000 (14:50 +0800)]
[SelectionDAG] Check use before combining into USUBSAT
Reviewed By: RKSimon
Differential Revision: https://reviews.llvm.org/D105789
Stanislav Mekhanoshin [Fri, 9 Jul 2021 21:05:57 +0000 (14:05 -0700)]
[AMDGPU] Make some VOP1 instructions rematerializable
This is a pilot change to verify the logic. The rest will be
done in a same way, at least the rest of VOP1.
Differential Revision: https://reviews.llvm.org/D105742
Qiu Chaofan [Tue, 13 Jul 2021 06:32:30 +0000 (14:32 +0800)]
[PowerPC] Fix typo in vector shuffle combining
a22ecb4 fixed a crash on big endian subtargets. This commit fixes a typo
in that commit which may cause miscompile.
hyeongyu kim [Tue, 13 Jul 2021 06:34:41 +0000 (15:34 +0900)]
[SimplifyCFG] Fix SimplifyBranchOnICmpChain to be undef/poison safe.
This patch fixes the problem of SimplifyBranchOnICmpChain that occurs
when extra values are Undef or poison.
Suppose the %mode is 51 and the %Cond is poison, and let's look at the
case below.
```
%A = icmp ne i32 %mode, 0
%B = icmp ne i32 %mode, 51
%C = select i1 %A, i1 %B, i1 false
%D = select i1 %C, i1 %Cond, i1 false
br i1 %D, label %T, label %F
=>
br i1 %Cond, label %switch.early.test, label %F
switch.early.test:
switch i32 %mode, label %T [
i32 51, label %F
i32 0, label %F
]
```
incorrectness: https://alive2.llvm.org/ce/z/BWScX
Code before transformation will not raise UB because %C and %D is false,
and it will not use %Cond. But after transformation, %Cond is being used
immediately, and it will raise UB.
This problem can be solved by adding freeze instruction.
correctness: https://alive2.llvm.org/ce/z/x9x4oY
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D104569
David Green [Tue, 13 Jul 2021 06:31:22 +0000 (07:31 +0100)]
[MIPS] Regenerate test after D105161. NFC
David Green [Tue, 13 Jul 2021 06:21:20 +0000 (07:21 +0100)]
[ARM] Introduce MVEEXT ISel lowering
Similar to D91921 (and D104515) this introduces two MVESEXT and MVEZEXT
nodes that larger-than-legal sext and zext are lowered to. These either
get optimized away or end up becoming a series of stack loads/store, in
order to perform the extending whilst keeping the order of the lanes
correct. They are generated from v8i16->v8i32, v16i8->v16i16 and
v16i8->v16i32 extends, potentially with a intermediate extend for the
larger v16i8->v16i32 extend. A number of combines have been added for
obvious cases that come up in tests, notably MVEEXT of shuffles. More
may be needed in the future, but this seems to cover most of the cases
that come up in the tests.
Differential Revision: https://reviews.llvm.org/D105090
hyeongyu kim [Tue, 13 Jul 2021 06:10:24 +0000 (15:10 +0900)]
[NFC] Edit the comment in M68kInstrInfo::ExpandMOVSZX_RM
Chen Zheng [Tue, 13 Jul 2021 05:37:05 +0000 (05:37 +0000)]
[PowerPC][NFC] add test case for preparing more loads/stores
Nathan Ridge [Tue, 6 Jul 2021 05:40:24 +0000 (01:40 -0400)]
[clang] Refactor AST printing tests to share more infrastructure
Differential Revision: https://reviews.llvm.org/D105457
Vitaly Buka [Tue, 13 Jul 2021 05:23:01 +0000 (22:23 -0700)]
[NFC][scudo] Clang format a file
Vitaly Buka [Tue, 13 Jul 2021 05:20:49 +0000 (22:20 -0700)]
Revert "[X86][SSE] X86ISD::FSETCC nodes (cmpss/cmpsd) return a 0/-1 allbits signbits result"
Fails here https://lab.llvm.org/buildbot/#/builders/37/builds/5267
This reverts commit
e4aa6ad132164839a4a97dff0d433ea4766f77f1.
Jessica Paquette [Wed, 30 Jun 2021 00:01:28 +0000 (17:01 -0700)]
[GlobalISel] Handle more types in narrowScalar for eq/ne G_ICMP
Generalize the existing eq/ne case using `extractParts`. The original code only
handled narrowings for types of width 2n->n. This generalization allows for any
type that can be broken down by `extractParts`.
General overview is:
- Loop over each narrow-sized part and do exactly what the 2-register case did.
- Loop over the leftover-sized parts and do the same thing
- Widen the leftover-sized XOR results to the desired narrow size
- OR that all together and then do the comparison against 0 (just like the old
code)
This shows up a lot when building clang for AArch64 using GlobalISel, so it's
worth fixing. For the sake of simplicity, this doesn't handle the non-eq/ne
case yet.
Also remove the code in this case that notifies the observer; we're just going
to delete MI anyway so talking to the observer shouldn't be necessary.
Differential Revision: https://reviews.llvm.org/D105161
Vitaly Buka [Tue, 13 Jul 2021 05:15:20 +0000 (22:15 -0700)]
Revert "[hwasan] More realistic setjmp test."
Breaks https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux-qemu
This reverts commit
5511bfdb671505c1e7968ab8ef6032414bba3852.
SharmaRithik [Tue, 13 Jul 2021 04:52:47 +0000 (04:52 +0000)]
[analyzer] Print time taken to analyze each function
Summary: This patch is a part of an attempt to obtain more
timer data from the analyzer. In this patch, we try to use
LLVM::TimeRecord to save time before starting the analysis
and to print the time that a specific function takes while
getting analyzed.
The timer data is printed along with the
-analyzer-display-progress outputs.
ANALYZE (Syntax): test.c functionName : 0.4 ms
ANALYZE (Path, Inline_Regular): test.c functionName : 2.6 ms
Authored By: RithikSharma
Reviewer: NoQ, xazax.hun, teemperor, vsavchenko
Reviewed By: NoQ
Differential Revision: https://reviews.llvm.org/D105565
Arthur Eubanks [Tue, 13 Jul 2021 04:14:35 +0000 (21:14 -0700)]
[OpaquePtr][ISel] Use ArgListEntry::IndirectType more
Arthur Eubanks [Fri, 9 Jul 2021 16:24:59 +0000 (09:24 -0700)]
[OpaquePointers][ThreadSanitizer] Cleanup calls to PointerType::getElementType()
Reviewed By: #opaque-pointers, dblaikie
Differential Revision: https://reviews.llvm.org/D105710
David Blaikie [Tue, 13 Jul 2021 01:39:41 +0000 (18:39 -0700)]
Fix test - mistaken hardcoded path from my local machine.
David Blaikie [Tue, 13 Jul 2021 01:10:58 +0000 (18:10 -0700)]
DebugInfo: Use debug_rnglists.dwo for ranges in debug_info.dwo when parsing DWARFv5
This call would incorrectly overwrite (with the .debug_rnglists.dwo from
the executable, if there was one) the rnglists section instead of the
correct value (from the .debug_rnglists.dwo in the .dwo file) that's
applied in DWARFUnit::tryExtractDIEsIfNeeded
Aart Bik [Mon, 12 Jul 2021 22:22:31 +0000 (15:22 -0700)]
[mlir][sparse] add support for AND and OR operations
Integral AND and OR follow the simple conjunction and disjuction rules
for lattice building. This revision also completes some of the Merge
refactoring by moving the remainder parts that are merger specific from
sparsification into utils files.
Reviewed By: gussmith23
Differential Revision: https://reviews.llvm.org/D105851
Fangrui Song [Tue, 13 Jul 2021 00:44:02 +0000 (17:44 -0700)]
[llc] Default MCUseDwarfDirectory to true
For Clang, `MCUseDwarfDirectory` is true by default for the majority cases
(-fintegrated-as or -gdwarf-5; most targets use -fintegrated-as by default).
Defaulting MCUseDwarfDirectory to true can reduce the differences between clang
and llc.
Reviewed By: #debug-info, dblaikie
Differential Revision: https://reviews.llvm.org/D105856
Hanhan Wang [Tue, 13 Jul 2021 00:25:55 +0000 (17:25 -0700)]
[mlir][Linalg] Add 3D pooling named ops to Linalg.
Reviewed By: gysit, hanchung
Differential Revision: https://reviews.llvm.org/D105329
Leonard Chan [Fri, 9 Jul 2021 20:41:48 +0000 (13:41 -0700)]
[compiler-rt][hwasan] Refactor kAliasRegionStart usage
This moves logic for setting kAliasRegionStart into hwasan_allocator.cpp
so other platforms that do not support aliasing mode will not need to define
kAliasRegionStart.
Differential Revision: https://reviews.llvm.org/D105725
Marco Elver [Mon, 12 Jul 2021 22:39:17 +0000 (15:39 -0700)]
sanitizer_common: Fix build for tests
It turns out that COMPILER_RT_TEST_COMPILER_CFLAGS is actually a string
that is being appended to and not a list.
Therefore, append the thread-safety flags to the string. Because CMake
separates list elements by ';' when turning into a string, also
substitute ';' with ' '.
Reviewed By: hctim
Differential Revision: https://reviews.llvm.org/D105829
Fangrui Song [Mon, 12 Jul 2021 22:46:20 +0000 (15:46 -0700)]
[Driver] Let -fno-integrated-as -gdwarf-5 use -fdwarf-directory-asm
While GNU as only allows the directory form of the .file directive for DWARF v5,
the integrated assembler prefers the directory form on all DWARF versions
(-fdwarf-directory-asm).
We currently set CC1 -fno-dwarf-directory-asm for -fno-integrated-as -gdwarf-5
which may cause the directory entry 0 and the filename entry 0 to be incorrect
(see D105662 and the example below). This patch makes -fno-integrated-as -gdwarf-5 use
-fdwarf-directory-asm as well.
```
cd /tmp/c
before
% clang -g -gdwarf-5 -fno-integrated-as e/a.c -S -o - | grep '\.file.*0'
.file 0 "/tmp/c/e/a.c" md5 0x97e31cee64b4e58a4af8787512d735b6
% clang -g -gdwarf-5 -fno-integrated-as e/a.c -c
% llvm-dwarfdump a.o | grep include_directories
include_directories[ 0] = "/tmp/c/e"
after
% clang -g -gdwarf-5 -fno-integrated-as e/a.c -S -o - | grep '\.file.*0'
.file 0 "/tmp/c" "e/a.c" md5 0x97e31cee64b4e58a4af8787512d735b6
% clang -g -gdwarf-5 -fno-integrated-as e/a.c -c
% llvm-dwarfdump a.o | grep include_directories
include_directories[ 0] = "/tmp/c"
```
Reviewed By: #debug-info, dblaikie, osandov
Differential Revision: https://reviews.llvm.org/D105835
Rob Suderman [Thu, 8 Jul 2021 22:17:15 +0000 (15:17 -0700)]
[mlir][tosa] Added shape propagation for TOSA pool operations.
Pool operations perform the same shape propagation. Included the shape
propagation and tests for these avg_pool2d and max_pool2d.
Differential Revision: https://reviews.llvm.org/D105665
Jon Roelofs [Mon, 12 Jul 2021 22:36:36 +0000 (15:36 -0700)]
[AArch64] Dump a little more info about unimplemented reg-to-reg copies. NFC
Eli Friedman [Mon, 12 Jul 2021 22:28:09 +0000 (15:28 -0700)]
[AArch64] Optimize overflow checks for [s|u]mul.with.overflow.i32.
Saves one instruction for signed, uses a cheaper instruction for
unsigned.
Differential Revision: https://reviews.llvm.org/D105770
Wouter van Oortmerssen [Mon, 12 Jul 2021 22:05:11 +0000 (15:05 -0700)]
[WebAssembly] Fixed LLD generation of 64-bit __wasm_init_memory
Differential Revision: https://reviews.llvm.org/D105849
Aart Bik [Fri, 9 Jul 2021 20:45:23 +0000 (13:45 -0700)]
[mlir][sparse] add restrictive versions of division support
Right now, we only accept x/c with nonzero c, since this
conceptually can be treated as a x*(1/c) conjunction for both
FP and INT as far as lattice computations go. The codegen
keeps the division though to preserve precise semantics.
See discussion:
https://llvm.discourse.group/t/sparse-tensors-in-mlir/3389/28
Reviewed By: gussmith23
Differential Revision: https://reviews.llvm.org/D105731
Eli Friedman [Mon, 12 Jul 2021 20:06:23 +0000 (13:06 -0700)]
[SelectionDAG][RISCV] Support @llvm.vscale.i64() on 32-bit targets.
Not really useful on its own, but D105673 depends on it.
Differential Revision: https://reviews.llvm.org/D105840
Louis Dionne [Mon, 12 Jul 2021 21:26:16 +0000 (17:26 -0400)]
[libc++] ci: Properly target macOS nodes per-os
Louis Dionne [Mon, 12 Jul 2021 21:22:26 +0000 (17:22 -0400)]
[libc++] Add the 'os=macos' tag to macOS nodes to workaround lack of wildcard matching
Jim Ingham [Fri, 9 Jul 2021 01:08:11 +0000 (18:08 -0700)]
Revert "Revert "Reset the wakeup timeout when we re-enter the continue wait.""
This reverts commit
82a38837150099288a1262391ef43e1fd69ffde4.
The original version had a copy-paste error: using the Interrupt timeout
for the ResumeSynchronous wait, which is clearly wrong. This error would
have been evident with real use, but the interrupt is long enough that it
only caused one testsuite failure (in the Swift fork).
Anyway, I found that mistake and fixed it and checked all the other places
where I had to plumb through a timeout, and added a test with a short
interrupt timeout stepping over a function that takes 3x the interrupt timeout
to complete, so that should detect a similar mistake in the future.