Simon Glass [Sat, 29 Aug 2020 17:36:15 +0000 (11:36 -0600)]
tools: Drop unnecessary use of __file__
There are few places where the path of the current modules is calculated
but not used. Drop them.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 29 Aug 2020 17:36:14 +0000 (11:36 -0600)]
binman: Use pkg_resources to find resources
At present we look for resources based on the path of the Python module
that wants them. Instead we should use Python's pkg_resources feature
which is designed for this purpose.
Update binman to use this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Alper Nebi Yasak [Mon, 31 Aug 2020 09:58:20 +0000 (12:58 +0300)]
binman: Build FIT image subentries with the section etype
When reading subentries of each image, the FIT entry type directly
concatenates their contents without padding them according to their
offset, size, align, align-size, align-end, pad-before, pad-after
properties.
This patch makes sure these properties are respected by offloading this
image-data building to the section etype, where each subnode of the
"images" node is processed as a section. Alignments and offsets are
respective to the beginning of each image. For example, the following
fragment can end up having "u-boot-spl" start at 0x88 within the final
FIT binary, while "u-boot" would then end up starting at e.g. 0x20088.
fit {
description = "example";
images {
kernel-1 {
description = "U-Boot with SPL";
type = "kernel";
arch = "arm64";
os = "linux";
compression = "none";
u-boot-spl {
};
u-boot {
align = <0x10000>;
};
};
};
}
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reinstate check in testPadInSections(), squash in
"binman: Allow FIT binaries to have missing external blobs"
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Alper Nebi Yasak [Mon, 31 Aug 2020 09:58:19 +0000 (12:58 +0300)]
binman: Respect pad-before property of section subentries
Other relevant properties (pad-after, offset, size, align, align-size,
align-end) already work since Pack() sets correct ranges for subentries'
data (.offset, .size variables), but some padding here is necessary to
align the data within this range to match the pad-before property.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Alper Nebi Yasak [Mon, 31 Aug 2020 09:58:18 +0000 (12:58 +0300)]
binman: Ignore hash*, signature* nodes in sections
Switch to str.startswith for matching like the FIT etype does since the
current version doesn't ignore 'hash-1', 'hash-2', etc.
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 21 Sep 2020 20:44:16 +0000 (16:44 -0400)]
Merge branch '2020-09-14-generic-phy-error-trace' into next
- Add error tracing messages to the generic PHY infrastructure
Tom Rini [Mon, 21 Sep 2020 18:25:37 +0000 (14:25 -0400)]
Merge branch 'master' into next
Merge in v2020.10-rc5
Tom Rini [Mon, 21 Sep 2020 17:45:23 +0000 (13:45 -0400)]
Prepare v2020.10-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 21 Sep 2020 17:45:07 +0000 (13:45 -0400)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 21 Sep 2020 15:01:07 +0000 (11:01 -0400)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86
- Several ACPI bug fixes
- Intel edison: Move config SYS_MALLOC_LEN to Kconfig
- Use "emmc" in ApolloLake FSP devicetree bindings
Wolfgang Wallner [Wed, 16 Sep 2020 14:57:53 +0000 (16:57 +0200)]
x86: acpi: Add memset to initialize SPCR table
Add a missing memset to acpi_create_spcr().
The other acpi_create_xxxx() functions perform a memset on their
structures, acpi_create_spcr() does not and as a result the contents of
this table are partly uninitialized (and thus random after every reset).
Fixes:
b288cd960072 ("x86: acpi: Generate SPCR table")
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: fix the tags format in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Wolfgang Wallner [Wed, 16 Sep 2020 14:57:52 +0000 (16:57 +0200)]
x86: acpi: Fix calculation of DSDT length
Currently, the calculation for the length of the DSDT table includes any
bytes that are added for alignment, but those bytes are not initialized.
This is because the DSDT length is calculated after a call to
acpi_inc_align(). Split this up into the following sequence:
* acpi_inc()
* Calculate DSDT length
* acpi_align()
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Wolfgang Wallner [Fri, 11 Sep 2020 14:52:28 +0000 (16:52 +0200)]
x86: fsp: Replace e-mmc with emmc in devicetree bindings
The term eMMC is used inconsistently within the FSP devicetree
bindings (e-mmc and emmc), especially for "emmc-host-max-speed"
documentation and code disagree.
Change all eMMC instances within the FSP bindings to consistently
use "emmc". The term "emmc" is already used a lot within U-Boot,
while "e-mmc" is only used in the FSP bindings.
Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: correct one typo in the commit message]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Mon, 21 Sep 2020 08:34:21 +0000 (11:34 +0300)]
cmd: acpi: Print revisions in hex format
The revisions are usually dates in hex-decimal format representing
YYYYmmdd. Print them in hex to see this clearly.
Before:
...
FACP
000e5420 0000f4 (v06 U-BOOT U-BOOTBL
538970376 INTL 0)
DSDT
000e4780 000ba0 (v02 U-BOOT U-BOOTBL 65536 INTL
538968870)
...
After:
...
FACP
000e5420 0000f4 (v06 U-BOOT U-BOOTBL
20200908 INTL 0)
DSDT
000e4780 000ba0 (v02 U-BOOT U-BOOTBL 10000 INTL
20200326)
...
Fixes:
0b885bcfd9b0 ("acpi: Add an acpi command")
Cc: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Andy Shevchenko [Tue, 8 Sep 2020 13:57:22 +0000 (16:57 +0300)]
x86: edison: Move config SYS_MALLOC_LEN to Kconfig
This patch moves the the config SYS_MALLOC_LEN to Kconfig
as it is already done for zynq arch in commit
01aa5b8f0503
("Kconfig: Move config SYS_MALLOC_LEN to Kconfig for zynq").
Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Sat, 19 Sep 2020 12:35:20 +0000 (08:35 -0400)]
Merge tag 'efi-2020-10-rc5-2' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5 (2)
The following bugs are fixed:
* incorrect online help for setenv and env
* description of function efi_mem_carve_out()
* replace printf() by log_err() in stm32mp1_rng driver
A unit test is provided to check that the boot hart id is provided in the
RISC-V device-tree.
Tom Rini [Sat, 19 Sep 2020 12:31:52 +0000 (08:31 -0400)]
Merge branch '2020-09-18-assorted-bugfixes'
- SquashFS Coverity fixes
- bitflip fix in the alternate memtest command
- Disable networking on bcmstb boards where we didn't have any network
drivers enabled.
Tom Rini [Sat, 19 Sep 2020 12:30:54 +0000 (08:30 -0400)]
Merge branch '2020-09-18-improve-ipq40xx-support' into next
- Assorted improvements to the Qualcomm IPQ40XX SoC
Maxim Uvarov [Fri, 28 Aug 2020 19:20:10 +0000 (22:20 +0300)]
efi: change 'env -e -i' usage syntax
'env -e -i' syntax was changed from "," to ":". Account for this also
in the documentation.
Fixes:
2b3fbcb59f41 ("efi_loader: use ':' as separator for setenv -i")
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Correct the usage description for setenv -e too.
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 17 Sep 2020 05:33:29 +0000 (07:33 +0200)]
efi_selftest: check for RISC-V boot-hartid in FDT
On RISC-V check that the /chosen node has a boot-hartid property.
To run the test configure with CONFIG_CMD_BOOTEFI_SELFTEST=y and issue
setenv efi_selftest device tree
setenv serial# myserial
bootefi selftest
If the test succeeds, it reports the boot-hartid, e.g.
boot-hartid: 1
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 17 Sep 2020 05:33:29 +0000 (07:33 +0200)]
efi_selftest: rework device tree test
Allow specifying the node on which a property is searched.
Test the device tree consistency more rigorously.
Some efi_st_printf() calls have been converted to efi_st_error().
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Maxim Uvarov [Fri, 28 Aug 2020 19:47:41 +0000 (22:47 +0300)]
efi_memory: refine overlap_only_ram description
Refine text for overlap_only_ram description to
match to what exactly flag does and aling description
with other functions.
Signed-off-by: Maxim Uvarov <maxim.uvarov@linaro.org>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 17 Sep 2020 14:49:02 +0000 (16:49 +0200)]
rng: stm32mp1: use log() instead of printf()
The logging system provides flexible filtering and enhanced output.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Sughosh Ganu <sughosh.ganu@linaro.org>
Robert Marko [Thu, 10 Sep 2020 14:00:06 +0000 (16:00 +0200)]
IPQ40xx: Add USB nodes
There are drivers to support built in USB controller and PHY-s now, so lets add the USB nodes to DTSI.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Robert Marko [Thu, 10 Sep 2020 14:00:05 +0000 (16:00 +0200)]
usb: dwc3: Add Qualcomm DWC3 compatible string
Lot of Qualcomm SoC-s use DWC3 controller for both USB2.0 and USB3.0
ports.
Qualcomm has some custom config registers on top of the generic ones,
but for host mode these are not needed.
So lets add the neccessary compatible string.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Robert Marko [Thu, 10 Sep 2020 14:00:04 +0000 (16:00 +0200)]
phy: add driver for Qualcomm IPQ40xx USB PHY
Add a driver to setup the USB PHY-s on Qualcomm IPQ40xx series SoCs.
The driver sets up HS and SS phys.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Robert Marko [Thu, 10 Sep 2020 14:00:03 +0000 (16:00 +0200)]
IPQ40xx: Add reset controller support
Since we have a driver for the reset controller, lets add the necessary node.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Robert Marko [Thu, 10 Sep 2020 14:00:02 +0000 (16:00 +0200)]
reset: Add IPQ40xx reset controller driver
On Qualcomm IPQ40xx SoC series, GCC clock IP also handles the resets.
So since this will be needed by further drivers, lets add a driver for the reset controller.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Robert Marko [Thu, 10 Sep 2020 14:00:01 +0000 (16:00 +0200)]
IPQ40xx: Add SMEM support
There is already existing driver for SMEM so lets enable it for IPQ40xx as well.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Robert Marko [Thu, 10 Sep 2020 14:00:00 +0000 (16:00 +0200)]
IPQ40xx: clk: Use dt-bindings instead of hardcoding
Its common to use dt-bindings instead of hard-coding clocks or resets.
So lets use the imported Linux GCC bindings on IPQ40xx target.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Ralph Siemsen [Wed, 9 Sep 2020 16:10:00 +0000 (12:10 -0400)]
cmd: mem: fix range of bitflip test
The bitflip test uses two equal sized memory buffers. This is achieved
by splitting the range of memory into two pieces. The address of the
second buffer, as well as the length of each buffer, were not correctly
calculated. This caused bitflip test to access beyond the end of range.
This patch fixes the pointer arithmetic problem.
A second problem arises because u-boot "mtest" command expects the
ending address to be inclusive. When computing (end - start) this
results in missing 1 byte of the requested length. The bitflip test
expects a count rather than an "ending" address. Thus it fails to test
the last word of the requested range. Fixed by using (end - start + 1).
Added Kconfig option to optionally disable the bitflip test, since it
does add significantly to the time taken for "mtest".
Fixes:
8e434cb705d463bc8cff935160e4fb4c77cb99ab ("cmd: mem: Add bitflip
memory test to alternate mtest")
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Thomas Fitzsimmons [Fri, 11 Sep 2020 18:41:44 +0000 (14:41 -0400)]
configs: bcmstb: Disable networking support
Silence the "Driver Model for Ethernet drivers" migration warning for
the bcm7445 and bcm7260 ports, neither of which supports networking yet.
Signed-off-by: Thomas Fitzsimmons <fitzsim@fitzsim.org>
Reviewed-by: Tom Rini <trini@konsulko.com>
Joao Marcos Costa [Fri, 11 Sep 2020 10:21:06 +0000 (12:21 +0200)]
fs/squashfs: Fix Coverity Scan defects
Fix control flow issues and null pointer dereferences.
Signed-off-by: Joao Marcos Costa <jmcosta944@gmail.com>
Tom Rini [Fri, 18 Sep 2020 14:42:12 +0000 (10:42 -0400)]
Merge tag 'u-boot-imx-
20200918' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
----------------------------------------------------------------
Fixes for 2020.10
-----------------
- Toradex boards
- mx6qsabrelite: fix env offset
- esdhc_imx: waiting for clock instead of sleep
- dyn RAM calibration for entry point i.MX6
Travis: https://travis-ci.org/github/sbabic/u-boot-imx/builds/
728274602
Soeren Moch [Thu, 27 Aug 2020 19:52:47 +0000 (21:52 +0200)]
board: tbs2910: Disable CONFIG_ENV_VARS_UBOOT_CONFIG in defconfig
This is not required for sysboot (we defined fdtfile), let's save a few
bytes in the binary image without these variables.
Signed-off-by: Soeren Moch <smoch@web.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Tom Rini [Thu, 17 Sep 2020 13:55:01 +0000 (09:55 -0400)]
Merge tag 'for-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c into next
mpc83xx, keymile boards: enable DM_ETH and add DTS
- mpc83xx: remove unneeded extern declaration in cpu_init
- powerpc, qe: fix codingstyle issues for drivers/qe
- powerpc, qe: add DTS support for parallel I/O ports
- net, qe: add DM support for QE UEC ethernet
- add DTS for all mpc83xx based boards from keymile
mainly they are not mainlined to linux.
- add u-boot specific dtsi
- add stdout-path
- add missing ucc4 par_io definitions, which were
in board code, but not in linux DTS
- remove not used ethernet nodes
Tom Rini [Thu, 17 Sep 2020 13:53:57 +0000 (09:53 -0400)]
Merge branch '2020-09-16-assorted-fixes'
- Assorted bug fixes
Philippe Schenker [Fri, 28 Aug 2020 18:08:06 +0000 (21:08 +0300)]
apalis-imx8qm: rename all occurences to apalis-imx8
The Toradex product is called apalis-imx8 consisting of SoM with
i.MX8QM and i.MX8QP SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Philippe Schenker [Fri, 28 Aug 2020 18:08:05 +0000 (21:08 +0300)]
colibri-imx8qxp: rename all occurences to colibri-imx8x
The Toradex product is called colibri-imx8x consisting of SoM with
i.MX8QXP and i.MX8DX SoCs.
Signed-off-by: Philippe Schenker <philippe.schenker@toradex.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Haibo Chen [Tue, 1 Sep 2020 07:34:06 +0000 (15:34 +0800)]
mmc: fsl_esdhc_imx: check the clock stable status after config the clock rate.
Currently, after config the clock rate, delay 10ms, this is quite a rough
method. Check the clock stable status in the present status register is
enough.
Tested-by: Ji Luo <ji.luo@nxp.com>
Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
Marek Vasut [Sat, 12 Sep 2020 23:35:08 +0000 (01:35 +0200)]
ARM: mx6: ddr: Add support for iMX6UL/ULL/SL/SDL
This patch adds support for iMX6UL/ULL/SL/SDL MMDC into the DDR calibration
code. The difference between MX6DQ and MX6UL/ULL/SL is that the later SoCs
have 2 SDQS registers, just like MX6SX, while the MX6DQ/MX6SDL has 8.
Fixes:
4f4c128c65 ("ARM: mx6: ddr: Add support for iMX6SX")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Eric Nelson <eric@nelint.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Denis Pynkin [Tue, 15 Sep 2020 11:37:14 +0000 (14:37 +0300)]
mx6qsabrelite: increase the environment offset
The size of the binary created with the default U-boot config is much
greater than the default offset for environment `0x60000`.
In case if that binary is used for booting via MMC it is overlapped with
the environment stored on MMC.
This leads to U-Boot corruption while saving environment with `saveenv`
command and non-bootable SabreLite board.
The offset for environment `CONFIG_ENV_OFFSET=0x60000` was added in
commit a09fea1 but did not count in the change to `0xC0000` if option
`CONFIG_ENV_IS_IN_MMC` is used.
The offset is also used for variant with environment saving onto SPI NOR
flash (with enabled option `CONFIG_ENV_IS_IN_SPI_FLASH`). In that case the
U-Boot binary flashed on SPI NOR is also corrupted after environment
saving with the original 0x60000 offset.
Signed-off-by: Denis Pynkin <denis.pynkin@collabora.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Peng Fan [Wed, 16 Sep 2020 07:17:22 +0000 (15:17 +0800)]
imx8mp: Remove parts MIMX8ML7 and MIMX8ML5 support
Latest datasheet revE has removed MIMX8ML7D/5D/7C/5C parts, so
update u-boot to remove decoding and support for those parts.
Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 16 Sep 2020 07:17:21 +0000 (15:17 +0800)]
imx8m: clock_imx8mm: add missed return
Add missed return
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Wed, 16 Sep 2020 07:17:20 +0000 (15:17 +0800)]
imx8mq: fix SSCG_PLL_REFCLK_SEL_x
Fix SSCG_PLL_REFCLK_SEL_x, the offset starts from 0, not 16
Reported-by: Coverity 3448860
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Peng Fan [Wed, 16 Sep 2020 07:17:19 +0000 (15:17 +0800)]
imx8mq: fix FRAC_PLL_REFCLK_SEL_MASK
Coverity reported dead code, however it is FRAC_PLL_REFCLK_SEL_MASK
was wrongly set.
Reported-by: Coverity 10045172
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Peng Fan [Wed, 16 Sep 2020 07:17:18 +0000 (15:17 +0800)]
imx7: ccm: correct target interface num
According to i.MX 7Dual Applications Processor Reference Manual, Rev. 1
The target interface CCM root index ranges [0,124], so the number
should be 125.
Reported-by: Coverity 18045
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Ye Li <ye.li@nxp.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:12 +0000 (11:01 +0300)]
apalis_imx6: provide fdtfile in env instead of setting it in runtime
Provide fdtfile value in default env instead of setting
it dynamically in runtime.
Fixes:
85cb2bc686("apalis/colibri imx6: provide proper fdtfile value")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:11 +0000 (11:01 +0300)]
colibri_imx6: provide fdtfile in env instead of setting it in runtime
Provide fdtfile value in default env instead of setting
it dynamically in runtime.
Fixes:
85cb2bc686("apalis/colibri imx6: provide proper fdtfile value")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:10 +0000 (11:01 +0300)]
colibri_imx7: use preboot for fdtfile evaluation
Enable and set preboot var with fdtfile evaluation.
preboot will be checked and run immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp.
entering interactive mode.
This provides possibility to use different boot cmds in interactive mode
without manual setting fdtfile value, as it it's already evaluated
before entering interactive mode.
Fixes:
a62c60610f("colibri_imx7_emmc: add Colibri iMX7D 1GB (eMMC) module support")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:09 +0000 (11:01 +0300)]
colibri_vf: use preboot for fdtfile evaluation
Enable and set preboot var with fdtfile evaluation.
preboot will be checked and run immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp.
entering interactive mode.
This provides possibility to use different boot cmds in interactive mode
without manual setting fdtfile value, as it it's already evaluated
before entering interactive mode.
Fixes:
304042c1f3("colibri_vf: set fdtfile for distroboot")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:08 +0000 (11:01 +0300)]
colibri-imx6ull: use preboot for fdtfile evaluation
Enable and set preboot var with fdtfile evaluation.
preboot will be checked and run immediately before starting the
CONFIG_BOOTDELAY countdown and/or running the auto-boot command resp.
entering interactive mode.
This provides possibility to use different boot cmds in interactive mode
without manual setting fdtfile value, as it it's already evaluated
before entering interactive mode.
Fixes: board:
31b1e17f44("toradex: add Colibri iMX6ULL support")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:07 +0000 (11:01 +0300)]
colibri_imx7: wrap video specific funcs with ifdefs
Wrap video specific functionality with ifdefs.
Fixes:
195011b24d("colibri-imx7: fix splash logo drawing")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:06 +0000 (11:01 +0300)]
toradex: drop legacy show_boot_logo function and use splashscreen
Drop show_boot_logo legacy function, as splashscreen functionality can
be used instead.
Fixes:
d324189772("toradex: common: show boot logo")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:05 +0000 (11:01 +0300)]
colibri_imx7: use splashcreen value instead of legacy function
Set proper splashscreen env value instead of calling legacy function
to show embed boot logo.
Fixes:
195011b24d("colibri-imx7: fix splash logo drawing")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Mon, 14 Sep 2020 08:01:04 +0000 (11:01 +0300)]
colibri-imx6ull: use splashcreen value instead of legacy function
Set proper splashscreen env value instead of calling legacy function
to show embed boot logo.
Fixes:
391c712dde("colibri-imx6ull: show boot logo")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Heiko Schocher [Mon, 3 Feb 2020 06:43:57 +0000 (07:43 +0100)]
mpc83xx, keymile boards: enable DM_ETH and add DTS
enable DTS support for keymile mpc83xx based boards.
get rid of compile warning:
===================== WARNING ======================
This board does not use CONFIG_DM_ETH (Driver Model
for Ethernet drivers). Please update the board to use
CONFIG_DM_ETH before the v2020.07 release. Failure to
update by the deadline may result in board removal.
See doc/driver-model/migration.rst for more info.
====================================================
Therefore done:
- add DTS for all mpc83xx based boards from keymile
mainly they are not mainlined to linux.
- add u-boot specific dtsi
- add stdout-path
- add missing ucc4 par_io definitions, which were
in board code, but not in linux DTS
- remove not used ethernet nodes
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Series-to: u-boot
Series-version: 3
Series-changes: 3
- rebase patchset to current mainline commit
c0192950df
- update defconfig files
Series-changes: 2
- add patch which fixes Codingstyle errors in drivers/qe
- add patch which converts the mpc83xx based boards from
keymile to DM_ETH
Cover-letter:
powerpc, mpc83xx: add DM_ETH support
This patch series adds DM ethernet support for mpc83xx based
keymile boards.
Travis build:
END
Heiko Schocher [Thu, 6 Feb 2020 08:48:16 +0000 (09:48 +0100)]
net, qe: add DM support for QE UEC ethernet
add DM/DTS support for the UEC ethernet on QUICC Engine
Block.
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Patch-cc: Madalin Bucur <madalin.bucur@oss.nxp.com>
Series-changes: 3
- revert:
commit "
3374264df97b" ("drivers: net: qe: deselect QE when DM_ETH is enabled")
as now qe works with DM and DM_ETH support.
- fix mailaddress from Holger
Series-changes: 2
- add comments from Qiang Zhao:
- add device node documentation
- I did not drop the dm_qe_uec_phy.c and use drivers/net/fsl_mdio.c
because using drivers/net/fsl_mdio.c leads in none existent
udevice mdio@3320
instead boards with DM ETH support should use now this
driver.
- remove RFC tag
Commit-notes:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This Code should be removed if all boards are converted
to DM/DTS.
- add the DM based qe uec driver under drivers/net/qe
- Therefore copied the files uccf.c uccf.h uec.h from
drivers/qe. So there are a lot of Codingstyle problems
currently. I fix them in next version if this RFC
patch is OK or it needs some changes.
- The dm based driver code is now under drivers/net/qe/dm_qe_uec.c
Used a lot of functions from drivers/qe/uec.c
- seperated the PHY specific code into seperate file
drivers/net/qe/dm_qe_uec_phy.c
END
Heiko Schocher [Mon, 3 Feb 2020 09:23:53 +0000 (10:23 +0100)]
powerpc, qe: add DTS support for parallel I/O ports
add DM support for parallel I/O ports on QUICC Engine Block
Signed-off-by: Heiko Schocher <hs@denx.de>
Patch-cc: Mario Six <mario.six@gdsys.cc>
Patch-cc: Qiang Zhao <qiang.zhao@nxp.com>
Patch-cc: Holger Brunck <holger.brunck@hitachi-powergrids.com>
Series-changes: 2
- remove RFC
- fixed Codingstyle errors, therefore new patch
powerpc, mpc83xx: fix codingstyle issues for qe_io.c
- moved DM part to drivers/pinctrl
Commit-notes:
Open questions / discussion:
- I let the old none DM based implementation in code
so boards should work with old implementation.
This should be removed if all boards are converted to
DM/DTS.
- Unfortunately linux DTS does not use "pinctrl-"
properties, instead "pio-handle" properties.
Even worser old U-Boot code initializes all pins
defined in "const qe_iop_conf_t qe_iop_conf_tab[]"
table in board code. As linux does the same I decided
to also scan through all subnodes containing "pio-map"
property and initialize them too.
The proper solution would be to check for "pio-handle"
when a device is probed.
END
Heiko Schocher [Mon, 25 May 2020 05:27:26 +0000 (07:27 +0200)]
powerpc, qe: fix codingstyle issues for drivers/qe
fix Codingstyle for files in drivers/qe, remaining following
check warnings:
$ ./scripts/checkpatch.pl -f drivers/qe/uec.h
CHECK: Macro argument reuse '_bd' - possible side-effects?
+#define BD_ADVANCE(_bd, _status, _base) \
+ (((_status) & BD_WRAP) ? (_bd) = \
+ ((struct buffer_descriptor *)(_base)) : ++(_bd))
total: 0 errors, 0 warnings, 1 checks, 692 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.h
total: 0 errors, 0 warnings, 0 checks, 214 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uccf.c
total: 0 errors, 0 warnings, 0 checks, 507 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec.c
total: 0 errors, 0 warnings, 0 checks, 1434 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/uec_phy.c
total: 0 errors, 0 warnings, 0 checks, 927 lines checked
$ ./scripts/checkpatch.pl -f drivers/qe/qe.c
CHECK: Lines should not end with a '('
+U_BOOT_CMD(
total: 0 errors, 0 warnings, 1 checks, 830 lines checked
Signed-off-by: Heiko Schocher <hs@denx.de>
Heiko Schocher [Wed, 15 Apr 2020 08:35:40 +0000 (10:35 +0200)]
mpc83xx: remove unneeded extern declaration in cpu_init
remove
extern void qe_init(uint qe_base);
extern void qe_reset(void);
and include fsl_qe.h instead.
Signed-off-by: Heiko Schocher <hs@denx.de>
Series-changes: 2
- new in v2
Heinrich Schuchardt [Tue, 15 Sep 2020 22:17:55 +0000 (00:17 +0200)]
doc: qemu: debug UART settings for QEMU ARM virt
Provide the settings for the debug UART on the QEMU ARM virt board.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Miquel Raynal [Mon, 14 Sep 2020 15:44:36 +0000 (17:44 +0200)]
MAINTAINERS: add myself as reviewer for SquashFS
I also followed the development of the SquashFS support in U-Boot
as part of Joao Marcos internship, so I would also appreciate receiving
new contributions and bug reports related to this topic.
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Thomas Petazzoni [Mon, 14 Sep 2020 11:52:39 +0000 (13:52 +0200)]
MAINTAINERS: add myself as reviewer for SquashFS
As I have followed the development of the SquashFS support in U-Boot
as part of Joao Marcos work, it makes sense to get Cc'ed on
contributions/bug reports related to the squashfs support.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Marek Vasut [Sat, 12 Sep 2020 10:42:52 +0000 (12:42 +0200)]
lib: fdt: Fix fdtdec_setup_mem..() conversion to livetree API
Repair incorrectly negated condition in the original patch which broke
DT memory node parsing on everything which has more than one DT memory
node, e.g. R-Car3.
In case multiple valid memory nodes are present in the DT, the original
patch would complete parsing cycle for the first memory node, then move
on to the next one, identify it as a valid, and end the parsing. The fix
is to invert the condition, to make the code behave as it did before the
livetree conversion, so it would continue parsing the subsequent memory
nodes as well.
Fixes:
c2f0950c33 ("lib: fdt: Convert fdtdes_setup_mem..() to livetree API")
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Simon Glass <sjg@chromium.org>
Cc: Tom Rini <trini@konsulko.com>
Tested-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Thirupathaiah Annapureddy [Tue, 18 Aug 2020 00:31:08 +0000 (17:31 -0700)]
include: phy: fix NULL pointer check in phy_write()
phy_write() uses bus->write() instead of bus->read(). This means NULL
pointer pre-check needs to happen on bus->write instead of bus->read.
Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com>
Reviewed-by: Michal Simek <michal.simek@xilinx.com>
Baruch Siach [Tue, 25 Aug 2020 06:01:41 +0000 (09:01 +0300)]
MAINTAINERS: update clk entry git tree
Signed-off-by: Baruch Siach <baruch@tkos.co.il>
Tom Rini [Wed, 16 Sep 2020 12:08:06 +0000 (08:08 -0400)]
Merge tag 'efi-2020-10-rc5' of https://gitlab.denx.de/u-boot/custodians/u-boot-efi
Pull request for UEFI sub-system for efi-2020-10-rc5
The following bugs are fixed:
* unaligned access in br_i32_decode()
* missing restore of global data pointer in UEFI selftest
* missing restore of global data pointer on RISC-V in UEfI subsystem
* efi_var_mem_notify_exit_boot_services() should not be __efi_runtime
Tom Rini [Wed, 16 Sep 2020 12:07:49 +0000 (08:07 -0400)]
Merge tag 'u-boot-rockchip-
20200916' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix rv1108 grf access issue
- make_fit_atf: ignore empty PT_LOAD segment
Heinrich Schuchardt [Tue, 15 Sep 2020 01:43:29 +0000 (03:43 +0200)]
rockchip: make_fit_atf: ignore empty PT_LOAD segment
The linker sometimes creates PT_LOAD segments with length (p_filesz) zero
as described in https://man7.org/linux/man-pages/man5/elf.5.html. This
leads to build failures. We should ignore empty segments.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tested-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 13 Apr 2020 01:38:32 +0000 (09:38 +0800)]
rockchip: rv1108: enable board early init
Enable board early init callback to init board specific hardware.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 13 Apr 2020 01:38:31 +0000 (09:38 +0800)]
rockchip: rv1108: Enable grf as pre-reloc node
The grf node will be used before relocate, enable it in dts.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Mon, 13 Apr 2020 01:38:30 +0000 (09:38 +0800)]
rockchip: rv1108: use correct API for board callback
Use board_early_init_f() instead of mach_cpu_init() for board, the
board_early_init_f() is used for board init and after dm_initf, while
the mach_cpu_init() is used for CPU/SOC and before dm_initf()(not able
to use syscon API).
Fixes:
9cec336708 ("rockchip: evb-rv1108: Use syscon API to get grf base")
Fixes:
4aa33690fc {"rockchip: elgin-rv1108: Use syscon API to get grf base")
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Tue, 15 Sep 2020 19:22:00 +0000 (15:22 -0400)]
Merge tag 'ti-v2021.01-next' of https://gitlab.denx.de/u-boot/custodians/u-boot-ti into next
- Hyperflash boot for J7200
- Update Main R5FSS lockstep mode
- R5F remoteproc support for J7200
- Minor env fixes
- Add SPI boot support for am335x-icev2
Faiz Abbas [Mon, 14 Sep 2020 06:41:17 +0000 (12:11 +0530)]
configs: Add spiboot support for am335x
am335x internal SRAM is too small to support the addition of
SPI bootmode to the default defconfig. Add a separate spiboot_defconfig
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Faiz Abbas [Mon, 14 Sep 2020 06:41:16 +0000 (12:11 +0530)]
spi: omap3_spi: Read platform data in ofdata_to_platdata()
Add an ofdata_to_platdata() callback to access dts in U-boot and
access all platform data in it. This prepares the driver for supporting
both device tree as well as static platform data structures in SPL.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Faiz Abbas [Mon, 14 Sep 2020 06:41:15 +0000 (12:11 +0530)]
arm: mach-omap2: am33xx: Add device structure for spi
Add platform data and a device structure for the spi device
present on am335x-icev2. This requires moving all omap3_spi
platform data structures and symbols to an omap3_spi.h so that
the board file can access them.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Faiz Abbas [Mon, 14 Sep 2020 06:41:14 +0000 (12:11 +0530)]
spi: spi-uclass: Block dm_scan_fdt_dev with OF_CONTROL to prevent build failures
There are devices which don't use OF_CONTROL or OF_PLATDATA but instead
rely on statically defined platdata. Block dm_scan_fdt_dev() with both
configs to avoid build failures under this condition.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Faiz Abbas [Mon, 14 Sep 2020 06:41:13 +0000 (12:11 +0530)]
arm: dts: am335x-icev2: Add spi node
Add spi and spi nor flash nodes for am335x-icev2.
Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Matwey V. Kornilov [Mon, 24 Aug 2020 18:00:33 +0000 (21:00 +0300)]
am335x_evm: Allow booting from usb-storage device
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Matwey V. Kornilov [Mon, 24 Aug 2020 18:00:32 +0000 (21:00 +0300)]
ti: Use devtype=mmc instead of setenv devtype mmc
If devtype variable is setted via setenv, then the following devtype=X style is
ignored. Currently, many u-boot commands use devtype variable in the latter
manner:
mmc_boot=if mmc dev ${devnum}; then devtype=mmc; run scan_dev_for_boot_part; fi
Use devtype=mmc instead of setenv devtype mmc to avoid bugs with booting from
another devtype.
Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com>
Suman Anna [Tue, 18 Aug 2020 19:09:45 +0000 (14:09 -0500)]
configs: j7200_evm_r5: Enable FS_LOADER
Enable the FS_LOADER and associated configs in the j7200_evm_r5_defconfig
so that the R5 SPL can support the loading of firmware files from a boot
media/file system.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Tue, 18 Aug 2020 19:09:44 +0000 (14:09 -0500)]
arm: dts: k3-j7200-r5: Add fs_loader node
Add a generic fs_loader node to the K3 J7200 R5 common board dts
file and use it as the chosen firmware-loader so that it can be
used for loading various firmwares from a boot media/filesystem
in R5 SPL on K3 J7200 EVM.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Tue, 18 Aug 2020 19:09:43 +0000 (14:09 -0500)]
env: ti: j721e-evm: Update R5 SPL rproc env variables for J7200
The R5 SPL on J7200 SoCs will be limited to booting just the
MCU R5FSS0 R5F core in LockStep-mode at present, so add the
two required environment variables 'addr_mcur5f0_0load' and
'name_mcur5f0_0fw' that are needed by the R5 SPL early-boot
logic. The firmware name used is also different from that on
J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:14 +0000 (18:15 -0500)]
configs: j7200_evm_a72: Enhance bootcmd to start remoteprocs
The A72 U-boot can support early booting of any of the Main or MCU R5F
remote processors from U-boot prompt to achieve various system usecases
before booting the Linux kernel. Update the default BOOTCOMMAND to provide
an automatic and easier way to start various remote processors through
added environment variables.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:13 +0000 (18:15 -0500)]
configs: j7200_evm_a72: Enable R5F remoteproc driver
The J7200 SoCs has two R5F sub-systems. Enable the TI K3
R5F remoteproc driver and the remoteproc command options
to allow these R5F processors to be booted from A72 U-Boot.
The Kconfigs are added using savedefconfig.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:12 +0000 (18:15 -0500)]
env: ti: j721e-evm: Update rproc_fw_binaries env variable for J7200
The J7200 SoCs have different number of remote processors, but reuse
the same environment settings as the J721E SoCs. The current env
variable rproc_fw_binaries is geared towards J721E SoCs and is
incorrect for J7200 SoCs. Please see the logic originally added in
commit
0b4ab9c9a754 ("env: ti: j721e-evm: Add support to boot rprocs
including R5Fs and DSPs").
Fix this by defining the DEFAULT_RPROCS macro appropriately using
the corresponding TARGET_EVM Kconfig symbol. This macro is used by
the 'rproc_fw_binaries' env variable in the common remoteproc env
header file k3_rproc.h.
The list of R5F cores to be started before loading and booting the
Linux kernel are as follows, and mainly comprises of the Main R5FSS0
cores in this order:
Main R5FSS0 (Split) Core0 : 2 /lib/firmware/j7200-main-r5f0_0-fw
Main R5FSS0 (Split) Core1 : 3 /lib/firmware/j7200-main-r5f0_1-fw
The MCU R5FSS0 is in LockStep mode and is expected to be booted by
R5 SPL, so it is not included in the list. The order of rprocs to
boot cannot be really modified as only the Main R5FSS0 cores are
involved and Core0 has to be booted first always before the
corresponding Core1.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:11 +0000 (18:15 -0500)]
arm: dts: k3-j7200-main: Add MAIN domain R5F cluster nodes
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MAIN domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in Split-mode by default, with the
ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:10 +0000 (18:15 -0500)]
arm: dts: k3-j7200-mcu: Add MCU domain R5F cluster node
The J7200 SoCs have 2 dual-core Arm Cortex-R5F processor (R5FSS)
subsystems/clusters. One R5F cluster is present within the MCU
domain (MCU_R5FSS0), and the other one is present within the MAIN
domain (MAIN_R5FSS0). Each of these can be configured at boot time
to be either run in a LockStep mode or in an Asymmetric Multi
Processing (AMP) fashion in Split-mode. These subsystems have 64 KB
each Tightly-Coupled Memory (TCM) internal memories for each core
split between two banks - ATCM and BTCM (further interleaved into
two banks). The TCMs of both Cores are combined in LockStep-mode
to provide a larger 128 KB of memory.
Add the DT node for the MCU domain R5F cluster/subsystem, the two
R5F cores are added as child nodes to the main cluster/subsystem node.
The cluster is configured to run in LockStep mode by default, with
the ATCMs enabled to allow the R5 cores to execute code from DDR with
boot-strapping code from ATCM. The inter-processor communication
between the main A72 cores and these processors is achieved through
shared memory and Mailboxes.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:09 +0000 (18:15 -0500)]
armv8: K3: j7200: Add custom MMU support
The A72 U-Boot code can load and boot a number of the available
R5FSS Cores on the J7200 SoC. Change the memory attributes for the
DDR regions used by the remote processors so that the cores can see
and execute the proper code.
The J7200 SoC has less number of remote processors compared to J721E,
so use less memory for the remote processors. So, a separate table
based on the current J721E table is added for J7200 SoCs, and selected
using the appropriate Kconfig CONFIG_TARGET_J7200_A72_EVM symbol.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:08 +0000 (18:15 -0500)]
remoteproc: k3-r5: Add support for J7200 R5Fs
The K3 J7200 SoC family has a revised R5F sub-system and contains a
subset of the R5F clusters present on J721E SoCs. The integration of
these clusters is very much similar to J721E SoCs otherwise.
The revised IP has the following two new features:
1. TCMs are auto-initialized during module power-up, and the behavior
is programmable through a MMR bit controlled by System Firmware.
2. The LockStep-mode allows the Core1 TCMs to be combined with the
Core0 TCMs effectively doubling the amount of TCMs available.
The LockStep-mode on previous SoCs could only use the Core0 TCMs.
This combined TCMs appear contiguous at the respective Core0 TCM
addresses.
Add the support to these clusters in the K3 R5F remoteproc driver
using J7200 specific compatibles and revised logic accounting for
the above IP features/differences.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 23:15:07 +0000 (18:15 -0500)]
dt-bindings: remoteproc: k3-r5f: Update bindings for J7200 SoCs
The K3 J7200 SoCs have two dual-core Arm R5F clusters/subsystems, with
2 R5F cores each, one in each of the MCU and MAIN voltage domains.
These clusters are a revised version compared to those present on
J721E SoCs. Update the K3 R5F remoteproc bindings with the compatible
info relevant to these R5F clusters/subsystems on K3 J7200 SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 21:57:36 +0000 (16:57 -0500)]
env: ti: j721e-evm: Limit scope of rproc env variables used by R5 SPL
The commit
316c927135d6 ("include: configs: j721e_evm: Add env variables
for mcu_r5fss0_core0 & main_r5fss0_core0") added four different new env
variables 'addr_mainr5f0_0load', 'name_mainr5f0_0fw', 'addr_mcur5f0_0load'
and 'name_mcur5f0_0fw' to the generic environment, but these are only
needed and used in R5 SPL for early-booting the MCU R5FSS0 and Main
R5FSS0 Core0 on J721E SoCs.
These are not really needed for A72 U-Boot, so limit the scope of
these variables only to R5 SPL. While at this, also fix the loadaddr
variable values to include the hex prefix like with other such env
variables.
Cc: Keerthy <j-keerthy@ti.com>
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 21:57:35 +0000 (16:57 -0500)]
configs: j721e_evm: Add Main R5FSS1 Core1 to default rproc boot list
The default rproc list currently used by A72 U-Boot to boot various
remote processors include the Main R5FSS0 (Split-mode) Core1, Main
R5FSS1 (LockStep mode) Core0 and the three DSPs. The Main R5FSS1 cluster
is configured for Split mode by default in the dts now, so add the
Main R5FSS1 Core1 (rproc #5) to the default rproc boot list. This
core is now booted after the Main R5FSS1 Core0 and before the DSPs.
The order of the rprocs to boot can always be changed at runtime if
desired by overwriting the 'rproc_fw_binaries' environment variable
at U-boot prompt. Note that the R5FSS Core1 cannot be booted before
its associated Core0.
Signed-off-by: Suman Anna <s-anna@ti.com>
Suman Anna [Mon, 17 Aug 2020 21:57:34 +0000 (16:57 -0500)]
arm: dts: k3-j721e-main: Configure MAIN R5FSS1 for Split-mode
Switch the MAIN R5FSS1 cluster to be configured for Split-mode as the
default so that two different applications can be run on each of the
R5F cores in performance mode. LockStep-mode would be available only
on SoCs efused with the appropriate bit, and Split-mode is the mode
that is available on all J721E SoCs.
Signed-off-by: Suman Anna <s-anna@ti.com>
Vignesh Raghavendra [Thu, 13 Aug 2020 09:26:19 +0000 (14:56 +0530)]
configs: j721e_evm.h: Add U-Boot image address for HyperFlash boot
Add memory mapped address location of U-Boot images in HyperFlash boot
mode.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vignesh Raghavendra [Thu, 13 Aug 2020 09:26:18 +0000 (14:56 +0530)]
configs: j7200_evm_*_defconfig: Enable HyperFlash boot related configs
Enable configs required to support HyperFlash boot and detection of
onboard mux switch for HyperFlash selection
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vignesh Raghavendra [Thu, 13 Aug 2020 09:26:17 +0000 (14:56 +0530)]
ARM: dts: k3-j7200-r5-common-proc-board: Enable HyperFlash
Enable HyperBus and HyperFlash to support HyperFlash boot.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vignesh Raghavendra [Thu, 13 Aug 2020 09:26:16 +0000 (14:56 +0530)]
board: ti: j721e: Add support for HyperFlash detection
On J7200 SoC OSPI and HypeFlash are muxed at HW level and only one of
them can be used at any time. J7200 EVM has both HyperFlash and OSPI
flash on board. There is a user switch (SW3.1) that can be toggled to
select OSPI flash vs HyperFlash.
Read the state of this switch via wkup_gpio0_6 line and fixup the DT
nodes to select OSPI vs HyperFlash
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Vignesh Raghavendra [Thu, 13 Aug 2020 09:26:15 +0000 (14:56 +0530)]
arm: mach-k3: Add HyperFlash boot mode support
HBMC controller on TI K3 SoC provides MMIO access to HyperFlash similar
to legacy Parallel CFI NOR flashes. Therefore alias HyperFlash bootmode
to NOR boot to enable SPL to load next stage using NOR boot flow.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>