Kenneth Graunke [Tue, 28 Nov 2017 16:30:50 +0000 (08:30 -0800)]
i965: Use old_bo->align when growing batch/state buffer instead of 4096.
The intention here is make the new BO use the same alignment as the old
BO. This isn't strictly necessary, but we would have to update the
'alignment' field in the validation list when swapping it out, and we
don't bother today.
The batch and state buffers use an alignment of 4096, so this should be
equivalent - it's just clearer than cut and pasting a magic constant.
Fixes:
2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Dave Airlie [Thu, 23 Nov 2017 00:19:14 +0000 (10:19 +1000)]
r600: no need to reinit compute regs
Compute setup gets emitted into the normal gfx state buffer,
so no need to reinit the basics.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 29 Nov 2017 03:55:52 +0000 (13:55 +1000)]
r600: split cb setup code out from evergreen compute path.
This just makes it easier to bypass for TGSI later.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 20 Nov 2017 21:28:56 +0000 (07:28 +1000)]
r600: add support for compute pkt flags to debug dumping.
This just lets us see packets marked for compute.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 28 Nov 2017 03:30:41 +0000 (13:30 +1000)]
r600: fix bfe where src/dst are same.
This fixes overlaps where src/dst are the same.
Fixes a bunch of the deqp bitfield tests.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Adam Jackson [Mon, 6 Nov 2017 21:28:36 +0000 (16:28 -0500)]
gallium/dri2: Enable {GLX_ARB,EGL_KHR}_context_flush_control
Reviewed-and-tested-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Adam Jackson <ajax@redhat.com>
Kenneth Graunke [Wed, 29 Nov 2017 08:27:18 +0000 (00:27 -0800)]
i965: Program the dynamic state heap size to MAX_STATE_SIZE.
STATE_BASE_ADDRESS specifies a maximum size of the dynamic state
section, beyond which data supposedly reads back as 0. On Gen8+,
we were programming it to the size of the buffer. This worked fine
until we started growing the state buffer in commit
2dfc119f22f25708.
When the state buffer grows, the value in STATE_BASE_ADDRESS becomes
too small, and our state beyond STATE_SZ bytes would read back as 0.
To avoid having to update the value, we program it to MAX_STATE_SIZE.
We used to program the upper bound to the maximum on older hardware
anyway, so programming it too large isn't a big deal.
Bogus SURFACE_STATE can easily lead to GPU hangs and misrendering.
DiRT Rally was hitting the statebuffer growth path, and suffered from
bad texture corruption and GPU hangs (usually around the same time).
This patch fixes both issues.
Fixes:
2dfc119f22f257082ab0 "i965: Grow the batch/state buffers if we need space and can't flush."
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103101
Tested-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Marek Olšák [Tue, 28 Nov 2017 16:54:55 +0000 (17:54 +0100)]
r300,r600,radeonsi: replace RADEON_FLUSH_* with PIPE_FLUSH_*
and handle PIPE_FLUSH_HINT_FINISH in r300.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:38:44 +0000 (03:38 +0100)]
radeonsi: remove r600_common_screen
Most files in gallium/radeon now include si_pipe.h.
chip_class and family are now here:
sscreen->info.family
sscreen->info.chip_class
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:19:20 +0000 (03:19 +0100)]
radeonsi: remove r600_pipe_common::barrier_flags::compute_to_L2
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:15:09 +0000 (03:15 +0100)]
radeonsi: remove query/apply_opaque_metadata callbacks
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:08:59 +0000 (03:08 +0100)]
radeonsi: move shader debug helpers out of r600_pipe_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sun, 26 Nov 2017 02:04:55 +0000 (03:04 +0100)]
radeonsi: dismantle si_common_screen_init/destroy
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 22:04:31 +0000 (23:04 +0100)]
radeonsi: document our vendor string situation
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 22:02:00 +0000 (23:02 +0100)]
radeonsi: set all pipe buffer functions in r600_buffer_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:51:43 +0000 (22:51 +0100)]
radeonsi/uvd: don't call ws->query_info
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:48:36 +0000 (22:48 +0100)]
radeonsi: move video queries into si_get.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:39:28 +0000 (22:39 +0100)]
radeonsi: remove more functions from r600_pipe_common.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:35:27 +0000 (22:35 +0100)]
radeonsi: move/remove ac_shader_binary helpers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 21:33:10 +0000 (22:33 +0100)]
radeonsi: move all get functions to si_get.c; disk_cache_create to si_pipe.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:37:30 +0000 (21:37 +0100)]
radeonsi: remove R600_CONTEXT_* flags
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:36:36 +0000 (21:36 +0100)]
radeonsi: just include si_pipe.h in r600_query.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:21:57 +0000 (21:21 +0100)]
radeonsi: remove some definitions and helpers from r600_pipe_common.h
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:16:02 +0000 (20:16 +0100)]
radeonsi: don't use fast color clear for small surfaces
This removes 35+ clear eliminate passes from DOTA 2.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 28 Nov 2017 20:37:26 +0000 (21:37 +0100)]
radeonsi: unify code setting dirty_level_mask for fast clear
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 20:08:20 +0000 (21:08 +0100)]
radeonsi: clean up si_do_fast_color_clear parameters
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:50:31 +0000 (20:50 +0100)]
radeonsi: remove r600_common_context::clear_buffer
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:45:21 +0000 (20:45 +0100)]
radeonsi: move r600_test_dma.c into si_test_dma.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:39:12 +0000 (20:39 +0100)]
radeonsi: move si_pipe_clear_buffer into si_cp_dma.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Sat, 25 Nov 2017 19:36:35 +0000 (20:36 +0100)]
radeonsi: move all clear() code into si_clear.c
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:41:47 +0000 (00:41 +0100)]
radeonsi: enable DCC with MSAA for VI
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:36:56 +0000 (00:36 +0100)]
radeonsi: implement fast color clear for DCC with MSAA for VI
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:33:53 +0000 (00:33 +0100)]
radeonsi: add a workaround for blending with DCC and MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 23:19:56 +0000 (00:19 +0100)]
radeonsi: clear PIPE_IMAGE_ACCESS_WRITE when it's invalid to be on the safe side
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 21:29:26 +0000 (22:29 +0100)]
ac/surface: enable DCC computation for MSAA
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 28 Nov 2017 19:57:10 +0000 (20:57 +0100)]
radeonsi: fix layered DCC fast clear
Cc: 17.2 17.3 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jon Turney [Mon, 27 Nov 2017 13:32:53 +0000 (13:32 +0000)]
util: Also include endian.h on cygwin
If u_endian.h can't determine the endianess, the default behaviour in sha1.c
is to build for big-endian
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Juan A. Suarez Romero [Wed, 29 Nov 2017 11:09:47 +0000 (12:09 +0100)]
mesa: deal with vs_inputs as 64-bit unsigned integer
Commit 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits") uses
vs_prog_data->vs_inputs as if it were a 32-bit unsigned integer.
But actually it is a 64-bit integer, and as such it is used in other
parts of Mesa code. It is worth to note that bits from the entire range
are used, and not only 32-bits. This is due our implementation for
handling 64-bit dual-slot input attributes, which requires to use a
larger bitfield to manage them.
This commit reverts the changes done in brw_draw_upload.c, keeping the
rest of the changes.
This fixes the following tests:
- KHR-GL45.enhanced_layouts.varying_array_locations
- KHR-GL45.enhanced_layouts.varying_locations
Fixes: 78942e ("mesa: shrink VERT_ATTRIB bitfields to 32 bits")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103942
CC: Marek Olšák <marek.olsak@amd.com>
CC: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Timothy Arceri [Thu, 15 Jun 2017 23:56:56 +0000 (09:56 +1000)]
mesa: rework _mesa_add_parameter() to only add a single param
This is more inline with what the functions name suggests it should
do, and makes the code much easier to follow.
This will also make adding uniform packing support much simpler.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Wed, 29 Nov 2017 03:13:17 +0000 (13:13 +1000)]
r600: lds load cleanups.
This is just some cleanups on top of the last patch from my compute branch.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Gert Wollny [Wed, 15 Nov 2017 09:29:12 +0000 (10:29 +0100)]
r600_shader: only load from LDS what is really used
Use the destination write mask to determine which values are really to be
read from LDS and load only these.
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Dave Airlie [Sun, 26 Nov 2017 23:36:39 +0000 (23:36 +0000)]
r600/sb: handle jump after target to end of program. (v2)
This fixes hangs on cayman with
tests/spec/arb_tessellation_shader/execution/trivial-tess-gs_no-gs-inputs.shader_test
This has a single if/else in it, and when this peephole activated,
it would set the jump target to NULL if there was no instruction
after the final POP. This adds a NOP if we get a jump in this case,
and seems to fix the hangs, so we have a valid target for the ELSE
instruction to go to, instead of 0 (which causes infinite loops).
v2: update last_cf correctly. (I had some other patches hide this)
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Tue, 28 Nov 2017 16:12:45 +0000 (08:12 -0800)]
i965: Change a ret == -1 check to ret != 0.
For consistency with most other ret checks. Suggested by Chris.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Kenneth Graunke [Sun, 26 Nov 2017 09:14:26 +0000 (01:14 -0800)]
i965: Use C99 struct initializers in brw_bufmgr.c.
This is cleaner than using a non-standard memclear macro (which does a
memset to 0) and then initializing fields after the fact. We move the
declarations to where we initialized the fields. While we're at it, we
move the declaration of 'ret' that goes with the ioctl, eliminating the
declaration section altogether.
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Kenneth Graunke [Sun, 26 Nov 2017 09:42:11 +0000 (01:42 -0800)]
i965: Move perf_debug and WARN_ONCE back to brw_context.h.
These were moved to src/intel/common/gen_debug.h, but they are not
common code. They assume that brw_context or gl_context variables
exist, named brw or ctx. That isn't remotely true outside of i965.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Eric Engestrom [Mon, 27 Nov 2017 13:46:43 +0000 (13:46 +0000)]
i965: const a few structs and vars to avoid writing to them by accident
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Sun, 26 Nov 2017 00:59:27 +0000 (16:59 -0800)]
i965: Fix Smooth Point Enables.
We want to program the 3DSTATE_RASTER field to the gl_context value,
not the other way around.
Fixes:
13ac46557ab1 (i965: Port Gen8+ 3DSTATE_RASTER state to genxml.)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Dylan Baker [Thu, 26 Oct 2017 22:45:40 +0000 (15:45 -0700)]
meson: build virgl driver
Build tested only.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Dylan Baker [Thu, 26 Oct 2017 21:19:19 +0000 (14:19 -0700)]
meson: build svga driver on linux
Build tested only.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Dylan Baker [Thu, 26 Oct 2017 01:55:38 +0000 (18:55 -0700)]
meson: build r600 driver
v4: - Ensure inc_amd_common defined when radeonsi is disabled (needed by
r600)
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Dylan Baker [Thu, 26 Oct 2017 00:59:11 +0000 (17:59 -0700)]
meson: build r300 driver
This is build tested only
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Dylan Baker [Wed, 25 Oct 2017 23:54:53 +0000 (16:54 -0700)]
meson: build i915g driver
Build tested only.
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Brian Paul [Tue, 21 Nov 2017 14:31:57 +0000 (07:31 -0700)]
svga: move svga_is_format_supported() to svga_format.c
where the other format-related functions live.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Tue, 21 Nov 2017 14:27:06 +0000 (07:27 -0700)]
svga: s/unsigned/SVGA3dDevCapIndex/
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Lionel Landwerlin [Thu, 9 Nov 2017 16:40:55 +0000 (16:40 +0000)]
i965: perf: add support for CoffeeLake GT3
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 31 Aug 2017 10:28:30 +0000 (11:28 +0100)]
i965: perf: add support for CoffeeLake GT2
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 9 Nov 2017 16:51:26 +0000 (16:51 +0000)]
i965: perf: add busyness metric sets on gen8/9 platforms
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 9 Nov 2017 16:48:45 +0000 (16:48 +0000)]
i965: fix time elapsed counter equations in VME/Media configs
There was a mistake just in those metric sets. We probably didn't
noticed because they're not really interesting for 3D workloads.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 9 Nov 2017 16:46:47 +0000 (16:46 +0000)]
i965: perf: update counter names on gen8/9 platforms
Just fixing names.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 29 Aug 2017 09:41:27 +0000 (10:41 +0100)]
i965: add a debug option to disable oa config loading
This provides a good way to verify we haven't broken using the perf
driver on older kernels (which don't have the oa config loading
mechanism).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Tue, 25 Jul 2017 16:22:58 +0000 (17:22 +0100)]
i965: perf: add support for userspace configurations
This allows us to deploy new configurations without touching the
kernel.
v2: Detect loadable configs without creating one (Chris)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Lionel Landwerlin [Thu, 31 Aug 2017 10:04:28 +0000 (11:04 +0100)]
i965: perf: update configs for loading from userspace
When making configs loadable from userspace in the kernel, we left to
userspace more responsability around programming some registers. In
particular one register we use to set directly in the driver has now
been moved into the configs.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Eric Engestrom [Mon, 27 Nov 2017 11:33:48 +0000 (11:33 +0000)]
util: add mesa-sha1 test to meson
Fixes:
513d7ffa23d42e96f831 "util: Add a SHA1 unit test program"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Fri, 24 Nov 2017 18:00:57 +0000 (18:00 +0000)]
compiler: fix typo
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Thu, 23 Nov 2017 13:16:43 +0000 (13:16 +0000)]
compiler: use NDEBUG to guard asserts
nir_validate.c's #endif already had the correct NDEBUG comment
Fixes:
dcb1acdea00a8f2c29777 "nir/validate: Only build in debug mode"
Fixes:
9ff71b649b4b3808a9e17 "i965/nir: Validate that NIR passes call nir_metadata_preserve()"
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Engestrom [Fri, 24 Nov 2017 17:59:23 +0000 (17:59 +0000)]
broadcom: use NDEBUG to guard asserts
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Eric Engestrom [Fri, 24 Nov 2017 16:58:43 +0000 (16:58 +0000)]
vc4: check preprocessor token existence using #ifdef instead of #if
(other uses of USE_VC4_SIMULATOR are already correct)
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Ben Crocker [Mon, 27 Nov 2017 19:44:59 +0000 (14:44 -0500)]
docs/llvmpipe.html: Minor edits
Language and spelling fixups in three places.
Cc: "17.2" "17.3" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Ben Crocker <bcrocker@redhat.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
[Eric: move two fixes from the other patch to this one.]
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Eric Engestrom [Fri, 24 Nov 2017 10:49:25 +0000 (10:49 +0000)]
st/dri: replace hard-coded array size with ARRAY_SIZE()
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 16 Nov 2017 16:23:43 +0000 (17:23 +0100)]
radeonsi/gfx9: simplify condition for on-chip ESGS
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sat, 18 Nov 2017 13:33:34 +0000 (14:33 +0100)]
radeonsi: clarify that si_shader_selector::esgs_itemsize is set for the ES part
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 16 Nov 2017 15:56:21 +0000 (16:56 +0100)]
radeonsi: use si_shader_context instead of lp_build_context in more places
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 16 Nov 2017 06:33:34 +0000 (07:33 +0100)]
radeonsi: cleanup si_initialize_color_surface
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sun, 19 Nov 2017 16:26:45 +0000 (17:26 +0100)]
radeonsi: avoid attempting to create CMASK if the tiling mode doesn't have it
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 14 Nov 2017 08:37:38 +0000 (09:37 +0100)]
radeonsi: check that we don't leak fine.buf references
Just as an added precaution.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Sun, 19 Nov 2017 15:09:28 +0000 (16:09 +0100)]
ac/surface: fix indentation
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 9 Nov 2017 09:59:22 +0000 (10:59 +0100)]
amd/common: sid.h cleanups
Fix a bunch of labels indicating when registers were added/removed
and normalize the SI-class GRBM_GFX_INDEX.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Fri, 17 Nov 2017 19:01:50 +0000 (20:01 +0100)]
st_glsl_to_tgsi: check for the tail sentinel in merge_two_dsts
This fixes yet another case where DFRACEXP has only one destination. Found
by address sanitizer.
Fixes tests/spec/arb_gpu_shader_fp64/execution/built-in-functions/fs-frexp-dvec4-only-mantissa.shader_test
Fixes:
3b666aa74795 ("st/glsl_to_tgsi: fix DFRACEXP with only one destination")
Acked-by: Marek Olšák <marek.olsak@amd.com>
Tapani Pälli [Mon, 20 Nov 2017 13:00:19 +0000 (15:00 +0200)]
mesa/gles: adjust internal format in glTexSubImage2D error checks
When floating point textures are created on OpenGL ES 2.0, driver
is free to choose used internal format. Mesa makes this decision in
adjust_for_oes_float_texture. Error checking for glTexImage2D properly
checks that sized formats are not used. We use same error checking
path for glTexSubImage2D (since there is lot of overlap), however since
those checks include internalFormat checks, we need to pass original
internalFormat passed by the client. Patch adds oes_float_internal_format
that does reverse adjust_for_oes_float_texture to get that format.
Fixes following test failure:
ES2-CTS.gtf.GL2ExtensionTests.texture_float.texture_float
(when running test with MESA_GLES_VERSION_OVERRIDE=2.0)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103227
Cc: "17.3" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Tue, 28 Nov 2017 02:28:51 +0000 (18:28 -0800)]
radv: Use the suffixed versions of VK_QUEUE_GLOBAL_PRIORITY_*
Acked-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Tue, 28 Nov 2017 02:26:21 +0000 (18:26 -0800)]
vulkan: Update the XML and headers to 1.0.66
Acked-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Sat, 11 Nov 2017 20:31:54 +0000 (12:31 -0800)]
intel/blorp: Drop blorp_resolve_ccs_attachment
The only reason why we needed that version was because the Vulkan driver
needed to be able to create the surface states so it could handle
indirect clear colors. Now that blorp handles them natively, there's no
need for the extra entrypoint.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sat, 11 Nov 2017 20:22:45 +0000 (12:22 -0800)]
anv: Let blorp handle indirect clear colors for CCS resolves
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sat, 11 Nov 2017 20:12:57 +0000 (12:12 -0800)]
anv: Move get_fast_clear_state_address into anv_private.h
While we're at it, we break it into two nicely named functions.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sat, 11 Nov 2017 19:26:23 +0000 (11:26 -0800)]
intel/blorp: Take a range of layers in blorp_ccs_resolve
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sat, 11 Nov 2017 19:10:59 +0000 (11:10 -0800)]
intel/blorp: Add initial support for indirect clear colors
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Mon, 13 Nov 2017 02:31:56 +0000 (18:31 -0800)]
i965/blorp: Use a designated initializer for blorp_surf
This way uninitialized fields get automatically zeroed and it's safe to
add more fields to blorp_surf.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sat, 11 Nov 2017 23:44:23 +0000 (15:44 -0800)]
intel/blorp: Add fast-clear to the special case in MSAA resolves
This doesn't go all the way of avoiding the txf_ms if it's fast-cleared,
however it does at least make us only do it once. This should improve
performance of MSAA resolves in the presence of lots of clear color.
Without the patch, enabling fast-clears in the multisampling Sascha demo
drops the framerate by about 10%. With this patch, enabling fast-clears
increases the demo's framerate by 25%.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Jason Ekstrand [Sat, 11 Nov 2017 23:42:51 +0000 (15:42 -0800)]
intel/blorp/blit: Rename blorp_nir_txf_ms_mcs
That name is already taken by one of the helpers in blorp_nir_builder.h
and, while we haven't moved the guts of blorp_blit.c there yet, we'd
like to start using some things from that header.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Rob Herring [Mon, 27 Nov 2017 19:32:19 +0000 (13:32 -0600)]
Android: disable warnings causing errors
AOSP master has changed the build default to -Werror making all the
warnings errors. Override that with -Wno-error.
Signed-off-by: Rob Herring <robh@kernel.org>
Timothy Arceri [Mon, 27 Nov 2017 05:25:11 +0000 (16:25 +1100)]
st/glsl_to_tgsi: make use of driver_cache_blob with the disk cache
driver_cache_blob was introduced with the i965 disk cache, it allows
us to simplify the cache a little and possibly offers some minor
speed improvements since we load the GLSL metadata and TGSI from
disk in one pass.
Using driver_cache_blob should also make it straight forward to
implement binary support for ARB_get_program_binary in gallium.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Gwan-gyeong Mun [Sat, 25 Nov 2017 14:08:23 +0000 (23:08 +0900)]
glsl: Fix typo nagivation -> navigation
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Emil Velikov [Thu, 23 Nov 2017 18:51:14 +0000 (18:51 +0000)]
gl_table.py: add extern C guard for the generated glapitable.h
The header can be included from C++, hence contents should have
appropriate notation.
Cc: mesa-stable@lists.freedesktop.org
Cc: Dylan Baker <dylan@pnwbakers.com>
Signed-off-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Marek Olšák [Tue, 14 Nov 2017 18:44:33 +0000 (19:44 +0100)]
ac: pack legacy_surf_level better
r600_texture: 1488 -> 1248 bytes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 14 Nov 2017 18:31:39 +0000 (19:31 +0100)]
ac: change legacy_surf_level::slice_size to dword units
The next commit will reduce the size even more.
v2: typecast to uint64_t manually
v3: add more typecasts, add asserts
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 14 Nov 2017 18:22:15 +0000 (19:22 +0100)]
ac: pack ac_surface better
r600_texture: 1736 -> 1488 bytes
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Fri, 24 Nov 2017 21:08:03 +0000 (22:08 +0100)]
radeonsi: always initialize max_forced_staging_uploads
r600_resource is malloc'd.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=103808
Fixes:
4b0dc098b256 ("gallium/u_threaded: don't map big VRAM buffers for the first upload directly")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 19:29:27 +0000 (20:29 +0100)]
radeonsi: remove an old hack for evergreen
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 23 Nov 2017 19:22:25 +0000 (20:22 +0100)]
radeonsi: set COMPUTE_RESOURCE_LIMITS.FORCE_SIMD_DIST when profitable
ported from Vulkan
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Dave Airlie [Tue, 14 Nov 2017 05:11:39 +0000 (15:11 +1000)]
ac/nir: don't write tcs outputs to LDS that aren't read back.
If the TCS doesn't read back the outputs, no need to store them
to LDS in the first place. (except for tess factors).
This seems to give about 50fps (3290->3330) with tessellation demo.
I haven't tested if it impacts DoW3 at all.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>