Simon Glass [Sat, 9 Oct 2021 15:28:21 +0000 (09:28 -0600)]
lz4: Use a private header for U-Boot
At present U-Boot has a header file called lz4.h for its own use. If the
host has its own lz4 header file installed (e.g. from the 'liblz4-dev'
package) then host builds will use that instead.
Move the U-Boot file into its own directory, as is done with various
other headers with the same problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 8 Oct 2021 20:02:55 +0000 (16:02 -0400)]
Merge branch '2021-10-08-image-cleanups'
- A large number of image file and tooling related cleanups
Simon Glass [Sun, 26 Sep 2021 01:43:41 +0000 (19:43 -0600)]
image: Split up boot_get_fdt()
This function is far too long. Before trying to remove #ifdefs, split out
the code that deals with selecting the FDT into a separate function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:40 +0000 (19:43 -0600)]
image: Reduce variable scope in boot_get_fdt()
Move the variables declarations to where they are needed, to reduce the
number of #ifdefs needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:39 +0000 (19:43 -0600)]
image: Remove some #ifdefs from image-fit and image-fit-sig
Drop the #ifdefs which are easy to remove without refactoring.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:38 +0000 (19:43 -0600)]
image: Remove #ifdefs from select_ramdisk()
Use boolean variables to deal with the strange #ifdef logic of this
function, so we can remove the #ifdefs.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:37 +0000 (19:43 -0600)]
image: Split up boot_get_ramdisk()
This function is far too long. Before trying to remove #ifdefs, split out
the code that deals with selecting the ramdisk into a separate function.
Leave the code indented as it was for easier review. The next patch cleans
this up along with checkpatch violations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:36 +0000 (19:43 -0600)]
image: Reduce variable scope in boot_get_ramdisk()
Move the variables declarations to where they are needed, to reduce the
number of #ifdefs needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:35 +0000 (19:43 -0600)]
image: Drop most #ifdefs in image-board.c
Remove ifdefs in this file, so far as possible without too much
refactoring.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:34 +0000 (19:43 -0600)]
image: Drop #ifdefs for fit_print_contents()
Use a simple return to drop the unwanted code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:33 +0000 (19:43 -0600)]
image: Drop unnecessary #ifdefs from image.h
This file has a lot of conditional code and much of it is unnecessary.
Clean this up to reduce the number of build combinations.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:32 +0000 (19:43 -0600)]
image: Tidy up fit_unsupported_reset()
This function is only used in one place and does not need to use the
preprocessor. Move it to the C file and convert it to a normal function.
Drop fit_unsupported() since it is not used.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:29 +0000 (19:43 -0600)]
efi: Correct dependency on FIT_SIGNATURE
At present EFI_SECURE BOOT selects RSA but does not necessarily enable
FIT_SIGNATURE. Mostly this is fine, but a few boards do not enable it,
so U-Boot tries to do RSA verification when loading FIT images, but it
is not enabled.
This worked because the condition for checking the RSA signature is
wrong in the fit_image_verify_with_data() function. In order to fix it
we need to fix this dependency. Make sure that FIT_SIGNATURE is enabled
so that RSA can be used.
It might be better to avoid using 'select' in this situation.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 26 Sep 2021 01:43:28 +0000 (19:43 -0600)]
image: Drop IMAGE_ENABLE_IGNORE
We can use the new host_build() function for this, so drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:27 +0000 (19:43 -0600)]
image: Drop IMAGE_OF_SYSTEM_SETUP
This is not needed with Kconfig, since we can use IS_ENABLED() easily
enough. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:26 +0000 (19:43 -0600)]
image: Drop IMAGE_OF_BOARD_SETUP
This is not needed with Kconfig, since we can use IS_ENABLED() easily
enough. Drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:25 +0000 (19:43 -0600)]
image: Drop IMAGE_BOOT_GET_CMDLINE
This is not needed with Kconfig, since we can use IS_ENABLED() easily
enough and the board code is now in a separate file. Update the only place
where this is used and drop it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:24 +0000 (19:43 -0600)]
image: Use the correct checks for CRC32
Add a host Kconfig for CRC32. With this we can use CONFIG_IS_ENABLED(CRC32)
directly in the host build, so drop the unnecessary indirection.
Add a few more conditions to SPL_CRC32 to avoid build failures as well as
TPL_CRC32. Also update hash.c to make crc32 optional and to actually take
notice of SPL_CRC32.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:23 +0000 (19:43 -0600)]
image: Use Kconfig to enable FIT_RSASSA_PSS on host
Add a host Kconfig for FIT_RSASSA_PSS. With this we can use
CONFIG_IS_ENABLED(FIT_RSASSA_PSS) directly in the host build, so drop the
forcing of this in the image.h header.
Drop the #ifdef around padding_pss_verify() too since it is not needed.
Use the compiler to check the config where possible, instead of the
preprocessor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:22 +0000 (19:43 -0600)]
image: Use Kconfig to enable CONFIG_FIT_VERBOSE on host
Add a host Kconfig for FIT_VERBOSE. With this we can use
CONFIG_IS_ENABLED(FIT_VERBOSE) directly in the tools build, so drop the
forcing of this in the image.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:21 +0000 (19:43 -0600)]
image: Drop IMAGE_ENABLE_OF_LIBFDT
Add a host Kconfig for OF_LIBFDT. With this we can use
CONFIG_IS_ENABLED(OF_LIBFDT) directly in the tools build, so drop the
unnecessary indirection.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:20 +0000 (19:43 -0600)]
image: Drop IMAGE_ENABLE_FIT
Make use of the host Kconfig for FIT. With this we can use
CONFIG_IS_ENABLED(FIT) directly in the host build, so drop the unnecessary
indirection.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:19 +0000 (19:43 -0600)]
hash: Drop some #ifdefs in hash.c
We can use the __maybe_unused attribute to avoid some of the #ifdefs in
this file. Update the functions accordingly.
Note: The actual hashing interface is still a mess, with four separate
combinations and lots of #ifdefs. This should really use a driver
approach, e.g. as is done with partition drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:18 +0000 (19:43 -0600)]
hash: Use Kconfig to enable hashing in host tools and SPL
At present when building host tools, we force CONFIG_SHAxxx to be enabled
regardless of the board Kconfig setting. This is done in the image.h
header file.
For SPL we currently just assume the algorithm is desired if U-Boot proper
enables it.
Clean this up by adding new Kconfig options to enable hashing on the host,
relying on CONFIG_IS_ENABLED() to deal with the different builds.
Add new SPL Kconfigs for hardware-accelerated hashing, to maintain the
current settings.
This allows us to drop the image.h code and the I_WANT_MD5 hack.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:17 +0000 (19:43 -0600)]
spl: cypto: Bring back SPL_ versions of SHA
Unfortunately these were removed by mistake. This means that adding hash
support to SPL brings in all software algorithms, with a substantial
increase in code size.
The origin of the problem was renaming them to SPL_FIT_xxx and then these
were removed altogether in a later commit.
Add them back. This aligns with CONFIG_MD5, for example, which has an SPL
variant.
Signed-off-by: Simon Glass <sjg@chromium.org>
Fixes:
f5bc9c25f31 ("image: Rename SPL_SHAxxx_SUPPORT to SPL_FIT_SHAxxx")
Fixes:
eb5171ddec9 ("common: Remove unused CONFIG_FIT_SHAxxx selectors")
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:16 +0000 (19:43 -0600)]
image: Add Kconfig options for FIT in the tools build
In preparation for enabling CONFIG_IS_ENABLED() on the host build, add
some options to enable the various FIT options expected in these tools.
This will ensure that the code builds correctly when CONFIG_TOOLS_xxx
is distinct from CONFIG_xxx.
Drop some #ifdefs which are immediately unnecessary (many more are in
later patches).
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:15 +0000 (19:43 -0600)]
kconfig: Add tools support to CONFIG_IS_ENABLED()
At present we must separately test for the host build for many options,
since we force them to be enabled. For example, CONFIG_FIT is always
enabled in the host tools, even if CONFIG_FIT is not enabled by the
board itself.
It would be more convenient if we could use, for example,
CONFIG_IS_ENABLED(FIT) and get CONFIG_HOST_FIT, when building for the
host. Add support for this.
With this and the tools_build() function, we should be able to remove all
the #ifdefs currently needed in code that is build by tools and targets.
This will be even nicer when we move to using CONFIG(xxx) everywhere,
since all the #ifdef and IS_ENABLED/CONFIG_IS_ENABLED stuff will go away.
Signed-off-by: Simon Glass <sjg@chromium.org>
Suggested-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> # b4f73886
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sun, 26 Sep 2021 01:43:14 +0000 (19:43 -0600)]
compiler: Rename host_build() to tools_build()
With the new TOOLS_LIBCRYPTO and some other changes, it seems that we are
heading towards calling this a tools build rather than a host build,
although of course it does happen on the host.
I cannot think of anything built by the host which cannot be described as
a tool, so rename this function.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Simon Glass [Sat, 25 Sep 2021 13:03:20 +0000 (07:03 -0600)]
image: Remove ifdefs around image_setup_linux() el at
Drop some more ifdefs in image-board.c and also the FPGA part of bootm.c
which calls into it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:19 +0000 (07:03 -0600)]
image: Avoid #ifdefs for manual relocation
Add a macro to handle manually relocating a pointer. Update the iamge code
to use this to avoid needing #ifdefs.
This also fixes a bug where the 'done' flag was not set.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:18 +0000 (07:03 -0600)]
image: Create a function to do manual relocation
Rather than adding an #ifdef and open-coding this calculation, add a
helper function to handle it. Use this in the image code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:17 +0000 (07:03 -0600)]
image: Split host code out into its own file
To avoid having #ifdefs in a few functions which are completely different
in the board and host code, create a new image-host.c file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:16 +0000 (07:03 -0600)]
image: Fix up checkpatch warnings in image-board.c
Tidy up the warnings.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:15 +0000 (07:03 -0600)]
image: Split board code out into its own file
To avoid a large #ifdef in the image.c file, move the affected code into
a separate file.
Avoid any style fix-ups for easier review. Those are in the next patch.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:14 +0000 (07:03 -0600)]
image: Update image_decomp() to avoid ifdefs
Adjust this function so that preprocessor macros are not needed. With
this, the host build uses more of the same header files as the target
build.
Rather than definining CONFIG_SYS_MALLOC_LEN, add a CONSERVE_MEMORY
define, since that is the purpose of the value.
This appears to have no impact on code size from a spot check of a few
boards (snow, firefly-rk3288, boston32r2el, m53menlo).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:13 +0000 (07:03 -0600)]
gzip: Avoid use of u64
The gzip API uses the u64 type in it, which is not available in the host
build. This makes it impossible to include the header file.
We could make this type available, but it seems unnecessary. Limiting the
compression size to that of the 'unsigned long' type seems good enough. On
32-bit machines the limit then becomes 4GB, which likely exceeds available
RAM anyway, therefore it should be sufficient. On 64-bit machines this is
effectively u64 anyway.
Update the header file and implementation to use 'ulong' instead of 'u64'.
Add a definition of u32 for the cases that seem to need exactly that
length. This should be safe enough.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:12 +0000 (07:03 -0600)]
image: Update zstd to avoid reporting error twice
The zstd implementation prints the error in image_decomp() which is
incorrect and does not match other algorithms. Drop this and let the
caller report the error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:11 +0000 (07:03 -0600)]
image: Avoid switch default in image_decomp()
At present this function is full of preprocessor macros. Adjust it to
check for an unsupported algorithm after the switch(). This will allow
us to drop the macros.
Fix up the return-value path and an extra blank line while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:10 +0000 (07:03 -0600)]
btrfs: Use U-Boot API for decompression
Use the common function to avoid code duplication.
Acked-by: Qu Wenruo <wqu@suse.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:09 +0000 (07:03 -0600)]
zstd: Create a function for use from U-Boot
The existing zstd API requires the same sequence of calls to perform its
task. Create a helper for U-Boot, to avoid code duplication, as is done
with other compression algorithms. Make use of of this from the image
code.
Note that the zstd code lacks a test in test/compression.c and this should
be added by the maintainer.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:08 +0000 (07:03 -0600)]
compiler: Add a comment to host_build()
This function should have a comment explaining what it does. Add one.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:07 +0000 (07:03 -0600)]
Add support for an owned buffer
When passing a data buffer back from a function, it is not always clear
who owns the buffer, i.e. who is responsible for freeing the memory used.
An example of this is where multiple files are decompressed from the
firmware image, using a temporary buffer for reading (since the
compressed data has to live somewhere) and producing a temporary or
permanent buffer with the resuilts.
Where the firmware image can be memory-mapped, as on x86, the compressed
data does not need to be buffered, but the complexity of having a buffer
which is either allocated or not, makes the code hard to understand.
Introduce a new 'abuf' which supports simple buffer operations:
- encapsulating a buffer and its size
- either allocated with malloc() or not
- able to be reliably freed if necessary
- able to be converted to an allocated buffer if needed
This simple API makes it easier to deal with allocated and memory-mapped
buffers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 25 Sep 2021 13:03:06 +0000 (07:03 -0600)]
lib: Add memdup()
Add a function to duplicate a memory region, a little like strdup().
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 8 Oct 2021 12:02:47 +0000 (08:02 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB (Pali)
- phy: marvell: a3700: Misc improvements (Pali)
- a38x serdes cleanup (Pali)
- A3720 PCIe enhancements (Pali & Marek)
- mvebu: mvebu_armada-8k: Puzzle M801 enhancements (Robert)
- mvebu: x530: Remove custom kwbimage.cfg (Chris)
- mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT (Stefan)
Chris Packham [Thu, 7 Oct 2021 08:39:23 +0000 (21:39 +1300)]
ARM: mvebu: x530: Remove custom kwbimage.cfg
Commit
ca1a4c863232 ("mvebu: select boot device at SoC level") made it
unnecessary for the A385 boards to have their own kwbimage.cfg but as
the x530 was in flight at the time it was added with it's own
kwbimage.cfg. Remove the custom kwbimage.cfg as the SoC level file is
suitable.
Signed-off-by: Chris Packham <judge.packham@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Robert Marko [Mon, 4 Oct 2021 13:12:54 +0000 (15:12 +0200)]
arm: mvebu: mvebu_armada-8k: drop Puzzle M801 early init code
Since the CP1 pinctrl is not properly set in the DTS, there is no
need for setting the pinctrl by writing hardcoded values to the MPP
registers.
So, drop the code relating to that.
Fixes:
87c220d0 ("arm: mvebu: mvebu_armada-8k: Add support for initializing iEi Puzzle-M801 networking")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Robert Marko [Mon, 4 Oct 2021 13:12:53 +0000 (15:12 +0200)]
arm: mvebu: dts: m801: correct CP1 pinctrl
Current CP1 pinctrl that is set on the Puzzle M801 is incorrect.
CP1 pins are only used for the SMI bus and the MSS I2C, all other
pins are just GPIO-s.
Due to this being set completely wrong, the pinctrl was actually
ended up being hardcoded in the board_early_init_f() step so that
SMI would work.
That is obviously not the right thing to do, so convert the register
hex values that were being written to individual pin modes and set it
in the DTS.
Add the SMI pins to the CP1 MDIO node as otherwise CP1 pinctrl does
not get probed without an consumer.
Fixes:
2ae2b8a2 ("arm: mvebu: Initial iEi Puzzle-M801 support")
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Stefan Roese <sr@denx.de>
Stefan Roese [Sun, 3 Oct 2021 09:53:45 +0000 (11:53 +0200)]
arm: mvebu: Select SPL_SKIP_LOWLEVEL_INIT on ARMADA_32BIT
Select SPL_SKIP_LOWLEVEL_INIT on 32bit Armada platforms via Kconfig,
as this was removed from mach/config.h in
a2ac2b96 ("Convert
CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig").
Signed-off-by: Stefan Roese <sr@denx.de>
Fixes:
a2ac2b96 ("Convert CONFIG_SKIP_LOWLEVEL_INIT et al to Kconfig")
Cc: Tom Rini <trini@konsulko.com>
Cc: Marek Behún <kabel@kernel.org>
Cc: Pali Rohár <pali@kernel.org>
Tested-by: Pali Rohár <pali@kernel.org>
Marek Behún [Sat, 25 Sep 2021 22:54:46 +0000 (00:54 +0200)]
arm: a37xx: pci: Update private structure documentation
There were several changes for this structure but the documentation was
not changed at the time. Fix this.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Marek Behún [Sat, 25 Sep 2021 22:54:45 +0000 (00:54 +0200)]
arm: a37xx: pci: Cosmetic change
Update indentation in driver's private structure.
Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 25 Sep 2021 22:54:44 +0000 (00:54 +0200)]
arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port
Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot,
add support for handling and propagation of CRSSVE bit.
When CRSSVE bit is unset (default), driver has to reissue config
read/write request on CRS response.
CRSSVE bit is supported only when CRSVIS bit is provided in read-only
Root Capabilities register. So manually inject this CRSVIS bit into read
response for that register.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 25 Sep 2021 22:54:43 +0000 (00:54 +0200)]
arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge
Now that PCI Bridge is working for the PCIe Root Port, U-Boot's PCI_PNP
code automatically enables memory access and bus mastering when needed.
We do not need to enable it when setting the HW up.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 25 Sep 2021 22:54:42 +0000 (00:54 +0200)]
arm: a37xx: pci: Add support for accessing PCI Bridge on root bus
Aardvark does not have a real PCIe Root Port device on the root bus.
Instead it has PCIe registers of PCIe Root Port device mapped in
internal Aardvark memory space starting at offset 0xc0.
The PCIe Root Port itself is normally available as a PCI Bridge device
on the root bus with bus number zero. Aardvark instead has the
configuration registers of this PCI Bridge at offset 0x00 of Aardvark's
memory space, but the class code of this device is Mass Storage
Controller (0x010400), instead of PCI Bridge (0x600400), which causes
U-Boot to fail to recognize it as a P2P Bridge
Add a hook into the pcie_advk_read_config() / pcie_advk_write_config()
functions to redirect access for root bus from PIO transfer to this
internal Aardvark memory space. This will allow U-Boot to access
configuration space of this PCI Bridge which represents PCIe Root Port.
Redirect access to PCI Bridge registers in range 0x10 - 0x34 to driver's
internal buffer (cfgcache[]). This is because at those addresses
Aardvark has different registers, incompatible with config space of a
PCI Bridge.
Redirect access to PCI Bridge register PCI_ROM_ADDRESS1 (0x38) to
Aardvark internal address for that register (0x30).
When reading PCI Bridge register PCI_HEADER_TYPE, set it explicitly to
value Type 1 (PCI_HEADER_TYPE_BRIDGE) as PCI Bridge must be of Type 1.
When writing to PCI_PRIMARY_BUS or PCI_SECONDARY_BUS registers on this
PCI Bridge, correctly update driver's first_busno and sec_busno
variables, so that pcie_advk_addr_valid() function can check if address
of any device behind the root bus is valid and that PIO transfers are
started with correct config type (1 vs 0), which is required for
accessing devices behind some PCI bridge after the root bus.
U-Boot's PCI_PNP code sets primary and secondary bus numbers as relative
to the configured bus number of the root bus. This is done so that
U-Boot can support multiple PCIe host bridges or multiple root port
buses, when internal bus numbers are different.
Now that root bus is available, update code in pcie_advk_read_config()
and pcie_advk_write_config() functions to correctly calculate real
Aardvark bus number of the target device from U-Boot's bus number as:
busno = PCI_BUS(bdf) - dev_seq(bus)
Stefan: Small fix of header masking as suggested by Pali.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Sat, 25 Sep 2021 22:54:41 +0000 (00:54 +0200)]
arm: a37xx: pci: Fix pcie_advk_link_up()
Aardvark reports Disabled and Hot Reset LTSSM states as values >= 0x20.
Link is not up in these states, so fix pcie_advk_link_up() function.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:22 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines
These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:21 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Remove unused PCIe macros and functions
Remove unused PCIe functions from SerDes code. They are unused and are
duplicated either from generic PCIe code or from pci_mvebu.c.
Remove also unused PCIe macros from SerDes code. They are just obfuscated
variants of standards macros in include/pci.h or in pci_mvebu.c.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:20 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Don't configure PCIe cards in SerDes init code
This code is trying to parse PCIe config space of PCIe card connected on
the other end of link and then is trying to force 5.0 GT/s speed via Target
Link Speed bits in PCIe Root Port Link Control 2 Register on the local part
of link if it sees that card supports 5.0 GT/s via Max Link Speed bits in
Link Capabilities Register.
The code is incorrect for more reasons:
- Accessing config space of an endpoint card cannot be done immediately.
If the PCIe link is not up, reading vendor/device ID registers will
return all ones.
- Parsing is incomplete, so it can cause issues even for working cards.
Moreover there is no need to force speed to 5.0 GT/s via Target Link Speed
bits on PCIe Root Port Link Control 2 Register. Hardware changes speed from
2.5 GT/s to 5.0 GT/s autonomously when it is supported.
Most importantly, this code does not change link speed at all, since
because after updating Target Link Speed bits on PCIe Root Port Link
Control 2 Register, it is required to retrain the link, and the code for
that is completely missing.
The code was probably needed for making buggy endpoint cards work. Such a
workaround, though, should be implemented via PCIe subsystem (via quirks,
for example), as buggy cards could also affect other PCIe controllers.
Note that this code is fully unrelated to a38x SerDes code and really
should not have been included in SerDes initialization. Usage of magic
constants without names and comments made this SerDes code hard to read and
understand.
Remove this PCIe application code from low level SerDes code. As this code
is configuring only 5.0 GT/s part, in the worst case, it could leave buggy
cards at the initial speed of 2.5 GT/s (if somehow before this change they
could have been "upgraded" to 5.0 GT/s speed even with missing link
retraining). Compliant cards which just need longer initialization should
work better after this change.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:19 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Don't overwrite PCI device ID
PCI device ID is part of the PCIe controller SoC / revision. For Root
Complex mode (which is the default and the only mode supported currently
by U-Boot and Linux kernel), it is PCI device ID of PCIe Root Port device.
If there is some issue with this device ID, it should be set / updated by
PCIe controller driver (pci_mvebu.c), as this register resides in address
space of the controller. It shouldn't be done in SerDes initialization
code.
In the worst case (a specific board for example) it could be done via
U-Boot's weak function board_pex_config().
But it should not be overwritten globally for all A38x devices.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:18 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration
Enabling Common Clock Configuration bit in PCIe Root Port Link Control
Register should not be done unconditionally. It is enabled by operating
system as part of ASPM. Also after enabling Common Clock Configuration it
is required to do more work, like retraining link. Some cards may be broken
due to this incomplete Common Clock Configuration and some cards are broken
and do not support ASPM at all.
Remove this incomplete code for Common Clock Configuration. It really
should not be done in SerDes code as it is not related to SerDes, but to
PCIe subsystem.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:17 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Don't overwrite read-only SAR PCIe registers
Device/Port Type bits of PCIe Root Port PCI Express Capabilities Register
are read-only SAR registers and are initialized according to current mode
configured by PCIe controller. Changing PCIe controller mode (from Root
Complex mode to Endpoint mode or the other way) is possible via PCI
Express Control Register (offset 0x41A00), bit 1 (ConfRoot Complex). This
has to be done in PCIe controller driver (in our case pci_mvebu.c). Note
that default mode is Root Complex.
Maximum Link Speed bits of PCIe Root Port Link Capabilities Register are
platform specific and overwriting them does not make sense. They are set by
PCIe controller according to current SerDes configuration. For A38x it is
5.0 GT/s if SerDes supports appropriate speed.
Maximum Link Width bits of PCIe Root Port Link Capabilities Register are
read-only SAR registers, but unfortunately if this is not set correctly
here, then access PCI config space of the endpoint card behind this Root
Port does not work.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:16 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Add comments for hws_pex_config() code
Add comments to understand what this magic code is doing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:15 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Remove duplicate macro SOC_CTRL_REG
SoC Control 1 Register (offset 0x18204) is already defined by macro
SOC_CONTROL_REG1.
Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c
code and remove the other definition.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 20:59:14 +0000 (22:59 +0200)]
arm: mvebu: a38x: serdes: Add comments and use macros in PCIe code
Replace magic register offsets by macros to make code more readable.
Add comments about what this code is doing.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 14:11:57 +0000 (16:11 +0200)]
phy: marvell: a3700: Return correct error code when power up fails
Subroutines in comphy_usb2_power_up() and comphy_sgmii_power_up() functions
may fail. In this case, do not continue execution of current function and
instead jump to the end. Return value in 'ret' variable is already set.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 14:11:56 +0000 (16:11 +0200)]
phy: marvell: a3700: Fix configuring polarity invert bits
phy_txd_inv or phy_rxd_inv needs to be set only in case when
appropriate polarity is inverted. Otherwise these bits should be
cleared.
Same change was included in TF-A project:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9406
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 24 Sep 2021 14:11:55 +0000 (16:11 +0200)]
phy: marvell: a3700: Set TXDCLK_2X_SEL bit during PCIe initialization
Marvell Armada 3700 Functional Specifications, section 52.2 PCIe Link
Initialization says that TXDCLK_2X_SEL bit needs to be enabled for PCIe
Root Complex mode.
Same change was included in TF-A project:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/9408
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Thu, 23 Sep 2021 09:07:18 +0000 (11:07 +0200)]
arm: a37xx: pci: Increase PCIe IO size from 64 KiB to 1 MiB
Commit
079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB
to 127 MiB") increased size of PCIe MEM to 127 MiB, which is the maximal
possible size for allocated 128 MiB PCIe window. PCIe IO size in that
commit was unchanged.
Armada 3720 PCIe controller supports 32-bit IO space mapping so it is
possible to assign more than 64 KiB if address space for IO.
Currently controller has assigned 127 MiB + 64 KiB memory and therefore
there is 960 KiB of unused memory. So assign it to IO space by increasing
IO window from 64 KiB to 1 MiB.
Signed-off-by: Pali Rohár <pali@kernel.org>
Fixes:
079b35a26111 ("arm: a37xx: pci: Increase PCIe MEM size from 16 MiB to 127 MiB")
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Thu, 7 Oct 2021 13:02:22 +0000 (09:02 -0400)]
Merge tag 'u-boot-amlogic-
20211007' of https://source.denx.de/u-boot/custodians/u-boot-amlogic
- Add new SoC ID for S905Y2 found in Radxa Zero
- pcie_dw_meson: fix usb fail when pci link fails to go up
- Sync Amlogic DT from Linux 5.14
- dwc3-meson-gxl: add AXG compatible
- dts: keep back HW order for MMC devices since change in Upstream Linux
- Cleanup local AXG DT USB nodes now everything is upstream
- distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot
- New Boards:
- Odroid-HC4: a variant of Odroid-C4 with 2 SATA ports (via PCIe-SATA bridge)
- Beelink GS-King X: A variant of the other Beelink board with 2 SATA ports (via USB3-SATA bridge)
- Banana Pi M5: another credit card SBC
- JetHub D1/H1: home automation controllers
- Radxa Zero: another RPi Zero sized SBC
Tom Rini [Thu, 7 Oct 2021 13:00:45 +0000 (09:00 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- Reset improvements, enable coherence manager on ae350, k210 clk
improvements, other fixes
Christian Hewitt [Wed, 15 Sep 2021 01:46:59 +0000 (01:46 +0000)]
doc: boards: amlogic: update for Radxa Zero
Add documentation bits for the Radxa Zero
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
[narmstrong: updated u200 MAINTAINERS]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Christian Hewitt [Wed, 15 Sep 2021 01:46:58 +0000 (01:46 +0000)]
boards: amlogic: add Radxa Zero defconfig
Add a defconfig for the Radxa Zero SBC, using an Amlogic S905Y2 chip.
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
[narmstrong: updated u200 MAINTAINERS & add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Christian Hewitt [Wed, 15 Sep 2021 01:46:57 +0000 (01:46 +0000)]
ARM: dts: add support for Radxa Zero
Import the initial dts queued for Linux 5.16.y
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Christian Hewitt [Wed, 15 Sep 2021 01:46:56 +0000 (01:46 +0000)]
ARM: dts: sort Amlogic Makefile section
Alpha sort the Amlogic dtb list (same as the kernel).
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Vyacheslav Bocharov [Mon, 20 Sep 2021 08:40:16 +0000 (11:40 +0300)]
ARM: amlogic: add JetHub D1/H1 docs
Fix doc/board/amlogic/index.rst:
- Add S905W to S905X column.
- Add JetHub devices to the corresponding columns.
- Fix tabs to spaces for table alignment
Add doc/board/amlogic files:
- jethub-j100.rst
- jethub-j80.rst
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Vyacheslav Bocharov [Mon, 20 Sep 2021 08:40:15 +0000 (11:40 +0300)]
ARM: amlogic: add JetHub D1/H1 device support
Add support for new home automation devices.
JetHome Jethub D1 (http://jethome.ru/jethub-d1) is a home automation controller with the following features:
- DIN Rail Mounting case
- Amlogic A113X (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- 512Mb/1GB DDR3
- 8/16GB eMMC flash
- 1 x USB 2.0
- 1 x 10/100Mbps ethernet
- WiFi / Bluetooth AMPAK AP6255 (Broadcom BCM43455) IEEE 802.11a/b/g/n/ac, Bluetooth 4.2.
- TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support.
- 2 x gpio LEDS
- GPIO user Button
- 1 x 1-Wire
- 2 x RS-485
- 4 x dry contact digital GPIO inputs
- 3 x relay GPIO outputs
- DC source with a voltage of 9 to 56 V / Passive POE
JetHome Jethub H1 (http://jethome.ru/jethub-h1) is a home automation controller with the following features:
- Square plastic case
- Amlogic S905W (ARM Cortex-A53) quad-core up to 1.5GHz
- no video out
- 1GB DDR3
- 8/16GB eMMC flash
- 2 x USB 2.0
- 1 x 10/100Mbps ethernet
- WiFi / Bluetooth RTL8822CS IEEE 802.11a/b/g/n/ac, Bluetooth 5.0.
- TI CC2538 + CC2592 Zigbee Wireless Module with up to 20dBm output power and Zigbee 3.0 support.
- MicroSD 2.x/3.x/4.x DS/HS cards.
- 1 x gpio LED
- ADC user Button
- DC source 5V microUSB with serial console
Patches from:
- JetHub H1
https://lore.kernel.org/r/
20210915085715.1134940-4-adeep@lexina.in
https://git.kernel.org/amlogic/c/
abfaae24ecf3e7f00508b60fa05e2b6789b8f607
- JetHub D1
https://lore.kernel.org/r/
20210915085715.1134940-5-adeep@lexina.in
https://git.kernel.org/amlogic/c/
8e279fb2903990cc6296ec56b3b80b2f854b6c79
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
[narmstrong: removed unused variable value]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Vyacheslav Bocharov [Mon, 20 Sep 2021 08:40:14 +0000 (11:40 +0300)]
ARM: amlogic: add JetHub common config header
JetHub devices uses its own boot sequence with "rescue" button
Signed-off-by: Vyacheslav Bocharov <adeep@lexina.in>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:09 +0000 (09:37 +0200)]
ARM: amlogic: add Banana Pi M5
Banana Pi BPI-M5 is a credit card format SBC with the following features:
- Amlogic S905X3 quad core Cortex-A55
- Mali-G31 GPU
- 4GB LPDDR4
- 16GB eMMC flash
- 4 USB 3.0
- 1 GbE ethernet
- HDMI output
- 2x LEDS
- SDCard
- 2.5mm Jack with Stereo Audio + CVBS
- Infrared Received
- ADC Button
- GPIO Button
- 40 pins header + 3pins debug header
[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:08 +0000 (09:37 +0200)]
ARM: meson: add Beelink GS-King X board
The Beelink GS-King X is a variant of the GS King boards but with an internal
USB to SATA bridge and advanced audio features.
[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:07 +0000 (09:37 +0200)]
doc: boards: amlogic: update for Odroid HC4
Add documentation bits for the Odroid-HC4.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:06 +0000 (09:37 +0200)]
ARM: amlogic: add support for Odroid-HC4 device
The Odroid-HC4 is a variant of the Odroid-C4 board but with a PCIe-SATA bridge
instead of the USB3 ports.
[narmstrong: add missing CONFIG_SYS_LOAD_ADDR from defconfig]
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:05 +0000 (09:37 +0200)]
distro_bootcmd: run pci enum for scsi_boot just like it is done for nvme_boot
The SCSI device can be a PCIe adapter, so run pcie enum if enabled.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:04 +0000 (09:37 +0200)]
configs: meson64: add SCSI boot target
Add SCSI target to be able to boot from the SATA disks on the Odroid HC4 using
an on-board AHCI PCIe controller.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Neil Armstrong [Fri, 17 Sep 2021 07:37:03 +0000 (09:37 +0200)]
ARM: meson-axg: remove local USB nodes
Drop the local USB nodes after Linux 5.14 sync.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:02 +0000 (09:37 +0200)]
ARM: meson: keep HW order for MMC devices
Since Linux commmit [1], the order is fixed with aliases, in order to keep the
MMC device order, set it back to HW order in U-Boot dtsi files.
[1]
ab547c4fb39f ("arm64: dts: amlogic: Assign a fixed index to mmc devices")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Fri, 17 Sep 2021 07:37:01 +0000 (09:37 +0200)]
usb: dwc3: meson-gxl: add AXG compatible
Upstream Linux uses the "amlogic,meson-axg-usb-ctrl" for AXG SoCs.
This adds it to the compatible list for this driver.
Reported-by: Vyacheslav Bocharov <adeep@lexina.in>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Tested-by: Vyacheslav Bocharov <adeep@lexina.in>
Neil Armstrong [Fri, 17 Sep 2021 07:37:00 +0000 (09:37 +0200)]
ARM: meson: Sync Amlogic DT from Linux 5.14
Import Amlogic DT changes from Linux commit
7d2a07b76933 ("Linux 5.14"),
dt-bindings clock changes and new meson-g12b-gsking-x.dts,
meson-sm1-bananapi-m5 & odroid-hc4 boards.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Wed, 8 Sep 2021 12:32:12 +0000 (14:32 +0200)]
pci: pcie_dw_meson: fix usb fail when pci link fails to go up
On Amlogic A311D, when the PCIe link fails disabling the related clocks
makes USB fail. For an unknown reason, this doesn happen on the S905D3 SoC.
Mimic the Linux behavior by not considering a link failure a probe failure,
and continue even if the PCIe link is down.
Reported-by: Art Nikpal <email2tema@gmail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Christian Hewitt [Fri, 20 Aug 2021 02:18:36 +0000 (02:18 +0000)]
ARM: meson: Add S905Y2 SOC ID
Add the SOC ID for the S905Y2 to board info, see below for before/after
tested with a Radxa Zero board:
SoC: Amlogic Meson G12A (Unknown) Revision 28:b (30:2)
SoC: Amlogic Meson G12A (S905Y2) Revision 28:b (30:2)
Signed-off-by: Christian Hewitt <christianshewitt@gmail.com>
Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Leo Yu-Chi Liang [Thu, 23 Sep 2021 02:34:29 +0000 (10:34 +0800)]
riscv: ae350: enable Coherence Manager for ae350
If Coherence Manager were not set in the beginning,
u-boot-spl would sometimes fail to boot to u-boot proper.
Enable CM and I/D cache at the same time in harts_early_init
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Heinrich Schuchardt [Sun, 12 Sep 2021 19:11:47 +0000 (21:11 +0200)]
configs: enable SYSRESET_SBI on qemu-riscvXX_smode_defconfig
There should be a platform compiled with the new driver.
Enable CONFIG_SYSRESET_SBI for all QEMU boards using SBI.
If you want to test the SBI sysreset driver, disable
CONFIG_SYSRESET_SYSCON.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Heinrich Schuchardt [Sun, 12 Sep 2021 19:11:46 +0000 (21:11 +0200)]
sysreset: provide SBI based sysreset driver
Provide sysreset driver using the SBI system reset extension.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tested-by: Samuel Holland <samuel@sholland.org>
Heinrich Schuchardt [Sun, 12 Sep 2021 19:11:45 +0000 (21:11 +0200)]
cmd/sbi: use constants instead of numerical values
Use constants for extension IDs.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Heinrich Schuchardt [Sun, 12 Sep 2021 19:11:44 +0000 (21:11 +0200)]
riscv: add missing SBI extension definitions
Add the System Reset Extension and the Hart State Management Extension
definitions.
Add missing RFENCE Extension enum values.
The SBI 0.1 extension constants are needed for the sbi command. Remove
an #ifdef.
Cf. https://github.com/riscv/riscv-sbi-doc/blob/master/riscv-sbi.adoc
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Samuel Holland [Sun, 12 Sep 2021 16:26:45 +0000 (11:26 -0500)]
riscv: image: Use the first DRAM bank for bootm_low
bootm_low is used as a base address is used to allocate space for the
FDT blob, initrd, cmdline, etc. when booting Linux. Set the default
value for RISC-V to the start of the first DRAM bank, so platforms can
get their DRAM layout from the device tree, and do not need to define
CONFIG_SYS_SDRAM_BASE.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Samuel Holland [Sun, 12 Sep 2021 16:05:47 +0000 (11:05 -0500)]
riscv: Fix setting no-map in reserved memory nodes
The no-map property is wrongly skipped if a no-map reserved memory
node follows one without that property. Fix this by not remembering
the absence of a no-map property across loop iterations.
Fixes:
d4ea649f179a ("riscv: Provide a mechanism to fix DT for reserved memory")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Atish Patra <atish.patra@wdc.com>
Samuel Holland [Sun, 12 Sep 2021 15:56:09 +0000 (10:56 -0500)]
serial: Add a debug console using the RISC-V SBI interface
The RISC-V SBI interface v0.1 provides a function for printing a
character to the console. Even though SBI v0.1 functions are deprecated,
the SBI console is quite useful for early debugging, because it works
without any dcache, memory, or MMIO access in S mode.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sean Anderson [Sat, 11 Sep 2021 17:20:03 +0000 (13:20 -0400)]
clk: k210: Try harder to get the best config
In some cases, the best config cannot be used because the VCO would be
out-of-spec. In these cases, we may need to try a worse combination of r/od
in order to find the best representable config. This also adds a few test
cases to catch this and other (possible) unlikely errors.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Sat, 11 Sep 2021 17:20:02 +0000 (13:20 -0400)]
test: dm: k210: Reduce duplication in test cases
Having to copy-paste the same 3 lines makes adding new test cases
error-prone. Use a macro.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Sean Anderson [Sat, 11 Sep 2021 17:20:01 +0000 (13:20 -0400)]
k210: clk: Refactor out_of_spec tests
Everything here sits in a while (true) loop. However, this introduces a
couple of layers of indentation. We can simplify the code by introducing a
single goto instead of using continue/break. This will also make adding
loops in the next patch easier.
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Sean Anderson [Sat, 11 Sep 2021 17:20:00 +0000 (13:20 -0400)]
clk: k210: Fix checking if ulongs are less than 0
The PLL functions take ulong arguments for rate, but still check if that
rate is negative (which is never true). The correct way to handle this is
to use IS_ERR_VALUE (like is already done in k210_clk_set_rate). While
we're at it, we can move the error checking up into the caller of the pll
set/get rate functions. This also protects our other calculations from
using bogus values for rate.
Fixes:
609bd60b94 ("clk: k210: Rewrite to remove CCF")
Reported-by: Coverity Scan <scan-admin@coverity.com>
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>