Jason Ekstrand [Mon, 26 Sep 2022 17:03:28 +0000 (12:03 -0500)]
vulkan/wsi: Support configuring swapchain images as part of swapchain init
The eventual goal here is to move as much of the prime and blit logic
out of the individual window-system back-ends as possible.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18826>
Dave Airlie [Mon, 26 Sep 2022 06:49:06 +0000 (16:49 +1000)]
llvmpipe/cs: move compute code to explicit pointer types
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
Dave Airlie [Mon, 26 Sep 2022 06:42:17 +0000 (16:42 +1000)]
llvmpipe/setup: move setup code to explicit pointers.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
Dave Airlie [Mon, 26 Sep 2022 03:52:21 +0000 (13:52 +1000)]
llvmpipe/fs: fix invocations access for opaque ptrs.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
Dave Airlie [Mon, 26 Sep 2022 03:00:11 +0000 (13:00 +1000)]
llvmpipe/cs: convert cs thread data to opaque friendly api
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
Dave Airlie [Mon, 26 Sep 2022 02:59:05 +0000 (12:59 +1000)]
llvmpipe/cs: convert cs context to opaque friendly api
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
Dave Airlie [Mon, 26 Sep 2022 02:56:23 +0000 (12:56 +1000)]
llvmpipe/fs: convert linear context to opaque pointers friendly
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
Dave Airlie [Mon, 26 Sep 2022 02:51:30 +0000 (12:51 +1000)]
llvmpipe/fs: convert thread data ptr to opaque ptr friendly apis
this converts the thread data code.
The cache code still isn't fixed but needs future API changes
to sampling code.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
Dave Airlie [Mon, 26 Sep 2022 02:44:53 +0000 (12:44 +1000)]
llvmpipe/fs: start passing explicit context pointer type.
In order to support opaque pointers in the future, we need to be
more explicit with the pointer types here.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18837>
nyanmisaka [Tue, 27 Sep 2022 18:38:42 +0000 (02:38 +0800)]
gallium: Do not include offscreen winsys if glx is disabled
Offscreen winsys introduced in Mesa 22.2 depends on glx(dri) and libswkmsdri.
The error message is:
/usr/bin/ld: src/gallium/auxiliary/libgalliumvlwinsys.a.p/vl_vl_winsys_dri_vgem.c.o: in function `vl_vgem_drm_screen_create':
vl_winsys_dri_vgem.c:(.text.vl_vgem_drm_screen_create+0x28): undefined reference to `kms_dri_create_winsys'
Fixes:
31dcb396 (gallium/vl: Add software winsys and offscreen winsys)
Cc: mesa-stable
Signed-off-by: nyanmisaka <nst799610810@gmail.com>
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18843>
LingMan [Tue, 27 Sep 2022 02:25:16 +0000 (04:25 +0200)]
docs/rusticl: Document minimum required bindgen version
rusticl requires at least bindgen 0.58.0 to build.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18834>
LingMan [Tue, 27 Sep 2022 01:50:46 +0000 (03:50 +0200)]
rusticl/bindgen: Use `allowlist-*` instead of `whitelist-*` switches
bindgen 0.58.0 deprecated the `whitelist-*` switches in favor of the new `allowlist-*` switches.
Currently rusticl uses a mixture of both.
Consistently move to the newer versions.
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18834>
Corentin Noël [Fri, 16 Sep 2022 14:28:47 +0000 (16:28 +0200)]
gallivm: avoid the use of an uninitialized value
When need_derivs is false, lp_build_cube_lookup does not set the value of
derivs_out which means that the stack is not initialized but its pointer
is then used.
Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18635>
Mike Blumenkrantz [Wed, 21 Sep 2022 17:18:39 +0000 (13:18 -0400)]
zink: set layouts before possibly reordering image copies
layout-setting may change which cmdbuf can be used
Fixes:
731d7be3756 ("zink: make get_cmdbuf() public")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18727>
Mike Blumenkrantz [Wed, 21 Sep 2022 17:15:53 +0000 (13:15 -0400)]
zink: always unflag unordered_write when binding image descriptors
image descriptors have to maintain their layout, which means it's no
longer possible to reorder any operations once they use a non-transfer
layout
Fixes:
ca03e35821d ("zink: expand unordered_exec")
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18727>
Mike Blumenkrantz [Wed, 10 Aug 2022 14:53:21 +0000 (10:53 -0400)]
aux/trace: dump depth_clamp for rasterizer state
cc: mesa-stable
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18783>
Mike Blumenkrantz [Thu, 23 Jun 2022 14:25:09 +0000 (10:25 -0400)]
aux/trace: dump line_rectangular member of rasterizer state
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18783>
Konstantin Seurer [Tue, 27 Sep 2022 12:47:00 +0000 (14:47 +0200)]
radv: Add and use AS and scratch layout structs
The memory layout logic is duplicated between
radv_GetAccelerationStructureBuildSizesKHR and
radv_CmdBuildAccelerationStructuresKHR. This patch adds a helper that
computes the scratch and acceleration structure memory layout for a
given build configuration.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Friedrich Vock <friedrich.vock@gmx.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18842>
Samuel Pitoiset [Mon, 26 Sep 2022 09:44:13 +0000 (11:44 +0200)]
radv: fix emitting RBPLUS state when MRTs are compacted
The RBPLUS state needs the non-compacted SPI_SHADER_COL_FORMAT value,
otherwise the state is wrongly emitted if there is holes.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7348
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7319
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7365
Fixes:
8fcb4aa0ebd ("radv: compact MRTs to save PS export memory space")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18818>
Bas Nieuwenhuizen [Mon, 26 Sep 2022 23:47:20 +0000 (01:47 +0200)]
radv: Do an early check of distance in triangle culling.
Culls like 99% of the triangles that are culled at all.
Reduces VALU usage in Q2RTX traversal by ~8%, though doesn't look
like VALU is a bottleneck at this point ...
For Control we get a ~5% reduction in VALU usage, but similarly it
doesn't look like a bottleneck.
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18830>
Pierre-Eric Pelloux-Prayer [Fri, 23 Sep 2022 10:15:36 +0000 (12:15 +0200)]
tc: don't use CPU storage for glBufferData
This fixes a performance regression with yquake2 cause by
the enablement of cpu_storage by default for radeonsi in
a5a8e197413.
Fixes:
a5a8e197413 ("radeonsi: enable tc cpu_storage by default")
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18774>
Pierre-Eric Pelloux-Prayer [Fri, 23 Sep 2022 10:16:59 +0000 (12:16 +0200)]
tc: do a GPU->CPU copy to initialize cpu_storage
If the GPU-side storage has been written to without using cpu_storage,
then we have to initialize the CPU-side storage correctly.
This requires a sync + copy but it's a one time operation so it shouldn't
affect performance much.
I don't think it fixes any existing bug, but the next commit will need
this to behave correctly.
cc: mesa-stable
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18774>
Lionel Landwerlin [Fri, 23 Sep 2022 19:21:10 +0000 (22:21 +0300)]
anv: flag BO for write combine when CPU visible and potentially in lmem
This should fix a performance regression with the internal kernel
branch which does not support the upstream I915_MMAP_OFFSET_FIXED.
With I915_MMAP_OFFSET_FIXED we defer the mapping flags to the kernel
since it knows better where buffers are going to end up (lmem or smem).
The internal kernel doesn´t have that and there we should use write
combined for anything that can be in lmem.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
Mark Janes [Fri, 28 Aug 2020 20:01:53 +0000 (13:01 -0700)]
anv: Allocate buffers with write-combined local memory
Marginally improves DG1 performance (< 1%)
v2: Only on local mem (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
Mark Janes [Tue, 27 Sep 2022 08:53:00 +0000 (11:53 +0300)]
anv: Use WC mapped local memory for block pool BO
Improve DG1 performance:
Fallout: +7%
Talos: +15%
v2: Don't drop SNOOP (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
Mark Janes [Mon, 24 Aug 2020 22:41:58 +0000 (15:41 -0700)]
anv: Track BOs that need a write-combined mapping
v2: simplify logic a bit (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18841>
Daniel Schürmann [Mon, 22 Aug 2022 15:26:34 +0000 (17:26 +0200)]
aco/opt_value_numbering: use monotonic_allocator for unordered_map
This patch also changes the rename map to unordered.
Roughly halves the time spent on CSE in ACO.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18112>
Daniel Schürmann [Mon, 22 Aug 2022 12:37:59 +0000 (14:37 +0200)]
aco: implement allocator_traits for monotonic_allocator<T>
For easier usage, this patch also adds aliases for std::map
and std::unordered_map using this allocator.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18112>
Daniel Schürmann [Mon, 15 Aug 2022 19:42:19 +0000 (21:42 +0200)]
aco: use monotonic_buffer_resource for instructions
As monotonic_buffer_resource is not thread-safe,
we use a thread_local instance which gets allocated once.
This change reduces the compile time spent in ACO by
approximately 10%.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18112>
Daniel Schürmann [Mon, 15 Aug 2022 19:42:05 +0000 (21:42 +0200)]
aco: implement custom memory resource
This basic allocator implements an arena allocation strategy
and cannot free individual allocations.
It is intended for very fast memory allocations in situations
where memory is used to build up a few objects and then is
released all at once.
This class mimics std::pmr::monotonic_buffer_resource.
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18112>
Daniel Schürmann [Tue, 27 Sep 2022 12:45:16 +0000 (14:45 +0200)]
aco: simplify operands_offset calculation in create_instruction()
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18112>
Kenneth Graunke [Mon, 28 Feb 2022 19:07:30 +0000 (11:07 -0800)]
blorp: Fix typo in blorp_xy_block_copy_blt
suppotred -> supported (Thanks to Tapani for catching this.)
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
Kenneth Graunke [Tue, 1 Feb 2022 08:12:46 +0000 (00:12 -0800)]
blorp: Implement blitter clears via XY_FAST_COLOR_BLT
Vulkan transfer queues need this functionality. A lot of the code is
pretty similar to what we have for XY_BLOCK_COPY_BLT.
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
Kenneth Graunke [Sat, 26 Feb 2022 08:56:51 +0000 (00:56 -0800)]
blorp: Make blitter_supports_aux accessible from multiple files.
We'll want it in blorp_clear.c shortly.
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
Kenneth Graunke [Tue, 1 Feb 2022 08:11:07 +0000 (00:11 -0800)]
intel/genxml: Add XY_FAST_COLOR_BLT
We'll need to use this for VkCmdFillBuffer on transfer queues.
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15183>
Eric Engestrom [Tue, 27 Sep 2022 08:46:05 +0000 (09:46 +0100)]
ci: bump mold to 1.5
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18838>
Eric Engestrom [Tue, 27 Sep 2022 08:45:25 +0000 (09:45 +0100)]
ci: unexport local variable (and fix formatting)
Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18838>
Jason Ekstrand [Thu, 5 Nov 2020 17:53:51 +0000 (11:53 -0600)]
intel/devinfo: DG2 supports ray-tracing
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Wed, 13 May 2020 20:45:06 +0000 (15:45 -0500)]
anv: Advertise ray-tracing on DG2
Also disable ray-tracing support if with_intel_vk_rt is not set.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jordan Justen [Thu, 21 Apr 2022 21:24:53 +0000 (14:24 -0700)]
meson: Define with_intel_vk_rt based on with_intel_clc
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jordan Justen [Sun, 6 Mar 2022 00:57:03 +0000 (16:57 -0800)]
meson: Deprecate vulkan-rt-drivers intel
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jordan Justen [Sat, 5 Mar 2022 23:49:35 +0000 (15:49 -0800)]
anv/meson: Use anv_flags and anv_cpp_flags in genX compiles
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Tue, 22 Feb 2022 13:51:50 +0000 (15:51 +0200)]
anv: use the right dispatch size for tracing shaders
We assumed the trampoline shader would always be SIMD8.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Wed, 18 Aug 2021 14:20:35 +0000 (17:20 +0300)]
anv: bump client visible address heap to 32GiB
Some raytracing tests are allocating lots of buffer and because of our
2Mb alignment restriction on local memory, we're running our of VMA...
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Zhang, Jianxun <jianxun.zhang@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Tue, 17 Aug 2021 11:51:12 +0000 (14:51 +0300)]
anv: setup scratch space correctly for RT shaders
Things are a bit confusing because we use the term "scratch" for 2
different things :
* the buffer for register allocation spilling
* the buffer for storing live values between splitted shaders around shader calls
Here we're fixing the missing register allocation spilling buffer.
v2: update comments (Caio)
fix scratch bo size computation with pipeline libraries (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Thu, 21 Jan 2021 08:18:32 +0000 (02:18 -0600)]
anv: Build BVHs on the GPU with GRL
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Tue, 2 Mar 2021 23:43:41 +0000 (17:43 -0600)]
intel/grl: Parse GRL files and generate C
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Tue, 2 Mar 2021 23:50:49 +0000 (17:50 -0600)]
anv/grl: Add a helper for dispatching our pre-built kernels
v2: Use the default pipeline cache (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Tue, 23 Feb 2021 04:18:29 +0000 (22:18 -0600)]
anv/grl: Build OpenCL kernels
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Iván Briano [Tue, 2 Mar 2021 20:34:10 +0000 (14:34 -0600)]
anv/grl: Add a GRL file parser
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Mon, 22 Feb 2021 23:44:46 +0000 (17:44 -0600)]
anv: Import GRL
GRL, or Graphics Library for Ray-tracing is a library we share with the
Windows drivers for doing BVH builds on the GPU. It consists of a few
headers shared between CL and C code, a bunch of CL kernels, and some
GRL meta-kernels in their own format.
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Thu, 17 Feb 2022 12:22:57 +0000 (14:22 +0200)]
anv: add new command buffer space allocation
To be used for acceleration structure building.
v2: fix missing u_vector_finish
Free all BOs
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jianxun Zhang <jianxun.zhang@linux.intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Tue, 29 Sep 2020 23:47:09 +0000 (18:47 -0500)]
anv: Add support for OpenCL-style kernel dispatch
v2: Use brw_cs_get_dispatch_info() (Lionel)
Merge barrier fixes (Lionel)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Tue, 29 Sep 2020 22:35:35 +0000 (17:35 -0500)]
anv: Add support for compiling OpenCL-style kernels
v2: remove unused definitions
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Thu, 24 Sep 2020 21:27:20 +0000 (16:27 -0500)]
anv: Add extern "C" guards
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Tue, 3 May 2022 19:12:57 +0000 (22:12 +0300)]
anv: disable SIMD16 for RT shaders
Since divergence is a lot more likely in RT than compute, it makes
sense to limit ourselves to SIMD8.
The trampoline shader defaults to SIMD16 since this one is uniform.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Mon, 9 Nov 2020 21:33:17 +0000 (15:33 -0600)]
anv: Set up the memory-backed FIFO buffer
v2: Fix incorrect goto (Caio)
Comment 3DSTATE_BTD programming (Caio)
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Mon, 7 Sep 2020 07:24:20 +0000 (02:24 -0500)]
anv: Implement VK_KHR_pipeline_library
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Wed, 5 Aug 2020 22:30:13 +0000 (17:30 -0500)]
anv: Add an anv_address_map helper
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Sat, 20 Jun 2020 15:40:34 +0000 (10:40 -0500)]
anv/formats: Advertise ACCELERATION_STRUCTURE_VERTEX_BUFFER_BIT
v2: Only expose the bit when ray tracing is supported.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Mon, 21 Feb 2022 12:15:14 +0000 (14:15 +0200)]
intel/mi_builder: allow half GP registers for dereferencing
Some of the GRL metakernels will generate 64bit value in a register,
then use only half of that as the last operation on that value.
v2: Add comment (Caio)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Fri, 5 Mar 2021 06:43:49 +0000 (00:43 -0600)]
intel/mi_builder: Add a helper for incrementing reference counts
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Fri, 26 Feb 2021 23:13:25 +0000 (17:13 -0600)]
intel/mi_builder: add a way to reserve a register
Will be useful for GRL metakernels.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Wed, 2 Jun 2021 09:31:56 +0000 (12:31 +0300)]
genxml: add missing no duplicate anyhit flag
This mirrors the VK_GEOMETRY_NO_DUPLICATE_ANY_HIT_INVOCATION_BIT_KHR
enum of VkGeometryFlagBitsKHR. Purely here for documentation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Mon, 8 Aug 2022 06:17:21 +0000 (09:17 +0300)]
intel/fs: disable split_array_vars on opencl kernels
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Fri, 18 Feb 2022 13:44:13 +0000 (15:44 +0200)]
intel/nir: disable assert on async stack id
This can be accessed from :
- RT shaders
- CS trampoline shader
We missed the second part here.
Fixes:
046571479028 ("intel/nir/rt: add more helpers for ray queries")
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Thu, 21 Apr 2022 14:32:51 +0000 (07:32 -0700)]
intel/nir: fix potential invalid function impl ptr usage
We keep the nir_builder::impl value around, but we've run some passes
that might have change the main function.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
96fde5518b5c ("intel/rt: Add a helper to create the raygen trampoline shader")
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Wed, 13 Apr 2022 13:04:25 +0000 (16:04 +0300)]
intel/nir: fixup preserved metadata in rayquery lowering
Another case of not clearing the metadata correctly.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
c78be5da300a ("intel/fs: lower ray query intrinsics")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Mon, 5 Jul 2021 13:01:41 +0000 (16:01 +0300)]
intel/fs: take a builder arg for resolve_source_modifiers()
There will be situations where we will want to use a local builder
rather than the one associated with NIR->backend translation.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Thu, 4 Nov 2021 10:43:04 +0000 (12:43 +0200)]
intel/nir: reuse rt helper
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Fri, 13 Aug 2021 14:15:55 +0000 (07:15 -0700)]
intel/rt: fix procedural primitive ID access
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Thu, 29 Oct 2020 14:35:10 +0000 (09:35 -0500)]
intel/fs: SEL_EXEC uses the integer pipe for 64-bit stuff
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Jason Ekstrand [Thu, 29 Oct 2020 14:34:08 +0000 (09:34 -0500)]
intel/fs: Always use integer types for indirect MOVs
There's a new Gen12.5 restriction which forbids using the VxH or Vx1 on
the floating-point pipe.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Thu, 19 Aug 2021 11:55:39 +0000 (14:55 +0300)]
intel/devinfo: Rename & implement num_dual_subslices
v2: Use the upper bound of dual subslices as the ID is not remapped
with fused off parts and this is what we'll use for a bunch of
computation in RT.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Thu, 22 Sep 2022 10:08:59 +0000 (13:08 +0300)]
meson: bump required llvm-spirv version with intel-clc
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Lionel Landwerlin [Tue, 7 Jun 2022 11:29:27 +0000 (14:29 +0300)]
anv: remove HDC flush from invalidate bits
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
a49b145e8d59 ("anv: Replace DC Flush with HDC Pipeline Flush")
Acked-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16970>
Kenneth Graunke [Thu, 4 Aug 2022 09:06:52 +0000 (02:06 -0700)]
intel/compiler: Vectorize gl_TessLevelInner/Outer[] writes
Setting the NIR options takes care of iris thanks to the common st/mesa
linking code, and updating brw_nir_link_shaders should handle anv.
The main effort here is updating remap_tess_levels, which needs to
handle vector stores, writemasking, and swizzling. Unfortunately,
we also need to continue handling the existing single-component
access because it's used for TES inputs, which we don't vectorize.
We could try to vectorize TES inputs too, but they're all pushed
anyway, so it wouldn't buy us much other than deleting this code.
Also, we do have opt_combine_stores, but not one for loads.
One limitation of using nir_vectorize_tess_levels is that it works
on variables, and so isn't able to combine outer/inner writes that
happen to live in the same vec4 slot (for triangle domains). That
said, it's still better than before.
For writes, we allow the intrinsics to supply up to the full size
of the variable (vec4 for outer, vec2 for inner) even if the domain
only requires a subset of those components (i.e. triangles needs 3).
shader-db results on Icelake:
total instructions in shared programs:
19605070 ->
19602284 (-0.01%)
instructions in affected programs: 65338 -> 62552 (-4.26%)
helped: 271 / HURT: 0
helped stats (abs) min: 6 max: 24 x̄: 10.28 x̃: 12
helped stats (rel) min: 1.30% max: 18.18% x̄: 5.80% x̃: 7.59%
95% mean confidence interval for instructions value: -10.71 -9.85
95% mean confidence interval for instructions %-change: -6.17% -5.43%
Instructions are helped.
total cycles in shared programs:
851854659 ->
851820320 (<.01%)
cycles in affected programs: 618749 -> 584410 (-5.55%)
helped: 271 / HURT: 0
helped stats (abs) min: 69 max: 540 x̄: 126.71 x̃: 108
helped stats (rel) min: 2.57% max: 37.97% x̄: 6.17% x̃: 5.06%
95% mean confidence interval for cycles value: -135.89 -117.54
95% mean confidence interval for cycles %-change: -6.72% -5.63%
Cycles are helped.
total sends in shared programs: 1025285 -> 1024355 (-0.09%)
sends in affected programs: 6454 -> 5524 (-14.41%)
helped: 271 / HURT: 0
helped stats (abs) min: 2 max: 8 x̄: 3.43 x̃: 4
helped stats (rel) min: 5.71% max: 25.00% x̄: 14.98% x̃: 17.39%
95% mean confidence interval for sends value: -3.57 -3.29
95% mean confidence interval for sends %-change: -15.42% -14.54%
Sends are helped.
According to Felix DeGrood, this results in a 10% improvement in
the draw call time for certain draw calls from Strange Brigade.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17944>
Kenneth Graunke [Thu, 4 Aug 2022 03:37:20 +0000 (20:37 -0700)]
st/mesa: Optionally call nir_vectorize_tess_levels()
This lets us vectorize gl_TessLevel{Inner,Outer} writes, using a pass
developed for RADV. Not all backends are prepared to handle this, so
we make it optional.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17944>
Kenneth Graunke [Thu, 4 Aug 2022 03:54:52 +0000 (20:54 -0700)]
intel/compiler: Use an existing URB write to end TCS threads when viable
VS, TCS, TES, and GS threads must end with a URB write message with the
EOT (end of thread) bit set. For VS and TES, we shadow output variables
with temporaries and perform all stores at the end of the shader, giving
us an existing message to do the EOT.
In tessellation control shaders, we don't defer output stores until the
end of the thread like we do for vertex or evaluation shaders. We just
process store_output and store_per_vertex_output intrinsics where they
occur, which may be in control flow. So we can't guarantee that there's
a URB write being at the end of the shader.
Traditionally, we've just emitted a separate URB write to finish TCS
threads, doing a writemasked write to an single patch header DWord.
On Broadwell, we need to set a "TR DS Cache Disable" bit, so this is
a convenient spot to do so. But on other platforms, there's no such
field, and this write is purely wasteful.
Insetad of emitting a separate write, we can just look for an existing
URB write at the end of the program and tag that with EOT, if possible.
We already had code to do this for geometry shaders, so just lift it
into a helper function and reuse it.
No changes in shader-db.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17944>
Lionel Landwerlin [Fri, 23 Sep 2022 14:21:27 +0000 (17:21 +0300)]
ci: disable intel-clc on debian-vulkan
We're getting a number of UBSan error while running intel-clc in that
image. It seems that we're the first ones to run into a number of code
paths with intel-clc and it shows a number of undefined behavior
operations like signed extension stuff in NIR/IntelBackend, unaligned
pointer accesses in embedded list iterators, etc...
Preparing some patches in a different MR to fix this.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18788>
Lionel Landwerlin [Fri, 23 Sep 2022 10:35:40 +0000 (13:35 +0300)]
ci: bump llvm to 13 for some builders
Namely :
- debian-clang
- debian-cl
- debian-vulkan
Seems to trigger/fix failures on llvmpipe, filed
https://gitlab.freedesktop.org/mesa/mesa/-/issues/7336
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18788>
Lionel Landwerlin [Thu, 22 Sep 2022 21:45:55 +0000 (00:45 +0300)]
ci/debian: don't use libclc from the system
Debian (unlike Ubuntu) has a broken libclc package missing files we
would very much like to have in our image, so that intel_clc doesn't
fail. Namely :
/usr/lib/clc/spirv-mesa3d-.spv
/usr/lib/clc/spirv64-mesa3d-.spv
Dropping libclc from the distribution and build int the build & base
test image.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18788>
Lionel Landwerlin [Thu, 22 Sep 2022 15:56:45 +0000 (18:56 +0300)]
ci: build our own version of the LLVM SPIRV translator
Debian stable and Fedora do not package the required version for
intel-clc.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18788>
Lionel Landwerlin [Thu, 22 Sep 2022 10:13:42 +0000 (13:13 +0300)]
ci: disable intel-clc on fedora
Would require Fedora 35.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18788>
Lionel Landwerlin [Thu, 22 Sep 2022 09:26:05 +0000 (12:26 +0300)]
ci: add python3-ply to debian/fedora images
This is needed by Anv to parse GRL (meta opencl kernels).
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18788>
Dave Airlie [Tue, 27 Sep 2022 05:26:42 +0000 (15:26 +1000)]
gallivm/nir: bitcast when non-float ptr type.
This matters more when opaque pointers are used.
Fixes:
203920d4c693 ("gallivm: add atomic 32-bit float support")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18835>
Dave Airlie [Mon, 26 Sep 2022 19:17:39 +0000 (05:17 +1000)]
gallivm/nir: fix fmin/fmax translation
Fixes:
203920d4c693 ("gallivm: add atomic 32-bit float support")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18835>
Dave Airlie [Mon, 26 Sep 2022 19:15:26 +0000 (05:15 +1000)]
lavapipe: add fmin/fmax to image lowering.
Fixes:
31695f81c925 ("lavapipe: export VK_KHR_shader_atomic_float")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18835>
Mike Blumenkrantz [Wed, 21 Sep 2022 16:21:28 +0000 (12:21 -0400)]
zink: also lower 64bit function temps
now that these aren't always lowered from indirects,
64bit function temp arrays may exist in shaders, and they need to use
all the same rewrite machinery
fixes #7310
SoroushIMG <soroush.kashani@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18728>
Mike Blumenkrantz [Wed, 21 Sep 2022 16:20:56 +0000 (12:20 -0400)]
zink: split up lower_64bit_vars pass
the component functions will be reused; no functional changes
SoroushIMG <soroush.kashani@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18728>
Mike Blumenkrantz [Wed, 21 Sep 2022 16:19:24 +0000 (12:19 -0400)]
zink: always run optimize_nir after lower_64bit_vars
it's otherwise possible (and likely) that optimizations won't
happen since there's no shader key data active
Fixes:
5b2f850425e ("zink: rewrite 64bit shader i/o as 32bit")
SoroushIMG <soroush.kashani@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18728>
Mike Blumenkrantz [Wed, 21 Sep 2022 16:18:26 +0000 (12:18 -0400)]
zink: don't flatten 64bit arrays during rewrite
dunno what I was thinking here
Fixes:
5b2f850425e ("zink: rewrite 64bit shader i/o as 32bit")
SoroushIMG <soroush.kashani@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18728>
Mike Blumenkrantz [Wed, 21 Sep 2022 13:49:11 +0000 (09:49 -0400)]
nir/opt_undef: add a pass to clean up 64bit undefs
somehow 64bit lowering creates patterns like
vec1 64 ssa_1 = undefined
ssa_2 = unpack_64_2x32_split_x ssa_1
and then the 64bit value is never otherwise used. for this case, rewriting
the unpack to just be a 32bit undef allows the 64bit undef to be optimized
out, avoiding spec violations
fixes #6945
SoroushIMG <soroush.kashani@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18728>
Karol Herbst [Sun, 25 Sep 2022 11:43:13 +0000 (13:43 +0200)]
rusticl/device: fix custom device detection
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18809>
Mike Blumenkrantz [Thu, 22 Sep 2022 17:27:14 +0000 (13:27 -0400)]
zink: always set VK_PIPELINE_CREATE_COLOR_ATTACHMENT_FEEDBACK_LOOP_BIT_EXT sometimes
some drivers (mostly desktop) are known to ignore this pipeline flag,
thus it can be set unconditionally in pipeline state to deduplicate
pipeline variants without affecting performance
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18787>
Mike Blumenkrantz [Thu, 22 Sep 2022 17:02:17 +0000 (13:02 -0400)]
zink: use feedback loop layout to correctly handle implicit feedback loops
an implicit feedback loop occurs when an app happens to bind the same image
as both a framebuffer attachment and a sampler for the same draw
an explicit feedback loop occurs when an app uses fbfetch to read data back
from the framebuffer using input attachments
fbfetch is already handled, but implicit feedback loops require more work:
* detecting them happens on-the-fly
* pipeline variants are required
this handles implicit feedback loops by detecting them at draw time during
barrier updates and then flagging pipeline state change to trigger variant creation.
the bits are then unset when the framebuffer/sampler binds are removed
fixes #7309
fixes (tu):
KHR-GL46.texture_barrier.disjoint-texels
KHR-GL46.texture_barrier.overlapping-texels
KHR-GL46.texture_barrier.same-texel-rw-multipass
KHR-GL46.texture_barrier_ARB.disjoint-texels
KHR-GL46.texture_barrier_ARB.overlapping-texels
KHR-GL46.texture_barrier_ARB.same-texel-rw-multipass
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18787>
Mike Blumenkrantz [Thu, 22 Sep 2022 15:33:20 +0000 (11:33 -0400)]
zink: add a mask of fb attachment idx for resources
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18787>
Mike Blumenkrantz [Thu, 22 Sep 2022 15:31:09 +0000 (11:31 -0400)]
zink: reorder zink_resource a little
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18787>
Mike Blumenkrantz [Thu, 22 Sep 2022 15:28:51 +0000 (11:28 -0400)]
zink: rename fb_binds -> fb_bind_count
this is more accurate
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18787>
Mike Blumenkrantz [Thu, 22 Sep 2022 15:16:14 +0000 (11:16 -0400)]
zink: remove zink_context::new_swapchain
this was my (feeble) attempt at tracking validity for swapchain images,
but it doesn't actually work right, and zink_resource::valid is better
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18787>