nir/from_ssa: Make additional assumptions in coalescing

At this point, everything is SSA.  Also, NIR no longer allows different
numbers of components on the two sides of a phi so we can just assert
rather than trying to gracefully handle mismatches.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

nir: Produce intrinsics in lower_{phis,ssa_defs}_to_regs

A number of passes lower SSA partially to registers, do work that would be
invalid in SSA, and then go back into SSA with nir_lower_regs_to_ssa. As a step
towards replacing nir_register with intrinsics,
the nir_lower_{phis,ssa_defs}_to_regs passes are changed to produce intrinsics
instead of nir_registers, and their callers are updated to call
nir_lower_reg_intrinsics_to_ssa instead of nir_lower_regs_to_ssa to compensate.

Jointly authored with Faith.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

nir: Add a reg_intrinsics flag to nir_convert_from_ssa

It doesn't do anything yet. We leave that to the subsequent patches so we can
keep the tree-wide refactor as simple as possible.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

nir: Add new version of lower_regs_to_ssa

in the sense of operating on register intrinsics instead of nir_registers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

nir: Add legacy data structures & helpers

These are registerful versions of core nir_src/nir_dest which will become
SSA-only soon enough, and modifierful versions of nir_alu_src/nir_alu_dest.
The latter will let us remove modifiers from nir_alu_instr finally.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

nir: Add pass for trivializing register access

After running the pass, all register access intrinsics are guaranteed to be
"trivial" in the sense that the program is free of hazards preventing
propagating them away without inserting any copies.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

nir: Add helpers for walking register uses

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

nir: Add intrinsics for register access

Note the writemask handling is chosen for consistency with the rest of NIR. In
every other instance, writemask=w requires a vec4 source. This is hardcoded into
nir_validate and nir_print as what it means to have a writemask.

More importantly, consistency with how register writemasks currently work.
nir_print hides it, but r0.w = fneg ssa_1.x is actually a vec4 instruction with
source ssa_1.xxxx. As a silly example nir_dest_num_components(that) = 4 in the
old model. I realize this is quite strange coming from a scalar ISA, but it's
perfectly natural for the class of vec4 hardware for which this was designed. In
that hardware, conceptually all instructions are vec4`, so the sequence "fneg
ssa_1 and write to channel w" is implemented as "fneg a vec4 with ssa_1.x in the
last component and write that vec4 out but mask to write only the w channel".

Isn't this inefficient? It can be. To save power, Midgard has scalar ALUs in
addition to vec4 ALUs. Those details are confined to the backend VLIW scheduler;
the instruction selection is still done as vec4. This mechanism has little in
common with AMD's SALUs. Midgard has a wave size of 1, with special hacks for
derivatives.

As a result, all backends consuming register writemasks are expecting this
pattern of code. Changing the store to take a vec1 instead of a vec4 would
require changing every backend to reswizzle the sources to resurrect the vec4. I
started typing a branch to do this yesterday, but it made a mess of both Midgard
and nir-to-tgsi. Without any good reason to think it'd actually help
performance, I abandoned the idea. Getting all 15 backends converted to the
helpers is enough of a challenge without forcing 10 backends to reswizzle their
sources too.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>

ci: split farm rules out of test-source-dep.yml

That file has become a bit of the new `.gitlab-ci.yml` with just about
everything in there, but a lot of its content doesn't need to be in the
same file anymore now that `!reference` exists.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24090>

llvmpipe/linear: don't allow linear path for shader output with location frac

This has been broken for a while, but we weren't hitting the linear paths in CI

This fixes:
tests/spec/arb_enhanced_layouts/execution/component-layout/fs-output.shader_test.

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24083>

ci: fix .valve-farm-manual-rules

28667995e4c3437868ee ("ci: create manual farm rules") was clearly written before
9a8a7aaf1d17c4586ca7 ("ci: split valve farm in two") and landed after but missed
this change when rebasing.

Fixes: 28667995e4c3437868ee ("ci: create manual farm rules")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24097>

nir/opt_dead_cf: Clarify comment

Make it obvious that the comment is about the block stitching behavior
of nir_cf_node_remove.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22064>

nir/opt_dead_cf: Run dead_cf_block while it makes progress

Previously, nir_opt_dead_cf could skip dead CF nodes because overwriting
cur after dead_cf_block is not enough to cover the whole CF list.
foreach_list_typed would select the next node, skipping the node that
previously made progress:

block 1
if (true) {}
block 2
if (true) {}
block 3
if (true) {}

Would turn into:

block 1, then, block 2
if (true) { }
block 3, then

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22064>

nir/lower_shader_calls: Remat derefs after shader calls

This avoids spilling deref instructions by wrapping shader calls inside
dummy blocks, rematerializing derefs in their use blocks and removing
the dummy blocks.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22064>

freedreno/drm/virtio: Trigger host side wait boost

Let the host know that we'll be waiting for a fence via an asynchronous
WAIT_FENCE command.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23955>

anv: fix utrace signaling with Xe

utrace submits can either have a batch or not.

When there is a batch, the utrace vk_sync is signaled by the utrace
batch (because utrace does a timestamp buffer copy using its own
batch). When there is no batch, the utrace vk_sync should be signaled
by the application batch (no timestamp copy required, utrace can read
the timestamps when the application batch has completed).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: fdea48df5e ("anv: Implement Xe version of anv_queue_exec_locked() and queue_exec_trace()")
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24085>

gallium: Remove `PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND`

Since the mesa state tracker can promote RGB texture formats
to RGBA texture formats (among other formats) without exposing
any of that information to a driver, it is more desirable to
have the behaviour of `PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND`
be the default. This avoids rendering bugs where an application
sets `DST_ALPHA` blending on a format where there is no alpha
channel, that has been promoted to a format that actually has an
alpha channel. The driver can instead rely on the common code
in the state tracker to convert the blending parameter to one
that reflects the limitations of the application requested format,
as long as `PIPE_CAP_INDEP_BLEND_FUNC` is supported.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24044>

tu: Fix zombie VMAs array not initialized when first BOs may be freed

First BOs were allocated before zombie_vmas was initialized so on
failure their clean up paths used uninitialized zombie_vmas.

Fixes
 dEQP-VK.api.device_init.create_instance_device_intentional_alloc_fail.basic
 dEQP-VK.api.object_management.alloc_callback_fail.device_group

See https://gitlab.freedesktop.org/mesa/mesa/-/issues/9247

Fixes: 63904240f21b192a5fb1e79046a2c351fbd98ace
("tu: Re-enable bufferDeviceAddressCaptureReplay")

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24086>

ci: set priority:low tag only on non-Marge pipelines

This allows dynamically setting the priority to avoid starving Marge.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23976>

ci: document workflow rules

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23976>

radeonsi/gfx11: fix a regression with PAIRS packets due to shader changes

When the vertex shader switches from hw GS to hw HS and vice versa, we need
to re-emit all draw user SGPRs.

Fixes: 1753b321f876 - radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for gfx by buffering reg writes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24087>

amd: Do shader binary alignment for prefetch at memory allocation time.

This makes it consistent between drivers and compilers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23799>

amd: move end-of-code marker padding to ACO.

This makes it consistent between drivers and compilers.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23799>

radeonsi: fix gfx9 regression causing GPU hangs

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Fixes: 283be8ac3b8610a77b2 - radeonsi: handle GE_CNTL and IA_MULTI_VGT_PARAM as a tracked register
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2651
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9249
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24082>

etnaviv: linker: clean up etna_link_shader(..)

There is no case that etna_link_shader(..) can fail now.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24030>

etnaviv: linker: handle scenario where there are FS inputs without matching VS output

If there is a FS input but no VS output the behavior is undefined
but okay. Use a register 0 (position) for such cases.

glsl-routing test triggers it with e.g. the following subtest.

Test: VS(C0 -- T0 -- T2 -- T4 T5)
      FS(C0 C1 T0 T1 T2 T3 T4 T5)

This will now end with following linker debug output:

link result:
  vs  -> fs  comps use     pa_attr
  t1  -> t1  xyzw  0,0,0,0 0x000002f1
  t2  -> t2  xyzw  0,0,0,0 0x000002f1
  t0  -> t3  xyzw  0,0,0,0 0x000002f1
  t3  -> t4  xyzw  0,0,0,0 0x000002f1
  t0  -> t5  xyzw  0,0,0,0 0x000002f1
  t4  -> t6  xyzw  0,0,0,0 0x000002f1
  t5  -> t7  xyzw  0,0,0,0 0x000002f1

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24030>

ci/freedreno: another batch of a530 flakes

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24081>

docs: Add inital PowerVR driver documentation

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8048
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23992>

radv: migrate radv_shader hash to BLAKE3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23974>

radv/meta: disable disk cache for meta shaders

Meta shaders are already stored in a separate cache file,
inserting them into the disk cache is unnecessary.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23909>

vulkan/pipeline_cache: add 'skip_disk_cache' option

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23909>

aco/assembler: change prefetch mode on GFX10.3+ during loops if beneficial

Totals from 8864 (6.68% of 132726) affected shaders: GFX11

CodeSize: 90776128 -> 90923760 (+0.16%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23748>

aco/assembler: align loops if it reduces the number of cache lines

This is especially beneficial on GFX6-9.

Totals from 11229 (8.46% of 132726) affected shaders: GFX11

CodeSize: 109608640 -> 109840916 (+0.21%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23748>

aco/assembler: align resume shaders with cache lines

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23748>

aux/trace: fix (u)int dump

The PRI* macros don't include the required introductory % character

Fixes: d29bb6467e2 ("aux/trace: use stdint.h types")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24057>

zink: drop linear D32_SFLOAT_S8_UINT requirement

Very likely a typo. Afaict radv/anv don't support this.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24078>

virgl/video: Fix out-of-bounds access in fill_mpeg4_picture_desc()

An out-of-bounds access has occurred to array ref[2] and it needs
to be fixed.

Fixes: 6b5aecb19558 ("virgl: add support for hardware video acceleration")
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23160>

zink: fix batch disambiguation on first submit

submit_count is used to disambiguate a batch_id based on the generation
id of a given batch: this value is incremented once on submit and once on
reset such that the diff of the values is > 1 any time the batch does not
represent the fence it was last submitted with

in the case of a batch's first use, however, this value was being incorrectly
incremented such that the first submit would cause disambiguation checks
to erroneously determine that the batch had already completed, breaking synchronization

fixes #9313

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24016>

zink: update profile vulkan version requirements

Pretty much all the profiles references Vulkan 1.2 or 1.3 only
structures but only say they need a 1.0.X version.

This fails parsing of the Vulkan Profile scripts for generating
implementation checks against a particular profile.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24072>

radeonsi/vcn: Remove unnecessary type conversion

The types of both 'encrypted' and 'picture->protected_playback'
are bool, so there is no need. I guess this is a typo.

Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23202>

frontends/va: Fix memory leak of decrypt_key

pipe_picture_desc.decrypt_key was alloced in function
handleVAProtectedSliceDataBufferType(), but nowhere to
free it. Now, it will be freed as the vlVaContext is
destroyed.

Fixes: deb7dc82f62 ("frontends/va: handle protected slice data buffer")
Signed-off-by: Feng Jiang <jiangfeng@kylinos.cn>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23202>

gallium/va: fix superres av1 decoding.

On a superres sample, vulkan was decoding fine, but vaapi failed,
fix the micols calculations.

Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23715>

ci/zink+radv: fix flake definition

Fixes: 741bfb52e674950e7731 ("zink/ci: add more tests to the flake list of vangogh")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24068>

ci/traces: switch from xvfb to Weston XWayland

 - Drop now unused RUN_CMD_WRAPPER.
 - Copy-paste Weston initiation code from init-stage2.sh with slightly adjustments.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24056>

ci/container: we need to keep the wine inside

Needed for testing with wine apitrace.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24056>

ci/container: add weston into Vulkan container

Reviewed-by: Daniel Stone <daniels@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24056>

nir: Remove nir_builder_init, it's not used anymore

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038>

treewide: remove unused nir_builder

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038>

treewide: Remove all usage of nir_builder_init with nir_builder_create and nir_builder_at

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24038>

docs: update etnaviv extensions

I went through the list and updated the extensions that are supported
and passing (most) of the piglit's and deqp's.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24032>

radv/rt: Miss rays that hit the triangle's v edge

The hardware seems to do this as well. Avoids invoking hit shaders twice
at shared edges.
Fixes the fails in watertightness tests on emulated RT.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24063>

radv/rt: Enable exact on software intersection functions

These functions need exact output, otherwise watertightness can't be
guaranteed in some cases.

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24063>

iris: Drop depth cache flush requirement after depth clear/resolve

From Bspec 46959, a programming note applicable to Gfx12+:

   "Since HZ_OP has to be sent twice (first time set the clear/resolve
   state and 2nd time to clear the state), and HW internally flushes the
   depth cache on HZ_OP, there is no need to explicitly send a Depth
   Cache flush after Clear or Resolve."

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027>

anv: Drop depth cache flush requirement after depth clear/resolve

From Bspec 46959, a programming note applicable to Gfx12+:

   "Since HZ_OP has to be sent twice (first time set the clear/resolve
   state and 2nd time to clear the state), and HW internally flushes the
   depth cache on HZ_OP, there is no need to explicitly send a Depth
   Cache flush after Clear or Resolve."

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24027>

freedreno/ci: add KHR-GL46.buffer_storage.map_persistent_flush to flakes

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Suggested-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>

mesa/main: add PIPE_FORMAT_VYUY and PIPE_FORMAT_B8R8_G8R8

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>

mesa/main: add PIPE_FORMAT_YVYU and PIPE_FORMAT_R8B8_R8G8

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>

gallium/st: add support for PIPE_FORMAT_NV21 and PIPE_FORMAT_G8_B8R8_420

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>

nir: add options to lower y_vu, yv_yu, yx_xvxu and xy_vxux

`y_vu` will be used to convert NV21 to RGB.
`yv_yu` will be used to convert YVYU and VYUY to RGB when the
subsampling formats PIPE_FORMAT_R8B8_R8G8 and PIPE_FORMAT_B8R8_G8R8
are supported.
`yx_xvxu` and `xy_vxux` will be used to convert YVYU and VYUY to RGB
when those subsampling formats are not supported.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21219>

ci/freedreno: add execution@varying-struct-copy-return-vs flake

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24069>

ci/freedreno: add KHR-GL46.buffer_storage flakes

Both flakes occuring time to time on Adreno 6xx series.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24069>

d3d12/ci: add piglit arb_clear_texture-integer fail to CI expectations

Likely related to other ARB_texture_integer fails, instead of something
specific to ARB_clear_texture.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Acked-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

lima/ci: add some ARB_clear_texture piglit tests to lima-fails.txt

Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

gallium: remove PIPE_CAP_CLEAR_TEXTURE

ARB_clear_texture is now implemented in common code.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

gallium: cleanup util_blitter_clear_render_target

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

clover: use fallback path when pipe->clear_texture is not available

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

rusticl: use fallback path when pipe->clear_texture is not available

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

mesa/st: use fallback path when pipe->clear_texture is not available

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

gallium: rename util_clear_texture to util_clear_texture_sw

This better explain what this function does, making it less likely that
people mistakenly use it instead of util_default_clear_texture.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

gallium: use u_default_clear_texture where applicable

This removes some shared code between backends that implemented their
version of pipe->clear_texture without anything driver-specific code.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

gallium: implement u_default_clear_texture

util_clear_texture implements clear_texture through a memset.
This patch implements u_default_clear_texture, which tries to clear the
given texture using a surface plus clear_render_target or
clear_depth_stencil.

In case this path fails, either because the formats are non-renderable
or for some other reason, we fallback to `util_clear_texture`, which is
guaranteed to work.

This will allow us to make ARB_clear_texture available to every driver,
as well as provide HW acceleration for the clear_texture operation.

If some hardware doesn't want to use it, such as llvmpipe, it can always
just directly point to the software version using pipe->clear_texture.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

d3d12: fix clear_depth_stencil texture deref

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

vc4: implement clear_render_target and clear_depth_stencil

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

v3d: implement clear_render_target and clear_depth_stencil

Also added some related piglit failures to broadcom-rpi4-fails.txt.

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

freedreno: implement clear_render_target and clear_depth_stencil

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23735>

nir: do not needlessly rely on optimizations

We're going to do this rewrite once we get to nir_opt_algebraic anyway,
so let's save a little bit of needless work here.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24004>

radv: do not rely on constant-folding

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24004>

nir: use nir_intrinsic_get_var

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24004>

nir: constify intrin

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24004>

ci: Uprev virglrenderer

Enable the latest changes with vrend-video

Change the default branch of virglrenderer to main as upstream did

Signed-off-by: Corentin Noël <corentin.noel@collabora.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24067>

rogue: Remove commented convert_from_ssa call

Currently, the rogue compiler does not support control flow upstream.
Imagination's plan is to implement an SSA-based register allocation (I wish them
well in this endeavour). As such they won't be needing convert_from_ssa. remove
the commented call so nobody is tempted to put it back in. This takes care of
the rogue portion of #9051.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Simon Perretta <simon.perretta@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24015>

virgl: remove check of VIRGL_CAP_V2_UNTYPED_RESOURCE

Remove check of VIRGL_CAP_V2_UNTYPED_RESOURCE flag in
virgl_resource_from_handle() so that guest can still call
into virglrenderer to import external vulkan resource via
OpenGL APIs even if egl is not initialized.

Signed-off-by: Julia Zhang <julia.zhang@amd.com>
Signed-off-by: Huang Rui <ray.huang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23680>

glsl: do vs attribute validation in NIR linker

This allows us to tidy up the code and call the attribute location
code a single time rather than doing a "dry run".

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24035>

glsl: remove dead varyings before assigning attr locations

The GLSL IR code used to clean these up. Some apps such as the Heaven
benchmark fail linking if we don't eliminate them before the linker
validation.

Fixes: a8534c7b4cfc ("glsl: drop the dce of global vars from GLSL IR linker")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9319

Tested-by: Marcus Seyfarth <m.seyfarth@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24035>

panfrost: fix refcnt imbalance related to blitter

This issue is mainly a consequence of a call to util_blitter_clear()
with unnecessary blitter states, these states are never freed.

This change is inspired from radeonsi and r600.

Note: PAN_SAVE_FRAGMENT_STATE is added and always enabled
at this stage.

For instance, this issue is triggered on Mali-T720 with
"piglit/bin/fcc-read-after-clear sample tex -auto -fbo", "piglit/bin/cubemap -auto"
and "piglit/bin/fbo-srgb -auto" or on Mali-T820 with "piglit/bin/longprim -auto -fbo"
and "piglit/bin/ext_render_snorm-render -auto -fbo"
while setting GALLIUM_REFCNT_LOG=refcnt.log.

cc: mesa-stable

Signed-off-by: Patrick Lerda <patrick9876@free.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22522>

radeonsi/gfx11: only use SET_*_PAIRS* packets on dGPUs

They are not available on APUs.

This adds a new template parameter HAS_PAIRS. into draw functions.
Other places add back the non-pairs code for gfx11.

Fixes: 22f3bcfb - radeonsi/gfx11: use SET_*_REG_PAIRS_PACKED packets for pm4 states
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9259

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24010>

wgl: Fix depth/stencil image support when using zink kopper

Kopper requires that any depth/stencil images are created through winsys which
was not taken into account by the WGL frontend causing it to hit an assert:
'Assertion failed: ctx->fb_state.zsbuf->texture->bind & PIPE_BIND_DISPLAY_TARGET'

fixes #9256
cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24055>

ci/zink+radv: document another flake

https://gitlab.freedesktop.org/mesa/mesa/-/jobs/45129393

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24053>

Revert "Revert "radv: Enable ray tracing pipelines by default""

This reverts commit 49b400423ce2ac3f0d868a38a51bcd9d02cccd1b.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23978>

Revert "radv/rt: Enable RT pipelines on GFX10_3+ excluding vangogh"

This reverts commit 7f3874981dd11821a4001671b5ee505868f9aa7d.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23978>

radv/ci: Skip ray tracing tests on vangogh

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23978>

ci/freedreno: document number of a630 devices available

Acked-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24050>

ci/freedreno: re-enable a530 as it's now stable with multiple skips

Extend a530 skips and flakes to make possible test again.

Acked-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24050>

ci/freedreno: switch a630_{piglit,skqp} and a618_gl to Weston

Slightly faster runtime.

Acked-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24050>

add initial .git-blame-ignore-revs

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24049>

clang-format: enforce formatting of egl

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23398>

egl: re-format using clang-format

No manual changes here, this is simply running
$ ninja -C build/ clang-format

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23398>

egl: prevent clang-format from reordering some headers

vulkan_xcb.h is missing an include of xcb.h, breaking the build if the headers are ordered alphabetically.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23398>

egl: protect the formatting in a couple of places

These do no follow the normal rules, but it's done on purpose because
it's easier to read like this.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23398>

egl: add a few trailing commas

This prevents clang-format from collapsing the closing brace into the
previous line.

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23398>