Nicolai Hähnle [Thu, 5 Oct 2017 17:25:48 +0000 (19:25 +0200)]
st/mesa: don't assign prog->ShadowSamplers
It's not used, and the assignment for the TGSI case was incorrect
for sampler arrays.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 5 Oct 2017 17:39:33 +0000 (19:39 +0200)]
st/glsl_to_tgsi: ignore GL_TEXTURE_SRGB_DECODE_EXT for samplers used with texelFetch*()
See the comment for the relevant spec quote.
Fixes dEQP-GLES31.functional.srgb_texture_decode.skip_decode.srgba8.texel_fetch
v2: note the interaction between ARB_bindless_texture and EXT_texture_sRGB_decode
as a TODO
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Thu, 5 Oct 2017 12:08:04 +0000 (14:08 +0200)]
st/mesa: store state that affects sampler views per context
This fixes sequences like:
1. Context 1 samples from texture with sRGB decode enabled
2. Context 2 samples from texture with sRGB decode disabled
3. Context 1 samples from texture with sRGB decode disabled
Previously, step 3 would see the prev_sRGBDecode value from context 2
and would incorrectly use the old sampler view with sRGB decode enabled.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tim Rowley [Tue, 10 Oct 2017 16:08:29 +0000 (11:08 -0500)]
swr: simd16 shaders work in progress
Start building vertex shaders as simd16.
Disabled by default, set USE_SIMD16_SHADERS in knobs.h to experiment.
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tim Rowley [Tue, 10 Oct 2017 16:07:11 +0000 (11:07 -0500)]
gallium: allow 512-bit vectors
Increase the max allowed vector size from 256 to 512.
No piglit llvmpipe regressions running on avx2.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kenneth Graunke [Tue, 10 Oct 2017 17:19:21 +0000 (10:19 -0700)]
i965: Drop brw_bo_alloc in ARB_indirect_parameters implementation.
The original implementation allocated a new BO here, but we decided to
switch to intel_upload_space, which returns a reference to the current
upload BO. We accidentally kept the brw_bo_alloc, even though it's no
longer necessary - intel_upload_space will immediately unreference it,
causing us to allocate and immediately free a buffer.
Reviewed-by: Plamena Manolova <plamena.manolova@intel.com>
Kenneth Graunke [Sun, 30 Jul 2017 23:15:56 +0000 (16:15 -0700)]
i965: Allow mapped VBOs during drawing in non-debug contexts.
Section 6.3.2 of the GL 4.5 spec says:
"Any GL command which attempts to read from, write to, or change
the state of a buffer object may generate an INVALID_OPERATION error
if all or part of the buffer object is mapped ... However, only
commands which explicitly describe this error are required to do so.
If an error is not generated, such commands will have undefined
results and may result in GL interruption or termination."
Setting this flag allows us to skip walking over the buffer bindings
for every enabled vertex attribute (_mesa_all_buffers_are_unmapped).
Improves performance in GFXBench4's gl_driver2_off microbenchmark by
3.05797% +/- 0.709031% (n=33) on Apollolake.
This breaks KHR-*.draw_elements_base_vertex_tests.invalid_mapped_bos,
but that test is invalid and has been removed from the upstream CTS.
Reviewed-by: Eric Anholt <eric@anholt.net>
Dylan Baker [Tue, 10 Oct 2017 21:50:53 +0000 (14:50 -0700)]
meson: fix glx test
That requires a generated header that was rolled into a loop.
fixes:
a47c525f3281a27 ("meson: build glx")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Ilia Mirkin [Wed, 11 Oct 2017 03:50:06 +0000 (23:50 -0400)]
nv50,nvc0: fix push hint logic in presence of a start offset
Previously buffer offsets were passed in explicitly as an offset, which
had to be added to the resource address. Now they are passed in via an
increased 'start' parameter. As a result, we were double-adding the
start offset in this kind of situation.
This condition was triggered by piglit's draw-elements test which has a
requisite glMultiDrawElements in combination with a small enough number
of vertices to go through the immediate push path.
Fixes:
330d0607ed6 ("gallium: remove pipe_index_buffer and set_index_buffer")
Reported-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Sat, 9 Sep 2017 07:18:39 +0000 (00:18 -0700)]
i965: Make brw_update_texture_surface static.
Trivial. It's not used in other files.
Rob Herring [Tue, 10 Oct 2017 22:01:29 +0000 (17:01 -0500)]
Android: fix build break from r600/radeon split
Commit
06bfb2d28f7a ("r600: fork and import gallium/radeon") broke the
Android build:
external/mesa3d/src/gallium/drivers/radeon/r600_pipe_common.c:43:10: fatal error: 'llvm-c/TargetMachine.h' file not found
^~~~~~~~~~~~~~~~~~~~~~~~
Update the Android makefiles so that drivers/radeon is only built when
radeonsi (and therefore LLVM) is enabled.
Fixes:
06bfb2d28f7a (r600: fork and import gallium/radeon)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Rob Herring [Fri, 15 Sep 2017 13:50:09 +0000 (08:50 -0500)]
Android: move libraries to /vendor
As part of Treble project in Android O, all the device specific files have
to be located in a separate vendor partition. This is done by setting
LOCAL_PROPRIETARY_MODULE (the name is misleading). This change will not
break existing platforms without a vendor partition as it will just move
files to /system/vendor.
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Rob Herring <robh@kernel.org>
Kenneth Graunke [Tue, 10 Oct 2017 08:02:44 +0000 (01:02 -0700)]
i965: Fix output register sizes when multiple variables share a slot.
ARB_enhanced_layouts allows multiple output variables to share the same
location - and these variables may not have the same sizes. For
example, consider these output variables:
// consume X/Y/Z components of 6 vectors
layout(location = 0) out vec3 a[6];
// consumes W component of the first vector
layout(location = 0, component = 3) out float b;
Looking at the first declaration, we see that VARYING_SLOT_VAR0 needs 24
components worth of space (vec3 padded out to a vec4, 4 * 6 = 24). But
looking at the second declaration, we would think that VARYING_SLOT_VAR0
needs only 4 components of space (a single float padded out to a vec4).
nir_setup_outputs() only considered the space requirements of the first
declaration it happened to see, so if 'float b' came first, it would
underallocate the output register space, causing brw_fs_validator.cpp
to assert fail about inst->dst.offset exceeding the register size.
Fixes Piglit's tests/spec/arb_enhanced_layouts/execution/component-layout/
vs-to-fs-array-interleave-single-location.shader_test.
Thanks to Tim Arceri for finding this bug and writing a test!
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Dave Airlie [Tue, 10 Oct 2017 23:48:21 +0000 (09:48 +1000)]
nir: bump loop unroll limit to 96.
With the ssao demo from Vulkan demos:
radv/rx480: 440->440fps
anv/haswell: 24->34 fps
The demo does a 0->32 loop across a ubo with 32 members.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 10 Oct 2017 23:45:44 +0000 (09:45 +1000)]
anv: fix assert in wsi image code.
This assert was firing just running demos.
Jason said it should be this.
Fixes:
6c7720ed78 (anv/wsi: Allocate enough memory for the entire image)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 15 Sep 2017 03:14:56 +0000 (13:14 +1000)]
mesa/st: fix atomic buffer sizing to align with ssbo.
This respects the size from the range setting like ssbo.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 15 Sep 2017 03:13:20 +0000 (13:13 +1000)]
mesa/bufferobj: consolidate some buffer binding code.
These paths are again 90% the same, consolidate them into
one.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 15 Sep 2017 02:55:50 +0000 (12:55 +1000)]
mesa/bufferobj: consolidate some codepaths between ubo/ssbo/atomics.
These are 90% the same code, consolidate them into a couple of
common codepaths.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 15 Sep 2017 02:43:55 +0000 (12:43 +1000)]
mesa: rename various buffer bindings to one struct.
One binding to bind them all, these are all the same thing.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 15 Sep 2017 02:38:18 +0000 (12:38 +1000)]
mesa: align atomic buffer handling code with ubo/ssbo (v1.1)
this adds automatic size support to the atomic buffer code,
but also realigns the code to act like the ubo/ssbo code.
v1.1:
add missing blank lines.
reindent one block properly.
check for NullBufferObj.
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Sat, 7 Oct 2017 07:14:34 +0000 (00:14 -0700)]
i965: Don't try to decode types for non-existent src1.
KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks has a MOV that hits
this validation path. MOVs don't have a src1 file, but calling
brw_inst_src1_type() was tripping on src1.file being BRW_IMMEDIATE_VALUE
and the hw_type being something invalid for immediates.
To work around this, just pretend src1 is src0 if there isn't a src1.
Fixes:
2572c2771d0cab0b9bc489d354ede44dfc88547b (i965: Validate "Special
Requirements for Handling Double Precision Data Types")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102680
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Karol Herbst [Wed, 16 Aug 2017 18:32:42 +0000 (20:32 +0200)]
main/format: skip format conversion if src and dst format are equal
Fixes 'KHR-GL45.copy_image.functional' on Nouveau and i965.
v2: (by Kenneth Graunke)
Rewrite patch according to Jason Ekstrand's review feedback.
This makes it handle differing strides, which i965 needed.
Signed-off-by: Karol Herbst <karolherbst@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Jason Ekstrand [Sat, 7 Oct 2017 04:11:59 +0000 (21:11 -0700)]
mesa: Make _mesa_get_format_bytes handle array formats.
This is easier than making callers handle a bunch of special cases.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bas Nieuwenhuizen [Sun, 8 Oct 2017 19:58:23 +0000 (21:58 +0200)]
radv: Only set the MTYPE flags on GFX9+.
Older kernels fail the va_op with this flag set. If the kernel
supports GFX9 usefully, it will also support this flag.
Fixes:
e8d57802fea "radv/gfx9: allocate events from uncached VA space"
Reviewed-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Fri, 6 Oct 2017 03:31:01 +0000 (20:31 -0700)]
i965: Disable auxiliary buffers when there are self-dependencies.
Jason and I investigated several OpenGL CTS failures where the tests
bind the same texture for rendering and texturing, at the same time.
This has defined results as long as the reads happen before writes,
or the regions are non-overlapping. Normally, this just works out.
However, CCS can cause problems. If the shader is reading one set of
pixels, and writing to different pixels that are adjacent, they may end
up being covered by the same CCS block. So rendering may be writing a
CCS block, while the sampler is trying to read it. Corruption ensues.
Disabling CCS is unfortunate, but safe.
Fixes several KHR-GL45.texture_barrier.* subtests.
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Dave Airlie [Mon, 9 Oct 2017 20:27:40 +0000 (06:27 +1000)]
r600: cleanup llvm ir target selection.
Only r600 target used now for compute IR.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Mon, 9 Oct 2017 20:27:10 +0000 (06:27 +1000)]
r600: drop tc_L2_dirty bit, this was SI only.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 10 Oct 2017 03:23:40 +0000 (13:23 +1000)]
radeonsi: lower ffma in nir to mad.
This lowers ffma to a * b + c.
This seems like it should keep Marek happiest, so
we'd never get to the fma instruction emission code.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 3 Oct 2017 20:33:02 +0000 (06:33 +1000)]
radv: lower ffma in nir.
So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
mad operation, and the fma hw opcode on AMD hw is issued like a double
opcode so is slower. Also the radeonsi stack does this.
This appears to improve performance on a number of games from Feral,
and thanks to Feral for noticing the problem.
I'm reposting this one as Marek indicated he thinks this is what
we should be doing on AMD hw.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Alex Smith [Tue, 10 Oct 2017 16:00:09 +0000 (17:00 +0100)]
radv: Add R16G16B16A16_SNORM fast clear support
Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Eric Anholt [Tue, 10 Oct 2017 18:19:23 +0000 (11:19 -0700)]
broadcom/vc5: Fix handling of 5551 textures using the new gallium format.
Like vc4, we have the alpha in the low bit. Fixes a bunch of piglit
texwrap failures.
Eric Anholt [Fri, 6 Oct 2017 00:18:34 +0000 (17:18 -0700)]
broadcom/vc5: Set the RCL's MSAA mode to match the BCL's MSAA state.
Eric Anholt [Thu, 5 Oct 2017 22:50:59 +0000 (15:50 -0700)]
braodcom/vc5: Set up clear color for higher-bpp formats.
Fixes arb_color_buffer_float-clear
Eric Anholt [Thu, 5 Oct 2017 22:40:18 +0000 (15:40 -0700)]
broadcom/vc5: Set up per-MRT clear colors.
Fixes fbo-mrt-alphatest.
Eric Anholt [Thu, 5 Oct 2017 22:19:49 +0000 (15:19 -0700)]
broadcom/vc5: Fix blendfactor zero handling.
I cut the line out to move it up to the top, when putting "0" in the
switch made the compiler complain that that wasn't a valid enum.
Eric Anholt [Wed, 4 Oct 2017 23:42:55 +0000 (16:42 -0700)]
broadcom/vc5: Fix Rendering Mode Common Config's color store bitmask.
This controls the RTs that get stored by the default resolved store, the
same way that the extended resolved store packet has a RT bitmask.
Eric Anholt [Tue, 3 Oct 2017 00:21:23 +0000 (17:21 -0700)]
broadcom/vc5: Add support for f32 render targets.
The TLB write code is getting ugly and needs a refactoring (that will
hopefully handle TLBU uniform coalescing as well).
Eric Anholt [Tue, 3 Oct 2017 00:05:24 +0000 (17:05 -0700)]
broadcom/vc5: Fix color masks for non-independent blending.
This gets fbo-mrt-alphatest working except for the second RT's clear color.
Eric Anholt [Mon, 2 Oct 2017 23:55:04 +0000 (16:55 -0700)]
broadcom/vc5: Make the BCL's number of render targets setup match the RCL.
Eric Anholt [Mon, 2 Oct 2017 23:54:09 +0000 (16:54 -0700)]
braodcom/vc5: Fix tile size setup for MRTs.
We need to divide the TLB in two for the 2nd color buffer, and again if
the 3rd or 4th are present.
Eric Anholt [Mon, 2 Oct 2017 23:43:33 +0000 (16:43 -0700)]
broadcom/vc5: Start hooking up multiple render targets support.
We now emit as many TLB color writes as there are color buffers.
Eric Anholt [Mon, 2 Oct 2017 21:09:56 +0000 (14:09 -0700)]
broadcom/vc5: Add support for GL_EXT_provoking_vertex.
The bit was missing from the spec, but it's there in the simulator. Fixes
the piglit clipflat test.
Eric Anholt [Mon, 2 Oct 2017 19:20:35 +0000 (12:20 -0700)]
braodcom/vc5: Find the actual first TF output for our TF spec.
This doesn't yet support PSIZ, but gets us at least some of TF working.
Eric Anholt [Mon, 2 Oct 2017 20:02:32 +0000 (13:02 -0700)]
broadcom/vc5: Fix translation of transform feedback's output_register field.
It's a NIR driver_location, not a slot offset.
Eric Anholt [Mon, 2 Oct 2017 19:17:30 +0000 (12:17 -0700)]
broadcom/vc5: Mark our primitives as needing TF processing.
The TF enable state appears to stick around until the next TF enable
packet is sent, so we only want to request TF when the shader is using it.
Eric Anholt [Mon, 2 Oct 2017 19:05:30 +0000 (12:05 -0700)]
broadcom/vc5: Fix setup of TF dword output count.
I missed the "- 1" when reading the spec.
Eric Anholt [Mon, 2 Oct 2017 18:41:57 +0000 (11:41 -0700)]
broadcom/vc5: Fix up a comment from vc4 about the predraw texture setup.
Eric Anholt [Sat, 30 Sep 2017 23:48:44 +0000 (16:48 -0700)]
broadcom/vc5: Flush the job when mapping a transform feedback buffer.
We will want something fancier for reusing a TF output within the same
frame, but we at least need this in order for piglit tests to work.
Eric Anholt [Thu, 28 Sep 2017 21:02:05 +0000 (14:02 -0700)]
broadcom/vc5: Fix handling of interp qualifiers on builtin color inputs.
The interpolation qualifier, if specified, is supposed to take precedence
over glShadeModel().
Eric Anholt [Thu, 28 Sep 2017 20:36:54 +0000 (13:36 -0700)]
broadcom/vc5: Fix CLIF dumping of lists that aren't capped by a HALT.
The HW will halt when you hit a HALT packet, or when you hit the end
address. Tell CLIF if there's an end address is so that it can stop
correctly. (There was usually a 0 byte after the CL, so it would stop
anyway).
Eric Anholt [Thu, 28 Sep 2017 18:41:31 +0000 (11:41 -0700)]
broadcom/vc5: Fix depth and stencil clear values.
I had misread the packet description: We always have a 32f depth, and a
separate u8 stencil.
Eric Anholt [Thu, 28 Sep 2017 18:47:50 +0000 (11:47 -0700)]
broadcom/vc5: Add missing Z16 format.
We can render to and sample from it just fine.
Eric Anholt [Thu, 28 Sep 2017 17:39:07 +0000 (10:39 -0700)]
braodcom/vc5: Fix incorrect early Z writes in discard shaders.
Fixes glsl-fs-discard-02.
Eric Anholt [Thu, 28 Sep 2017 17:37:02 +0000 (10:37 -0700)]
broadcom/compiler: Set up passthrough Z when doing FS discards.
In order to keep early-Z from writing early in a discard shader, you need
to set the "modifies Z" bit in the shader state (which the new
prog_data.discards will indicate). Then, in the shader we do a TLB write
to make Z passthrough happen (the QPU result is ignored, so we use a NULL
source).
Eric Anholt [Thu, 28 Sep 2017 18:06:53 +0000 (11:06 -0700)]
broadcom/compiler: Don't forget the discard state on TLB Z writes.
We don't want to write Z for discarded fragments.
Eric Anholt [Thu, 28 Sep 2017 17:56:47 +0000 (10:56 -0700)]
broadcom/compiler: Use defines instead of magic values in TLB write setup.
Eric Anholt [Wed, 27 Sep 2017 22:06:09 +0000 (15:06 -0700)]
broadcom/vc5: Add proper support for base_vertex and base_instance.
I had base_vertex hacked into the shader state setup like in vc4, but it's
not correct for big offsets. Using the proper packet is easier and
hopefully means we can re-emit shader state setup less frequently.
Eric Anholt [Wed, 27 Sep 2017 22:05:14 +0000 (15:05 -0700)]
broadcom/xml: Add the vc5 Base Vertex/Base Instance packet.
This lets us do index_bias and ARB_base_instance.
Eric Anholt [Wed, 27 Sep 2017 22:27:31 +0000 (15:27 -0700)]
broadcom/vc5: Use supertiles and generic tile lists.
This massively reduces the size of our RCL setup. It also gets us closer
to supporting multicore platforms.
Eric Anholt [Wed, 27 Sep 2017 21:51:05 +0000 (14:51 -0700)]
broadcom/xml: Add a bunch more vc5 tile list management packets.
We're going to need these for MSAA, and to use the generic per-tile list.
Eric Anholt [Wed, 27 Sep 2017 23:38:28 +0000 (16:38 -0700)]
broadcom/xml: Remove vc5 base packet for tile bin/render mode config.
These existed so I could unpack just the sub-id field to switch on in the
old manual CLIF dumper. The new codegen handles sub-id automatically, but
only if these stub packets aren't there with an implicit sub-id=0.
Eric Anholt [Wed, 27 Sep 2017 21:54:05 +0000 (14:54 -0700)]
braodcom/xml: Fix a pasteo in vc5 store tile buffer general.
Eric Anholt [Fri, 3 Feb 2017 00:24:13 +0000 (16:24 -0800)]
broadcom: Add V3D 3.3 gallium driver called "vc5", for BCM7268.
V3D 3.3 is a continuation of the 3D implementation in VC4 (v2.1 and v2.6).
V3D 3.3 introduces an MMU (no more CMA allocations) and support for
GLES3.1. This driver is not currently conformant, though that will be a
target as soon as possible.
V3D 3.x parts use a new texture tiling layout common across many Broadcom
graphics parts including and the HVS scanout engine. It also massively
changes the QPU instructions, introducing a common physical register file
(no more A/B split) and half-float instructions, while removing the 4x8
unorm instructions in favor of half-float for talking to fixed function
interfaces. Because so much has changed, vc5 is implemented in a separate
gallium driver, using only the XML code-generation support from vc4.
v2: Fix tile layout for 64bpp textures. Fix texture swizzling for 32-bit
returns. Fix up a bit of MRT setup. Sync the simulator to kernel
behavior a bit more. Improve uniform debugging code. Rebase on
QIR->VIR rename. Move texture state mostly to the CSOs. Improve
cache flushing on the simulator. Fix program deletion
use-after-frees.
Acked-by: Dave Airlie <airlied@gmail.com> (uabi plan)
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch> (uabi plan)
Eric Anholt [Fri, 3 Feb 2017 18:24:14 +0000 (10:24 -0800)]
broadcom: Add VC5 NIR compiler.
This is a pretty straightforward fork of VC4's NIR compiler to VC5. The
condition codes, registers, and I/O have all changed, making the backend
hard to share, though their heritage is still recognizable.
v2: Move to src/broadcom/compiler to match intel's layout, rename more
"vc5" to "v3d", rename QIR to VIR ("V3D IR") to avoid symbol conflicts
with vc4, use new v3d_debug header, add compiler init/free functions,
do texture swizzling in NIR to allow optimization.
Eric Anholt [Fri, 3 Feb 2017 00:25:12 +0000 (16:25 -0800)]
broadcom: Add vc5 CLIF dumping
This will be usable with "VC5_DEBUG=cl" on the vc5 driver to stream a CLIF
file (the Broadcom equivalent of i965's AUB) to stderr. I haven't tested
that this is actually usable with the internal CLIF-consuming tools, but
is close enough as a baseline and is useful for visually inspecting the
command stream.
Eric Anholt [Fri, 3 Feb 2017 00:15:18 +0000 (16:15 -0800)]
broadcom: Add V3D 3.3 QPU instruction pack, unpack, and disasm.
Unlike VC4, I've defined an unpacked instruction format with pack/unpack
functions to convert to 64-bit encoded instructions. This will let us
incrementally put together our instructions and validate them in a more
natural way than the QPU_GET_FIELD/QPU_SET_FIELD used to.
The pack/unpack unfortuantely are written by hand. While I could define
genxml for parts of it, there are many special cases (like operand order
of commutative binops choosing which binop is being performed!) and it
probably wouldn't come out much cleaner.
The disasm unit test ensures that we have the same assembly format as
Broadcom's internal tools, other than whitespace changes.
v2: Fix automake variable redefinition complaints, add test to .gitignore
Eric Anholt [Fri, 1 Sep 2017 21:38:54 +0000 (14:38 -0700)]
broadcom: Introduce a v3d_debug.h header for vc5 and broadcom Vulkan.
Unlike vc4, where the compiler and gallium driver live together, for vc5
the compiler will live up in the shared broadcom directory, and need
access to the debug flags. Define a set of debug flags and helpers there,
so it can be shared between compiler, vc5, and vulkan.
Eric Anholt [Fri, 18 Aug 2017 19:55:43 +0000 (12:55 -0700)]
configure: Add the new "vc5" driver to the list, requiring a simulator.
My intent is to develop the vc5 driver in-tree for some time to build the
CL generation and shader compiler code, and keep out-of-tree patches for
talking to an actual kernel driver until the kernel driver can be
stabilized on the hardware.
v2: Define a HAVE_BROADCOM_DRIVERS, like HAVE_INTEL or HAVE_AMD.
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Eric Anholt [Thu, 23 Feb 2017 00:53:18 +0000 (16:53 -0800)]
nir: Move vc4's alpha test lowering to core NIR.
I've been doing this inside of vc4, but vc5 wants it as well and it may be
useful for other drivers (Intel has a related path for pre-gen6 with MRT,
and freedreno had a TGSI path for it at one point).
This required defining a common enum for the standard comparison
functions, but other lowering passes are likely to also want that enum.
v2: Add to meson.build as well.
Acked-by: Rob Clark <robdclark@gmail.com>
Eric Anholt [Tue, 10 Oct 2017 18:41:29 +0000 (11:41 -0700)]
mesa: Alphabetize GL_MESA_tile_raster_order in the extensions list.
trivial, fixes make check.
Eric Anholt [Tue, 25 Jul 2017 23:13:57 +0000 (16:13 -0700)]
mesa: Implement a new GL_MESA_tile_raster_order extension.
The intent is to use this extension on vc4 to allow X11 to do overlapping
CopyArea() within a pixmap without first blitting the pixmap to a
temporary. With associated glamor patches, improves x11perf
-copywinwin100 performance on a Raspberry Pi 3 from ~4700/sec to
~5130/sec, and is an even larger boost to uncomposited window movement
performance (most copywinwin100 copies don't overlap).
v2: Fix glIsEnabled() on the new enums.
v3: Drop the local spec since I'm upstreaming the spec.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Thu, 27 Jul 2017 19:05:56 +0000 (12:05 -0700)]
broadcom/vc4: Expose PIPE_CAP_TILE_RASTER_ORDER
Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.
v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Split from the core gallium commit, drop some unnecessary code related
to glBlitFramebuffer(), fix a crash with clears before state has been
bound.
Eric Anholt [Thu, 27 Jul 2017 19:05:56 +0000 (12:05 -0700)]
gallium: Create a new PIPE_CAP_TILE_RASTER_ORDER for vc4.
Because vc4 can control the order that tiles are rasterized in, we can use
it to implement overlapping blits using normal drawing and
GL_ARB_texture_barrier, as long as we can tell the kernel what order to
render the tiles in.
This commit introduces the core gallium support, vc4 changes will follow.
v2: Fix on the simulator.
v3: Add the cap (disabled) to other drivers, add rst docs for the cap.
v4: Rebase on PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
v5: Drop vc4 changes from this commit, for clarity.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v3)
Eric Anholt [Thu, 5 Oct 2017 18:08:23 +0000 (11:08 -0700)]
broadcom/vc4: Implement GL_ARB_texture_barrier.
Improves x11perf -copywinwin100 from ~2000/sec to ~4700/sec. More
importantly, this is a prerequisite for the new GL_MESA_tile_raster_order
extension.
Eric Anholt [Wed, 26 Jul 2017 23:02:07 +0000 (16:02 -0700)]
docs: Update the list of used MESA GL enums.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Wed, 26 Jul 2017 23:00:50 +0000 (16:00 -0700)]
docs: Fix a typo in the old MESA_program_debug spec.
Noticed that we had two 0x8bb4 in the spec while grepping to find an open
slot in the MESA enums set. gl.xml had the right value.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Brian Paul [Mon, 9 Oct 2017 19:47:20 +0000 (13:47 -0600)]
git_sha1_gen: accept MESA_GIT_SHA1_OVERRIDE env var
If one uses a parent build script to download/build Mesa we may not
have a full git repository (maybe a tar archive) so the 'git rev-parse'
command will fail.
This updates the script to look for a MESA_GIT_SHA1_OVERRIDE env var.
If it's set, use that sha1 instead of using git rev-parse. With this
change we can put a git hash in the GL_VERSION string even when we
don't have a git repo.
v2: incorporate Dylan's suggestions to simplify the code
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Dylan Baker <dylan@pnwbakers.com>
Brian Paul [Thu, 5 Oct 2017 19:34:52 +0000 (13:34 -0600)]
mesa: move _mesa_half_is_negative() to half_float.h
v2: use !! in the function to be explicit about type conversion. Though,
gcc generates the same code with or without the logical !!.
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Brian Paul [Thu, 5 Oct 2017 19:30:32 +0000 (13:30 -0600)]
mesa: move _mesa_exec_malloc/free() prototypes to their own header
Try to start removing things from the cluttered imports.h file.
v2: add new header to Makefile.sources
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Kenneth Graunke [Tue, 10 Oct 2017 17:18:04 +0000 (10:18 -0700)]
i965: minor whitespace fix
Eric Anholt [Mon, 1 May 2017 17:21:36 +0000 (10:21 -0700)]
mesa: Set new renderbuffers to RGBA4 on all GLES contexts.
Before we were doing RGBA4 on GLES3 only, but as of GLES2 2.0.22 it should
be RGBA4 as well. Fixes DEQP
functional.state_query.rbo.renderbuffer_internal_format.
Tested-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Mon, 1 May 2017 16:28:33 +0000 (09:28 -0700)]
mesa: Expose GL_OES_required_internalformat on GLES contexts.
This extension is effectively a backport of GLES3's internalformat
handling to GLES 1/2. It guarantees that sized internalformats specified
for textures and renderbuffers have at least the specified size stored.
That's a pretty minimal requirement, so I think it can be dummy_true and
exposed as a standard in Mesa.
As a side effect, it also allows GL_RGB565 to be specified as a texture
format, not just as a renderbuffer. Mesa had previously been allowing 565
textures, which angered DEQP in the absence of this extension being
exposed.
v2: Allow 2101010rev with sized internalformats even on GLES3, citing the
extension spec. Extend extension checks for GLES2 contexts exposing
with texture_float, texture_half_float, and texture_rg.
v3: Fix ALPHA/LUMINANCE/LUMINANCE_ALPHA error checking (GLES3 CTS
failures)
v4: Mark GL_RGB10 non-color-renderable on ES, fix A/L/LA errors on GLES2
with float formats.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Mon, 1 May 2017 16:51:01 +0000 (09:51 -0700)]
mesa: Only expose GLES's EXT_texture_type_2_10_10_10_REV if supported in HW.
Previously, we were downconverting to 8888 automatically if the hardware
didn't suport it. However, with the advent of
GL_OES_required_internalformat, we have to actually store the
internalformats we advertise support for. And, it seems rather
disingenuous to advertise the extension if we don't actually support it.
v2: Throw an error when using the format on ES2 without the extension present.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Eric Anholt [Mon, 1 May 2017 18:25:06 +0000 (11:25 -0700)]
vc4: Add support for 5551 textures.
This keeps us from promoting them up to 8888, at the cost of not being
color-renderable.
Eric Anholt [Mon, 1 May 2017 18:16:20 +0000 (11:16 -0700)]
gallium: Add support for 5551 with the 1-bit field in the low bit.
This is how VC4 stores 5551 textures, which we need to support for
GL_OES_required_internalformat.
v2: Extend commit message, fix svga driver build, add BE ordering from
Roland.
v3: Rebase on PIPE_FORMAT_R10G10B10X2_UNORM addition.
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v2)
Eric Anholt [Mon, 1 May 2017 18:21:27 +0000 (11:21 -0700)]
mesa: Add X1B5G5R5 along with A1B5G5R5.
For supporting RGB5 in hardware with A in the low bit (vc4), we need this
format as well.
v2: Add proper _mesa_format_matches_format_and_type() support (from
Nicolai).
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:48 +0000 (13:58 +0200)]
st_api: remove unused get_resource_for_egl_image
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:48 +0000 (13:58 +0200)]
st/dri: implement createImageFromRenderbuffer(2)
Tested with dEQP-EGL.functional.image.*renderbuffer* tests.
Reviewed-by: Eric Anholt <eric@anholt.net>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:47 +0000 (13:58 +0200)]
egl/dri: remove old left-overs
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:47 +0000 (13:58 +0200)]
egl/dri: use createImageFromRenderbuffer2 when available
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:47 +0000 (13:58 +0200)]
egl/dri: factor out egl_error_from_dri_image_error
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:46 +0000 (13:58 +0200)]
dri_interface: add an error-returning version of createImageFromRenderbuffer
We ought to be able to distinguish between allocation errors and bad
parameters (non-existent renderbuffer object).
Bumps the version of the DRI Image extension to 17.
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:46 +0000 (13:58 +0200)]
st/mesa: don't clobber glGetInternalformat* buffer for GL_NUM_SAMPLE_COUNTS
Applications might pass in a buffer that is sized too large and rely
on the extra space of the buffer not being overwritten.
Fixes dEQP-GLES31.functional.state_query.internal_format.partial_query.num_sample_counts
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:46 +0000 (13:58 +0200)]
u_threaded_context: fix a memory leak
The uploaders can own transfers which need to be unmapped. Destroy them
before the final sync (they're not used from the driver thread anyway)
so that the transfer_unmap call is processed by the driver.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:45 +0000 (13:58 +0200)]
disk_cache: remove unnecessary NULL-pointer guards
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:45 +0000 (13:58 +0200)]
disk_cache: fix a memory leak
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:44 +0000 (13:58 +0200)]
st/mesa: whitespace fix
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:44 +0000 (13:58 +0200)]
st/mesa: fix import of EGL images with non-zero level or layer
In GL state, textures created from EGL images look like plain 2D textures
with a single level, so we use the existing layer_override facility and
add an analogous level_override one.
Fixes dEQP-EGL.functional.image.create.gles2_cubemap_{positive,negative}_{x,y,z}_rgba_texture
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:44 +0000 (13:58 +0200)]
st/mesa: fix switching from surface-based to non-surface-based textures
This can happen with surface-based texture objects derived from EGL
images, since those aren't immutable.
Fixes tests in dEQP-EGL.functional.sharing.gles2.multithread.random.images.teximage2d.* and others
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 10 Oct 2017 11:58:43 +0000 (13:58 +0200)]
glsl/linker: add check for compute shared memory size
Unlike uniforms, the limit on shared memory size is not called out
explicitly in the list of things that cause linker errors, but presumably
that's just an oversight in the spec.
Fixes dEQP-GLES31.functional.debug.negative_coverage.{callbacks,get_error,log}.compute.exceed_shared_memory_size_limit
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>