Tom Rini [Thu, 2 Jan 2020 15:28:26 +0000 (10:28 -0500)]
Merge tag 'u-boot-rockchip-
20191231' of https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip
- Fix latest mainline kernel for rk3308
- Update rk3288-evb config to suport OP-TEE
- Fix for firefly-px30 DEBUG_UART channel and make it standalone
- Script make_fit_atf add python3 support
- Fix rk3328 timer with correct COUNTER_FREQUENCY
- Fix rk3328 ATF support with enable spl-fifo-mode
Tom Rini [Thu, 2 Jan 2020 15:27:47 +0000 (10:27 -0500)]
Merge branch '2020-01-02-master-imports'
- Assorted test.py fixes
- Other minor changes
Simon Glass [Fri, 27 Dec 2019 14:46:30 +0000 (07:46 -0700)]
test: Fix the boardspec for the SPL handoff test
This test currently does not run because it specifies the sandbox board
instead of sandbox_spl. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Igor Opaniuk [Tue, 17 Dec 2019 12:48:54 +0000 (14:48 +0200)]
mailmap: Update mail address for Igor Opaniuk
My address at Linaro doesn't exist anymore, so people
keep getting mail delivery error responses. Map this address
to the actual one.
Signed-off-by: Igor Opaniuk <igor.opaniuk@gmail.com>
Reviewed-by: Oleksandr Suvorov <oleksandr.suvorov@toradex.com>
Stephen Warren [Wed, 18 Dec 2019 18:37:21 +0000 (11:37 -0700)]
test_env: don't strip() printenv results
get_env() was originally written to strip() the output of printenv to
isolate the test from any whitespace changes in printenv's output.
However, this throws away any whitespace in the variable value, which can
cause issues when test code expects to see that whitespace. In fact,
printenv never adds any whitespace at all, so there's no need to strip.
The strip causes a practical problem for test_env_echo_exists() if
state_test_env.get_existent_var() happens to choose a U-Boot variable that
contains trailing whitespace. This is true for variable boot_targets.
With Python 2, get_existent_var() never returned boot_targets so this
issue never caused a practical problem.
With Python 3, get_existent_var does sometimes return boot_targets, no
doubt due to Python 3's different dict hash key order implementation,
about 0.5-2% of the time, so this test appears intermittent. With the
strip removed, this intermittency is solved, since the test passes for all
possible U-Boot variables.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Robert P. J. Day [Wed, 25 Dec 2019 11:34:07 +0000 (06:34 -0500)]
arch/arm/Kconfig: typo/grammar/punctuation fixes
Various (mostly minor) spelling, grammar and punctuation tweaks for
arch/arm/Kconfig.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Dario Binacchi [Sun, 29 Dec 2019 12:47:32 +0000 (13:47 +0100)]
.gitignore: ignore files generated by asn1 compiler
As described in doc/README.asn1 document the tools/asn1_compiler is used
to "generate bytecode as a C file (*.asn1.[ch]) from *.asn1 file".
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Dario Binacchi [Sun, 29 Dec 2019 12:44:18 +0000 (13:44 +0100)]
tools: .gitignore: add asn1_compiler
Add the tool to the ignore list to prevent being marked as unversioned.
Signed-off-by: Dario Binacchi <dariobin@libero.it>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Kever Yang [Tue, 31 Dec 2019 08:02:59 +0000 (16:02 +0800)]
rockchip: evb-rk3328: Enable support ATF in SPL
Enable the ATF in SPL and adjust the SPL STACK/HEAD at the same time to
support ATF entry at 0x40000.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 31 Dec 2019 07:57:55 +0000 (15:57 +0800)]
rockchip: rk3328: enable spl-fifo-mode for emmc and sdmmc
Since mmc to sram can't do dma, add patch to prevent aborts transfering
TF-A parts.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Tue, 31 Dec 2019 07:17:56 +0000 (15:17 +0800)]
rockchip: rk3328: add COUNTER_FREQUENCY definition
The arch timer needs COUNTER_FREQUENCY to get correct counter, add it to
make the timer works correct.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Sat, 28 Dec 2019 13:07:16 +0000 (08:07 -0500)]
Merge tag 'u-boot-imx-
20191228' of https://gitlab.denx.de/u-boot/custodians/u-boot-imx
Fixes for 2020.01
-----------------
- Fixes for Nitrogen6x
- Fix corruption for mx51evk
- colibri i.MX6: fix broken ESDHC conversion
- mx6sxsabresd: fix broken mmcdev
- imx6q_logic: cleanup boot sequence
- update ATF for imx8mq_evk
- pfuze: fix pmic_get()
Travis CI: https://travis-ci.org/sbabic/u-boot-imx/builds/
630007464
Tom Rini [Fri, 27 Dec 2019 21:46:38 +0000 (16:46 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxi
- Orange Pi Zero Plus 2 support
- sunxi psci, prcm fixes
Tom Rini [Fri, 27 Dec 2019 21:46:15 +0000 (16:46 -0500)]
Merge https://gitlab.denx.de/u-boot/custodians/u-boot-spi
- rk spi transfer limit fix
- Gigadevice, gd25q128 support
- spi-nor-core warnings
Patrik Dahlström [Sat, 21 Dec 2019 16:18:22 +0000 (17:18 +0100)]
omap3_beagle: Change NAND ECC scheme back to OMAP_ECC_HAM1_CODE_HW
The omap3_beagle NAND ECC scheme was changed in
4b37928d357 for unknown
reasons, leading to uncorrectible ecc errors. This commit changes it
back to what it was before.
Signed-off-by: Patrik Dahlström <risca@dalakolonin.se>
Robert Beckett [Tue, 29 Oct 2019 19:07:03 +0000 (19:07 +0000)]
rtc: rx8010js: add compatible string
Add compatible string used by Linux.
Allows for simpler syncing of device trees.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Robert Beckett [Mon, 28 Oct 2019 19:10:10 +0000 (19:10 +0000)]
rtc: s35392a: add compatible strings
Add compatible strings used by Linux.
Allows for simpler syncing of device trees.
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Robert Beckett [Mon, 28 Oct 2019 18:49:15 +0000 (18:49 +0000)]
rtc: rx8010sj: fix DM initialization
pass the udevice by reference instead of double ref
Signed-off-by: Robert Beckett <bob.beckett@collabora.com>
Adam Ford [Sun, 3 Nov 2019 13:58:40 +0000 (07:58 -0600)]
ARM: imx6q_logic: Cleanup boot sequence check
The board_boot_order() function currenly assumes that the boot source
is MMC/eMMC, but this isn't true for the NAND devices.
This patch cleans up board_boot_order() to check for NAND, SD, ESD,
MMC or EMMC. Anything beyond these are not supported, so it will
default back to the serial downloader if any of those devices are not
available.
Fixes:
9fb50c68daa6 ("ARM: imx6q_logic: Fix MMC2 booting")
Signed-off-by: Adam Ford <aford173@gmail.com>
Troy Kisky [Mon, 4 Nov 2019 02:20:05 +0000 (18:20 -0800)]
ARM: i.MX6: TARGET_NITROGEN6X: add 'select MX6QDL'
This fixes commit <
91435cd40d30> "ARM: i.MX6: exclude the ARM errata
from i.MX6 UP system"
for nitrogen6x. The above commit removed the errata for the board
since MX6Q/MXDL/MX6S is selected via CONFIG_SYS_EXTRA_OPTIONS
This restores the errata configs.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Troy Kisky [Mon, 4 Nov 2019 02:20:04 +0000 (18:20 -0800)]
nitrogen6x: prepare for CONFIG_MX6QDL
The next patch adds CONFIG_MX6QDL so that
errata will be enabled again.
Signed-off-by: Troy Kisky <troy.kisky@boundarydevices.com>
Jagan Teki [Sat, 21 Dec 2019 07:54:30 +0000 (13:24 +0530)]
spi: rk: Limit transfers to (64K - 1) bytes
The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.
Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.
Note, that the size is further divided into 'minus 1' while writing
into CTRLR1.
This change fixed two different read issues,
1. sf read failure when with > 0x10000
2. Boot from SPI flash failed during spi_flash_read call in
common/spl/spl_spi.c
Observed and Tested in
- Rockpro64 with Gigadevice flash
- ROC-RK3399-PC with Winbond flash
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Vignesh Raghavendra [Sat, 9 Nov 2019 06:34:13 +0000 (12:04 +0530)]
mtd: spi-nor-core: Fix static checker warnings
Static checker warns 'ret' variable may be used uninitialized in
spi_nor_erase() and spi_nor_write() in case of zero length requests.
Fix these warnings by checking for zero length requests and returning
early.
Reported-by: Dan Murphy <dmurphy@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Jorge Ramirez-Ortiz [Wed, 11 Dec 2019 09:42:36 +0000 (10:42 +0100)]
tools/imximage: share DCD information via Kconfig
IMX based platforms can have the DCD table located on different
addresses due to differences in their memory maps (ie iMX7ULP).
This information is required by the user to sign the images for secure
boot so continue making it accessible via mkimage.
Signed-off-by: Jorge Ramirez-Ortiz <jorge@foundries.io>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Wed, 11 Dec 2019 13:49:30 +0000 (10:49 -0300)]
imx8mq_evk: Update the required ATF branch
Following the README instructions leads to a non-booting
U-Boot:
U-Boot SPL 2020.01-rc3-00070-g9a0cbae22a (Nov 25 2019 - 13:08:24 -0300)
PMIC: PFUZE100 ID=0x10
DDRINFO: start DRAM init
DDRINFO:ddrphy calibration done
DDRINFO: ddrmix config done
Normal Boot
Trying to boot from MMC2
(It hangs here)
Use the "imx_4.19.35_1.0.0" ATF branch instead, which
fixes such problem and allow the boot to complete again.
Suggested-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Acked-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Wed, 11 Dec 2019 17:31:03 +0000 (14:31 -0300)]
imx8m_evk: Remove unneeded earlycon string
Passing earlycon string in the command line may be
useful during bring up, but not after such phase.
Remove the earlycon string to align with the other i.MX SoCs
command lines.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Fabio Estevam [Wed, 11 Dec 2019 20:37:09 +0000 (17:37 -0300)]
imx8m: ddr_init: Move ddr_init() messages to debug level
Currently inside ddr_init() there is a mix of printf() and debug()
level messages.
Since this type of information is useful for debug purposes,
convert all of them to debug level for consistency.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Fabio Estevam [Thu, 19 Dec 2019 16:52:39 +0000 (13:52 -0300)]
mx51evk: Fix U-Boot corruption after saving the environment
U-Boot binary has grown in such a way that it goes beyond the reserved
area for the environment variables.
Running "saveenv" followed by a "reset" causes U-Boot to hang because
of this overlap.
Fix this problem by increasing the CONFIG_ENV_OFFSET size.
Also, in order to prevent this same problem to happen in the future,
use CONFIG_BOARD_SIZE_LIMIT, which will detect the overlap in build-time.
CONFIG_BOARD_SIZE_LIMIT does not accept math expressions, so declare
CONFIG_ENV_OFFSET with its direct value instead.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Fabio Estevam [Thu, 19 Dec 2019 17:59:42 +0000 (14:59 -0300)]
mx6sxsabresd: Adjust the mmcdev after DM conversion
After the DM conversion the boot SD card is now device 3.
Adjust it so that we can boot the kernel again.
While at it avoid a hardcoded mmc dev inside the finduuid script.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Fabio Estevam [Thu, 19 Dec 2019 17:59:41 +0000 (14:59 -0300)]
pfuze: Fix the pmic_get() parameter in the DM case
Currently the following hang is observed when booting a imx6sx-sdb
board:
U-Boot 2020.01-rc5-00004-g643366bcd5 (Dec 19 2019 - 14:56:23 -0300)
CPU: Freescale i.MX6SX rev1.0 996 MHz (running at 792 MHz)
CPU: Extended Commercial temperature grade (-20C to 105C) at 32C
Reset cause: POR
Model: Freescale i.MX6 SoloX SDB RevB Board
Board: MX6SX SABRE SDB revA
DRAM: 1 GiB
initcall sequence
bffd8514 failed at call
87804cc0 (err=-19)
### ERROR ### Please RESET the board ###
When pmic_get() is used with DM the first parameter must be
the complete node name plus the unit address.
Fix the pmic_get() parameter to fix the boot regression.
Tested on a imx6sx-sdb and imx6q-sabresd boards.
Signed-off-by: Fabio Estevam <festevam@gmail.com>
Reviewed-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Igor Opaniuk [Fri, 6 Dec 2019 16:24:16 +0000 (18:24 +0200)]
colibri_imx6: fix broken fsl_esdhc_imx conversion
Not all CONFIG_FSL_ESDHC defines were properly replaced with
CONFIG_FSL_ESDHC_IMX, which broke U-boot proper booting on
Colibri iMX6 SoMs.
U-boot is stuck after this message:
Commercial temperature grade DDR3 timings, 64bit bus width.
Trying to boot from MMC1
Fixes:
e37ac717d7("Convert to use fsl_esdhc_imx for i.MX platforms")
Signed-off-by: Igor Opaniuk <igor.opaniuk@toradex.com>
Jeffy Chen [Thu, 5 Dec 2019 10:58:29 +0000 (18:58 +0800)]
rockchip: mkimage: fix wrong range of rc4 encoding for boot image
The rc4 encoding should cover spl header as well, and the file_size
contains spl header too.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jeffy Chen [Thu, 5 Dec 2019 10:58:28 +0000 (18:58 +0800)]
doc: rockchip: document packing second level loader with mkimage
Add documentation about packing optional second level boot-loader with
mkimage tool.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jeffy Chen [Fri, 27 Dec 2019 03:24:41 +0000 (11:24 +0800)]
rockchip: mkimage: support packing optional second level boot-loader
Support packing optional second level boot-loader:
$ ./tools/mkimage -n rk3399 -T rksd -d \
rk3399_ddr_800MHz_v1.24.bin:rk3399_miniloader_v1.19.bin out -v
Adding Image rk3399_ddr_800MHz_v1.24.bin
Size 116492(pad to 116736)
Adding Image rk3399_miniloader_v1.19.bin
Size 88060(pad to 88064)
Image Type: Rockchip RK33 (SD/MMC) boot image
Init Data Size: 116736 bytes
Boot Data Size: 88064 bytes
Mainly parse init file and boot file from datafile option, copy them to
the image with 2KB alignment.
Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 26 Dec 2019 07:20:34 +0000 (15:20 +0800)]
doc: rockchip: Fix reference the wrong defconfig name of ROC-CC-RK3308
The defconfig file for ROC-CC-RK3308 is roc-cc-rk3308_defconfig.
Fixes:
7f08bfb74f04 ("doc: rockchip: Add documentation for rk3308 based
boards")
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Andy Yan [Thu, 26 Dec 2019 07:20:04 +0000 (15:20 +0800)]
rockchip: rk3308: allow loading larger kernel Image
When compile the curren mainline linux kernel(Linux 5.5-rc3)
with defconfig, the final Image is 29M, it's much
larger than Linux 5.4.
On the current u-boot side on rk3308, the gap between
kernel and fdt is 25M, the fdt will overwrite kernel
Image, so move ftd to a higher memory to give 34M
gab for them.
Signed-off-by: Andy Yan <andy.yan@rock-chips.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Thomas Hebb [Sat, 21 Dec 2019 02:05:22 +0000 (18:05 -0800)]
rockchip: add description for TPL_ROCKCHIP_COMMON_BOARD
SPL_ROCKCHIP_COMMON_BOARD, an almost identical option, has a title but
this one doesn't for some reason. Add a description to make the menu
easier to read.
Signed-off-by: Thomas Hebb <tommyhebb@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 13 Dec 2019 09:41:17 +0000 (17:41 +0800)]
rockchip: px30-firefly add standalone dts
Firefly Core-PX30-JD4 use UART2M1 while PX30 evb using UART2M0, the U-Boot
proper will use the dts setting to do the IOMUX init, and a separate dts
is needed for px30-firefly.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Fri, 13 Dec 2019 02:48:51 +0000 (10:48 +0800)]
rockchip: firefly-px30: Fix the MACRO for CONFIG_DEBUG_UART2_CHANNEL
The Macro has update without update the defconfig, update the defconfig
to make Mcaro correct.
Fixes:
ec4fafdf1f ("rockchip: px30: Rename CONFIG_DEBUG_UART2_CHANNEL to...")
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jack Mitchell [Tue, 10 Dec 2019 13:07:21 +0000 (13:07 +0000)]
rockchip: make_fit_atf: explicitly use python3
On a distribution with no python2 installed and no
python->python3 symlink the script will fail to execute.
Specify python3 explicitly as it's already a requirement
to build u-boot.
Signed-off-by: Jack Mitchell <ml@embed.me.uk>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Thu, 26 Dec 2019 14:07:08 +0000 (09:07 -0500)]
Merge branch '2019-12-26-ti-imports'
- Update maintainer on omapl138_lcdk
- Match TRM sequence & settings in the TI pipe3 PHY
Lokesh Vutla [Fri, 20 Dec 2019 06:05:20 +0000 (11:35 +0530)]
board: davinci: Update OMAPL138_LCDK maintainer
As per the email discussion[0], add myself as a maintainer to
OMAPL138_LCDK and drop Peter's entry.
[0] http://u-boot.10912.n7.nabble.com/OMAP-L138-LCDK-giving-up-maintainership-td394211.html
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Roger Quadros [Wed, 6 Nov 2019 14:21:18 +0000 (16:21 +0200)]
phy: ti-pipe3: Fix SATA & USB PHY power up sequence
As per "Table 26-7. SATA PHY Subsystem Low-Level Programming Sequence"
in TRM [1] we need to turn on SATA_PHY_TX before SATA_PHY_RX.
[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Roger Quadros [Wed, 6 Nov 2019 14:21:17 +0000 (16:21 +0200)]
phy: ti-pipe3: improve DPLL stability for SATA & USB
For increased DPLL stability use the settings recommended in
the TRM [1] for PHY_RX registers for SATA and USB.
For SATA we need to use spread spectrum settings even
though we don't have spread spectrum enabled. The
suggested non-spread spectrum settings don't work.
[1] DRA75x, DRA74x TRM - http://www.ti.com/lit/ug/sprui30f/sprui30f.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Roger Quadros [Wed, 6 Nov 2019 14:21:16 +0000 (16:21 +0200)]
phy: ti-pipe3: Introduce mode property in driver data
Introduce a mode property in the driver data so that
we don't have to keep using "of_device_is_compatible()"
throughtout the driver.
No functional change.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Roger Quadros [Wed, 6 Nov 2019 14:21:15 +0000 (16:21 +0200)]
phy: ti-pipe3: Use TRM recommended settings for SATA DPLL
The AM572x Technical Reference Manual, SPRUHZ6H,
Revised November 2016 [1], shows recommended settings for the
SATA DPLL in Table 26-8. DPLL CLKDCOLDO Recommended Settings.
Use those settings in the driver. The TRM does not show
a value for 20MHz SYS_CLK so we use something close to the
26MHz setting.
[1] - http://www.ti.com/lit/ug/spruhz6h/spruhz6h.pdf
Signed-off-by: Roger Quadros <rogerq@ti.com>
Kever Yang [Thu, 5 Dec 2019 10:11:55 +0000 (18:11 +0800)]
rockchip: rk3288-evb: update config to support OPTEE
Upstream kernel and rockchip kernel has default enable PSCI which needs
OPTEE in trust word, enable OPTEE support for evb by default and SPL_FIT
option to pack OPTEE with U-Boot proper.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Thu, 5 Dec 2019 10:11:54 +0000 (18:11 +0800)]
rockchip: rk3288-evb: update CONFIG_NR_DRAM_BANKS to 2
The OPTEE will use the ram start at 0x8400000 which make the DRAM be two
banks.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Thu, 5 Dec 2019 10:11:53 +0000 (18:11 +0800)]
rockchip: rk3288-evb: update SPL_STACK/MALLOC_LEN config with rk3399
Update the SPL_STACK_R_MALLOC_SIMPLE_LEN which also including space for
STACK and the size may not enough when loding FIT image in SPL.
If the size is not enough, you can see log like this when loding FIT:
U-Boot TPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53)
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2020.01-rc3-00082-g4b19b89ca4-dirty (Dec 05 2019 - 11:52:53 +0800)
Trying to boot from MMC2
And if enable the DEBUG for everyting in SPL, the log will hang at dwmmc
sending CMD16 for 'uboot' loadables binary because this step need a
large stack cost(about 0x2d00).
External data: dst=8400000, offset=72638, size=b3580
Image OS is Trusted Execution Environment
board_fit_config_name_match: rk3288-evb
Selecting config 'rk3288-evb'loadables: 'uboot'
blk_find_device: if_type=6, devnum=1: dwmmc@
ff0c0000.blk, 6, 0
blk_find_device: if_type=6, devnum=1: dwmmc@
ff0f0000.blk, 6, 1
Sending CMD16
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Kever Yang [Thu, 5 Dec 2019 10:11:52 +0000 (18:11 +0800)]
rockchip: fit_spl_optee: get text and optee base from build
Instead of hardcode the base address, we can get them from the build
output, eg. get the SYS_TEXT_BASE from .config and get optee base from
DRAM_BASE.
We can use this script for SoCs with DRAM base not from 0x60000000(rk3229
and many other 32bit Rockchip SoCs), eg. rk3288 DRAM base is 0.
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Sun, 22 Dec 2019 14:14:35 +0000 (09:14 -0500)]
Merge branch 'master' of git://git.denx.de/u-boot-usb
- dwc3 and cdns3 bug fixes
Tom Rini [Sun, 22 Dec 2019 14:13:50 +0000 (09:13 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-net
- Fix phy_connect() call in two drivers
- fw_setenv bugfix
Jagan Teki [Wed, 18 Dec 2019 07:30:02 +0000 (13:00 +0530)]
usb: dwc3: Fix UTMI/UTMIW phy interface initialization
DWC3 support phy interfaces like 8/16-bit UTMI+. phy interface
initialization code would handle them properly along with UNKNOWN
type by default if none of the user/board doesn't need to use the
phy interfaces at all.
The current code is masking the 8/16-bit UTMI+ interface bits globally
which indeed effect the UNKNOWN cases, therefore it effects the platforms
which are not using phy interfaces at all.
So, handle the phy masking bits accordingly on respective interface
type cases.
Fixes:
6b7ebff00190 ("usb: dwc3: Add phy interface for dwc3_uboot")
Reported-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Heinrich Schuchardt [Tue, 17 Dec 2019 09:37:19 +0000 (10:37 +0100)]
MAINTAINERS: assign usb.c and and usb_kbd.c
Marek is already maintaining USB. Assign files common/usb.c and
common/usb_kbd.c to him.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Vignesh Raghavendra [Thu, 5 Dec 2019 07:59:25 +0000 (13:29 +0530)]
usb: cdns3: ep0: Fix build warnings related to cache ops
Since, commit
62f9b6544728 ("common: Move older CPU functions to their own header")
cache ops functions are declared in a separate header. Include the same
to avoid build warnings.
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Rasmus Villemoes [Thu, 27 Sep 2018 20:45:26 +0000 (22:45 +0200)]
fw_setenv: avoid writing environment when nothing has changed
In the case where one deletes an already-non-existing variable, or sets
a variable to the value it already has, there is no point in writing the
environment back, thus reducing wear on the underlying storage
device.
In the case of redundant environments, if the two environments
differ (e.g. because one is corrupt), make sure that any call of
fw_setenv causes the two to become synchronized, even if the fw_setenv
call does not change anything in the good copy.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Alex Marginean [Thu, 19 Dec 2019 12:35:37 +0000 (14:35 +0200)]
drivers: net: bcm-sf2: pass -1 to phy_connect()
Passing 0 to PHY connect used to trigger a MDIO scan due to a bug fixed in
the meantime. It's unclear if bcm-sf2 wants to connect to PHY @ addr 0 or
is scanning the bus, passing -1 here should keep it functional either way.
Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com>
Cc: Jiandong Zheng <jdzheng@broadcom.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Wed, 18 Dec 2019 06:48:50 +0000 (07:48 +0100)]
net: dwc_eth_qos: Pass -1 to phy_connect() to scan for all PHYs
PHY address 0 is a valid PHY address, to scan for all PHYs, pass -1 to
phy_connect(). Passing 0 used to work before be accident, but does no
longer.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Patrice Chotard <patrice.chotard@st.com>
Cc: Patrick Delaunay <patrick.delaunay@st.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Heinrich Schuchardt [Tue, 17 Dec 2019 21:55:42 +0000 (22:55 +0100)]
sunxi: remove __packed from struct sunxi_prcm_reg
struct sunxi_prcm_reg is naturally packed. There is no need to define it as
packed. Defining it as packed leads to compilation errors with GCC 9.2.1:
CC arch/arm/lib/reloc_arm_efi.o
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
:qarch/arm/cpu/armv7/sunxi/psci.c:163:21: error: taking address of packed
member of ‘struct sunxi_prcm_reg’ may result in an unaligned pointer value
[-Werror=address-of-packed-member]
163 | sunxi_power_switch(&prcm->cpu_pwr_clamp[cpu], &prcm->cpu_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~~~
Remove __packed attribute from struct sunxi_prcm_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Diego Rondini [Tue, 19 Nov 2019 13:43:33 +0000 (14:43 +0100)]
sun8i: h3: Support H3 variant of Orange Pi Zero Plus 2
Orangepi Zero Plus 2 is an open-source single-board computer, available
in two Allwinner SOC variants, H3 and H5. We add support for H3 variant
here, as the H5 is already supported.
H3 Orangepi Zero Plus 2 has:
- Quad-core Cortex-A7
- 512MB DDR3
- microSD slot and 8GB eMMC
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG + power supply
Sync dts from linux v5.2 commit:
"ARM: dts: sunxi: h3/h5: Remove stale pinctrl-names entry"
(sha1:
75f9a058838be9880afd75c4cb14e1bf4fe34a0b)
Commit:
"ARM: dts: sun8i: h3: Refactor the pinctrl node names"
(sha1:
a4dc791974e568a15f7f37131729b1a6912f4811)
has been avoided as it breaks U-Boot build.
Signed-off-by: Diego Rondini <diego.rondini@kynetics.com>
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Heinrich Schuchardt [Sun, 10 Nov 2019 03:10:27 +0000 (04:10 +0100)]
sunxi: psci: avoid error address-of-packed-member
Compiling with GCC 9.2.1 leads to build errors:
arch/arm/cpu/armv7/sunxi/psci.c: In function ‘sunxi_cpu_set_power’:
arch/arm/cpu/armv7/sunxi/psci.c:144:21: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~~~~
arch/arm/cpu/armv7/sunxi/psci.c:144:46: error: taking address of packed
member of ‘struct sunxi_cpucfg_reg’ may result in an unaligned pointer
value [-Werror=address-of-packed-member]
144 | sunxi_power_switch(&cpucfg->cpu1_pwr_clamp, &cpucfg->cpu1_pwroff,
| ^~~~~~~~~~~~~~~~~~~~
Use memcpy() and void* pointers to resolve the problem caused by packing
the struct sunxi_cpucfg_reg.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Acked-by: Jagan Teki <jagan@amarulasolutions.com>
Peter Robinson [Thu, 14 Nov 2019 00:01:22 +0000 (00:01 +0000)]
mtd: spi-nor: ids: Add GigaDevice gd25q128
Add gd25q128 128Mbit chip to spi-nor id table.
Tested on Pinebook Pro
Signed-off-by: Peter Robinson <pbrobinson@gmail.com>
Acked-by: Vignesh Raghavendra <vigneshr@ti.com>
Tested-by: Jagan Teki <jagan@amarulasolutions.com> # roc-rk3399-pc
Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Wed, 18 Dec 2019 13:25:49 +0000 (08:25 -0500)]
Merge tag 'u-boot-stm32-
20191218' of https://gitlab.denx.de/u-boot/custodians/u-boot-stm
- Fix stm32mp1 crash (bootstage) and warning (cls)
Patrick Delaunay [Wed, 18 Dec 2019 09:12:59 +0000 (10:12 +0100)]
stm32mp1: configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 18 Dec 2019 09:12:58 +0000 (10:12 +0100)]
stm32mp1: remove the imply BOOTSTAGE
This patch is only a temporarily workaround for crash introduced by
commit
ac9cd4805c8b ("bootstage: Correct relocation algorithm").
The crash occurs because the bootstage struct is not correctly aligned
when BOOTSTAGE feature is activated.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Tue, 3 Dec 2019 08:38:58 +0000 (09:38 +0100)]
stm32mp1: imply CMD_CLS
Activate by default the command CLS (clear screen);
this command used in pxe or sysboot command (DISTRO support)
when the "menu background" keyword is present.
This patch avoid the warning "Unknown command 'cls'"
with extlinux.conf:
# Generic Distro Configuration file generated by OpenEmbedded
menu title Select the boot mode
MENU BACKGROUND /splash.bmp
TIMEOUT 20
DEFAULT stm32mp157c-ev1-emmc
LABEL stm32mp157c-ev1-emmc
KERNEL /uImage
FDT /stm32mp157c-ev1.dtb
APPEND root=/dev/mmcblk1p4 rootwait rw console=ttySTM0,115200
...
Retrieving file: /mmc0_stm32mp157c-ev1_extlinux/extlinux.conf
614 bytes read in 36 ms (16.6 KiB/s)
Retrieving file: /splash.bmp
46180 bytes read in 40 ms (1.1 MiB/s)
Unknown command 'cls' - try 'help'
Select the boot mode
1: stm32mp157c-ev1-sdcard
...
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Acked-by: Patrick Delaunay <patrick.delaunay@st.com>
Tom Rini [Mon, 16 Dec 2019 12:39:56 +0000 (07:39 -0500)]
Prepare v2020.01-rc5
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Sat, 14 Dec 2019 01:58:49 +0000 (20:58 -0500)]
Merge branch '2019-12-13-master-imports'
- Assorted minor fixes
Grygorii Strashko [Wed, 20 Nov 2019 19:13:26 +0000 (21:13 +0200)]
arm: ti: dra7: move BOOTP_DNS2 and PHY_TI in defconfig
Move BOOTP_DNS2 and PHY_TI from dra7xx_evm.h to
dra7xx_evm_defconfig.
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com>
Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com>
Heinrich Schuchardt [Tue, 10 Dec 2019 06:43:33 +0000 (07:43 +0100)]
common: remove duplicate typedef for uchar
With commit
37db55b7e9db ("linux/types.h: fix typo unchar") we have a
duplicate typedef for uchar. As linux/types.h is included in common.h we
don't need another typedef for uchar there.
Fixes:
37db55b7e9db ("linux/types.h: fix typo unchar")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Reviewed-by: Joe Hershberger <joe.hershberger@ni.com>
Heinrich Schuchardt [Wed, 11 Dec 2019 09:45:50 +0000 (10:45 +0100)]
doc: fitImage: example of a signature node
Describe that a signature node can be added to a binary device tree using
the mkimage tool.
Provide an example device tree node.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Heinrich Schuchardt [Thu, 12 Dec 2019 17:07:49 +0000 (18:07 +0100)]
mailmap: Update mail address for Boris Brezillon
Boris' email address has changed. Copy two entries from the Linux .mailmap
file.
Boris confirmed the new email address:
https://lists.denx.de/pipermail/u-boot/2019-December/393774.html
Cc: Boris Brezillon <bbrezillon@kernel.org>
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Rasmus Villemoes [Thu, 12 Dec 2019 14:38:23 +0000 (14:38 +0000)]
doc: really get rid of Documentation/ directory
Commit
656d8da9d2 (doc: Remove duplicated documentation directory) got
rid of most of Documentation/. But there's still an obviously useless
.gitignore left behind.
Also, there's a copy of the linux kernel's net/ethernet.txt binding
imported from v5.0, while the existing one in doc/ is from 4.0-rc1. So
replace the latter by the former, and making Documentation/ finally
empty.
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Reviewed-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
Rasmus Villemoes [Fri, 13 Dec 2019 15:47:58 +0000 (15:47 +0000)]
sysreset_mpc83xx: fix mcp83xx -> mpc83xx typo
Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
Hannes Schmelzer [Fri, 13 Dec 2019 07:12:45 +0000 (08:12 +0100)]
dts: am335x-brsmarc1/xre1: insert phy_id again
commit
3b3e8a37d36e
("arm: dts: am335x: sync cpsw/mdio/phy with latest linux - drop phy_id")
did sync with recent linux kernel and replaced therefore the 'phy_id'
property with a phy-handle pointing to the mdio.
This is OK for linux, but introduces trouble with the already running
vxWorks on this target.
So this commit here re-inerts the phy_id property beside the phy-handle
property to be compatible with both.
Signed-off-by: Hannes Schmelzer <hannes.schmelzer@br-automation.com>
Tom Rini [Wed, 11 Dec 2019 14:29:39 +0000 (09:29 -0500)]
Merge tag 'rpi-next-2020.01.2' of https://gitlab.denx.de/u-boot/custodians/u-boot-raspberrypi
- fix DRAM bank detection for unified binary
- fix 32bit RPi4 config
Tom Rini [Wed, 11 Dec 2019 13:17:19 +0000 (08:17 -0500)]
Merge tag 'fix-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-i2c
i2c bugfixes for 2020.01
- i2c: i2c_cdns: fix write timeout on fifo boundary
fixes timout issue when writting number of bytes is multiple
of the FIFO depth.
Tom Rini [Wed, 11 Dec 2019 13:16:16 +0000 (08:16 -0500)]
Merge tag 'u-boot-atmel-fixes-2020.01-a' of https://gitlab.denx.de/u-boot/custodians/u-boot-atmel
- First set of u-boot-atmel fixes for 2020.01 cycle:
This set includes a small fix for gpio bank names, one for removing
unused headers (also touches some other boards), and a fix for the QSPI
env read on one of the boards.
Matthias Brugger [Thu, 5 Dec 2019 17:53:15 +0000 (18:53 +0100)]
ARM: defconfig: Fix 32bit config for RPi4
The rpi_4_32b_defconfig states that only one DRAM bank is present. This
leads to a wrong configuration of the available DRAM. Fix this by
setting the DRAM bank config accordingly.
Fixes:
193279d784 ("RPI: Add defconfigs for rpi4 (32/64)")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Matthias Brugger [Thu, 5 Dec 2019 17:53:14 +0000 (18:53 +0100)]
rpi: Enable DRAM bank initialization on arm64
Up to now we only update the DRAM banks when we are define
CONFIG_BCM2711. But our one binary approach uses a config that supports
BCM2837 and BCM2711. As a result we only see one gibibyte of RAM on
Raspberry Pi 4, even if it has more RAM.
Fix this by calling dram_init_banksize.
Fixes:
5694090670 ("ARM: defconfig: add unified config for RPi3 and RPi4")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Matthias Brugger [Thu, 5 Dec 2019 17:53:13 +0000 (18:53 +0100)]
rpi: fix dram bank initialization
To update the dram bank information from device-tree we use
fdtdec_decode_ram_size() which expectes the the size-cells and
address-cells to be defined in the memory node. For normal system RAM
these values are defined in the root node. When the values differ from
the default values defined in the spec, we can end up with wrong RAM
bank information.
Switch to the "standard" way to update the RAM bank information to
avoid this.
Fixes:
9de5b89e4c ("rpi4: enable dram bank initialization")
Signed-off-by: Matthias Brugger <mbrugger@suse.com>
Michael Auchter [Mon, 9 Dec 2019 18:16:16 +0000 (18:16 +0000)]
i2c: i2c_cdns: fix write timeout on fifo boundary
This fixes an issue that would cause I2C writes to timeout when the
number of bytes is a multiple of the FIFO depth (i.e. 16 bytes).
Within the transfer loop, after writing the data register with a new
byte to transfer, if the transfer size equals the FIFO depth, the loop
pauses until the INTERRUPT_COMP bit asserts to indicate data has been
sent. This same check is performed after the loop as well to ensure data
has been transferred prior to returning.
In the case where the amount of data to be written is a multiple of the
FIFO depth, the transfer loop would wait for the INTERRUPT_COMP bit to
assert after writing the final byte, and then wait for this bit to
assert once more. However, since the transfer has finished at this
point, no new data has been written to the data register, and hence
INTERRUPT_COMP will never assert.
Fix this by only waiting for INTERRUPT_COMP in the transfer loop if
there's still data to be written.
Signed-off-by: Michael Auchter <michael.auchter@ni.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 10 Dec 2019 20:41:15 +0000 (15:41 -0500)]
Merge tag 'fixes-for-2020.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-video
- fix crash and board reset when drawing RLE8 bitmaps
bigger than the framebuffer resolution
- reduce dead code in video and console uclass routines
(tested on mx53cx9020, sama5d2_xplained, stm32mp157c-ev1,
stm32f746-disco, stm32f769-disco and wandboard)
Swapna Gurumani [Mon, 2 Dec 2019 21:06:10 +0000 (21:06 +0000)]
configs: sama5d27_som1_ek: Add default config to read ENV from QSPI
In the initial SPI flash setup, the default bus mode being used was 3,
which is incorrect, causing a CRC error when the ENV was being read from
QSPI. Setting the default bus mode to 0 which is the correct mode.
Signed-off-by: Swapna Gurumani <swapna.gurumani@microchip.com>
Tom Rini [Tue, 10 Dec 2019 02:53:23 +0000 (21:53 -0500)]
Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-riscv
- Increase stack size to avoid a stack overflow during distro boot.
- Add hifive-unleashed-a00.dts for SIFIVE FU540.
- Add OF_SEPARATE support for SIFIVE FU540.
- Add SPL support for Andes AX25 AE350.
- Improve U-Boot SPL / OpenSBI smp boot flow for RISC-V.
Lukas Auer [Sun, 8 Dec 2019 22:28:52 +0000 (23:28 +0100)]
spl: opensbi: wait for ack from secondary harts before entering OpenSBI
At the start, OpenSBI relocates itself to its link address. If the link
address ranges of U-Boot SPL and OpenSBI overlap, the relocation can
lead to code corruption if a hart is still running U-Boot SPL during
relocation. To avoid this problem, the main hart is specified as the
preferred boot hart to perform the relocation. This fixes the code
corruption problems based on the assumption that since the main hart
schedules the secondary harts to enter OpenSBI, it will be the last to
enter OpenSBI. However it was reported that this assumption is not
always correct.
To make sure the assumption always holds true, wait for all secondary
harts to acknowledge the call-function request before entering OpenSBI
on the main hart.
Reported-by: Rick Chen <rick@andestech.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Lukas Auer [Sun, 8 Dec 2019 22:28:51 +0000 (23:28 +0100)]
riscv: add option to wait for ack from secondary harts in smp functions
Add a wait option to smp_call_function() to wait for the secondary harts
to acknowledge the call-function request. The request is considered to
be acknowledged once each secondary hart has cleared the corresponding
IPI.
As part of the call-function request, the secondary harts invalidate the
instruction cache after clearing the IPI. This adds a delay between
acknowledgment (clear IPI) and fulfillment (call function) of the
request. We want to use the acknowledgment to be able to judge when the
request has been completed. Remove the delay by clearing the IPI after
cache invalidation and just before calling the function from the
request.
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Lukas Auer [Sun, 8 Dec 2019 22:28:50 +0000 (23:28 +0100)]
riscv: add functions for reading the IPI status
Add the function riscv_get_ipi() for reading the pending status of IPIs.
The supported controllers are Andes' Platform Level Interrupt Controller
(PLIC), the Supervisor Binary Interface (SBI), and SiFive's Core Local
Interruptor (CLINT).
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Lukas Auer [Sun, 8 Dec 2019 22:28:49 +0000 (23:28 +0100)]
spl: opensbi: specify main hart as preferred boot hart
OpenSBI uses a relocation lottery to determine the hart to relocate
OpenSBI to its link address. In the U-Boot SPL boot flow, the main hart
schedules the secondary harts to enter OpenSBI before doing so itself.
One of the secondary harts will therefore always be the winner of the
relocation lottery. This is problematic if the link address ranges of
OpenSBI and U-Boot SPL overlap. OpenSBI will be relocated and therefore
overwrite U-Boot SPL while some harts may still run it, leading to code
corruption.
Avoid this problem by specifying the main hart as the preferred boot
hart to perform the OpenSBI relocation. The main hart will be the last
hart to enter OpenSBI, relocation can therefore occur safely.
The boot hart field was added to version 2 of the OpenSBI FW_DYNAMIC
info structure. The header file include/opensbi.h is synchronized with
include/sbi/fw_dynamic.h from the OpenSBI project to update the info
structure. The header file is recent as of commit
7a13beb21326 ("firmware: Add preferred boot HART field in struct
fw_dynamic_info").
Reported-by: Rick Chen <rick@andestech.com>
Suggested-by: Anup Patel <Anup.Patel@wdc.com>
Signed-off-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
Reviewed-by: Rick Chen <rick@andestech.com>
Tested-by: Rick Chen <rick@andestech.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Rick Chen [Thu, 14 Nov 2019 05:52:30 +0000 (13:52 +0800)]
doc: update AX25-AE350 RISC-V documentation
Add descriptions about U-Boot SPL feature and how to build and run.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:29 +0000 (13:52 +0800)]
riscv: dts: Add #address-cells and #size-cells in nor node
Those are required for cfi-flash driver to get correct address information.
Also modify size description correctly.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:28 +0000 (13:52 +0800)]
riscv: dts: Support four cores SMP
Add CPU2 and CPU3 information in cpus node
to support four cores SMP booting.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:27 +0000 (13:52 +0800)]
riscv: Fix clear bss loop in the start-up code
For RV64, it will use sd instruction to clear t0
register, and the increament will be 8 bytes. So
if the difference between__bss_strat and __bss_end
was not 8 bytes aligned, the clear bss loop will
overflow and acks like system hang.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:26 +0000 (13:52 +0800)]
spl: cache: Allow cache drivers in SPL
When ax25-ae350 try to enable v5l2 cache
driver in SPL configuration, it need this
option for cache support in SPL.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:25 +0000 (13:52 +0800)]
riscv: ax25: cache: Add SPL_RISCV_MMODE for SPL
The mcache_ctl csr only can be manipulated in M mode.
Add SPL_RISCV_MMODE for U-Boot SPL to control cache
operation.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:24 +0000 (13:52 +0800)]
riscv: andes_plic: Fix some wrong configurations
Fix two wrong settings of andes plic driver as below:
1. Fix wrong pending register base definition.
2. Declaring the en variable in enable_ipi() as unsigned int instead of
int can help to fix wrong plic enabling setting in RV64.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:23 +0000 (13:52 +0800)]
riscv: ax25-ae350: Use generic memory size setup
To get memory size from device tree instead of
get_ram_size(). This can avoid memory access fault
in U-Boot proper after PMP configurations in OpenSBI.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:22 +0000 (13:52 +0800)]
riscv: ax25-ae350: add SPL configuration
This patch provides four configurations which can support U-Boot SPL
to boot from RAM or FLASH and then boot FIT image including OpenSBI
FW_DYNAMIC firmware and U-Boot proper images from RAM or MMC boot devices.
With ae350_rv[32|64]_spl_defconfigs:
U-Boot SPL will be loaded by gdb or FSBL and runs in RAM in machine mode
and then load FIT image from RAM device on AE350.
With ae350_rv[32|64]_spl_xip_defconfigs:
U-Boot SPL can be burned into SPI flash and run in flash in machine mode
and then load FIT image from SPI flash or MMC device on AE350.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Thu, 14 Nov 2019 05:52:21 +0000 (13:52 +0800)]
riscv: ax25: add SPL support
The U-Boot SPL will boot in M mode and load the FIT image which
include OpenSBI and U-Boot proper images. After loading progress,
it will jump to OpenSBI first and then U-Boot proper which will
run in S mode.
Also remove V5L2_CACHE due to U-Boot SPL code size consideration.
Without this concern, it can be enable manually for performance.
Signed-off-by: Rick Chen <rick@andestech.com>
Cc: KC Lin <kclin@andestech.com>
Cc: Alan Kao <alankao@andestech.com>
Rick Chen [Wed, 4 Dec 2019 06:52:46 +0000 (14:52 +0800)]
Use dts support from U-Boot via OF_SEPARATE instead of depending from opensbi.
This would help to make the necessary changes in drivers and device trees
in U-Boot tree itself. This feature would also be helpful to not pass
dtb during opensbi builds.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Anup Patel <anup.patel@wdc.com>
Signed-off-by: Rick Chen <rick@andestech.com>