Kenneth Graunke [Thu, 20 Jul 2017 23:33:15 +0000 (16:33 -0700)]
i965: Remove tabs in intel_batchbuffer.c.
Our coding style is to use spaces. Some of this was also messed up
during my bufmgr import series.
(Trivial, just whitespace changes.)
Jason Ekstrand [Thu, 17 Aug 2017 22:27:25 +0000 (15:27 -0700)]
i965/miptree: Return NONE from texture_aux_usage when fully resolved
This little optimization improves the performance of SynMark v7
TexFilterTri by almost 10% on Sky Lake GT4 among other improvements.
We've been doing it for some time but somehow it got dropped during
the miptree refactoring.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/102258
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Fri, 18 Aug 2017 23:10:39 +0000 (16:10 -0700)]
i965: Stop looking at NewDriverState when emitting 3DSTATE_URB
Looking at NewDriverState is not safe in general. The state atom system
is set up to ensure that new bits that get added to NewDriverState get
accumulated into the set of bits used when emitting atoms but it doesn't
go the other way. If we read NewDriverState, we may not get the full
picture because the per-pipeline state (3D or compute) does not get
added to NewDriverState before state emit is done. It's especially
dangerous to do this from BLORP (either explicitly or implicitly when
BLORP calls gen7_upload_urb) because that does not happen during one of
the normal state upload paths.
This commit solves the problem by whacking all of the per-shader-stage
URB sizes to zero whenever we change the total URB size. We still have
to flag BRW_NEW_URB_SIZE to ensure that the gen7_urb atom triggers but
the actual decision in gen7_upload_urb can now be based entirely on URB
sizes rather than on state atoms. This also makes BLORP correct because
it just asks for a new URB config whenever the vsize is too small and so
any change to the total URB size will trigger blorp to re-emit as well
because 0 < vs_entry_size.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/102289
Cc: mesa-stable@lists.freedesktop.org
Kenneth Graunke [Wed, 16 Aug 2017 18:15:24 +0000 (11:15 -0700)]
i965: Mark all EGLimages as non-coherent.
EGLimages are shared with external users, and we don't know what they're
going to do with them. They might scan them out. They might access
them in a way that doesn't work with our explicit clflushing.
It's safest to simply mark them non-coherent.
Chris Wilson caught this problem and wrote a similar (though less
aggressive) patch to solve it; the miptree code has since undergone
a lot of refactoring so I had to rewrite it.
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Eric Anholt [Fri, 3 Feb 2017 00:20:15 +0000 (16:20 -0800)]
broadcom/genxml: Add V3D 3.3 packet definitions.
This will be used by the new vc5 gallium driver, and a future Vulkan
driver.
Eric Anholt [Thu, 13 Jul 2017 20:20:29 +0000 (13:20 -0700)]
broadcom/genxml: Check the sub-id field when decoding instructions.
VC5 introduces packet variants where the same opcode has behavior that is
decided by a sub-id field in the early bits of the packet. Keep iterating
over packets until we find the one with the matching sub-id.
Eric Anholt [Mon, 19 Dec 2016 19:11:44 +0000 (11:11 -0800)]
broadcom/genxml: Emit code for default headers for structs as well.
In the vc5 NIR backend, I want to use the XML code-generation to set up
pack/unpack of structs for the texture uniforms, and setting up the
unpacked copy needs a default header.
Eric Anholt [Sat, 21 Jan 2017 05:22:15 +0000 (16:22 +1100)]
anv: Move a comment that got left behind in the u_vector refactor.
Marek Olšák [Tue, 15 Aug 2017 00:50:22 +0000 (02:50 +0200)]
gallium/radeon: remove old_fence parameter from r600_gfx_write_event_eop
just use the new scratch buffer.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 15 Aug 2017 00:40:30 +0000 (02:40 +0200)]
radeonsi/gfx9: prevent a GPU hang after a timestamp event
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Tue, 15 Aug 2017 15:51:05 +0000 (17:51 +0200)]
radeonsi: don't use CLEAR_STATE on SI
This fixes random hangs with Unigine Valley.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102201
Fixes:
064550238ef0 ("radeonsi: use CLEAR_STATE to initialize some registers")
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Jon Turney [Thu, 17 Aug 2017 21:10:52 +0000 (22:10 +0100)]
Fix build when HAVE_LIBDRM isn't defined
make[4]: Entering directory '/wip/mesa/build/src/gallium/targets/dri'
CXXLD gallium_dri.la
../../../../src/gallium/auxiliary/pipe-loader/.libs/libpipe_loader_static.a(libpipe_loader_static_la-pipe_loader.o): In function `pipe_loader_get_driinfo_xml':
/mesa/build/src/gallium/auxiliary/pipe-loader/../../../../../src/gallium/auxiliary/pipe-loader/pipe_loader.c:117: undefined reference to `pipe_loader_drm_get_driinfo_xml'
b4ff5e90 uses pipe_loader_get_driinfo_xml() unconditionally in
pipe_loader.c, but it's definition in pipe_loader_get_driinfo_xml() is only
built if HAVE_LIBDRM.
Arrange to always use the default XML if HAVE_LIBDRM isn't defined.
Signed-off-by: Jon Turney <jon.turney@dronecode.org.uk>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Kenneth Graunke [Fri, 18 Aug 2017 06:41:50 +0000 (23:41 -0700)]
i965: Fix missing newlines in perf_debug messages.
perf_debug() doesn't append a newline for you.
Ilia Mirkin [Thu, 17 Aug 2017 02:18:39 +0000 (22:18 -0400)]
glsl: add a few missing int64 constant propagation cases
Fixes KHR-GL45.shader_ballot_tests.ShaderBallotAvailability, which
causes some silly swizzles to appear, triggering this optimization to
get hit.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
Timothy Arceri [Thu, 17 Aug 2017 23:32:15 +0000 (09:32 +1000)]
glsl: set old ldexp operand to NULL when lowering
This fixes an assert during IR validation in LLVMpipe.
Fixes:
e2e2c5abd279 (glsl: calculate number of operands in an expression once)
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102274
Reviewed-by: Brian Paul <brianp@vmware.com>
Tested-by: Brian Paul <brianp@vmware.com>
Jason Ekstrand [Thu, 17 Aug 2017 21:57:06 +0000 (14:57 -0700)]
intel/isl: Replace switch statements of doom with a macro
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Jason Ekstrand [Thu, 17 Aug 2017 21:56:46 +0000 (14:56 -0700)]
intel/isl: Reduce header file duplication
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Dave Airlie [Thu, 17 Aug 2017 23:33:41 +0000 (09:33 +1000)]
radv: disable support for VEGA for now.
I'm working on this, but I'm not sure I'll make 17.2 at this stage,
maybe 17.2.1.
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jeremy Huddleston Sequoia [Thu, 17 Aug 2017 22:08:36 +0000 (15:08 -0700)]
glxcmds: Fix a typo in the __APPLE__ codepath
s/DummyContext/dummyContext/
Regressed-in:
5d9b50e596c9d81c37ce0844ae0f8c9da3f6bea6
Signed-off-by: Jeremy Huddleston Sequoia <jeremyhu@apple.com>
Roland Scheidegger [Tue, 15 Aug 2017 15:53:49 +0000 (17:53 +0200)]
llvmpipe: enable PIPE_CAP_QUERY_SO_OVERFLOW
The driver supported this since way before the GL spec for it existed.
Just need to support both the per-stream and for all streams variants
(which are identical due to only supporting 1 stream).
Passes piglit arb_transform_feedback_overflow_query-basic.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Roland Scheidegger [Tue, 15 Aug 2017 15:52:41 +0000 (17:52 +0200)]
softpipe: enable PIPE_CAP_QUERY_SO_OVERFLOW
The driver was supposed to support this since way before the GL spec for it
existed, albeit it was apparently broken, so fix and enable it.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Gwan-gyeong Mun [Thu, 10 Aug 2017 16:18:57 +0000 (01:18 +0900)]
dri: fix typo in comment
Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Vinson Lee [Sat, 5 Aug 2017 20:31:50 +0000 (13:31 -0700)]
configure.ac: Check for expat21 if expat is not found.
Fixes build error on CentOS 6.9.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102052
Fixes:
5c007203b73d ("configure.ac: drop manual detection of expat header/library")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Michel Dänzer [Tue, 15 Aug 2017 00:41:57 +0000 (09:41 +0900)]
configure: Check llvm-config --shared-mode
https://bugs.llvm.org/show_bug.cgi?id=6823 still affects current LLVM.
llvm-config --libs only reports the single shared library if LLVM was
built with -DLLVM_LINK_LLVM_DYLIB=ON. llvm-config --shared-mode reports
"shared" in that case, "static" otherwise (even if LLVM was built with
-DLLVM_BUILD_LLVM_DYLIB=ON).
v2: Keep the LLVM < 4.0 test. (llvm-config --shared-mode is actually
available since LLVM 3.8, but that would make the test too
complicated :)
Fixes:
3d8da1f678e1 ("configure: Trust LLVM >= 4.0 llvm-config --libs
for shared libraries")
Bugzilla: https://bugs.freedesktop.org/102247
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Thomas Hellstrom [Fri, 11 Aug 2017 07:49:54 +0000 (09:49 +0200)]
loader_dri3: Make sure we have an updated back v3
With GLX_SWAP_COPY_OML and GLX_SWAP_EXCHANGE_OML it may happen in situations
when glXSwapBuffers() is immediately followed by for example another
glXSwapBuffers() or glXCopyBuffers() or back buffer age querying, that we
haven't yet allocated and initialized a new back buffer because there was
no GL rendering in between.
Make sure that we have a back buffer in those situations.
v2: Eliminate the drawable have_back_format member.
v3: Make sure we re-initialize the back even if it exists.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Thu, 10 Aug 2017 15:34:05 +0000 (17:34 +0200)]
loader_dri3: Support GLX_SWAP_EXCHANGE_OML
Add support for the exchange swap method. Since we're now forcing a fake front
buffer and we exchange the back and fake front on swaps, we don't need to add
much code.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Thu, 10 Aug 2017 15:20:49 +0000 (17:20 +0200)]
loader_dri3: Eliminate the back-to-fake-front copy
Eliminate the back-to-fake-front copy by exchanging the previous back buffer
and the fake front buffer. This is a gain except when we need to preserve
the back buffer content but in that case we still typically gain by replacing
a server-side blit by a client side non-flushing blit.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Wed, 28 Jun 2017 06:31:56 +0000 (08:31 +0200)]
loader_dri3: Remove buffer_type from buffer metadata
It's not used anywhere and now that we're about to exchange back- and
fake fronts it doesn't serve a purpose.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Thu, 10 Aug 2017 15:10:47 +0000 (17:10 +0200)]
loader_dri3: Support GLX_SWAP_COPY_OML
Support the GLX_SWAP_COPY_OML method. When this method is requested, we use
the same swapbuffer code path as EGL_BUFFER_PRESERVED.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Thu, 10 Aug 2017 14:14:23 +0000 (16:14 +0200)]
loader_dri3: Honor the request to preserve back buffer content
EGL uses the force_copy parameter to loader_dri3_swap_buffers_msc() to indicate
that it wants to preserve back buffer contents across a buffer swap.
While the loader then turns off server-side page-flipping there's nothing to
guarantee that a new backbuffer isn't chosen when EGL starts to render again,
and that buffer's content is of course undefined.
So rework the functionality:
If the client supports local blits, allow server-side page flipping and when
a new back is grabbed, if needed, blit the old back's content to the new back.
If the client doesn't support local blits, disallow server-side page-flipping
to avoid a client deadlock and then, when grabbing a new back buffer, sleep
until the old back is idle, which may take a substantial time depending on
swap interval.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Thu, 10 Aug 2017 13:59:58 +0000 (15:59 +0200)]
loader_dri3: Increase the likelyhood of reusing the current swap buffer
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Thu, 10 Aug 2017 13:35:39 +0000 (15:35 +0200)]
loader_dri3/glx/egl: Optionally use a blit context for blitting operations
The code was relying on us always having a current context for client local
image blit operations. Otherwise the blit would be skipped. However,
glxSwapBuffers, for example, doesn't require a current context and that was a
common problem in the dri1 era. It seems the problem has resurfaced with dri3.
If we don't have a current context when we want to blit, try creating a private
dri context and maintain a context cache of a single context.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Thomas Hellstrom [Fri, 11 Aug 2017 07:57:51 +0000 (09:57 +0200)]
loader_dri3/glx/egl: Remove the loader_dri3_vtable get_dri_screen callback
It's not very usable since in the rare, but definitely existing case that
we don't have a current context, it will return NULL.
Presumably it will always be safe to use the dri screen the drawable was
created with for operations on that drawable.
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Ilia Mirkin [Wed, 16 Aug 2017 04:33:34 +0000 (00:33 -0400)]
nv50/ir: fix TXQ srcMask
src0.x is always read for the LOD, irrespective of which outputs are
read.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Wed, 16 Aug 2017 04:25:40 +0000 (00:25 -0400)]
nv50/ir: fix srcMask computation for TG4 and TXF
This affects which inputs are marked as used. In a situation where only
the texture instruction uses an input, it might have been ignored as
unused due to input masks.
Affects subtests of KHR-GL45.texture_cube_map_array.sampling
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Jason Ekstrand [Thu, 17 Aug 2017 01:43:11 +0000 (18:43 -0700)]
anv/gem: Add a stub for sync_file_merge
This fixes make check
Fixes:
5c4e4932e02164e18cba9ae2cf3ec56afa2f2a6b
Dave Airlie [Wed, 16 Aug 2017 23:17:20 +0000 (00:17 +0100)]
radv: disable texture gather workaround on gfx9.
Not required anymore.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Brian Paul [Wed, 16 Aug 2017 15:50:34 +0000 (09:50 -0600)]
st/mesa: remove Windows hack for glFinish
I see no evidence that opengl32.dll's wglSwapBuffers calls glFinish.
It looks like Jose removed that dependency years ago, but this hack
remained.
Removing this code also fixes the Piglit sync_api test since commit
eceb6710024716.
No piglit regressions. No glretrace regressions, per Charmaine.
Fixes VMware bug 1937990.
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Frank Richter [Tue, 15 Aug 2017 13:46:35 +0000 (15:46 +0200)]
gallium/os: fix os_time_get_nano() to roll over less
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102241
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Frank Richter [Mon, 14 Aug 2017 14:05:22 +0000 (16:05 +0200)]
st/wgl: check for negative delta in wait_swap_interval()
This can happen because of rollover. See bug report for details.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102241
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Frank Richter [Wed, 7 Jun 2017 12:40:23 +0000 (14:40 +0200)]
st/mesa: fix a null pointer access
Fixes crash with llvmpipe on Windows.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102148
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Brian Paul <brianp@vmware.com>
Kenneth Graunke [Wed, 16 Aug 2017 23:09:29 +0000 (16:09 -0700)]
i965: Alphabetize TCS image dirty bits
Trivial.
Chris Wilson [Sat, 5 Aug 2017 09:39:59 +0000 (10:39 +0100)]
i965: Always allow CPU readback of the scanout on LLC platforms
LLC platforms are magic in that reads from the CPU are always cache
coherent, or rather GPU writes that bypass LLC do still invalidate the
appropriate cache line.
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Tim Rowley [Tue, 8 Aug 2017 01:33:24 +0000 (20:33 -0500)]
swr/rast: Fix invalid casting for calls to Interlocked* functions
CID: 1416243, 1416244, 1416255
CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Boyuan Zhang [Wed, 16 Aug 2017 18:24:29 +0000 (14:24 -0400)]
radeon/vce: support all firmwares with major ver 53
The vce firmware interface should now be stable, all firmwares with
major version equals to 53 are supported.
Signed-off-by: Boyuan Zhang <boyuan.zhang@amd.com>
Reviewed-by: Christian König <christian.koenig at amd.com>
Tapani Pälli [Tue, 15 Aug 2017 06:26:09 +0000 (09:26 +0300)]
i965: make sure check_and_emit_atom gets inlined
Improves performance of 3DMark "Ice Storm Unlimited" benchmark
by 1-2% on Apollolake (on Android-IA using clang 3.8.256229).
Change is based on the performance profiling work and results
by Aravindan Muthukumar and Yogesh Marathe.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Aravindan Muthukumar <aravindan.muthukumar@intel.com>
Signed-off-by: Yogesh Marathe <yogesh.marathe@intel.com>
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Ilia Mirkin [Tue, 15 Aug 2017 05:38:17 +0000 (01:38 -0400)]
a2xx: only update rasterizer settings when they're there
The rasterizer being empty can happen e.g. during clears
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 15 Aug 2017 03:38:52 +0000 (23:38 -0400)]
a2xx: add logicop support
This passes both gl-1.0-logicop and gl-1.1-xor piglits.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Tue, 15 Aug 2017 17:47:08 +0000 (13:47 -0400)]
glsl/ast: update rhs in addition to the var's constant_value
We continue in the code to do some more things with the rhs, including
setting a constant initializer. If the type is wrong, this causes some
confusion down the line, leading to assertions. This makes sure that the
rhs processing continues to flow as-if the type was correct to start
with (even though the state has been marked as an error state).
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101766
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: mesa-stable@lists.freedesktop.org
Jason Ekstrand [Thu, 13 Jul 2017 22:23:21 +0000 (15:23 -0700)]
anv: Advertise VK_KHR_external_semaphore
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 11 Apr 2017 01:36:42 +0000 (18:36 -0700)]
anv: Use DRM sync objects for external semaphores when available
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 11 Apr 2017 01:27:46 +0000 (18:27 -0700)]
anv/gem: Add a drm syncobj support
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Fri, 30 Jun 2017 17:26:58 +0000 (10:26 -0700)]
intel/drm: Pull in the i915 fence array API
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Wed, 10 May 2017 21:28:33 +0000 (14:28 -0700)]
anv: Implement support for exporting semaphores as FENCE_FD
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 28 Feb 2017 02:02:02 +0000 (18:02 -0800)]
anv/gem: Use EXECBUFFER2_WR when the FENCE_OUT flag is set
Reviewed-by: Chad Versace <chadversary@chromium.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Tue, 28 Feb 2017 00:34:13 +0000 (16:34 -0800)]
anv: Submit a dummy batch when only semaphores are provided.
Vulkan allows you to do a submit whose only job is to wait on and
trigger semaphores. The easiest way for us to support that right
now is to insert a dummy execbuf.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Jason Ekstrand [Thu, 13 Jul 2017 22:14:31 +0000 (15:14 -0700)]
anv: Add a basic implementation of VK_KHX_external_semaphore
This patch adds an implementation based on DRM BOs. We don't actually
advertise the extension yet because we want to add a couple more paths
first.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Aaron Watry [Fri, 4 Aug 2017 01:55:18 +0000 (20:55 -0500)]
clover/event: Include additional event statuses for clSetEventCallback
From CL 2.0 Section 5.11 (Event Objects):
clSetEventCallback returns CL_SUCCESS if the function is executed successfully. Otherwise, it
returns one of the following errors:
...
CL_INVALID_VALUE if pfn_event_notify is NULL or if command_exec_callback_type is
not CL_SUBMITTED , CL_RUNNING or CL_COMPLETE .
Fixes: OpenCL CTS test_conformance/events/test_events callbacks
Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Jonas Pfeil [Sat, 29 Jul 2017 19:23:52 +0000 (21:23 +0200)]
broadcom/vc4: Port NEON-code to ARM64
Changed all register and instruction names, works the same.
v2: Rebase on build system changes (by anholt)
v3: Fix build on clang (by anholt, reported by Rob)
Signed-off-by: Jonas Pfeil <pfeiljonas@gmx.de>
Tested-by: Rob Herring <robh@kernel.org>
Eric Anholt [Mon, 31 Jul 2017 21:59:38 +0000 (14:59 -0700)]
broadcom/vc4: Build the vc4_tiling_lt_neon.c with -mfpu=neon on ARM.
If you don't pass this, the compiler refuses to compile the assembly for
pre-v7 CPUs. This also keeps us from building identical, non-NEON code on
aarch64 and x86.
Fixes:
a373f77662c5 ("vc4: Use a wrapper file to set VC4_BUILD_NEON instead of CFLAGS.")
v2: Fix Android build by just appending NEON_C_SOURCES when
ARCH_ARM_HAVE_NEON.
Tested-by: Rob Herring <robh@kernel.org>
Eric Anholt [Mon, 31 Jul 2017 22:15:14 +0000 (15:15 -0700)]
configure.ac: Introduce HAVE_ARM_ASM/HAVE_AARCH64_ASM and the -D flags.
I've been trying to get away without these conditionals in vc4's NEON
code, but it meant compiling extra unused code on x86, and build failing
on ARMv6.
v2: Use the _arm/_arm64 flags to simplify detection (suggested by Rob),
but hide the _arm version under ARCH_ARM_HAVE_NEON to keep from trying
to build this stuff for armv5te.
Tested-by: Rob Herring <robh@kernel.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Anholt [Mon, 31 Jul 2017 21:47:12 +0000 (14:47 -0700)]
util: Fix build on old glibc.
We need to link librt for u_thread.h's clock_gettime() call.
Fixes:
b822d9dd67b5 ("gallium/util: move u_queue.{c,h} to src/util")
Reviewed-by: Matt Turner <mattst88@gmail.com>
Eric Anholt [Mon, 31 Jul 2017 22:04:02 +0000 (15:04 -0700)]
broadcom: Add v3d_xml.h to gitignore.
Eric Anholt [Mon, 31 Jul 2017 21:35:53 +0000 (14:35 -0700)]
broadcom: Add missing libexpat cflags for the decoder.
The Raspbian ARMv6 cross compiler wasn't picking up my (amd64) system copy
of the header the way that the system gcc and armhf cross-compile did.
Dave Airlie [Tue, 15 Aug 2017 05:28:09 +0000 (15:28 +1000)]
radv/gfx9: for fast clear use is_linear flag.
The legacy test won't work on gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
David Airlie [Tue, 15 Aug 2017 02:40:41 +0000 (12:40 +1000)]
radv/gfx9: fix tile swizzle handling for gfx9
This sets the tile swizzle up properly for gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
David Airlie [Tue, 15 Aug 2017 04:02:54 +0000 (14:02 +1000)]
radv/gfx9: handle GFX9 opaque metadata
port the opaque metadata changes from radeonsi for gfx9.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
David Airlie [Tue, 15 Aug 2017 04:20:16 +0000 (14:20 +1000)]
radv: emit db_htile_surface reg on gfx9 as well
This is also a GFX9 register.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 15 Aug 2017 05:18:04 +0000 (15:18 +1000)]
radv/gfx9: remove some leftover gfx6 descriptor setup.
We set this later in the non-gfx9 path, just remove these
bits from here.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Tue, 15 Aug 2017 05:17:38 +0000 (15:17 +1000)]
radv/gfx9: fix set predication packet.
The predication packet changed format on GFX9, update the driver.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Scott D Phillips [Fri, 4 Aug 2017 22:21:43 +0000 (22:21 +0000)]
intel/genxml: Fix gen10 BLEND_STATE variable length packing
BLEND_STATE packing was modified to be variable-length in:
9670124e31 genxml: Make BLEND_STATE command support variable length array.
The initial gen10.xml still had the old, fixed-length style
definition for BLEND_STATE. So gen10_upload_blend_state would
overwrite the packed BLEND_STATE_ENTRYs with its own fixed array
of all-zero entries when packing BLEND_STATE. This caused
BLEND_STATE upload to not work at all.
Fixes:
aa416f515a ("i965/genxml: Add gen10.xml")
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Timothy Arceri [Tue, 15 Aug 2017 10:42:29 +0000 (20:42 +1000)]
mesa: count uniform against storage when its bindless
Gallium drivers use this code path so we need to account for
bindless after all.
Fixes:
365d34540f33 ("mesa: correctly calculate the storage offset for i915")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Marek Olšák [Sun, 13 Aug 2017 17:22:06 +0000 (19:22 +0200)]
radeonsi: disable CE by default
It makes performance worse by a very small (hard to measure) amount.
We've done extensive profiling of this feature internally.
Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Christian König <christian.koenig@amd.com>
Dave Airlie [Mon, 14 Aug 2017 06:01:54 +0000 (07:01 +0100)]
radeonsi: initialise imported surface to 0.
For memobj imports we weren't setting the surface to 0, which
meant sometimes we'd end up with tile_swizzle garbage, which
would corrupt rendering.
This seems to fix the image corruption on the imported memory
objects in vrdashboard for me.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 1 Aug 2017 07:35:07 +0000 (17:35 +1000)]
st/mesa: correctly calculate the storage offset
When generating the storage offset for struct members we need
to skip opaque types as they no longer have backing storage.
Fixes:
fcbb93e86024 ("mesa: stop assigning unused storage for non-bindless opaque types")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101983
Reviewed-by: Dave Airlie <airlied@redhat.com>
Timothy Arceri [Tue, 1 Aug 2017 07:35:06 +0000 (17:35 +1000)]
mesa: correctly calculate the storage offset for i915
When generating the storage offset for struct members we need
to skip opaque types as they no longer have backing storage.
Fixes:
fcbb93e86024 ("mesa: stop assigning unused storage for non-bindless opaque types")
V2: simplify since bindless will never be supported in this code
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101983
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ben Widawsky [Tue, 30 May 2017 11:54:06 +0000 (17:24 +0530)]
i965: Advertise the CCS modifier
v2: Rename modifier to be more smart (Jason)
FINISHME: Use the kernel's final choice for the fb modifier
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube none
Read bandwidth: 603.91 MiB/s
Write bandwidth: 615.28 MiB/s
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ytile
Read bandwidth: 571.13 MiB/s
Write bandwidth: 555.51 MiB/s
bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube ccs
Read bandwidth: 259.34 MiB/s
Write bandwidth: 337.83 MiB/s
v2: Move all references to the new fourcc code(s) to this patch.
v3: Rebase, remove Yf_CCS (Daniel)
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Tue, 13 Jun 2017 21:27:37 +0000 (14:27 -0700)]
i965/miptree: More conservatively resolve external images
Instead of always doing a full resolve, only resolve the bits that are
needed. This means that we only do a partial resolve when the miptree
modifier is I915_FORMAT_MOD_Y_TILED_CCS.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Ben Widawsky [Tue, 30 May 2017 11:53:59 +0000 (17:23 +0530)]
i965: Pretend that CCS modified images are two planes
v2: move is_aux into if block. (Jason)
Use else block instead of goto (Jason)
v3: Fix up logic for is_aux (Ben)
Fix up size calculations and add FIXME (Ben)
v4 (Jason Ekstrand):
Use the aux_pitch in the image instead of calculating it
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Fri, 14 Jul 2017 22:53:26 +0000 (15:53 -0700)]
i965/screen: Support import and export of surfaces with CCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Ben Widawsky [Tue, 30 May 2017 11:53:50 +0000 (17:23 +0530)]
i965/miptree: Allocate mcs_buf for an image's CCS
This code will disable actually creating these buffers for the scanout,
but it puts the allocation in place.
Primarily this patch is split out for review, it can be squashed in
later if preferred.
v2:
assert(mt->offset == 0) in ccs creation (as requested by Topi)
Remove bogus is_scanout check in miptree_release
v3:
Remove is_scanout assert in intel_miptree_create. It doesn't work with
latest codebase - not sure it ever should have worked.
v4:
assert(mt->last_level == 0) and assert(mt->first_level == 0) in ccs setup
(Topi)
v5 (Jason Ekstrand):
- Base the decision to allocate a CCS on the image modifier
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Ben Widawsky [Tue, 30 May 2017 11:53:50 +0000 (17:23 +0530)]
i965: Support images with aux buffers
Previously images did not support any auxiliary compression surfaces
(CCS, MCS, or HiZ). That's about to change. This patch just adds the
fields to __DRIimageRec to make auxiliary surfaces possible.
v2 (Jason Ekstrand):
- Add an aux_pitch parameter as well as aux_offset
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Tue, 13 Jun 2017 19:06:49 +0000 (12:06 -0700)]
intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Jason Ekstrand [Mon, 14 Aug 2017 17:08:14 +0000 (10:08 -0700)]
i965/screen: Stop redefining DRM_FORMAT_MOD_(INVALID|LINEAR)
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Jason Ekstrand [Mon, 14 Aug 2017 17:03:43 +0000 (10:03 -0700)]
drm-uapi/forcc: Pull in new modifiers
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Scott D Phillips [Wed, 9 Aug 2017 22:52:30 +0000 (15:52 -0700)]
i965/blorp: Correct type of src_format in call to intel_miptree_texture_aux_usage
intel_miptree_texture_aux_usage() takes an isl_format, but we are
passing a mesa_format. clang warns:
brw_blorp.c:305:52: warning: implicit conversion from enumeration
type 'mesa_format' to different enumeration type
'enum isl_format' [-Wenum-conversion]
intel_miptree_texture_aux_usage(brw, src_mt, src_format);
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ ^~~~~~~~~~
Fixes:
fc1639e46d ("i965/blorp: Use texture/render_aux_usage for blits")
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Julien Isorce [Tue, 25 Jul 2017 14:31:28 +0000 (15:31 +0100)]
st/va: change frame_idx from array to hash table
The picture_id was assumed to be a frame number so in 0-31.
But the vaapi client gstreamer-vaapi uses the surfaces handles
as identifier which are unsigned int.
This bug can happen when using a lot of vaapi surfaces within
the same process. Indeed Mesa/st/va increments a counter for the
surface ID: mesa/util/u_handle_table.c::handle_table_add which
starts from 0 and incremented by 1 at each call.
So creating more than 32 surfaces was a problem.
The following bug contains a test that reproduces the problem
by running a couple of vaapih264enc in the same process. The
above also explains why there was no pb when running them in
separated processes.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102006
Signed-off-by: Julien Isorce <jisorce@oblong.com>
Tested-by: Tomas Rataj <rataj28@gmail.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-and-tested-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Michel Dänzer [Tue, 8 Aug 2017 07:20:55 +0000 (16:20 +0900)]
configure: Trust LLVM >= 4.0 llvm-config --libs for shared libraries
No need to manually look for the library files anymore with current
LLVM. This sidesteps the manual method failing when LLVM was built with
-DLLVM_APPEND_VC_REV=ON.
(This might already work with older versions of LLVM)
Acked-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Ilia Mirkin [Sat, 12 Aug 2017 17:43:34 +0000 (13:43 -0400)]
nv50/ir: clean up saturated values immediately
Since we don't iterate to a fixed point, we can end up in situations
where we have a SAT instruction + a long immediate. This is not legal.
However since it's immediately computable, just run unary straight away
to handle the situation.
Fixes:
24a799ad35a82 ("nv50/ir: fix ConstantFolding with saturation")
Reported-by: Tobias Klausmann <tobias.johannes.klausmann@mni.thm.de>
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
Ilia Mirkin [Sat, 12 Aug 2017 04:02:34 +0000 (00:02 -0400)]
nvc0/ir: unlink values pre- and post-call to division function
While technically correct, this can lead to e.g. getImmediate assuming
that it can walk up the value chain. It could be fixed to not do this,
but it seems easier and less error-prone to just not link the two values
to save on one LValue object.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Fri, 11 Aug 2017 04:10:31 +0000 (21:10 -0700)]
i965: Guard GetBufferSubData's streaming memcpy load with USE_SSE41
This should hopefully fix build issues on 32-bit Android-x86.
v2: s/USE_SSE4_1/USE_SS41/, caught by Gražvydas Ignotas.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102050
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Kenneth Graunke [Fri, 11 Aug 2017 03:47:53 +0000 (20:47 -0700)]
i965: Clean up intel_batchbuffer_init().
Passing screen lets us get the kernel features, devinfo, and bufmgr,
without needing container_of.
This use of container_of could cause crashes due to issues with the
"sample" macro parameter.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102062
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Marek Olšák [Thu, 10 Aug 2017 10:22:33 +0000 (12:22 +0200)]
gallium/radeon: only pass shader-specific debug flags to the disk shader cache
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Marek Olšák [Thu, 10 Aug 2017 19:50:59 +0000 (21:50 +0200)]
radeonsi/gfx9: fix the scissor bug workaround
otherwise there is corruption in most apps.
Fixes: 0fe0320 radeonsi: use optimal packet order when doing a pipeline sync
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Marek Olšák [Thu, 10 Aug 2017 20:29:54 +0000 (22:29 +0200)]
radeonsi/gfx9: use the VI codepath for clamping Z
This fixes corrupted shadows in Unigine Valley.
The corruption disappeared when I stopped setting IMG_DATA_FORMAT_24_8
for depth.
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Daniel Stone [Mon, 31 Jul 2017 14:08:29 +0000 (15:08 +0100)]
egl: Update headers from Khronos
Taken from egl-registry
7d68647c4dab.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Daniel Stone [Mon, 31 Jul 2017 17:34:57 +0000 (18:34 +0100)]
egl/dri2: Allow modifiers to add FDs to imports
When using dmabuf import, make sure that the modifier is actually
allowed to add planes to the base format, as implied by the comment.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Iago Toral Quiroga [Fri, 21 Jul 2017 08:26:31 +0000 (10:26 +0200)]
intel/compiler: properly size attribute wa_flags array for Vulkan
Mesa will map user defined vertex input attributes to slots
starting at VERT_ATTRIB_GENERIC0 which gives us room for only 16
slots (up to GL_VERT_ATTRIB_MAX). This sufficient for GL, where
we expose exactly 16 vertex attributes for user defined inputs, but
in Vulkan we can expose up to 28 (which are also mapped from
VERT_ATTRIB_GENERIC0 onwards) so we need to account for this when
we scope the size of the array of attribute workaround flags
that is used during the brw_vertex_workarounds NIR pass. This
prevents out-of-bounds accesses in that array for NIR shaders
that use more than 16 vertex input attributes.
Fixes:
dEQP-VK.pipeline.vertex_input.max_attributes.*
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Timothy Arceri [Wed, 9 Aug 2017 03:34:07 +0000 (13:34 +1000)]
glsl: stop cloning builtin fuctions _mesa_glsl_find_builtin_function()
The cloning was introduced in
f81ede469910d to fix a problem with
shaders including IR that was owned by builtins.
However the approach of cloning the whole function each time we
reference a builtin lead to a significant reduction in the GLSL
IR compilers performance.
The previous patch fixes the ownership problem in a more precise
way. So we can now remove this cloning.
Testing on a Ryzen 7 1800X shows a ~15% decreases in compiling the
Deus Ex: Mankind Divided shaders on radeonsi (which take 5min+ on
some machines). Looking just at the GLSL IR compiler the speed up
is ~40%.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Timothy Arceri [Thu, 10 Aug 2017 10:42:29 +0000 (20:42 +1000)]
glsl: pass mem_ctx to constant_expression_value(...) and friends
The main motivation for this is that threaded compilation can fall
over if we were to allocate IR inside constant_expression_value()
when calling it on a builtin. This is because builtins are shared
across the whole OpenGL context.
f81ede469910d worked around the problem by cloning the entire
builtin before constant_expression_value() could be called on
it. However cloning the whole function each time we referenced
it lead to a significant reduction in the GLSL IR compiler
performance. This change along with the following patch
helps fix that performance regression.
Other advantages are that we reduce the number of calls to
ralloc_parent(), and for loop unrolling we free constants after
they are used rather than leaving them hanging around.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>