platform/kernel/u-boot.git
2 years agofpga: pass compatible flags to fpga_load()
Oleksandr Suvorov [Fri, 22 Jul 2022 14:16:07 +0000 (17:16 +0300)]
fpga: pass compatible flags to fpga_load()

These flags may be used to check whether an FPGA driver is able to
load a particular FPGA bitstream image.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-7-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: xilinx: pass compatible flags to xilinx_load()
Oleksandr Suvorov [Fri, 22 Jul 2022 14:16:06 +0000 (17:16 +0300)]
fpga: xilinx: pass compatible flags to xilinx_load()

This flag is used to check whether a Xilinx FPGA driver is able to
load a particular FPGA bitstream image.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-6-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: zynqmp: add str2flags call
Oleksandr Suvorov [Fri, 22 Jul 2022 14:16:05 +0000 (17:16 +0300)]
fpga: zynqmp: add str2flags call

Add a call to convert FPGA "compatible" string to a binary flag.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-5-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: xilinx: add bitstream flags to driver desc
Oleksandr Suvorov [Fri, 22 Jul 2022 14:16:04 +0000 (17:16 +0300)]
fpga: xilinx: add bitstream flags to driver desc

Store a set of supported bitstream types in xilinx_desc structure.
It will be used to determine whether an FPGA image is able to be
loaded with a given driver.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-4-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: xilinx: add missed identifier names
Oleksandr Suvorov [Fri, 22 Jul 2022 14:16:03 +0000 (17:16 +0300)]
fpga: xilinx: add missed identifier names

Function definition arguments should also have identifier names.
Add missed ones to struct xilinx_fpga_op callbacks, unifying code.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-3-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: add option for loading FPGA secure bitstreams
Oleksandr Suvorov [Fri, 22 Jul 2022 14:16:02 +0000 (17:16 +0300)]
fpga: add option for loading FPGA secure bitstreams

It allows using this feature without enabling the "fpga loads"
command.

Signed-off-by: Oleksandr Suvorov <oleksandr.suvorov@foundries.io>
Co-developed-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Signed-off-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Tested-by: Ricardo Salveti <ricardo@foundries.io>
Tested-by: Adrian Fiergolski <adrian.fiergolski@fastree3d.com>
Link: https://lore.kernel.org/r/20220722141614.297383-2-oleksandr.suvorov@foundries.io
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig
Alexander Dahl [Thu, 21 Jul 2022 13:31:22 +0000 (15:31 +0200)]
fpga: Convert SYS_FPGA_PROG_FEEDBACK to Kconfig

This converts the following to Kconfig: SYS_FPGA_PROG_FEEDBACK

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20220721133122.32428-3-ada@thorsis.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agofpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig
Alexander Dahl [Thu, 21 Jul 2022 13:31:21 +0000 (15:31 +0200)]
fpga: Convert SYS_FPGA_CHECK_CTRLC to Kconfig

After commit 8cca60a2cbf2 ("Kconfig: Remove some symbols from the
whitelist") downstream builds failed for boards setting this in
include/configs/…

Signed-off-by: Alexander Dahl <ada@thorsis.com>
Link: https://lore.kernel.org/r/20220721133122.32428-2-ada@thorsis.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoarm64: versal: Enable power domain driver and its dependencies
Ashok Reddy Soma [Fri, 22 Jul 2022 08:46:58 +0000 (02:46 -0600)]
arm64: versal: Enable power domain driver and its dependencies

Enable power domain driver to configure pmufw config object and request
node for all the IP's that are enabled in DT.

This driver depends on mailbox and IPI driver, hence enable them as well.
Add ARCH_VERSAL in the depends on of mailbox Kconfig to compile for
Versal platforms.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220722084658.30995-6-ashok.reddy.soma@xilinx.com
2 years agomailbox: zynqmp: Move struct zynqmp_ipi_msg from sys_proto.h
Ashok Reddy Soma [Fri, 22 Jul 2022 08:46:57 +0000 (02:46 -0600)]
mailbox: zynqmp: Move struct zynqmp_ipi_msg from sys_proto.h

Mailbox driver might be need for Versal and other future platforms.
To remove the dependency, move struct zynqmp_ipi_msg to
zynqmp_firmware.h so that mailbox driver compiles for other platforms
easily.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220722084658.30995-5-ashok.reddy.soma@xilinx.com
2 years agoarm64: zynqmp: Enable power domain driver
Ashok Reddy Soma [Fri, 22 Jul 2022 08:46:56 +0000 (02:46 -0600)]
arm64: zynqmp: Enable power domain driver

Enable power domain driver to configure pmufw config object and request
node for all the IP's that are enabled in DT.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220722084658.30995-4-ashok.reddy.soma@xilinx.com
2 years agofirmware: zynqmp: Load config overlay for core0 to pmufw
Ashok Reddy Soma [Fri, 22 Jul 2022 08:46:55 +0000 (02:46 -0600)]
firmware: zynqmp: Load config overlay for core0 to pmufw

Try loading pmufw config overlay for core0, if it doesn't return any
error it means pmufw is accepting nodes for other IP's. Otherwise dont
try to load config object for any other IP, just return from
zynqmp_pmufw_node function.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220722084658.30995-3-ashok.reddy.soma@xilinx.com
2 years agofirmware: zynqmp: Change prototype of zynqmp_pmufw_load_config_object()
Ashok Reddy Soma [Fri, 22 Jul 2022 08:46:54 +0000 (02:46 -0600)]
firmware: zynqmp: Change prototype of zynqmp_pmufw_load_config_object()

zynqmp_pmufw_load_config_object() has some error cases and it is better
to return those errors. Change prototype of this function to return
errors.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/20220722084658.30995-2-ashok.reddy.soma@xilinx.com
2 years agoarm64: zynqmp: Enable reset driver
Ashok Reddy Soma [Wed, 20 Jul 2022 09:59:59 +0000 (03:59 -0600)]
arm64: zynqmp: Enable reset driver

Enable reset driver for ZynqMP platforms. This will enable us to reset
the IP's using generic reset_assert and reset_deassert calls.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220720095959.29610-4-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoarm64: versal: Enable reset driver for versal
Michal Simek [Wed, 20 Jul 2022 09:59:58 +0000 (03:59 -0600)]
arm64: versal: Enable reset driver for versal

Add CONFIG_DM_RESET and CONFIG_RESET_ZYNQMP configs in versal default
configuration to enable support for reset driver for versal
platform.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Signed-off-by: T Karthik Reddy <t.karthik.reddy@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220720095959.29610-3-ashok.reddy.soma@xilinx.com
2 years agoreset: zynqmp: Add reset driver support for versal
T Karthik Reddy [Wed, 20 Jul 2022 09:59:57 +0000 (03:59 -0600)]
reset: zynqmp: Add reset driver support for versal

Add support for versal platform by adding "xlnx,versal-reset"
compatible string in zynqmp-reset driver. Reset numbering schema
for versal is not same as zynqmp, so nr_reset and reset_id are
set to zero. In case of assert/dessert, required device reset id
is sent from respective driver through struct reset_ctl.

Signed-off-by: T Karthik Reddy <t.karthik.reddy@amd.com>
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/20220720095959.29610-2-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoxilinx: common: Use strlcpy instead of strncpy
Michal Simek [Thu, 21 Jul 2022 14:19:18 +0000 (16:19 +0200)]
xilinx: common: Use strlcpy instead of strncpy

It is recommendation done by checkpatch to all the time have \0 terminated
strings.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c7bfab50c40f6213f1b347b5e4674e382e83cb94.1658413156.git.michal.simek@amd.com
2 years agoxilinx: Wire uuid reading from FRU
Michal Simek [Thu, 21 Jul 2022 14:19:17 +0000 (16:19 +0200)]
xilinx: Wire uuid reading from FRU

UUID is already recorded when FRU is parsed but it is not copied to local
structures and exported to variable that's why simply add it.
Data is saved in binary format but there must be conversion to string for
exporting it to variable and string should be in uuid format too.

One way how to use it directly is to setup pxeuuid based on it. For
example via preboot with "setenv pxeuuid ${board_uuid}"

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1dfa4b4220a508abc05351da2119880811b77612.1658413156.git.michal.simek@amd.com
2 years agoserial: zynq: Use DIV_ROUND_CLOSEST() to calcurate divider value
Kunihiko Hayashi [Wed, 13 Jul 2022 01:38:59 +0000 (10:38 +0900)]
serial: zynq: Use DIV_ROUND_CLOSEST() to calcurate divider value

Since the calulation of "bgen" is rounded down, using a higher
baudrate will result in a larger difference from the actual
baudrate. Should use DIV_ROUND_CLOSEST() like the Linux driver.

Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com>
Link: https://lore.kernel.org/r/1657676339-6055-1-git-send-email-hayashi.kunihiko@socionext.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agotools: relocate-rela: Define all macros for e_machine and reloc types
Michal Simek [Fri, 8 Jul 2022 06:15:06 +0000 (08:15 +0200)]
tools: relocate-rela: Define all macros for e_machine and reloc types

With some old toolchain not all values should be available that's why
better to define all of them to avoid compilation issues.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/e2a66854c5506100eb82b5b33cec7f0b5fca1008.1657260903.git.michal.simek@amd.com
2 years agotools: relocate-rela: Remove guard around R_AARCH64_RELATIVE
Michal Simek [Fri, 8 Jul 2022 06:15:05 +0000 (08:15 +0200)]
tools: relocate-rela: Remove guard around R_AARCH64_RELATIVE

In code you can find out this fragment:
 19 #ifndef R_AARCH64_RELATIVE
 20 #define R_AARCH64_RELATIVE      1027
 21 #endif

which means that R_AARCH64_RELATIVE is defined all the time that's why
ifdef is not needed.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/0d40a09ab6edcd88ba3059f7a0b63a819b71256a.1657260903.git.michal.simek@amd.com
2 years agodt-bindings: versal: Add versal reset IDs
Michal Simek [Thu, 7 Jul 2022 11:10:53 +0000 (13:10 +0200)]
dt-bindings: versal: Add versal reset IDs

The same file is already the part of Linux kernel that's why add it also to
u-boot to be able to use it in source code and DT files.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1c3bc464536a9bf64a2e8bfe18a938c9cb490620.1657192249.git.michal.simek@amd.com
2 years agoxilinx: Remove duplicate PMIO_NODE_ID_BASE macro
Michal Simek [Thu, 7 Jul 2022 11:06:16 +0000 (13:06 +0200)]
xilinx: Remove duplicate PMIO_NODE_ID_BASE macro

PMIO_NODE_ID_BASE is defined twice that's why remove one instance.

Fixes: 248fe9f302df ("spi: cadence_qspi: Enable apb linear mode for apb read & write operations")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ce9a601bb99418aa20272d046c74678829d942cc.1657191974.git.michal.simek@amd.com
2 years agotest/py: Run simple dm commands without checking
Michal Simek [Thu, 7 Jul 2022 10:59:42 +0000 (12:59 +0200)]
test/py: Run simple dm commands without checking

Just to make sure that dm commands can operate.
This was the problem on Microblaze in past without fixing manual
relocation.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/e6c4b8b44445c16cee84436627642ccc9886f507.1657191580.git.michal.simek@amd.com
2 years agopy: tests: Bind should run only on sandbox
Michal Simek [Thu, 7 Jul 2022 10:52:26 +0000 (12:52 +0200)]
py: tests: Bind should run only on sandbox

Disable test to run on any other platform than sandbox.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/786bfdfda7dee4494e39c3fff699970ecd623116.1657191142.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Disable LMB for mini configurations
Michal Simek [Thu, 7 Jul 2022 08:45:38 +0000 (10:45 +0200)]
arm64: zynqmp: Disable LMB for mini configurations

There is no need to have LMB enabled that's why save some space by
disabling it.

   aarch64: (for 8/8 boards) all -1168.5 rodata -105.5 text -1063.0
            xilinx_zynqmp_mini: all -2013 rodata -185 text -1828
            xilinx_zynqmp_mini_qspi: all -2013 rodata -185 text -1828
            xilinx_zynqmp_mini_emmc0: all -2661 rodata -237 text -2424
            xilinx_zynqmp_mini_emmc1: all -2661 rodata -237 text -2424

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/f735d7691f4e7a7958d985b22c40aeb26e37a404.1657183534.git.michal.simek@amd.com
2 years agozynqmp: Run board_get_usable_ram_top() only on main U-Boot
Ashok Reddy Soma [Thu, 7 Jul 2022 08:45:37 +0000 (10:45 +0200)]
zynqmp: Run board_get_usable_ram_top() only on main U-Boot

With commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory
location"), the function board_get_usable_ram_top() is allocating
MMU_SECTION_SIZE of about 2MB using lmb_alloc(). But we dont have this
much memory in case of mini U-Boot.

Keep these functions which use lmb under CONFIG_LMB so that they are
compiled and used only when LMB is enabled.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/75e52def75f573e554a6b177a78504c128cb0c4a.1657183534.git.michal.simek@amd.com
2 years agolmb: Fix lmb property's defination under struct lmb
Ashok Reddy Soma [Thu, 7 Jul 2022 08:45:36 +0000 (10:45 +0200)]
lmb: Fix lmb property's defination under struct lmb

Under struct lmb {} the lmb property's should be defined only if
CONFIG_LMB_MEMORY_REGIONS is defined.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/c24a2b1d6f5db4eb65393f6a77fae129b30b6233.1657183534.git.michal.simek@amd.com
2 years agoarm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED
Michal Simek [Thu, 7 Jul 2022 08:47:16 +0000 (10:47 +0200)]
arm: riscv: Remove additional ifdef from code guarded by CONFIG_IS_ENABLED

CONFIG_OF_LIBFDT is used twice for guarding the same code. It is enough to
do it once that's why remove additional ifdefs from arm and risc-v code.

Fixes: 0c303f9a6628 ("image: Drop IMAGE_ENABLE_OF_LIBFDT")
Signed-off-by: Michal Simek <michal.simek@amd.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://lore.kernel.org/r/f8e3ff9124195cbd957874de9a65ef79760ef5e7.1657183634.git.michal.simek@amd.com
2 years agoarm64: zynqmp: Enable SLG gpo driver by default
Michal Simek [Mon, 4 Jul 2022 14:09:00 +0000 (16:09 +0200)]
arm64: zynqmp: Enable SLG gpo driver by default

This device is used on SOM CCs that's why enable it by default.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/ebbfc0c883ca7d4f70c75d8d3655aaa6a81d77be.1656943737.git.michal.simek@amd.com
2 years agoxilinx: zynqmp: Do not use 0 as spl bss start address
Stefan Herbrechtsmeier [Thu, 14 Jul 2022 13:47:33 +0000 (15:47 +0200)]
xilinx: zynqmp: Do not use 0 as spl bss start address

Do not use 0 as address for memory because of the special meaning for
pointers (null pointer). Change the spl bss start address to the second
page.

Signed-off-by: Stefan Herbrechtsmeier <stefan.herbrechtsmeier@weidmueller.com>
Link: https://lore.kernel.org/r/20220714134733.7487-1-stefan.herbrechtsmeier-oss@weidmueller.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agotools: relocate-rela: Fix ELF decoding on big-endian hosts
Samuel Holland [Fri, 15 Jul 2022 06:40:25 +0000 (01:40 -0500)]
tools: relocate-rela: Fix ELF decoding on big-endian hosts

The new ELF decoding logic assumed that the target binary has the same
endianness as the host, which broke building ARM64 firmware binaries on
big-endian machines.

This commit fixes the ELF64 decoding to be host-endianness-neutral, and
applies the same changes to the ELF32 decoding. It does not fix the
microblaze-specific dynamic symbol decoding.

It also corrects the functions used for byte swapping in rela_elf64()
and rela_elf32(). The result is the same, but semantically the code is
converting bytes read from a foreign-endianness file to host byte order.

Fixes: 4c9e2d643460 ("tools: relocate-rela: Read rela start/end directly from ELF")
Fixes: a1405d9cfedb ("tools: relocate-rela: Check that relocation works only for EM_AARCH64")
Signed-off-by: Samuel Holland <samuel@sholland.org>
Link: https://lore.kernel.org/r/20220715064026.54551-1-samuel@sholland.org
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agommc: zynq_sdhci: Fix timing macros for MMC High speed
Ashok Reddy Soma [Mon, 27 Jun 2022 08:52:45 +0000 (14:22 +0530)]
mmc: zynq_sdhci: Fix timing macros for MMC High speed

Timing macro's are wrong for MMC_HS_52 and MMC_DDR_52. Fix it with
correct values of MMC_TIMING_MMC_HS and MMC_TIMING_MMC_DDR52 respectively.

Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com>
Link: https://lore.kernel.org/r/1656319965-12124-1-git-send-email-ashok.reddy.soma@xilinx.com
Signed-off-by: Michal Simek <michal.simek@amd.com>
2 years agoarm64: zynqmp: Used fixed-partitions for QSPI in k26
Michal Simek [Wed, 29 Jun 2022 09:13:14 +0000 (11:13 +0200)]
arm64: zynqmp: Used fixed-partitions for QSPI in k26

Using fixed partitions is recommended way how to describe QSPI. Also add
label for qspi flash memory to be able to reference it in future.

Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/a84f7ce8d6472fce66539ba29d31fbaae511d94b.1655732762.git.michal.simek@amd.com
2 years agoxilinx: Remove the legacy property "#stream-id-cells"
Ayan Kumar Halder [Wed, 22 Jun 2022 08:26:57 +0000 (10:26 +0200)]
xilinx: Remove the legacy property "#stream-id-cells"

"#stream-id-cells" was being used with "mmu-masters" for Xen specific
device trees.
With Xen commit 2278d2cbb0b7c1b48b298c6c4c6a7de2271ac928 (Link below)
Xen is able to support smmu bindings in both formats ie :
1. Using iommus (linux format)
2. Using mmu-masters (legacy format).

Thus, "#stream-id-cells" which was used for the legacy format, can be
removed as Xen can use smmu bindings in linux format.

Link: https://www.mail-archive.com/xen-devel@lists.xenproject.org/msg101649.html
Signed-off-by: Ayan Kumar Halder <ayankuma@amd.com>
Signed-off-by: Michal Simek <michal.simek@amd.com>
Link: https://lore.kernel.org/r/1e062acb233dee47cd7dd2429cb482132617cbc8.1655886415.git.michal.simek@amd.com
2 years agoPrepare v2022.10-rc1
Tom Rini [Tue, 26 Jul 2022 00:31:12 +0000 (20:31 -0400)]
Prepare v2022.10-rc1

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoconfigs: Resync with savedefconfig
Tom Rini [Mon, 25 Jul 2022 21:19:18 +0000 (17:19 -0400)]
configs: Resync with savedefconfig

Resync all defconfig files using moveconfig.py

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agoMerge branch '2022-07-25-assorted-platform-updates'
Tom Rini [Mon, 25 Jul 2022 20:40:43 +0000 (16:40 -0400)]
Merge branch '2022-07-25-assorted-platform-updates'

- Assorted TI, Apple, Snapdragon and Xen updates.

2 years agodrivers: xen: unmap Enlighten page before jumping to Linux
Dmytro Firsov [Tue, 19 Jul 2022 14:55:28 +0000 (14:55 +0000)]
drivers: xen: unmap Enlighten page before jumping to Linux

This commit fixes issue with usage of Xen hypervisor shared info page.
Previously U-boot did not unmap it at the end of OS boot process. Xen
did not prevent guest from this. So, it worked, but caused wierd
issues - one memory page, that was returned by memalign in U-boot
for Enlighten mapping was not unmaped by Xen (shared_info values was
not removed from there) and returned to allocator. During the Linux
boot, it uses shared_info page as regular RAM page, which leads to
hypervisor shared info corruption.

So, to fix this issue, as discussed on the xen-devel mailing list, the
code should:
   1) Unmap the page
   2) Populate the area with memory using XENMEM_populate_physmap

This patch adds page unmapping via XENMEM_remove_from_physmap, fills
hole in address space where page was mapped via XENMEM_populate_physmap
and return this address to memory allocator for freeing.

Signed-off-by: Dmytro Firsov <dmytro_firsov@epam.com>
Reviewed-by: Anastasiia Lukianenko <vicooodin@gmail.com>
2 years agoarm: Remove unused references to CONFIG_SOC_DM*
Tom Rini [Mon, 18 Jul 2022 15:33:39 +0000 (11:33 -0400)]
arm: Remove unused references to CONFIG_SOC_DM*

There are no references to CONFIG_SOC_DM355 / CONFIG_SOC_DM365 /
CONFIG_SOC_DM644X / CONFIG_SOC_DM646X and the files these Makefile lines
reference have already been dropped.

Signed-off-by: Tom Rini <trini@konsulko.com>
2 years agospl: Use SPL_TEXT_BASE instead of ISW_ENTRY_ADDR
Andrew Davis [Fri, 15 Jul 2022 17:31:48 +0000 (12:31 -0500)]
spl: Use SPL_TEXT_BASE instead of ISW_ENTRY_ADDR

The ISW_ENTRY_ADDR symbol was used for OMAP devices in place of
SPL_TEXT_BASE. Keystone2 HS devices were not using it right either.
Remove ISW_ENTRY_ADDR and use SPL_TEXT_BASE directly.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoarm: k3: config.mk: Read software revision information from file on HS
Andrew Davis [Fri, 15 Jul 2022 16:38:54 +0000 (11:38 -0500)]
arm: k3: config.mk: Read software revision information from file on HS

Read the swrv.txt file from the TI Security Development Tools when
TI_SECURE_DEVICE is enabled. This allows us to set our software
revision in one place and have it used by all the tools that create
TI x509 boot certificates.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agok3_gen_x509_cert: Make SWRV configurable for anti-rollback protection
Yogesh Siraswar [Fri, 15 Jul 2022 16:38:53 +0000 (11:38 -0500)]
k3_gen_x509_cert: Make SWRV configurable for anti-rollback protection

The x509 certificate SWRV is currently hard-coded to 0. This need to be
updated to 1 for j721e 1.1, j7200 and am64x. It is don't care for other
k3 devices.

Added new config K3_X509_SWRV to k3. Default is set to 1.

Signed-off-by: Yogesh Siraswar <yogeshs@ti.com>
Reviewed-by: Dave Gerlach <d-gerlach@ti.com>
2 years agoarm: mach-k3: Remove ROM firewalls on GP devices
Andrew Davis [Fri, 15 Jul 2022 16:21:27 +0000 (11:21 -0500)]
arm: mach-k3: Remove ROM firewalls on GP devices

This isn't strictly needed as these firewalls should all be disabled on
GP, but it also doesn't hurt, so do this unconditionally to remove this
use of CONFIG_TI_SECURE_DEVICE.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agodefconfigs: j721e_hs_evm: Sync HS and non-HS defconfigs
Andrew Davis [Fri, 15 Jul 2022 16:19:41 +0000 (11:19 -0500)]
defconfigs: j721e_hs_evm: Sync HS and non-HS defconfigs

Additions have been made to the non-HS defconfig without the same
being made to the HS defconfig, sync them.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agodefconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigs
Andrew Davis [Fri, 15 Jul 2022 16:19:39 +0000 (11:19 -0500)]
defconfigs: am57xx_hs_evm: Sync HS and non-HS defconfigs

Sync new additions to non-HS defconfig with HS defconfig.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agodefconfigs: Add a config for AM43xx HS EVM with QSPI Boot support
Andrew Davis [Fri, 15 Jul 2022 15:58:49 +0000 (10:58 -0500)]
defconfigs: Add a config for AM43xx HS EVM with QSPI Boot support

On AM43xx HS devices, QSPI boot is XIP and we use a single stage
bootloader. Add a defconfig for this.

Signed-off-by: Andrew Davis <afd@ti.com>
2 years agoarm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654
Andrew Davis [Fri, 15 Jul 2022 15:25:27 +0000 (10:25 -0500)]
arm: mach-k3: Rename SOC_K3_AM6 to SOC_K3_AM654

The first AM6x device was the AM654x, but being the first we named it
just AM6, since more devices have come out with this same prefix we
should switch it to the normal convention of using the full name of the
first compatibility device the series. This makes what device we are
talking about more clear and matches all the K3 devices added since.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoarm: mach-k3: Only build init files for SPL
Andrew Davis [Fri, 15 Jul 2022 15:25:26 +0000 (10:25 -0500)]
arm: mach-k3: Only build init files for SPL

The content of these files are only used in SPL builds. The contents are
already ifdef for the same, remove that and only include the whole file
in the build when building for SPL.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoarm: dts: db410c/db820c: Fix SPMI addresses
Stephan Gerhold [Wed, 13 Jul 2022 19:17:11 +0000 (21:17 +0200)]
arm: dts: db410c/db820c: Fix SPMI addresses

The Qualcomm device trees in U-Boot are currently not consistent with
the upstream DTs used in the Linux kernel. While some bindings are
similar to the official specification in the Linux kernel, several
nodes have subtle differences, e.g. the "compatible"s or the exact
specification of memory registers.

This means that some of the Qualcomm-related U-Boot drivers are not
compatible with the Linux DT (and vice versa).

The SPMI node is one such example: the "core" region starts at
0x0200f000 in the upstream Linux MSM8916 DT, but in U-Boot it starts at
0x0200f800. The end result is normally the same, since the Linux SPMI
driver simply adds the 0x800 internally.

However, commit f5a2d6b4b03a ("spmi: msm: add arbiter version 5
support") imported this behavior into the U-Boot driver, without
adjusting the DB410c/DB820c device trees. This means that the 0x800
offset is now added twice, breaking all SPMI read/write operations:

  Failed to find PMIC pon node. Check device tree
  Failed to find pm8916_gpios@c000 node.
  USB init failed: -6
  starting USB...
  Bus ehci@78d9000: Failed to find pm8916_gpios@c000 node.
  probe failed, error -6
  No working controllers found

While the mistake is strictly speaking in the spmi-msm driver, fix the
issue by making the SPMI nodes in the DB410c/DB820c consistent with the
upstream Linux DT instead.

Ideally we should even go a step further by fixing the remaining uses
of custom bindings in the U-Boot drivers and moving to using the Linux
DTs as-is. This would likely avoid such mistakes in the future and
would also make the porting process much easier.

Cc: Dzmitry Sankouski <dsankouski@gmail.com>
Fixes: f5a2d6b4b03a ("spmi: msm: add arbiter version 5 support")
Signed-off-by: Stephan Gerhold <stephan@gerhold.net>
Reviewed-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoboard: ti: am65x: Do not disable SA2UL in DT
Andrew Davis [Wed, 13 Jul 2022 16:12:48 +0000 (11:12 -0500)]
board: ti: am65x: Do not disable SA2UL in DT

This is no longer needed as the SA2UL can now be shared with Linux.
Leave the SA2UL DT node enabled.

Signed-off-by: Andrew Davis <afd@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoarmv8: mach-k3: correct define checking for AM625/AM642 memory maps
Matt Ranostay [Wed, 13 Jul 2022 11:49:36 +0000 (04:49 -0700)]
armv8: mach-k3: correct define checking for AM625/AM642 memory maps

Using CONFIG_IS_ENABLED breaks accessing memory map structure when
doing a A53 SPL build for AM625 and AM642 platforms. This is due to
'abc if CONFIG_SPL_BUILD is defined and CONFIG_SPL_FOO is set to 'y''
in which there is no CONFIG_SPL_SOC_K3_AM625/CONFIG_SPL_SOC_K3_AM642
defined in the configuration.

For the A53 SPL builds on these platform to access the memory mapping
which it will need for enabling the mmu/cache it must use #if defined(X)
checks and not CONFIG_IS_ENABLED.

Cc: Suman Anna <s-anna@ti.com>
Cc: Neha Francis <n-francis@ti.com>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoarm: dts: mt7622: remove default pinctrl of uart0
Weijie Gao [Wed, 13 Jul 2022 03:16:39 +0000 (11:16 +0800)]
arm: dts: mt7622: remove default pinctrl of uart0

Currently u-boot running on mt7622 will print an warning log at beginning:
> serial_mtk serial@11002000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

It turns out that the pinctrl uclass can't work properly in board_f stage.

Since the uart0 is the default UART device used by bootrom, and will be
initialized in both bootrom and tf-a bl2. It's ok not to setup pinctrl for
uart0 in u-boot.

This patch removes the default pinctrl of uart0 to suppress the unwanted
warning.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
2 years agoarm: dts: k3-am64-ddr fix typo causing DDR4 register corruption
Anand Gadiyar [Wed, 13 Jul 2022 00:59:04 +0000 (19:59 -0500)]
arm: dts: k3-am64-ddr fix typo causing DDR4 register corruption

The entry for DDRSS_PI_321_DATA was accidentally repeated leading to the
last few PI registers being incorrectly programmed.

Fix this.

Reported-by: Bin Liu <b-liu@ti.com>
Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Anand Gadiyar <gadiyar@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoboard: qualcomm: Add support for QCS404 EVB
Sumit Garg [Tue, 12 Jul 2022 07:12:12 +0000 (12:42 +0530)]
board: qualcomm: Add support for QCS404 EVB

Add support for Qualcomm QCS404 SoC based evaluation board.

Features:
- Qualcomm Snapdragon QCS404 SoC
- 1GiB RAM
- 8GiB eMMC, uSD slot

U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/qcs404.rst.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agoclocks: qcom: Add clock driver for QCS404 SoC
Sumit Garg [Tue, 12 Jul 2022 07:12:11 +0000 (12:42 +0530)]
clocks: qcom: Add clock driver for QCS404 SoC

Currently this clock driver initializes clocks for UART and eMMC. Along
with this import "qcom,gcc-qcs404.h" header from Linux mainline to
support DT bindings.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
2 years agopinctrl: qcom: Add pinctrl driver for QCS404 SoC
Sumit Garg [Tue, 12 Jul 2022 07:12:10 +0000 (12:42 +0530)]
pinctrl: qcom: Add pinctrl driver for QCS404 SoC

Currently this pinctrl driver only supports BLSP UART2 specific pin
configuration.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agommc: msm_sdhci: Add SDCC version 5.0.0 support
Sumit Garg [Tue, 12 Jul 2022 07:12:09 +0000 (12:42 +0530)]
mmc: msm_sdhci: Add SDCC version 5.0.0 support

For SDCC version 5.0.0, MCI registers are removed from SDCC interface
and some registers are moved to HC. So add support to use the new
compatible string "qcom,sdhci-msm-v5". Based on this new msm variant,
pick the relevant variant data and use it to detect MCI presence thereby
configuring register read/write to msm specific registers.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agoboard: qualcomm: Add support for dragonboard845c
Sumit Garg [Tue, 12 Jul 2022 07:12:08 +0000 (12:42 +0530)]
board: qualcomm: Add support for dragonboard845c

Add support for 96Boards Dragonboard 845C aka Robotics RB3 development
platform. This board complies with 96Boards Open Platform Specifications.

Features:
- Qualcomm Snapdragon SDA845 SoC
- 4GiB RAM
- 64GiB UFS drive

U-boot is chain loaded by ABL in 64-bit mode as part of boot.img.
For detailed build and boot instructions, refer to
doc/board/qualcomm/sdm845.rst, board: dragonboard845c.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agouart: sdm845: Fix debug UART pinmux
Sumit Garg [Tue, 12 Jul 2022 07:12:07 +0000 (12:42 +0530)]
uart: sdm845: Fix debug UART pinmux

Configure debug UART pins as function: "qup9" rather than being regular
gpios. It fixes a hang seen during pinmux setting.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agoclocks: sdm845: Import qcom,gcc-sdm845.h
Sumit Garg [Tue, 12 Jul 2022 07:12:06 +0000 (12:42 +0530)]
clocks: sdm845: Import qcom,gcc-sdm845.h

Rather than using magic numbers as clock ids for peripherals import
qcom,gcc-sdm845.h from Linux to be used standard macros for clock ids.
So start using corresponding clk-id macro for debug UART.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agoarm64: dts: sdm845: Remove redundant u-boot DT properties
Sumit Garg [Tue, 12 Jul 2022 07:12:05 +0000 (12:42 +0530)]
arm64: dts: sdm845: Remove redundant u-boot DT properties

According to u-boot DT recomendation, u-boot specific DT properties belong
to *-uboot.dtsi. Also for starqltechn board (which is the only current
consumer of sdm845.dtsi), the properties are already included in
starqltechn-uboot.dtsi, so remove corresponding redundant properties.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agoboard: starqltechn: Align DT node overrides with sdm845.dtsi
Sumit Garg [Tue, 12 Jul 2022 07:12:04 +0000 (12:42 +0530)]
board: starqltechn: Align DT node overrides with sdm845.dtsi

Currently there is a mismatch among DT node overrides in starqltechn
board DTS file and the actual DT nodes in the sdm845.dtsi. So fix that
to align with DT nodes in sdm845.dtsi.

Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
2 years agoNokia RX-51: Remove CONFIG_PREBOOT from defconfig
Pali Rohár [Sun, 10 Jul 2022 11:42:56 +0000 (13:42 +0200)]
Nokia RX-51: Remove CONFIG_PREBOOT from defconfig

CONFIG_PREBOOT just cause putting "preboot=CONFIG_PREBOOT" into env list.
Value CONFIG_PREBOOT="run preboot" in defconfig is just nonsense and does
not do anything useful (it is infinite recursion). Config file for this
board already contains default preboot= env variable with correct value,
which has higher priority than CONFIG_PREBOOT and this is reason why
nonsense CONFIG_PREBOOT is ignored.

Remove nonsense and unused CONFIG_PREBOOT from nokia_rx51_defconfig file.

Signed-off-by: Pali Rohár <pali@kernel.org>
2 years agoboard: ti: am335x: Use correct dtbs for SanCloud boards
Paul Barker [Fri, 8 Jul 2022 09:25:46 +0000 (10:25 +0100)]
board: ti: am335x: Use correct dtbs for SanCloud boards

We have different dtbs for the Lite and Extended WiFi variants of the
SanCloud BBE.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agoboard: ti: am335x: Enable spi0 bus on SanCloud BBE Lite
Paul Barker [Fri, 8 Jul 2022 09:25:45 +0000 (10:25 +0100)]
board: ti: am335x: Enable spi0 bus on SanCloud BBE Lite

The SanCloud BBE Lite has a Micron Authenta flash device connected to
the spi0 bus.

Signed-off-by: Paul Barker <paul.barker@sancloud.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
2 years agocmd: ti: ddr3: correct minor spelling mistake in Ti DDR3
Ramin Zaghi [Fri, 8 Jul 2022 08:02:56 +0000 (09:02 +0100)]
cmd: ti: ddr3: correct minor spelling mistake in Ti DDR3

Just a spelling mistake.

Signed-off-by: Ramin Zaghi <rzaghi@visualSilicon.com>
2 years agophy: ti: j721e-wiz: use OF data for device specific data
Matt Ranostay [Fri, 8 Jul 2022 06:41:52 +0000 (23:41 -0700)]
phy: ti: j721e-wiz: use OF data for device specific data

Move device specific data into OF data structure so it
is easier to maintain and we can get rid of if statements.

Based on: https://lore.kernel.org/linux-phy/20220526064121.27625-1-rogerq@kernel.org/T/#u

Cc: Roger Quadros <rogerq@kernel.org>
Signed-off-by: Matt Ranostay <mranostay@ti.com>
2 years agoconfigs: am62x_evm_r5: Add support for ESM
Julien Panis [Fri, 1 Jul 2022 12:30:12 +0000 (14:30 +0200)]
configs: am62x_evm_r5: Add support for ESM

Enable ESM driver for AM62x in R5 SPL/u-boot build.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2 years agoarm64: mach-k3: am625_init: Probe ESM nodes
Julien Panis [Fri, 1 Jul 2022 12:30:11 +0000 (14:30 +0200)]
arm64: mach-k3: am625_init: Probe ESM nodes

On AM62x devices, main ESM error event outputs can be routed to
MCU ESM as inputs. So, two ESM device nodes are expected in the
device tree : one for main ESM and another one for MCU ESM.
MCU ESM error output can trigger the reset logic to reset
the device when CTRLMMR_MCU_RST_CTRL:MCU_ESM_ERROR_RESET_EN_Z is
set to '0'.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2 years agoarm64: dts: k3-am625-r5: Add support for ESM devices
Julien Panis [Fri, 1 Jul 2022 12:30:10 +0000 (14:30 +0200)]
arm64: dts: k3-am625-r5: Add support for ESM devices

Add main ESM and MCU ESM nodes to AM625-R5 device tree.

Signed-off-by: Julien Panis <jpanis@baylibre.com>
2 years agoarm: apple: Add initial Apple M2 support
Janne Grunau [Thu, 30 Jun 2022 22:06:17 +0000 (00:06 +0200)]
arm: apple: Add initial Apple M2 support

Apple's M2 SoC very similar to the M1 and can use the same memory map.
The keyboard/trackpad on the MacBook Pro (13-inch, M2, 2022) uses
"dockchannel" as transport instead of SPI and needs a new driver.
USB, NVMe, uart, framebuffer and watchdog are working with the existing
drivers.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2 years agoiommu: Add M2 support to Apple DART driver
Janne Grunau [Thu, 30 Jun 2022 22:06:16 +0000 (00:06 +0200)]
iommu: Add M2 support to Apple DART driver

"apple,t8112-dart" uses an incompatible register interface but still
offers the same functionality. This DART is found on the M2 and M1
Pro/Max/Ultra SoCs.

Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
2 years agoMerge commit '90ba25b7cb78bd85c6af0b6429226c6616dedefa' of https://source.denx.de...
Tom Rini [Sun, 24 Jul 2022 11:46:55 +0000 (07:46 -0400)]
Merge commit '90ba25b7cb78bd85c6af0b6429226c6616dedefa' of https://source.denx.de/u-boot/custodians/u-boot-nand-flash

In preparation of re-sync of mtd stack, we opt to move the current stack
slowly in order to have a more easy sync and test. We would like to
prepare uboot to support no-jedec and no-onfi compliant nand so we need
to clean up a bit the code we have now and upstream some of the support.
In this series we expect no functional change

Tested on:
 - imx6ull Micron   MT29F2G08ABAGAH4
 - imx8mn  Macronix MX30LF4G18AC

2 years agoMerge tag 'efi-2022-10-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi
Tom Rini [Sat, 23 Jul 2022 00:48:51 +0000 (20:48 -0400)]
Merge tag 'efi-2022-10-rc1-2' of https://source.denx.de/u-boot/custodians/u-boot-efi

Pull request for efi-2022-10-rc1-2

Documentation:

* doc: add package uuid-dev to build dependencies

UEFI:

* remove support for CONFIG_LCD
* fix authenticated capsules tests

Others:

* pxe: simplify label_boot()
* cli: support bracketed paste

2 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-watchdog
Tom Rini [Sat, 23 Jul 2022 00:48:28 +0000 (20:48 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-watchdog

- octeontx_wdt: Add MIPS Octeon support (Stefan)
- watchdog: add amlogic watchdog support (Philippe)
- watchdog: add pulse support to gpio watchdog driver (Paul)

2 years agomtd: decommission the NAND museum
Michael Trimarchi [Wed, 20 Jul 2022 16:22:16 +0000 (18:22 +0200)]
mtd: decommission the NAND museum

Upstream linux commit f7025a43a9da26.

The MTD subsystem has its own small museum of ancient NANDs in a form of
the CONFIG_MTD_NAND_MUSEUM_IDS configuration option. The museum contains
stone age NANDs with 256 bytes pages, as well as iron age NANDs with 512
bytes per page and up to 8MiB page size.

It is with great sorrow that I inform you that the museum is being
decommissioned. The MTD subsystem is out of budget for Kconfig options and
already has too many of them, and there is a general kernel trend to
simplify the configuration menu.

We remove the stone age exhibits along with closing the museum

REMARK Don't apply this part from upstream:

Some of the iron age ones are transferred to the regular NAND depot.
Namely, only those which have unique device IDs are transferred, and the
ones which have conflicting device IDs are removed.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: toshiba: Retrieve ECC requirements from extended ID
Michael Trimarchi [Wed, 20 Jul 2022 16:22:15 +0000 (18:22 +0200)]
mtd: nand: toshiba: Retrieve ECC requirements from extended ID

Upstream linux commit fb3bff5b407e58.

This patch enables support to read the ECC strength and size from the
NAND flash using Toshiba Memory SLC NAND extended-ID. This patch is
based on the information of the 6th ID byte of the Toshiba Memory SLC
NAND.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Move Macronix specific initialization in nand_macronix.c
Michael Trimarchi [Wed, 20 Jul 2022 16:22:14 +0000 (18:22 +0200)]
mtd: nand: Move Macronix specific initialization in nand_macronix.c

Upstream linux commit 3b5206f4be9b65.

Move Macronix specific initialization logic into nand_macronix.c. This
is part of the "separate vendor specific code from core" cleanup
process.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Move AMD/Spansion specific init/detection logic in nand_amd.c
Michael Trimarchi [Wed, 20 Jul 2022 16:22:13 +0000 (18:22 +0200)]
mtd: nand: Move AMD/Spansion specific init/detection logic in nand_amd.c

Upstream linux commit 229204da53b31d.

Move AMD/Spansion specific initialization/detection logic into
nand_amd.c. This is part of the "separate vendor specific code from
core" cleanup process.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Move Micron specific init logic in nand_micron.c
Michael Trimarchi [Wed, 20 Jul 2022 16:22:12 +0000 (18:22 +0200)]
mtd: nand: Move Micron specific init logic in nand_micron.c

Upstream linux commit 10d4e75c36f6c1.

Move Micron specific initialization logic into nand_micron.c. This is
part of the "separate vendor specific code from core" cleanup process.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Move Toshiba specific init/detection logic in nand_toshiba.c
Michael Trimarchi [Wed, 20 Jul 2022 16:22:11 +0000 (18:22 +0200)]
mtd: nand: Move Toshiba specific init/detection logic in nand_toshiba.c

Upstream linux commit 9b2d61f80b060c.

Move Toshiba specific initialization and detection logic into
nand_toshiba.c. This is part of the "separate vendor specific code from
core" cleanup process.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Move Hynix specific init/detection logic in nand_hynix.c
Michael Trimarchi [Wed, 20 Jul 2022 16:22:10 +0000 (18:22 +0200)]
mtd: nand: Move Hynix specific init/detection logic in nand_hynix.c

Upstream linux commit 01389b6bd2f4f7.

Move Hynix specific initialization and detection logic into
nand_hynix.c. This is part of the "separate vendor specific code from
core" cleanup process.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Move Samsung specific init/detection logic in nand_samsung.c
Michael Trimarchi [Wed, 20 Jul 2022 16:22:09 +0000 (18:22 +0200)]
mtd: nand: Move Samsung specific init/detection logic in nand_samsung.c

Upstream linux commit c51d0ac59f2420.

Move Samsung specific initialization and detection logic into
nand_samsung.c. This is part of the "separate vendor specific code from
core" cleanup process.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Export symbol nand_decode_ext_id
Michael Trimarchi [Wed, 20 Jul 2022 16:22:08 +0000 (18:22 +0200)]
mtd: nand: Export symbol nand_decode_ext_id

In preparation of moving specific nand support that are not jedec
or onfi

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Fix MediaTek MT7621 SoC build
Michael Trimarchi [Fri, 22 Jul 2022 08:28:36 +0000 (10:28 +0200)]
mtd: nand: Fix MediaTek MT7621 SoC build

nand_get_flash_type was reworked in commit 1ca6f9483e9ab5. This change
break the Mediatek MT721. Fix it adjust the function call parameters

+include/linux/mtd/rawnand.h:32:62: note: expected 'struct nand_chip *' but argument is of type 'struct mtd_info *'
+   32 | struct nand_flash_dev *nand_get_flash_type(struct nand_chip *chip,
+      |                                            ~~~~~~~~~~~~~~~~~~^~~~
+drivers/mtd/nand/raw/mt7621_nand.c:1189:48: error: passing argument 2 of 'nand_get_flash_type' from incompatible pointer type [-Werror=incompatible-pointer-types]
+      |                                                ^~~~
+      |                                                |
+      |                                                struct nand_chip *
+include/linux/mtd/rawnand.h:33:49: note: expected 'int *' but argument is of type 'struct nand_chip *'
+   33 |                                            int *maf_id, int *dev_id,

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Get rid of mtd variable in function calls
Michael Trimarchi [Wed, 20 Jul 2022 16:22:07 +0000 (18:22 +0200)]
mtd: nand: Get rid of mtd variable in function calls

chip points to mtd. Passing chip is enough to have a reference
to mtd when is necessary

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Add manufacturer specific initialization/detection steps
Michael Trimarchi [Wed, 20 Jul 2022 16:22:06 +0000 (18:22 +0200)]
mtd: nand: Add manufacturer specific initialization/detection steps

Upstream linux commit abbe26d144ec22.

A lot of NANDs are implementing generic features in a non-generic way,
or are providing advanced auto-detection logic where the NAND ID bytes
meaning changes with the NAND generation.

Providing this vendor specific initialization step will allow us to get
rid of full-id entries in the nand_ids table or all the vendor specific
cases added over the time in the generic NAND ID decoding logic.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Store nand ID in struct nand_chip
Michael Trimarchi [Wed, 20 Jul 2022 16:22:05 +0000 (18:22 +0200)]
mtd: nand: Store nand ID in struct nand_chip

Upstream linux commit 7f501f0a72036d.

Store the NAND ID in struct nand_chip to avoid passing id_data and id_len
as function parameters.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agomtd: nand: Get rid of busw parameter
Michael Trimarchi [Wed, 20 Jul 2022 16:22:04 +0000 (18:22 +0200)]
mtd: nand: Get rid of busw parameter

Upstream linux commit 29a198a1592d83.

Auto-detection functions are passed a busw parameter to retrieve the actual
NAND bus width and eventually set the correct value in chip->options.
Rework the nand_get_flash_type() function to get rid of this extra
parameter and let detection code directly set the NAND_BUSWIDTH_16 flag in
chip->options if needed.

Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
2 years agoMerge https://source.denx.de/u-boot/custodians/u-boot-marvell
Tom Rini [Thu, 21 Jul 2022 13:16:59 +0000 (09:16 -0400)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell

- turris: Misc updates (Pali)
- mvebu: handle non-zero base address for RAM (Chris)
- mvebu: add support for Methode eDPU (Robert)
- mvebu: a3720: Set BOOT_TARGET_DEVICES list to enabled peripherals
  (Pali)
- tlv_eeprom: Add missing CRC32 dependency (Pali)
- treewide: Fix Marek's name and change my e-mail address (Marek)
- mvebu: eDPU/uDPU: Misc updates (Robert)
- mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times
  (Pali)

2 years agoarm: mvebu: turris_omnia: Set ETHPRIME to DT alias
Pali Rohár [Fri, 15 Jul 2022 08:16:00 +0000 (10:16 +0200)]
arm: mvebu: turris_omnia: Set ETHPRIME to DT alias

CONFIG_ETHPRIME can be set to DT node name or alias which refers to DT
node. Define ethernet aliases and set ETHPRIME to eth2 which refers to WAN
ethernet port. This removes hardcoded DT node name from U-Boot
configuration file.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoarm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times
Pali Rohár [Fri, 15 Jul 2022 08:13:12 +0000 (10:13 +0200)]
arm: mvebu: Avoid reading MVEBU_REG_PCIE_DEVID register too many times

Change detection of platform/cpu from runtime to compile time via config
define. This completely eliminates compiling code which is not going to run
on selected platform. Code which parses and prints device / revision id
still reads device id from MVEBU_REG_PCIE_DEVID register, but only once.

Signed-off-by: Pali Rohár <pali@kernel.org>
Acked-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agomvebu: uDPU: disable non-present peripherals
Robert Marko [Fri, 3 Jun 2022 10:53:05 +0000 (12:53 +0200)]
mvebu: uDPU: disable non-present peripherals

uDPU like eDPU does not expose SCSI based peripherals like SATA nor PCI
and for sure it does not have the Intel E1000 PCI card.

So, like for eDPU remove those from the defconfig.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agomvebu: eDPU: disable SCSI support
Robert Marko [Fri, 3 Jun 2022 10:53:04 +0000 (12:53 +0200)]
mvebu: eDPU: disable SCSI support

eDPU does not use SCSI nor it has SATA exposed, and commit
arm: mvebu: a3720: Set BOOT_TARGET_DEVICES list to enabled peripherals
now allows compiling U-boot wihout all of the BOOT_TARGET_DEVICES since
not all boards have all of the listed peripherals exposed.

So, disable SCSI support in defconfig for eDPU.

Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agotreewide: Fix Marek's name and change my e-mail address
Marek Behún [Wed, 1 Jun 2022 15:17:06 +0000 (17:17 +0200)]
treewide: Fix Marek's name and change my e-mail address

Fix diacritics in some instances of my name and change my e-mail address
to kabel@kernel.org.

Add corresponding .mailmap entries.

Signed-off-by: Marek Behún <kabel@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoboard: turris: Fix MAINTAINERS and add Pali
Marek Behún [Wed, 1 Jun 2022 15:17:05 +0000 (17:17 +0200)]
board: turris: Fix MAINTAINERS and add Pali

Fix MAINTAINERS files for Turris devices, add missing files and add Pali
as maintainer.

Signed-off-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agotlv_eeprom: Add missing CRC32 dependency
Pali Rohár [Mon, 30 May 2022 08:42:35 +0000 (10:42 +0200)]
tlv_eeprom: Add missing CRC32 dependency

tlv_eeprom uses crc32() function, so add dependency into Kconfig.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoarch: mvebu: Disable by default unused peripherals in SPL
Pali Rohár [Tue, 24 May 2022 08:58:42 +0000 (10:58 +0200)]
arch: mvebu: Disable by default unused peripherals in SPL

SPL on mvebu loads proper U-Boot from custom Marvell kwbimage format and
therefore support for other binary formats is not required to be present in
SPL. Boot source of proper U-Boot is defined by compile time options and
therefore it is not required to enable all possible and unused peripherals
in SPL by default.

This change decrease size of SPL binaries.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>
2 years agoarm: mvebu: a3720: Add NVMe to BOOT_TARGET_DEVICES list
Pali Rohár [Mon, 23 May 2022 09:14:36 +0000 (11:14 +0200)]
arm: mvebu: a3720: Add NVMe to BOOT_TARGET_DEVICES list

Enable NVMe booting on boards which have enabled NVMe drivers.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Stefan Roese <sr@denx.de>