Erik Faye-Lund [Tue, 8 Jun 2021 11:20:59 +0000 (13:20 +0200)]
llvmpipe: fix edge-rule logic for lines
In
2737abb44ef, the handling of pixel-offsets and edge rules were
untangled, but one case was missed.
This fixes the following dEQP test-cases on VirGL + LLVMpipe
- dEQP-GLES2.functional.draw.random.10
- dEQP-GLES2.functional.draw.random.42
- dEQP-GLES3.functional.draw.random.105
- dEQP-GLES3.functional.draw.random.114
- dEQP-GLES3.functional.draw.random.135
- dEQP-GLES3.functional.draw.random.144
- dEQP-GLES3.functional.draw.random.155
- dEQP-GLES3.functional.draw.random.174
- dEQP-GLES3.functional.draw.random.206
- dEQP-GLES3.functional.draw.random.31
- dEQP-GLES3.functional.draw.random.43
- dEQP-GLES3.functional.draw.random.84
- dEQP-GLES31.functional.draw_indirect.random.20
...as well as these on Zink + Lavapipe:
- spec@nv_primitive_restart@primitive-restart-disable_vbo
- spec@nv_primitive_restart@primitive-restart-vbo_combined_vertex_and_index
- spec@nv_primitive_restart@primitive-restart-vbo_index_only
- spec@nv_primitive_restart@primitive-restart-vbo_separate_vertex_and_index
- spec@nv_primitive_restart@primitive-restart-vbo_vertex_only
Fixes:
2737abb44ef ("gallium: Replace gl_rasterization_rules with lower_left_origin and half_pixel_center.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11183>
Yiwei Zhang [Fri, 4 Jun 2021 05:56:38 +0000 (05:56 +0000)]
virgl: forward the host renderer hardware info
Some game engines rely on the real hardware info to adjust default
graphics quality and other attributes.
Prepend "virgl" to avoid app compat issues and to distinguish from
native platforms while giving engines/apps a chance to adjust graphics
defaults.
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11179>
Georg Lehmann [Thu, 10 Jun 2021 10:47:51 +0000 (12:47 +0200)]
ac: Enable 32bit predication on gfx9 with fw feature version 52.
Amdvlk does this as well and it passes the vulkan CTS on renoir.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
Georg Lehmann [Thu, 10 Jun 2021 12:14:24 +0000 (14:14 +0200)]
ac: Enable 32bit predication on gfx10.
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
Georg Lehmann [Thu, 10 Jun 2021 10:46:22 +0000 (12:46 +0200)]
ac: Check me_fw_feature for 32bit predication on gfx10.3
Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11297>
Samuel Pitoiset [Thu, 10 Jun 2021 16:20:19 +0000 (18:20 +0200)]
radv: fix aligning the image offset by using align64()
This doesn't fix anything known. Found by inspection.
Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11302>
Mike Blumenkrantz [Mon, 10 May 2021 11:37:09 +0000 (07:37 -0400)]
util/disk_cache: add nocopy variant of disk cache store function
this is a bit more convenient in some cases
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11304>
Yiwei Zhang [Thu, 10 Jun 2021 04:23:40 +0000 (04:23 +0000)]
egl/android: add aosp_nougat system/window.h back for back compat
Also layer ANativeWindow_* APIs on top of legacy APIs for api level less
than 26 in a new platform_android.h header.
v2: persist frozen system/window.h header
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11286>
Rob Clark [Thu, 10 Jun 2021 19:33:32 +0000 (12:33 -0700)]
docs: Update freedreno features
Bring features.txt a bit more up to date.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11311>
Rob Clark [Thu, 10 Jun 2021 21:20:36 +0000 (14:20 -0700)]
freedreno: Add missing valid range tracking for SSBOs/images
Normally TC takes care of this for us. But we might as well not get it
wrong in cases where TC is disabled.
Reported-by: Alyssa Rosenzweig <alyssa@collabora.com>
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11311>
Rob Clark [Thu, 10 Jun 2021 19:42:30 +0000 (12:42 -0700)]
freedreno/registers: add A5XX_RBBM_STATUS3 bit
Same bit as a6xx.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11311>
Emma Anholt [Tue, 8 Jun 2021 21:40:48 +0000 (14:40 -0700)]
ci/piglit: Skip WGL on all the Linux runs.
We don't build the tests, since we don't have WGL.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
Emma Anholt [Tue, 8 Jun 2021 21:35:42 +0000 (14:35 -0700)]
ci/freedreno: Enable running all of piglit_gl for a530's manual test.
Otherwise the xfails will end up stale after piglit uprevs that change the
test set.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
Emma Anholt [Tue, 8 Jun 2021 00:10:31 +0000 (17:10 -0700)]
ci: Update piglit and deqp/piglit-runner.
This brings in some major new features in the runner:
- piglit tests now include subtest reporting
- "-t" support for quick include-filtering of tests.
- piglit tests that crash after their result report are considered crashes.
- throws a nice error if you try to annotate the same failure twice
(e.g. lvp's dEQP-VK.glsl.builtin.precision.pow.highp.vec2,Fail)
Since the runner catches piglit test bugs where the same subtest is run
twice, we also uprev piglit to pull in the fixes for those.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11283>
Tomeu Vizoso [Thu, 10 Jun 2021 11:43:56 +0000 (13:43 +0200)]
ci/lava: Don't overwrite PIGLIT_REPLAY_EXTRA_ARGS
Other Piglit jobs will want different values for this env var.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
Daniel Stone [Thu, 10 Jun 2021 09:35:21 +0000 (10:35 +0100)]
ci/lava: Add --dump-yaml option to submitter
Also useful for local development and testing.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
Daniel Stone [Thu, 10 Jun 2021 08:42:40 +0000 (09:42 +0100)]
ci/lava: Add validate-only mode to job submitter
Useful for development.
Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
Tomeu Vizoso [Thu, 10 Jun 2021 08:45:54 +0000 (10:45 +0200)]
ci/lava: Improve error reporting in lava_job_submitter.py
I'm having trouble figuring out why this is breaking.
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
Emma Anholt [Fri, 4 Jun 2021 18:59:15 +0000 (11:59 -0700)]
ci/lava: Finish garbage-collecting the TEST_SUITE variable
We no longer name the template by the test suite being run.
Fixes:
93ec399b2850 ("ci: Use a single template for LAVA jobs")
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11293>
Paulo Zanoni [Thu, 10 Jun 2021 00:09:05 +0000 (17:09 -0700)]
iris: don't munmap NULL pointers
This is a regression, the previous commit had this check which was
removed in the patch mentioned below. What happens is that when we
have a buffer that's not mmapped and we try to bo_free it we get some
very funny backtraces. Easily reproducible with fullscreen
gputest.triangle.
Fixes:
f62724ccacff ("iris: Pick a single mmap mode (WB/WC) at BO allocation time")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4890
Tested-by: Michel Dänzer <mdaenzer@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11284>
Dave Airlie [Thu, 10 Jun 2021 20:11:13 +0000 (06:11 +1000)]
iris: drop unused function declaration
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11306>
Hoe Hao Cheng [Tue, 1 Jun 2021 08:58:52 +0000 (16:58 +0800)]
zink/codegen: clean the constructor of Extension up
the `functions` parameter is now unused, also rewrote some comments
since they are now outdated
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
Hoe Hao Cheng [Sun, 30 May 2021 10:53:56 +0000 (18:53 +0800)]
zink/codegen: allow conditional enabling of instance extensions
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
Hoe Hao Cheng [Thu, 27 May 2021 19:45:38 +0000 (03:45 +0800)]
zink: use the dispatch tables
- removed all usage of GET_PROC_ADDR
- find-and-replaced all instances of `screen->vk_` to `screen->vk.`
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
Hoe Hao Cheng [Thu, 27 May 2021 19:59:02 +0000 (03:59 +0800)]
zink: slight refactor of load_device_extensions()
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
Hoe Hao Cheng [Thu, 27 May 2021 19:04:42 +0000 (03:04 +0800)]
zink/codegen: add zink_verify_*_extensions()
those are meant to be used with the dispatch tables, by checking whether
the functions added by the enabled extensions are actually loaded
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
Hoe Hao Cheng [Sun, 30 May 2021 10:02:56 +0000 (18:02 +0800)]
zink/codegen: split commands into three groups
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
Hoe Hao Cheng [Wed, 26 May 2021 19:10:09 +0000 (03:10 +0800)]
zink: introduce vk_dispatch_table
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11036>
Connor Abbott [Thu, 4 Mar 2021 14:47:39 +0000 (15:47 +0100)]
ir3: Copy propagate immed/const to meta instructions
This is allowed with the new RA, and makes a huge difference in
preventing extra moves when preferential coloring doesn't work.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Thu, 4 Mar 2021 11:21:50 +0000 (12:21 +0100)]
ir3: Insert output collects in the main shader
We were inserting them in what was NIR's end block with the "end"
instruction, which meant that the moves they generated couldn't be
scheduled with the rest of the last block as part of post-RA scheduling.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Thu, 4 Mar 2021 11:18:44 +0000 (12:18 +0100)]
ir3: Add simple CSE pass
RA currently can't handle a live value that's part of a vector and
introduces extra copies. This was espeically a problem for bary.f, where
the bary coords were being split and repeatedly re-collected. But this
could be a problem in other situations as well.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Mon, 26 Apr 2021 21:37:04 +0000 (23:37 +0200)]
ir3/sched: Consider unused destinations when computing live effect
If an instruction's destination is unused, then we shouldn't penalize
it. For example, this helps us schedule atomic operations whose results
aren't read. This works around RA failures when CSE is enabled in some
robustness2 tests.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 23 Apr 2021 11:05:48 +0000 (13:05 +0200)]
ir3/sched: Make collects count against tex/sfu limits
In a scenario where there are a lot of texture fetches with constant
coordinates, this prevents the scheduler from scheduling all the setup
instructions after the first group of textures has been scheduled
because they are the only non-syncing thing and scheduling them didn't
decrease tex_delay. Collects with immed/const sources will turn into
moves of those sources, so we should treat them the same.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Thu, 11 Mar 2021 14:00:15 +0000 (15:00 +0100)]
ir3/sched: Don't schedule collect early
I don't think there was ever a good reason to do this, but when we start
folding constants/immediates into collect, this can become actively
harmful.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Wed, 3 Mar 2021 14:11:14 +0000 (15:11 +0100)]
ir3: Remove right and left copy prop restrictions
This is leftover from the old RA, and inhibits copy propagation
unnecessarily with the new RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Mon, 26 Apr 2021 21:05:53 +0000 (23:05 +0200)]
ir3/ra: Add a validation pass
This helps catch tricky-to-debug bugs in RA, or helps rule them out.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 19 Feb 2021 11:33:49 +0000 (12:33 +0100)]
ir3: Rewrite register allocation
Switch to the new SSA-based register allocator.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Mon, 22 Mar 2021 14:02:48 +0000 (15:02 +0100)]
ir3: Expose occupancy calculation functions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 19 Feb 2021 11:14:14 +0000 (12:14 +0100)]
ir3: Add pass to lower arrays to SSA
This will be run right after nir->ir3. Even though we have SSA coming
out of NIR, we still need it for NIR registers, even though we keep the
original array around to insert false dependencies.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 19 Feb 2021 11:03:47 +0000 (12:03 +0100)]
ir3: Add dominance infrastructure
Mostly lifted from nir.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 14 May 2021 17:14:47 +0000 (19:14 +0200)]
ir3: Remove unused check_src_cond()
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Tue, 23 Mar 2021 17:13:26 +0000 (18:13 +0100)]
ir3/postsched: Don't use SSA source information
This was only used for calculating if a source is a tex or SFU
instruction, which is easily replacable. It's going away with the new
RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Mon, 17 May 2021 14:16:55 +0000 (16:16 +0200)]
ir3/delay: Delete pre-RA repeat handling
It looks likely that any implementation of (rptN) in ir3 will have to
actually create (rptN) instructions after RA, which means that this can
be dropped.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 19 Feb 2021 09:53:08 +0000 (10:53 +0100)]
ir3: Rewrite delay calculation
The old delay calculation relied on the SSA information staying around,
and wouldn't work once we start introducing phi nodes and making
"normal" values defined in multiple blocks not array regs anymore.
What's worse is that properly inserting phi nodes when splitting live
ranges would make that code even more complicated, and this was the last
place post-RA that actually needed that information.
The new version only compares the physical registers of sources and
destinations. It works by going backwards up to a maximum number of
cycles, so it might be slightly slower when the definition is closer but
should be faster when it is farther away.
To avoid complicating the new method, the old method is kept around, but
only for pre-RA scheduling and it can therefore be drastically
simplified as the array case can be dropped.
ir3_delay_calc() is split into a few variants to avoid an explosion of
boolean arguments in users, especially now that merged_regs now has to
be passed to it.
The new method is a little more complicated when it comes to handling
(rptN), because both the assigner and consumer may be (rptN). This adds
some unit tests for those cases, in addition to dropping the to-SSA code
in the test harness since it's no longer needed.
Finally, ir3_legalize has to be switched to using physical registers for
the branch condition. This was the one place where IR3_REG_SSA remained
after RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Mon, 17 May 2021 14:38:26 +0000 (16:38 +0200)]
ir3: Make branch conditions non-SSA
In particular, make sure they have a physreg assigned. This was the last
place after RA where SSA registers were created, which won't work with
the new post-RA delay calculation that relies on the physreg.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Thu, 25 Mar 2021 14:22:44 +0000 (15:22 +0100)]
ir3: Add reg_elems(), reg_elem_size(), and reg_size()
For working with registers in units of half-regs in the new RA.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Mon, 22 Feb 2021 14:00:55 +0000 (15:00 +0100)]
ir3/delay: Fix full->half and half->full delay
The current compiler never does this, but the new compiler will start to
in mergeregs mode. There is an extra penalty for this.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 19 Feb 2021 10:18:02 +0000 (11:18 +0100)]
ir3: Add ir3_register::array.base
There were two different approaches I saw in the post-RA code for
figuring out what regiser range a relative access touched:
1. Use reg->array.offset and reg->array.size. This is wrong in case
reg->array.offset was non-zero before RA, because array.size is
the size of the whole array and array.offset has the const offset
within the array baked in.
2. Lookup the array from the array ID and use the base + range there.
This is correct, but won't work with the new RA, where an array might
not always be assigned to the same register.
This replaces both methods with a new ir3_register::array.base field,
and switches all the users I could find to it.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Fri, 5 Mar 2021 21:09:41 +0000 (22:09 +0100)]
ir3: Improve register printing for SSA
Print the ssa name for array destinations, and handle printing undef SSA
sources.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Thu, 18 Feb 2021 16:57:49 +0000 (17:57 +0100)]
ir3: Prepare for instructions with multiple destinations
To simplify the pre-RA merge set code and express the result live-range
splitting in RA, we need to add support for parallel copy instructions,
and for the merge set code these parallel copies need to be in SSA form.
Parallel copies have multiple destinations by necessity, but there was
no way to express this in the existing IR. In particular there was no
support for marking a register as being a destination, and no support
for indicating which destination register out of several an SSA source
refers to. This replaces ir3_register::instr with ir3_register::def and
re-purposes ir3_register::instr. I haven't propagated this into common
helpers, like ssa(), because that would vastly increase the amount of
churn and the number of places that produce such instructions should be
limited -- only RA will create parallel copies and they will be
destroyed right after RA. In the future swz will have multiple
destinations too, but it will only be created after RA via parallel copy
lowering.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Wed, 10 Feb 2021 18:49:46 +0000 (19:49 +0100)]
ir3: Readd support for translating NIR phi nodes
This is roughly based on the support removed a while ago, but it handles
sources better by associating each source with a predecessor block.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Tue, 4 May 2021 09:11:04 +0000 (11:11 +0200)]
ir3: Add ir3_start_block()
Name based on nir_start_block(). A number of places were already
open-coding this, convert them.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Connor Abbott [Wed, 10 Feb 2021 18:47:18 +0000 (19:47 +0100)]
ir3: Introduce phi and parallelcopy instructions
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9842>
Alyssa Rosenzweig [Wed, 9 Jun 2021 20:15:19 +0000 (16:15 -0400)]
docs/panfrost: Update API versions
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 22:00:29 +0000 (18:00 -0400)]
docs/features: Mark GLES3.1 as done on Panfrost
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 10 Jun 2021 17:18:04 +0000 (13:18 -0400)]
panfrost/ci: Do fractional dEQP-GLES31 run on Midgard
Drop the skip list and correspondingly populate the fails list.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 10 Jun 2021 17:16:56 +0000 (13:16 -0400)]
panfrost/ci: Don't skip SSBO tests on G52
These were blocked on failing RA, but that's been resolved now.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 19:03:29 +0000 (15:03 -0400)]
panfrost/ci: Blank G52 flakes file
Haven't seen these tests flake, and we don't even run dEQP-GLES2 on G52
in CI anymore. (I still do local runs, and I don't see them flake
there.)
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 20:43:29 +0000 (16:43 -0400)]
pan/decode: Handle cache flush jobs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 2 Jun 2021 19:42:05 +0000 (15:42 -0400)]
pan/decode: Fix image attribute counting
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 3 Jun 2021 22:07:09 +0000 (18:07 -0400)]
panfrost: Advertise GLES3.1
We have CI, we're just a few tests away from conformance on v7, and
Midgard is just a few hundred tests behind. Given the branch point isn't
for another month, I think this is a good time to flip the switch.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 20:42:54 +0000 (16:42 -0400)]
panfrost: Add "Cache Flush" job XML
Likely useful for efficient memory_barrier and texture_barrier
operations.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Thu, 10 Jun 2021 17:16:44 +0000 (13:16 -0400)]
panfrost: Set vertex job_barrier
Fixes KHR-GLES31.core.vertex_attrib_binding.advanced-iterations which
pingpongs XFB/attributes
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 15:33:52 +0000 (11:33 -0400)]
panfrost: Flush before compute jobs
Suboptimal but fixes KHR-GLES31.core.compute_shader.pipeline-post-xfb,
which is stubbornly still broken with memory barriers implemented and
cache flush jobs inserted. More investigation needed but probably not
right now.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:36:07 +0000 (18:36 -0400)]
panfrost: Flush everything for glMemoryBarrier
This is inefficient but so far I see the DDK doing the same thing. Fixes
KHR-GLES31.core.shader_storage_buffer_object.advanced-usage-sync-vsfs
In the future we should look into cache flush jobs.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 19:28:08 +0000 (15:28 -0400)]
panfrost: Clean up vertex/instance ID on Midgard
Use the proper XML.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 19:26:05 +0000 (15:26 -0400)]
panfrost: Add XML for vertex/instance ID records
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:42:26 +0000 (13:42 -0400)]
panfrost: Set valid_buffer_range for GPU writes
Transform feedback, SSBO writes, and image writes in particular can
affect this and have bad interactions. Fixes
KHR-GLES31.core.shader_atomic_counters.basic-usage-vs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:42:03 +0000 (20:42 -0400)]
panfrost: Remove pan_image_state
Instead just group the fields about validity into a simpler structure in
panfrost_resource. Panvk can do the same. Common code shouldn't be
thinking in terms of this 'larger' structure anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:32:43 +0000 (20:32 -0400)]
panfrost: Make data_valid a bitset
More compact and will allow simpler code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:09:44 +0000 (13:09 -0400)]
panfrost: Don't clobber indirect dispatch fields
These should be kept as zero so they can be packed correctly. Fixes a
number of KHR-GLES31 fails.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Tue, 8 Jun 2021 15:20:42 +0000 (11:20 -0400)]
panfrost: Use direct dispatch with shared memory
This would require memory allocations we don't handle.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:36:54 +0000 (12:36 -0400)]
pan/indirect_dispatch: Use extracted values
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:31:10 +0000 (12:31 -0400)]
pan/indirect_dispatch: Expand split expressions
Careful algebraic transforms makes these much simpler.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:08:19 +0000 (12:08 -0400)]
pan/indirect_dispatch: Distinguish minus-1 defs
This makes the logic clearer and allows the original values to be
accessed.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 16:00:20 +0000 (12:00 -0400)]
pan/indirect_dispatch: Simplify empty command case
Job type is alone with bitsize in the bottom byte of the addressed
worse, so if we use an 8-bit store we avoid the RMW complexity.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 15:50:37 +0000 (11:50 -0400)]
pan/indirect_dispatch: Indent NIR blocks
Easier to visualize the control flow this way.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:27:52 +0000 (20:27 -0400)]
panfrost: Reduce pan_image_state indirection
In actuality, this just shadows the crc_valid for pan_cs... the
data_valid checks are contained in the caller and just add noise.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 00:17:23 +0000 (20:17 -0400)]
panfrost: Don't CRC mipmapped textures
CRC is intended for final render targets and especially for UI, not the
kind of things you'd mipmap. Meanwhile CRC only works for a single
level, meaning at any given point, half the CRC buffer would be wasted
for a full miptree.
"Arm Mali Best Practices Guide" tells developers that the DDK only
enables CRC for non-mipmapped resources (at least the Vulkan DDK), so
let's do the same, save some memory, and simplify our code.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:28:36 +0000 (18:28 -0400)]
panfrost: Drop todo on PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
They work fine.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 13:21:22 +0000 (09:21 -0400)]
panfrost: Set PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
Fixes KHR-GLES31.core.gpu_shader5.images_array_indexing
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:28:16 +0000 (18:28 -0400)]
panfrost: Set PIPE_COMPUTE_CAP_SUBGROUP_SIZE
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 21:40:17 +0000 (17:40 -0400)]
panfrost: Lower max compute size
Match the DDK's limit (Mali G52), I think there's undocumented errata
here. Fixes
KHR-GLES31.core.texture_buffer.texture_buffer_operations_image_store
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 22:47:49 +0000 (18:47 -0400)]
panfrost: Make image buffers robust
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 21:01:59 +0000 (17:01 -0400)]
panfrost: Fix BUFFER image handling
Fixes:
KHR-GLES31.core.shader_image_load_store.advanced-allMips-cs
KHR-GLES31.core.shader_image_load_store.advanced-allMips-fs
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 19:25:49 +0000 (15:25 -0400)]
panfrost: Allocate XFB buffers per-instance
Somehow XFB gets so little use we never noticed. Fixes:
KHR-GLES31.core.vertex_attrib_binding.basic-input-case9
KHR-GLES31.core.vertex_attrib_binding.basic-input-case11
KHR-GLES31.core.vertex_attrib_binding.basic-inputI-case2
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 18:08:42 +0000 (14:08 -0400)]
panfrost: Don't set a blend shader for no_colour
It's pointless and confuses the hardware. Fixes (on Bifrost)
KHR-GLES31.core.draw_buffers_indexed.color_masks
Yes, this is a silly edge case. Yes, we still have to handle it
correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Mon, 7 Jun 2021 17:38:45 +0000 (13:38 -0400)]
panfrost: Remove scissor_culls_everything
Based on a misunderstanding of how the scissor test works, and in
particular breaks transform feedback and SSBO writes from vertex
shaders.
Replace it with a moral equivalent to rasterizer_discard so vertex
shaders still run.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Sat, 5 Jun 2021 00:23:33 +0000 (20:23 -0400)]
panfrost: Add some missing BGRA formats
Fixes:
KHR-GLES3.copy_tex_image_conversions.forbidden.*
KHR-GLES3.packed_pixels.pbo_rectangle.rgb5_a1
KHR-GLES3.packed_pixels.pbo_rectangle.rgba
KHR-GLES3.packed_pixels.pbo_rectangle.rgba4
KHR-GLES3.packed_pixels.pbo_rectangle.rgba8
KHR-GLES3.packed_pixels.rectangle.rgb5_a1
KHR-GLES3.packed_pixels.rectangle.rgba
KHR-GLES3.packed_pixels.rectangle.rgba4
KHR-GLES3.packed_pixels.rectangle.rgba8
KHR-GLES3.packed_pixels.varied_rectangle.rgb5_a1
KHR-GLES3.packed_pixels.varied_rectangle.rgba
KHR-GLES3.packed_pixels.varied_rectangle.rgba4
KHR-GLES3.packed_pixels.varied_rectangle.rgba8
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:18:23 +0000 (19:18 -0400)]
panfrost: Emulate indirect draws on Midgard
I can't really justify spending time on this right now, even to myself.
So take the perf hit and get out checkbox.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:06:36 +0000 (19:06 -0400)]
panfrost: Fix dirty state emission
If we have per-draw state (vertex ID stuff), there's an ordering
mismatch. Fixes
dEQP-GLES31.functional.draw_base_vertex.draw_elements_instanced_base_vertex.builtin_variable.vertex_id
on Midgard, and I'm not sure why it was passing on Bifrost before. Also
should fix (on both architectures) DRAWID issues.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:19:41 +0000 (13:19 -0400)]
pan/mdg: Insert moves to load/store registers
Ensures a valid schedule/regalloc is possible when vectors are used in
funny ways, as occurs in dEQP-GLES31 resulting in a scheduler hang (or
with prior patches, an RA failure).
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:18:13 +0000 (13:18 -0400)]
pan/mdg: Assert scheduled instructions are reasonable
Would've got a scheduler hang.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:17:39 +0000 (13:17 -0400)]
pan/mdg: Don't skip unit-based checks in choose_instruction
If an explicit unit isn't specified, we still should check.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Wed, 9 Jun 2021 17:17:04 +0000 (13:17 -0400)]
pan/mdg: Use more accurate ld/st reg estimates
And assert that we got them right.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 23:07:41 +0000 (19:07 -0400)]
pan/mdg: Lower away gl_VertexID offset
Technically we can stick the offset in the vertex ID attribute record,
but this is a faster way to get the test passing and Midgard perf?
what's that?
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 22:57:28 +0000 (18:57 -0400)]
pan/mdg: Wire in PAN_SYSVAL_VERTEX_INSTANCE_OFFSETS
If we're going to advertise the CAP, better not crash..
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 22:36:43 +0000 (18:36 -0400)]
panfrost: Don't allocate WLS when not needed
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:36:26 +0000 (17:36 -0400)]
panfrost: Mark 16/32_UNORM as non-renderable (v5)
You'd just get a blend shader anyway, and since they're not spec
requirements, let's not worry about backporting the Midgard lowerings.
Takes dEQP-GLES31.functional.fbo.color.tex2d.* on Midgard from crashing
to not supported.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>
Alyssa Rosenzweig [Fri, 4 Jun 2021 21:17:28 +0000 (17:17 -0400)]
pan/mdg: Fix incorrect rewrite in Midgard scheduler
Fixes on Midgard
dEQP-GLES31.functional.shaders.builtin_functions.uniform.findLSBMinusOne.highp_fragment
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11123>