Christian König [Fri, 4 Dec 2015 13:25:10 +0000 (14:25 +0100)]
st/va: cleanup filter color standard handling
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Julien Isorce <j.isorce@samsung.com>
Tested-by: ulien Isorce <j.isorce@samsung.com>
Tapani Pälli [Fri, 11 Dec 2015 08:45:28 +0000 (10:45 +0200)]
meta: clear_state structure cleanup
Remove unused variables from clear_state and use a hardcoded location
for color uniform to get rid of 2 more variables. Modify shaders to use
explicit location for vertex attribute too as extension is enabled.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Ilia Mirkin [Sun, 13 Dec 2015 08:23:13 +0000 (03:23 -0500)]
glsl: assign varying locations to tess shaders when doing SSO
GRID Autosport uses SSO shaders. When a tessellation evaluation shader
is passed through this, it triggers assertion failures down the line
with unassigned varying locations. Make sure to do this when the first
shader in the pipeline is not a vertex shader.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Neil Roberts [Fri, 11 Dec 2015 12:32:18 +0000 (12:32 +0000)]
i965: Use MESA_FORMAT_B8G8R8X8_SRGB for RGB visuals
Previously if the visual didn't have an alpha channel then it would
pick a format that is not sRGB-capable. I don't think there's any
reason not to always have an sRGB-capable visual. Since
28090b30 there
are now visuals advertised without an alpha channel which means that
games that don't request alpha bits in the config would end up without
an sRGB-capable visual. This was breaking supertuxkart which assumes
the winsys buffer is always sRGB-capable.
The previous code always used an RGBA format if the visual config
itself was marked as sRGB-capable regardless of whether the visual has
alpha bits. I think we don't actually advertise any sRGB-capable
visuals (but we just use sRGB formats anyway) so it shouldn't make any
difference. However this patch also changes it to use RGBX if an
sRGB-capable visual is requested without alpha bits for consistency.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92759
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Neil Roberts [Fri, 11 Dec 2015 12:32:17 +0000 (12:32 +0000)]
i965: Add B8G8R8X8_SRGB to the alpha format override
brw_init_surface_formats overrides the render format for RGBX formats
which aren't supported for rendering so that they internally use RGBA
instead. However, B8G8R8X8_SRGB was missing so it wasn't marked as a
renderable format. This patch just adds it.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Neil Roberts [Fri, 11 Dec 2015 12:32:16 +0000 (12:32 +0000)]
i965: Add MESA_FORMAT_B8G8R8X8_SRGB to brw_format_for_mesa_format
This will be used in a subsequent patch as the format for RGB visuals.
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Suggested-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ilia Mirkin [Thu, 10 Dec 2015 23:19:44 +0000 (18:19 -0500)]
gk104/ir: simplify and fool-proof texbar algorithm
With the current algorithm, we only look at tex uses. However there's a
write-after-write hazard where we might decide to, on some path, not use
a texture's output at all, but instead to write a different value to
that register. However without the barrier, the texture might complete
later and overwrite that value.
This fixes Unreal Elemental demo on GK110/GK208, flightgear on GK10x,
and likely other random-looking failures.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Thu, 10 Dec 2015 20:24:47 +0000 (15:24 -0500)]
nv50/ir: combine sequences of conversions
In some cases shaders want non-default rounding when converting float to
integer. This can be done in one go, so merge the two ops. This comes up
in the packUnorm4x8 & co functions, as well as a few random shaders.
Overall shader-db impact is minimal, helping a handful of witcher2 and
other misc shaders.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 11 Dec 2015 05:40:15 +0000 (00:40 -0500)]
nv50/ir: manually optimize multiplication expansion logic
The conversion of 32-bit integer multiplies into 16-bit ones happens
after the regular optimization loop. However it's fairly common to
multiply by a small integer, rendering some of the expansion pointless.
Firstly, propagate immediates when possible into mul ops, secondly just
remove the ops when they are unnecessary.
Including the change to generate imad immediates, the effect is:
total instructions in shared programs : 6365463 -> 6351898 (-0.21%)
total gprs used in shared programs : 728684 -> 728684 (0.00%)
total local used in shared programs : 9904 -> 9904 (0.00%)
total bytes used in shared programs :
44001576 ->
44036120 (0.08%)
local gpr inst bytes
helped 0 0 3288 4
hurt 0 0 0 842
It's easy for this to hurt bytes since we end up always generating the
8-byte form, while we can't always get rid of the immediate in question.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 11 Dec 2015 05:39:47 +0000 (00:39 -0500)]
nv50/ir: fix imul emission in the presence of an immediate
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 11 Dec 2015 03:50:31 +0000 (22:50 -0500)]
nv50/ir: teach post-ra immediate folding into mad about integers
There will usually be a split before the mad op, peer through that and
pick out the right word of the immediate.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Fri, 11 Dec 2015 02:20:32 +0000 (21:20 -0500)]
nv50/ir: add short imad support
Support emission of the short imad, but also include it in the various
logic that tries to make it possible to emit.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Thu, 10 Dec 2015 17:18:51 +0000 (12:18 -0500)]
nv50/ir: can't have predication and immediates
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Ilia Mirkin [Wed, 9 Dec 2015 06:47:19 +0000 (01:47 -0500)]
nv50/ir: fix texture grad for cubemaps
We were ignoring the partial derivatives on the last dim.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Ilia Mirkin [Wed, 9 Dec 2015 04:55:18 +0000 (23:55 -0500)]
nv50/ir: fix assumption that prog->maxGPR is in 32-bit reg units
On NV50, we use 16-bit reg units (to make it all work with half-regs). A
few places assumed that it was always in 32-bit units.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Nicolai Hähnle [Tue, 8 Dec 2015 22:56:23 +0000 (17:56 -0500)]
gallium/ddebug: regularly log the total number of draw calls
This helps in the use of GALLIUM_DDEBUG_SKIP: first run a target application
with skip set to a very large number and note how many draw calls happen
before the bug. Then re-run, skipping the corresponding number of calls.
Despite the additional run, this can still be much faster than not skipping
anything.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Nicolai Hähnle [Tue, 8 Dec 2015 11:49:12 +0000 (06:49 -0500)]
gallium/ddebug: add GALLIUM_DDEBUG_SKIP option
When we know that hangs occur only very late in a reproducible run (e.g.
apitrace), we can save a lot of debugging time by skipping the flush and hang
detection for earlier draw calls.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Roland Scheidegger [Wed, 9 Dec 2015 03:56:15 +0000 (04:56 +0100)]
llvmpipe: fix layer/vp input into fs when not written by prior stages
ARB_fragment_layer_viewport requires that if a fs reads layer or viewport
index but it wasn't output by gs (or vs with other extensions), then it reads
0. This never worked for llvmpipe, and is surprisingly non-trivial to fix.
The problem is the mechanism to handle non-existing outputs in draw is rather
crude, it will simply redirect them to whatever is at output 0, thus later
stages will just get garbage. So, rather than trying to fix this up (which
looks non-trivial), fix this up in llvmpipe setup by detecting this case there
and output a fixed zero directly.
While here, also optimize the hw vertex layout a bit - previously if the gs
outputted layer (or vp) and the fs read those inputs, we'd add them twice
to the vertex layout, which is unnecessary.
And do some minor cleanup, slots don't require that many bits, there was some
bogus (but harmless) float/int mixup for psize slot too, make the slots all
unsigned (we always put pos at pos zero thus everything else has to be positive
if it exists), and make sure they are properly initialized (layer and vp index
slot were not which looked fishy as they might not have got set back to zero
when changing from a gs which outputs them to one which does not).
This fixes the failures in piglit's arb_fragment_layer_viewport group
(3 each for layer and vp).
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 10 Dec 2015 21:55:33 +0000 (14:55 -0700)]
svga: avoid emitting redundant SetSamplers() commands
This greatly reduces the number of SetSamplers() commands for some
applications.
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Brian Paul [Wed, 9 Dec 2015 19:54:35 +0000 (12:54 -0700)]
svga: avoid emitting redundant SetIndexBuffer commands
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: José Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 10 Dec 2015 19:25:22 +0000 (12:25 -0700)]
st/mesa: trivial indentation fix
Brian Paul [Thu, 10 Dec 2015 19:25:04 +0000 (12:25 -0700)]
util/blitter: minor formatting fixes
Jason Ekstrand [Fri, 11 Dec 2015 19:59:53 +0000 (11:59 -0800)]
i965/fs: Use the correct source for local memory load offsets
The offset for loads is in src[0]. This was a copy+paste error in the
nir_intrinsic_load/store refactoring. This commit fixes a segfault in
ES31-CTS.compute_shader.work-group-size. I have no idea how piglit failed
to catch this...
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93348
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Thu, 12 Nov 2015 07:22:06 +0000 (23:22 -0800)]
i965: Add Gen8+ tessellation control shader state (3DSTATE_HS).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 12 Nov 2015 07:15:23 +0000 (23:15 -0800)]
i965: Add Gen7+ tessellation engine state (3DSTATE_TE).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Tue, 10 Nov 2015 22:35:27 +0000 (14:35 -0800)]
i965: Add Gen8+ tessellation evaluation shader state (3DSTATE_DS).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Thu, 1 Oct 2015 00:04:23 +0000 (17:04 -0700)]
i965: Add tessellation shader push constant support.
Based on a patch by Chris Forbes.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Sat, 10 Oct 2015 00:07:23 +0000 (17:07 -0700)]
i965: Add tessellation shader sampler support.
Based on code by Chris Forbes and Fabian Bieler.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Kenneth Graunke [Wed, 30 Sep 2015 22:42:54 +0000 (15:42 -0700)]
i965: Add tessellation shader surface support.
This is brw_gs_surface_state.c copy and pasted twice with search and
replace.
brw_binding_table.c code is similarly copy and pasted.
v2: Drop dword_pitch related fields.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Acked-by: Jason Ekstrand <jason.ekstrand@intel.com>
Kenneth Graunke [Wed, 2 Dec 2015 01:52:58 +0000 (17:52 -0800)]
i965: Make fs_visitor::emit_urb_writes set EOT for TES as well.
Tessellation evaluation shaders work almost identically to vertex
shaders - we have a set of URB writes at the end of the program, and the
last one should terminate it.
Geometry shaders really are the special case, where multiple
EmitVertex() calls trigger URB writes in the middle of the program.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Wed, 2 Dec 2015 01:51:33 +0000 (17:51 -0800)]
i965: Don't hardcode g1 for URB handles in fs_visitor::emit_urb_writes().
Tessellation evaluation shaders will use g4 instead. For now, make an
fs_reg called urb_handle and use that in place of hardcoding g1.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kenneth Graunke [Wed, 2 Dec 2015 02:20:54 +0000 (18:20 -0800)]
i965: Make brw_set_message_descriptor() non-static.
I want to use this directly from brw_vec4_generator.cpp.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Kristian Høgsberg Kristensen [Fri, 11 Dec 2015 19:18:18 +0000 (11:18 -0800)]
i965: Move brw_cs_fill_local_id_payload() to libi965_compiler
This is a helper function for setting up the local invocation ID
payload according to the cs_prog_data generated by the compiler. It's
intended to be available to users of libi965_compiler so move it there.
Eric Anholt [Fri, 11 Dec 2015 05:54:41 +0000 (21:54 -0800)]
vc4: Add quick algebraic optimization for clamping of unpacked values.
GL likes to saturate your incoming color, but if that color's coming from
unpacking from unorms, there's no point. Ideally we'd have a range
propagation pass that cleans these up in NIR, but that doesn't seem to be
going to land soon. It seems like we could do a one-off optimization in
nir_opt_algebraic, except that doesn't want to operate on expressions
involving unpack_unorm_4x8, since it's sized.
total instructions in shared programs: 87879 -> 87761 (-0.13%)
instructions in affected programs: 6044 -> 5926 (-1.95%)
total estimated cycles in shared programs: 349457 -> 349252 (-0.06%)
estimated cycles in affected programs: 6172 -> 5967 (-3.32%)
No SSPD on openarena (which had the biggest gains, in its VS/CSes), n=15.
Eric Anholt [Fri, 11 Dec 2015 06:02:30 +0000 (22:02 -0800)]
vc4: When doing algebraic optimization into a MOV, use the right MOV.
If there were src unpacks, changing to the integer MOV instead of float
(for example) would change the unpack operation.
Eric Anholt [Fri, 11 Dec 2015 06:23:10 +0000 (22:23 -0800)]
vc4: Fix handling of src packs on in qir_follow_movs().
The caller isn't going to expect it from a return, so it would probably
get misinterpreted. If the caller had an unpack in its reg, that's fine,
but don't lose track of it.
Eric Anholt [Fri, 11 Dec 2015 05:51:03 +0000 (21:51 -0800)]
vc4: Add missing progress note in opt_algebraic.
Eric Anholt [Wed, 9 Dec 2015 01:55:36 +0000 (17:55 -0800)]
vc4: Add debugging of the estimated time to run the shader to shader-db.
Eric Anholt [Wed, 9 Dec 2015 01:18:37 +0000 (17:18 -0800)]
vc4: Fix handling of sample_mask output.
I apparently broke this in a late refactor, in such a way that I decided
its tests were some of those interminable ones that I should just
blacklist from my testing. As a result, the refactors related to it were
totally wrong.
Edward O'Callaghan [Fri, 11 Dec 2015 11:43:31 +0000 (22:43 +1100)]
softpipe: enable GL_ARB_viewport_array support, update GL3.txt doc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Edward O'Callaghan [Fri, 11 Dec 2015 11:43:30 +0000 (22:43 +1100)]
softpipe: implement some support for multiple viewports
Mostly related to making sure the rasterizer can correctly
pick out the correct scissor box for the current viewport.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Roland Scheidegger [Fri, 11 Dec 2015 03:53:21 +0000 (04:53 +0100)]
draw: don't assume fixed offset for data in struct vertex_info
Otherwise, if struct vertex_info is changed, you're in for some surprises...
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Neil Roberts [Wed, 25 Nov 2015 11:14:37 +0000 (12:14 +0100)]
i965/gen9: Don't do fast clears when GL_FRAMEBUFFER_SRGB is enabled
When GL_FRAMEBUFFER_SRGB is enabled any single-sampled renderbuffers
are resolved in intel_update_state because the hardware can't cope
with fast clears on SRGB buffers. In that case it's pointless to do a
fast clear because it will just be immediately resolved.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Neil Roberts [Tue, 24 Nov 2015 15:34:46 +0000 (16:34 +0100)]
i965/gen9: Allow fast clears for non-MSRT SRGB buffers
SRGB buffers are not marked as losslessly compressible so previously
they would not be used for fast clears. However in practice the
hardware will never actually see that we are using SRGB buffers for
fast clears if we use the linear equivalent format when clearing and
make sure to resolve the buffer as a linear format before sampling
from it.
This is an important use case because by default the window system
framebuffers are created as SRGB so without this fast clears won't be
used there.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Neil Roberts [Tue, 24 Nov 2015 18:23:14 +0000 (19:23 +0100)]
i965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabled
SKL can't cope with the CCS buffer for SRGB buffers. Normally the
hardware won't see the SRGB formats because when GL_FRAMEBUFFER_SRGB
is disabled these get mapped to their linear equivalents. In order to
avoid relying on the CCS buffer when it is enabled this patch now
makes it flush the renderbuffers.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Neil Roberts [Tue, 24 Nov 2015 16:59:28 +0000 (17:59 +0100)]
i965/gen8+: Don't upload the MCS buffer for single-sampled textures
For single-sampled textures the MCS buffer is only used to implement
fast clears. However the surface always needs to be resolved before
being used as a texture anyway so the the MCS buffer doesn't actually
achieve anything. This is important for Gen9 because in that case SRGB
surfaces are not supported for fast clears and we don't want the
hardware to see the MCS buffer in that case.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Neil Roberts [Tue, 24 Nov 2015 16:01:03 +0000 (17:01 +0100)]
i965/meta-fast-clear: Disable GL_FRAMEBUFFER_SRGB during clear
Adds MESA_META_FRAMEBUFFER_SRGB to the meta save state so that
GL_FRAMEBUFFER_SRGB will be disabled when performing the fast clear.
That way the render surface state will be programmed with the linear
equivalent format during the clear. This is important for Gen9 because
the SRGB formats are not marked as losslessly compressible so in
theory they aren't support for fast clears. It shouldn't make any
difference whether GL_FRAMEBUFFER_SRGB is enabled for the fast clear
operation because the color is not actually written to the framebuffer
so there is no chance for the hardware to apply the SRGB conversion on
it anyway.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Marek Olšák [Wed, 9 Dec 2015 21:45:56 +0000 (22:45 +0100)]
winsys/amdgpu: clear the buffer cache on mmap failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Wed, 9 Dec 2015 21:45:56 +0000 (22:45 +0100)]
winsys/radeon: clear the buffer cache on mmap failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Wed, 9 Dec 2015 21:36:26 +0000 (22:36 +0100)]
winsys/amdgpu: clear the buffer cache on allocation failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Wed, 9 Dec 2015 21:36:26 +0000 (22:36 +0100)]
winsys/radeon: clear the buffer cache on allocation failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 23:00:59 +0000 (00:00 +0100)]
gallium/radeon: remove radeon_winsys_cs_handle
"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf".
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 19:57:05 +0000 (20:57 +0100)]
winsys/radeon: use pb_cache instead of pb_cache_manager
This is a prerequisite for the removal of radeon_winsys_cs_handle.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 21:48:45 +0000 (22:48 +0100)]
winsys/radeon: use radeon_bomgr less
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 21:34:01 +0000 (22:34 +0100)]
winsys/radeon: rename radeon_bomgr_init_functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 21:32:33 +0000 (22:32 +0100)]
winsys/radeon: move variables from radeon_bomgr to radeon_drm_winsys
radeon_bomgr is going away.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 21:10:04 +0000 (22:10 +0100)]
winsys/radeon: remove redundant radeon_bomgr::va
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 21:19:38 +0000 (22:19 +0100)]
winsys/amdgpu: don't use the "rws" abbreviation for amdgpu_winsys
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 19:57:05 +0000 (20:57 +0100)]
winsys/amdgpu: use pb_cache instead of pb_cache_manager
This is a prerequisite for the removal of radeon_winsys_cs_handle.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 23:23:06 +0000 (00:23 +0100)]
gallium/pb_bufmgr_cache: use the new pb_cache module
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Sun, 6 Dec 2015 18:38:26 +0000 (19:38 +0100)]
gallium/pb_cache: add a copy of cache bufmgr independent of pb_manager
This simplified (basically duplicated) version of pb_cache_manager will
allow removing some ugly hacks from radeon and amdgpu winsyses and
flatten simplify their design.
The difference is that winsyses must manually add buffers to the cache
in "destroy" functions and the cache doesn't know about the buffers before
that. The integration is therefore trivial and the impact on the winsys
design is negligible.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
Marek Olšák [Thu, 10 Dec 2015 00:37:39 +0000 (01:37 +0100)]
radeonsi: implement fast stencil clear
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Tue, 8 Dec 2015 16:33:55 +0000 (17:33 +0100)]
radeonsi: re-enable Hyper-Z for stencil
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 10 Dec 2015 00:46:17 +0000 (01:46 +0100)]
r600g: remove a Hyper-Z workaround that's likely not needed anymore
FORCE_OFF == 0, no need to set that
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 10 Dec 2015 00:40:14 +0000 (01:40 +0100)]
r600g: re-enable Hyper-Z for stencil on Evergreen & Cayman
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Wed, 9 Dec 2015 19:26:21 +0000 (20:26 +0100)]
gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly
This is the recommended setting according to hw people and it makes Hyper-Z
stable. Just the two magic states.
This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code).
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Fri, 4 Dec 2015 20:24:46 +0000 (21:24 +0100)]
radeonsi: don't use the CP DMA workaround on Fiji and newer
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Fri, 4 Dec 2015 20:24:21 +0000 (21:24 +0100)]
radeonsi: apply the streamout workaround to Fiji as well
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Wed, 9 Dec 2015 22:39:45 +0000 (23:39 +0100)]
radeonsi: also print hexadecimal values for register fields in the IB parser
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Marek Olšák [Tue, 1 Dec 2015 13:56:54 +0000 (14:56 +0100)]
radeonsi: implement RB+ for Stoney (v2)
v2: fix dual source blending
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Wed, 9 Dec 2015 21:14:32 +0000 (22:14 +0100)]
radeonsi: don't call of u_prims_for_vertices for patches and rectangles
Both caused a crash due to a division by zero in that function.
This is an alternative fix.
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Marek Olšák [Thu, 10 Dec 2015 12:16:58 +0000 (13:16 +0100)]
radeonsi: use tgsi_shader_info::colors_written
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 10 Dec 2015 12:19:45 +0000 (13:19 +0100)]
r600g: write all MRTs only if there is exactly one output (fixes a hang)
This fixes a hang in
piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD.
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Thu, 10 Dec 2015 12:15:50 +0000 (13:15 +0100)]
tgsi/scan: add flag colors_written
This is a prerequisite for the following r600g fix.
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Marek Olšák [Fri, 11 Dec 2015 14:08:00 +0000 (15:08 +0100)]
Revert "radeonsi: disable DCC on Stoney"
This reverts commit
32f05fadbbdf2a3fb60055e610bbbdcd82dd3ce5.
It turned out the problem with Stoney was caused by incorrect handling of
a non-power-two VRAM size in the kernel driver.
This is an optional BIOS setting and can be worked around by choosing
a different VRAM size in the BIOS.
Cc: 11.1 <mesa-stable@lists.freedesktop.org>
Timothy Arceri [Fri, 11 Dec 2015 00:07:14 +0000 (11:07 +1100)]
nir: silence uninitialized warning
Reviewed-by: Rob Clark <robdclark@gmail.com>
Dave Airlie [Thu, 10 Dec 2015 01:44:34 +0000 (11:44 +1000)]
mesa/shader: return correct attribute location for double matrix arrays
If we have a dmat2[4], then dmat2[0] is at 17, dmat2[1] at 19,
dmat2[2] at 21 etc. The old code was returning 17,18,19.
I think this code is also wrong for float matricies as well.
There is now a piglit for the float case.
This partly fixes:
GL41-CTS.vertex_attrib_64bit.limits_test
[airlied: update with Tapani suggestion to clean it up].
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Roland Scheidegger [Fri, 11 Dec 2015 01:21:17 +0000 (02:21 +0100)]
draw: fix clipping with linear interpolated values and gl_ClipVertex
Discovered this when working on other clip code, apparently didn't work
correctly - the combination of linear interpolated values and using
gl_ClipVertex produced wrong values (failing all such combinations
in piglits glsl-1.30 interpolation tests, named
interpolation-noperspective-XXX-vertex).
Use the pre-clip-pos values when determining the interpolation factor to
fix this.
Noone really understands this code well, but everybody agrees this looks
sane... This fixes all those failing tests (10 in total) both with
the llvm and non-llvm draw paths, with no piglit regressions.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 10 Dec 2015 23:36:36 +0000 (09:36 +1000)]
r600: add missing return value check.
Pointed out by coverity scan.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jason Ekstrand [Wed, 25 Nov 2015 22:14:05 +0000 (14:14 -0800)]
nir: Get rid of *_indirect variants of input/output load/store intrinsics
There is some special-casing needed in a competent back-end. However, they
can do their special-casing easily enough based on whether or not the
offset is a constant. In the mean time, having the *_indirect variants
adds special cases a number of places where they don't need to be and, in
general, only complicates things. To complicate matters, NIR had no way to
convdert an indirect load/store to a direct one in the case that the
indirect was a constant so we would still not really get what the back-ends
wanted. The best solution seems to be to get rid of the *_indirect
variants entirely.
This commit is a bunch of different changes squashed together:
- nir: Get rid of *_indirect variants of input/output load/store intrinsics
- nir/glsl: Stop handling UBO/SSBO load/stores differently depending on indirect
- nir/lower_io: Get rid of load/store_foo_indirect
- i965/fs: Get rid of load/store_foo_indirect
- i965/vec4: Get rid of load/store_foo_indirect
- tgsi_to_nir: Get rid of load/store_foo_indirect
- ir3/nir: Use the new unified io intrinsics
- vc4: Do all uniform loads with byte offsets
- vc4/nir: Use the new unified io intrinsics
- vc4: Fix load_user_clip_plane crash
- vc4: add missing src for store outputs
- vc4: Fix state uniforms
- nir/lower_clip: Update to the new load/store intrinsics
- nir/lower_two_sided_color: Update to the new load intrinsic
NIR and i965 changes are
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
NIR indirect declarations and vc4 changes are
Reviewed-by: Eric Anholt <eric@anholt.net>
ir3 changes are
Reviewed-by: Rob Clark <robdclark@gmail.com>
NIR changes are
Acked-by: Rob Clark <robdclark@gmail.com>
Jason Ekstrand [Tue, 8 Dec 2015 06:41:50 +0000 (22:41 -0800)]
i965/fs_nir: Refactor store_output, load_input, and load_uniform
There was way too much incrementing of things going on. Instead, let's
just start everything off at the right base location, and then increment in
the loop.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Patrick Rudolph [Thu, 10 Dec 2015 18:50:38 +0000 (19:50 +0100)]
gallium/util: return correct number of bound vertex buffers
In case a state tracker unbinds every slot by a seperate
pipe->set_vertex_buffers() call, starting from slot zero, the number
of bound buffers would not reach zero at all.
The current algorithm does not account for pre-existing holes in the
buffer list.
Unbinding all buffers at once or starting at the top-most slot results
in correct behaviour.
Calculating the correct number of bound buffers fixes a NULL pointer
dereference in nvc0_validate_vertex_buffers_shared().
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Neil Roberts [Thu, 19 Nov 2015 14:29:19 +0000 (15:29 +0100)]
blit: Don't take into account the Mesa format when checking MSRT blit
According to the GLES3 spec, blitting between multisample FBOs with
different internal formats should not be allowed. The
compatible_resolve_formats function implements this check. Previously
it had a shortcut where if the Mesa formats of the two renderbuffers
were the same then it would assume the blit is ok. However some
drivers map different internal formats to the same Mesa format, for
example it might implement both GL_RGB and GL_RGBA textures with
MESA_FORMAT_R8G8B8A_UNORM. The function is used to generate a GL error
according to what the GL spec requires so the blit should not be
allowed in that case. This patch just removes the shortcut so that it
only ever looks at the internal format.
Note that I posted a related patch to disable this check altogether
for desktop GL. However this function is still used on GLES3 because
there are conformance tests that require this behaviour so this patch
is still useful.
Cc: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Neil Roberts [Thu, 19 Nov 2015 14:06:08 +0000 (15:06 +0100)]
i965: Check base format to determine whether to use tiled memcpy
The tiled memcpy doesn't work for copying from RGBX to RGBA because it
doesn't override the alpha component to 1.0. Commit
2cebaac479d4 added
a check to disable it for RGBX formats by looking at the TexFormat.
However a lot of the rest of the code base is written with the
assumption that an RGBA texture can be used internally to implement a
GL_RGB texture. If that is done then this check breaks. This patch
makes it instead check the base format of the texture which I think
more directly matches the intention.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Neil Roberts [Thu, 19 Nov 2015 13:02:59 +0000 (14:02 +0100)]
i965/gen8: Allow rendering to B8G8R8X8
Since Gen8 this is allowed as a rendering target so we don't need to
override it to B8G8R8A8. This is helpful on Gen9+ where using this
override causes fast clears not to work.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Neil Roberts [Wed, 18 Nov 2015 17:14:33 +0000 (18:14 +0100)]
i965/gen9: Allow fast clear for MSRT formats matching render
Previously fast clear was disallowed on Gen9 for MSRTs with the claim
that some formats don't work but we didn't understand why. On further
investigation it seems the formats that don't work are the ones where
the render surface format is being overriden to a different format
than the one used for texturing. The one used for texturing is not
actually a renderable format. It arguably makes sense that the sampler
hardware doesn't handle the fast color correctly in these cases
because it shouldn't be possible to end up with a fast cleared surface
that is non-renderable.
This patch changes the limitation to prevent fast clear for surfaces
where the format for rendering is overriden.
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
Neil Roberts [Tue, 24 Nov 2015 15:15:20 +0000 (16:15 +0100)]
i965/gen9/fast-clear: Handle linear→SRGB conversion
If GL_FRAMEBUFFER_SRGB is enabled when writing to an SRGB-capable
framebuffer then the color will be converted from linear to SRGB
before being written. There is no chance for the hardware to do this
itself because it can't modify the clear color that is programmed in
the surface state so it seems pretty clear that the driver should be
handling this itself.
Note that this wasn't a problem before Gen9 because previously we were
only able to do fast clears to 0 or 1 and those values are the same in
linear and SRGB space.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Jordan Justen [Sun, 27 Sep 2015 06:50:55 +0000 (23:50 -0700)]
docs: Add ARB_compute_shader to 11.2.0 release notes
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Sun, 27 Sep 2015 06:49:52 +0000 (23:49 -0700)]
docs: Mark ARB_compute_shader as done for i965
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Wed, 2 Sep 2015 22:47:33 +0000 (15:47 -0700)]
i965: Enable ARB_compute_shader extension on supported hardware
Enable ARB_compute_shader on gen7+, on hardware that supports the
OpenGL 4.3 requirements of a local group size of 1024.
With SIMD16 support, this is limited to Ivy Bridge and Haswell.
Broadwell will work with a local group size up to 896 on SIMD16
meaning programs that use this size or lower should run when setting
MESA_EXTENSION_OVERRIDE=GL_ARB_compute_shader.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Sat, 10 Oct 2015 20:01:03 +0000 (13:01 -0700)]
i965/nir: Implement shared variable atomic operations
v3:
* Update based on latest SSBO code (Iago)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Sat, 10 Oct 2015 19:25:39 +0000 (12:25 -0700)]
nir: Add nir intrinsics for shared variable atomic operations
v3:
* Update min/max based on latest SSBO code (Iago)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Sat, 10 Oct 2015 18:30:33 +0000 (11:30 -0700)]
glsl: Disable several optimizations on shared variables
Shared variables can be accessed by other threads within the same
local workgroup. This prevents us from performing certain
optimizations with shared variables.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Sat, 10 Oct 2015 16:36:22 +0000 (09:36 -0700)]
glsl: Buffer atomics are supported for compute shaders
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Sat, 10 Oct 2015 14:55:42 +0000 (07:55 -0700)]
glsl: Translate atomic intrinsic functions on shared variables
When an intrinsic atomic operation is used on a shared variable, we
translate it to a new 'shared variable' specific intrinsic function
call.
For example, a call to __intrinsic_atomic_add when used on a shared
variable will be translated to a call to
__intrinsic_atomic_add_shared.
v3:
* Fix stale comments copied from SSBOs (Iago)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Tue, 17 Nov 2015 18:55:26 +0000 (10:55 -0800)]
glsl: Check for SSBO variable in check_for_ssbo_store
The compiler probably already blocks this earlier on, but we should be
checking for an SSBO here.
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Sat, 10 Oct 2015 00:43:53 +0000 (17:43 -0700)]
glsl: Check for SSBO variable in SSBO atomic lowering
When an atomic function is called, we need to check to see if it is
for an SSBO variable before lowering it to the SSBO specific intrinsic
function.
v2:
* is_in_buffer_block => is_in_shader_storage_block (Iago)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Fri, 9 Oct 2015 22:55:34 +0000 (15:55 -0700)]
glsl: Replace atomic_ssbo and ssbo_atomic with atomic
The atomic functions can also be used with shared variables in compute
shaders.
When lowering the intrinsic in lower_ubo_reference, we still create an
SSBO specific intrinsic since SSBO accesses can be indirectly
addressed, whereas all compute shader shared variable live in a single
shared variable area.
v2:
* Also remove the _internal suffix from ssbo atomic intrinsic names (Iago)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Fri, 9 Oct 2015 22:32:33 +0000 (15:32 -0700)]
glsl: Allow atomic functions to be used with shared variables
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Jordan Justen [Tue, 28 Jul 2015 21:55:00 +0000 (14:55 -0700)]
i965: Lower shared variable references to intrinsic calls
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>