Jesse Natalie [Thu, 6 Jan 2022 15:42:22 +0000 (07:42 -0800)]
d3d12: Handle input clip array size in the shader key
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Wed, 5 Jan 2022 15:38:38 +0000 (07:38 -0800)]
d3d12: Update varying creation logic to handle location_frac
When multiple variables are packed into the same location, we need
to re-construct variables that read/write the same components of that
register so that the DXIL signature is correct. We could try to
merge these variables, but getting the types right sounds harder than
just preserving the multiple individual variables.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Thu, 6 Jan 2022 00:07:51 +0000 (16:07 -0800)]
d3d12: Add a state variable for patch_vertices_in
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 20:49:28 +0000 (12:49 -0800)]
d3d12: Handle passthrough TCS in the case where eval is bound
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 23:21:55 +0000 (15:21 -0800)]
d3d12: Handle patch_vertices and patch topology
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 21:03:32 +0000 (13:03 -0800)]
d3d12: Link tesselation control and eval shaders
GLSL puts a bunch of tessellation info in the eval shaders, because
passthrough control shaders can exist. D3D12 puts it in the control
(hull) shader instead. So, when specializing, copy info from domain
to hull. For initial compiles (no domain shader), just make something
up.
D3D12 also requires the domain and hull shaders to have identical
patch constant signatures. Use the existing infrastructure and extend
it to also propagate patch constants. Notably, patch constant locations
are outside of the 64-bit range value so they require a separate pass
to avoid shifts larger than 64.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sat, 1 Jan 2022 22:49:28 +0000 (14:49 -0800)]
d3d12: Initial plumbing for tesselation
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Thu, 6 Jan 2022 17:03:18 +0000 (09:03 -0800)]
d3d12: Enable PIPE_CAP_TGSI_TEXCOORD
This is required to be able to use the necessary number of varyings,
otherwise we hit asserts because mesa/st starts assigning varyings
locations above 64 due to the +9 reserving these texcoords.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Thu, 6 Jan 2022 15:40:24 +0000 (07:40 -0800)]
microsoft/compiler: Handle clip/cull distance as an input to tess shaders
In order to get the semantics right, we need to know how many of the clip/
cull fields are designated for which purpose. In the case of a shader that
can receive these fields as both input and output, the shader_info property
is reserved to store the output info. We could add a dedicated input field
to shader_info, but since it'd probably only be useful for us, just send
it through a side channel during shader linking.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Wed, 5 Jan 2022 15:40:49 +0000 (07:40 -0800)]
microsoft/compiler: Location_frac needs to be included in sort order
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 22:47:35 +0000 (14:47 -0800)]
microsoft/compiler: Primitive ID should only be added as a sysval in geometry shaders
Docs say that its presence in signatures as a "shadow" element (meaning it's not
accessed via load/store, but with a dedicated opcode) is legacy. It seems it
wasn't carried forward when HS/DS were added in D3D11.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 17:04:03 +0000 (09:04 -0800)]
microsoft/compiler: Emit DS PSV validation and entrypoint metadata
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 23:23:06 +0000 (15:23 -0800)]
microsoft/compiler: Handle domain location intrinsic
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 4 Jan 2022 16:39:26 +0000 (08:39 -0800)]
microsoft/compiler: Handle load_output in the HS stage as reading a previously written patch constant
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 4 Jan 2022 00:15:12 +0000 (16:15 -0800)]
microsoft/compiler: Handle load_per_vertex_output as LoadOutputControlPoint
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 21:35:39 +0000 (13:35 -0800)]
microsoft/compiler: For load_input from DS, use loadPatchConstant
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 17:56:08 +0000 (09:56 -0800)]
microsoft/compiler: For store_output from HS, use storePatchConstant
In HS, store_per_vertex_output maps to storeOutput in DXIL. The data
that isn't per-vertex is patch constants.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:51:36 +0000 (05:51 -0800)]
microsoft/compiler: Add a pass for hull and domain shaders to shrink tess level vars
DXIL validation will complain if the tess factor signature entries have the
wrong number of components for the shader's domain. Make sure that both
hull and domain shaders have the right number, and drop loads and stores
from the removed components.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 14:08:35 +0000 (06:08 -0800)]
microsoft/compiler: Add patch constant signature into PSV and as container blob
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 14:01:14 +0000 (06:01 -0800)]
microsoft/compiler: Gather patch const signature and handle tess factor in it
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 21:33:53 +0000 (13:33 -0800)]
microsoft/compiler: When sorting patch varyings, adjust location to be in normal varying range
This way, patch varyings come before the patch sysvals (tess levels).
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 18:15:58 +0000 (10:15 -0800)]
microsoft/compiler: Overlap patch and non-patch varyings so both are separately 0-indexed
Also add tess factors to the list of sysvals that can cause vars to be sorted last.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:45:48 +0000 (05:45 -0800)]
microsoft/compiler: Fix I/O signatures for tess shaders
- Skip patch variables, those go into a separate patch constant signature
- Use nir_is_arrayed_io and only strip one level of array when it's true
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 14:20:25 +0000 (06:20 -0800)]
microsoft/compiler: Emit HS PSV validation and entrypoint metadata
Note that this requires the shader info "tess" data to be correct.
For GLSL tess control shaders, only the output primitive count is
automatically available. The rest will need to be either guessed
or filled in from a matching tess eval (domain) shader. This is handled
by the d3d12 driver in a later patch.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 19:56:09 +0000 (11:56 -0800)]
microsoft/compiler: Delete misleading TODO comments about semantic table
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
We've been writing a valid semantic table for a while now.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sat, 1 Jan 2022 21:14:05 +0000 (13:14 -0800)]
microsoft/compiler: Split hull (tess ctrl) shaders into main and patch constant funcs
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:23:48 +0000 (05:23 -0800)]
microsoft/compiler: Handle store_per_vertex_output for HS outputs
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:17:25 +0000 (05:17 -0800)]
microsoft/compiler: Emit all NIR functions into the DXIL module
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 00:04:47 +0000 (16:04 -0800)]
microsoft/compiler: Emit functions with actual function names
Once we start writing multiple functions, we can't keep calling all
of them "main"
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 13:13:39 +0000 (05:13 -0800)]
microsoft/compiler: Support emitting multiple functions into a DXIL module
The instruction and block lists are moved into a new "function definition"
struct, and the DXIL module tracks one at a time for adding instructions
into. The NIR side still only emits the main function here though.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 25 Jan 2022 23:20:23 +0000 (15:20 -0800)]
microsoft/compiler: Emit statically-indexed resource handles and scratch later
The resource declarations are module-wide, but the resource handles
are function-local. A future change will add multi-function support,
but requires these handles to be potentially emitted multiple times.
The alloca used for scratch is also function-local.
This is the same pattern that the DXBC to DXIL converter uses.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Tue, 25 Jan 2022 23:20:31 +0000 (15:20 -0800)]
microsoft/compiler: Fix typo in enum entry
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 12:59:36 +0000 (04:59 -0800)]
microsoft/compiler: Add mapping from MESA_SHADER_* to DXIL_*_SHADER for tessellation
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 12:59:03 +0000 (04:59 -0800)]
microsoft/compiler: Getting a builtin function with an undeclared signature should be unreachable
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 19:58:00 +0000 (11:58 -0800)]
microsoft/compiler: Multi-row output semantics need to write multiple never_writes_masks
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Sun, 2 Jan 2022 19:57:34 +0000 (11:57 -0800)]
microsoft/compiler: Semantic table should be de-duped for multi-row semantics too
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 17:48:12 +0000 (09:48 -0800)]
microsoft/compiler: Use driver_location instead of location for inter-stage varying index in GL
In the case of two vars being packed into the same register / location,
they'll still get unique driver_location, which is what we need.
This does require some tweaks to stream output handling, which also needs to
produce the varying index.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Jesse Natalie [Mon, 3 Jan 2022 17:47:36 +0000 (09:47 -0800)]
microsoft/compiler: Force integer I/O vars to use flat/constant interpolation
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Bill Kristiansen <billkris@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14399>
Dave Airlie [Tue, 25 Jan 2022 03:39:02 +0000 (13:39 +1000)]
mesa/st: refactor program translation into one file.
This moves the notify callback into the file where it's all called
from.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 06:20:48 +0000 (16:20 +1000)]
mesa/st: move program new/delete into mesa
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 06:15:22 +0000 (16:15 +1000)]
mesa/st: move st_vertex_program to gl_vertex_program in mesa
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 06:00:43 +0000 (16:00 +1000)]
mesa/st: move new ati fragment shader to mesa
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Dave Airlie [Mon, 20 Dec 2021 05:54:08 +0000 (15:54 +1000)]
mesa/st: collapse st_program into gl_program object.
Remove the subclass for this.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14700>
Jordan Justen [Tue, 25 Jan 2022 07:40:07 +0000 (23:40 -0800)]
intel/genxml: Extend length of 3DSTATE_DEPTH_BUFFER for gfx12.5
The two added dwords are MBZ.
Ref: bspec 46935
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702>
Jordan Justen [Wed, 9 Oct 2019 10:59:16 +0000 (03:59 -0700)]
intel/genxml: Extend length of 3DSTATE_WM_HZ_OP for gfx12.5
The added dword is MBZ.
Ref: bspec 46981
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14702>
Mike Blumenkrantz [Tue, 25 Jan 2022 21:48:22 +0000 (16:48 -0500)]
zink: add anv (icl) fails
mesa/mesa#5918
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14722>
Mike Blumenkrantz [Fri, 21 Jan 2022 14:39:22 +0000 (09:39 -0500)]
zink: never use SpvOpImageQuerySizeLod for texel buffers
this is illegal
cc: mesa-stable
affects KHR-GL46.texture_buffer.texture_buffer_texture_buffer_range
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14696>
Mike Blumenkrantz [Tue, 25 Jan 2022 21:29:57 +0000 (16:29 -0500)]
zink: update radv fails list
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14717>
Mike Blumenkrantz [Thu, 20 Jan 2022 20:14:23 +0000 (15:14 -0500)]
zink: update nv fails
more passes
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14716>
Caio Oliveira [Sun, 23 Jan 2022 21:08:03 +0000 (13:08 -0800)]
intel/fs/xehp: Add unit test for handling of RaR deps across multiple pipelines.
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Paulo Zanoni [Wed, 15 Dec 2021 23:53:29 +0000 (15:53 -0800)]
intel/fs: Assert the GPU supports 64bit ops if present at lower_scoreboard time.
On platforms where we don't support 64 bit instructions we shouldn't
pass such instructions for the code generator to lower into supported
instructions, because this makes their execution pipeline
unpredictable to the scoreboard lowering pass on XeHP+ platforms.
We really should be reducing all these 64 bit instructions before code
generation, so here we add an assert to help us catch and fix these
cases more easily.
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
[ Francisco Jerez: Also allow has_integer_dword_mul. ]
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:34:13 +0000 (14:34 -0800)]
intel/fs: Perform 64-bit CLUSTER_BROADCAST lowering in the lower_regioning pass.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 08:20:38 +0000 (00:20 -0800)]
intel/fs: Honor strided source regions specified by the IR for CLUSTER_BROADCAST.
This fixes a bug in the CLUSTER_BROADCAST code generation that causes
the original IR region to be ignored, this will be a problem when we
start lowering 64-bit CLUSTER_BROADCAST instructions at the IR level,
since it will lead to instructions with non-trivial regioning.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:33:45 +0000 (14:33 -0800)]
intel/fs: Perform 64-bit SEL_EXEC lowering in the lower_regioning pass.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:52:16 +0000 (14:52 -0800)]
intel/fs: Perform 64-bit SHUFFLE lowering in the lower_regioning pass.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:49:02 +0000 (14:49 -0800)]
intel/fs: Fix destination suboffset calculations for non-trivial strides in SHUFFLE codegen.
One of the two SHUFFLE implementations wasn't taking into account the
destination stride at all, and the other (more commonly used) one was
taking it into account incorrectly since brw_reg::hstride represents
the stride logarithmically, so we need to use a left-shift operator
instead of product. Found by inspection.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 09:54:57 +0000 (01:54 -0800)]
intel/fs: Take into account region strides during SIMD lowering decision of SHUFFLE.
This fixes a bug in the handcrafted SIMD lowering done by the SHUFFLE
code generation, which wasn't taking into account the source and
destination region strides while deciding whether it needs to split an
instruction.
v2: Use new element_sz() helper instead of left shift. (Lionel)
Fixes:
90c9f29518d ("i965/fs: Add support for nir_intrinsic_shuffle")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:15:47 +0000 (14:15 -0800)]
intel/fs: Teach the lower_regioning pass how to split instructions of unsuported exec type.
This adds some generic infrastructure that allows splitting any
instruction into a number of instructions of a smaller legal execution
type. This is meant to replace several instances of handcrafted 64bit
type lowering done manually in the code generator, which is rather
error-prone, prevents scheduling of the lowered instructions, and
makes them invisible to the SWSB pass on Gfx12+ platforms, which will
become especially problematic on Gfx12.5+ since the EUs introduce
multiple asynchronous execution pipelines which the SWSB pass needs to
be able to synchronize to one another, so it's critical for the real
execution type of the instruction to be visible to the SWSB pass.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Mon, 20 Dec 2021 22:01:50 +0000 (14:01 -0800)]
intel/fs: Move legal exec type calculation into helper function in lower_regioning pass.
Right now the execution type lowering functionality of this pass
assumes that an integer type of the original bit size is always
acceptable, however we'll want more complex behavior than that in
order to leverage this pass to automate the lowering of unsupported
64-bit operations into multiple 32-bit operations.
In order to do that calculate the closest legal execution type from a
new helper function, and take advantage of that function from the
has_invalid_exec_type() helper, along the lines of other
lower_regioning() helpers structured as a pair of has_invalid_foo() +
required_foo() functions.
This shouldn't have any functional changes.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Francisco Jerez [Tue, 14 Dec 2021 07:48:29 +0000 (23:48 -0800)]
intel/fs/xehp: Merge repeated in-order read dependencies instead of replacement.
Previously the software scoreboard structure would drop previous
dependencies for a given register and replace them with the most
recent one for the same register when a new instruction (or set of
instructions) is processed. This worked correctly on the Gfx12LP
platforms this code was originally designed for, because a repeated
dependency on the same register would either require the second
instruction to synchronize against the first (so the first dependency
could be disregarded from that point on) *or* require the dependency
to be RaR and in-order, which allows the synchronization to be
optimized out (the first dependency could still be disregarded as
well, since the pipeline is in-order). However the latter assumption
will break on upcoming Gfx12HP platforms, because they have multiple
asynchronous FPU pipelines, so whenever we hit a RaR dependency we
need to propagate forward both dependencies, since the order in which
both reads will complete is not guaranteed by the hardware in cases
where they occur from different asynchronous pipelines.
Note that this dependency propagation change requires us to change the
definition of dependency::done as well, since that constant is defined
to discard any previous dependency information when used as argument
for shadow().
This has been reported to fix the following conformance failures on DG2:
KHR-GL46.shaders.uniform_block.random.all_per_block_buffers.19
dEQP-GLES3.functional.shaders.derivate.fwidth.*
Reported-by: Tapani Pälli <tapani.palli@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5670
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14273>
Alejandro Piñeiro [Tue, 25 Jan 2022 12:59:45 +0000 (13:59 +0100)]
vc4/nir_lower_blend: update write mask when we update num components
As explained at the header of the lowering:
"Once this pass is done, the color write will either have one
component (for single sample) with packed argb8888, or 4 components
with the per-sample argb8888 result."
So in several cases the lowering was updating the number of
components, so we need to update the writemask too.
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Jose Maria Casanova Crespo <jmcasanova@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14708>
Bas Nieuwenhuizen [Thu, 20 Jan 2022 23:57:52 +0000 (00:57 +0100)]
radv/amdgpu: Use aligned sizing for IB buffers.
Otherwise aligning might run over buffer size ...
Fixes:
1f36f6b83f2 ("radv/winsys: use same IBs padding as the kernel")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14644>
Bas Nieuwenhuizen [Thu, 20 Jan 2022 23:03:14 +0000 (00:03 +0100)]
radv/amdgpu: Fix handling of IB alignment > 4 words.
We reserved space for chaining by subtracting 4 words from max_dw, but
then the new alignment code in radv_amdgpu_cs_finalize ended up running
all over that. That resulted in going over buffer size when chaining.
When lucky you'd get a crash, and when unlucky other stuff might happen.
This always adds the 4 words at the end, but initializes with NOP by
default. That way we still adhere to the alignment rules.
Fixes:
1f36f6b83f2 ("radv/winsys: use same IBs padding as the kernel")
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14644>
Dave Airlie [Tue, 25 Jan 2022 06:01:00 +0000 (16:01 +1000)]
mesa: consolidate setting no error state and checking suid.
This makes MESA_NO_ERROR and mesa_no_error via drirc do the same thing.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14701>
Samuel Pitoiset [Tue, 25 Jan 2022 14:40:18 +0000 (15:40 +0100)]
radv/ci: mark dEQP-VK.api.version_check.version as expected failure on Stoney
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Mon, 4 Oct 2021 14:47:58 +0000 (16:47 +0200)]
radv: advertise Vulkan 1.3
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Wed, 12 Jan 2022 07:18:10 +0000 (08:18 +0100)]
radv: bump conformance version to 1.3.0.0 for RDNA2
We can't report conformance for an older major API version and this is
required to pass dEQP-VK.api.driver_properties.conformance_version.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Fri, 19 Nov 2021 15:44:26 +0000 (16:44 +0100)]
radv: switch a bunch of struct/enum to 1.3 versions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Thu, 13 Jan 2022 06:55:57 +0000 (07:55 +0100)]
radv: add a no-op version of vkGetPhysicalDeviceToolPropertiesEXT()
It seems the vulkan common runtime code exposes VK_EXT_tooling but
doesn't (yet) have a fallback if the backend doesn't enable this
extension. Implement it as a no-op for a temporary workaround.
This fixes crashes with dEQP-VK.api.tooling_info.*.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Wed, 12 Jan 2022 07:10:28 +0000 (08:10 +0100)]
radv: report textureCompressionASTC_HDR as not supported
To fix a mismatch with
dEQP-VK.api.info.get_physical_device_properties2.features.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Mon, 4 Oct 2021 14:34:28 +0000 (16:34 +0200)]
radv: implement 1.3 features/properties
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Jason Ekstrand [Wed, 12 Jan 2022 20:15:45 +0000 (12:15 -0800)]
vulkan/runtime: Implement 1.3 features/properties
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Samuel Pitoiset [Fri, 19 Nov 2021 15:44:15 +0000 (16:44 +0100)]
vulkan: Update the XML and headers to 1.3.204
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14707>
Michel Dänzer [Tue, 25 Jan 2022 14:48:47 +0000 (15:48 +0100)]
Revert "wsi/x11: Avoid a class of deadlocks in the WSI queue thread"
This reverts commit
272fba8e7540f09163169a6e95bc108919ca24ff.
Multiple regressions have been reported against this. Let's revert and
maybe try again.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5910
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5913
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14710>
Jordan Justen [Tue, 3 Aug 2021 20:39:12 +0000 (13:39 -0700)]
intel/dev: Add device info for RPL
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=
52407c220c44c8dcc6aa8aa35ffc8a2db3c849a9
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14664>
Danylo Piliaiev [Wed, 19 Jan 2022 15:10:17 +0000 (17:10 +0200)]
tu: add reference counting for descriptor set layouts
The spec states that descriptor set layouts can be destroyed almost
at any time:
"VkDescriptorSetLayout objects may be accessed by commands that operate
on descriptor sets allocated using that layout, and those descriptor
sets must not be updated with vkUpdateDescriptorSets after the descriptor
set layout has been destroyed. Otherwise, a VkDescriptorSetLayout object
passed as a parameter to create another object is not further accessed
by that object after the duration of the command it is passed into."
Copied mostly from ANV.
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5893
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14622>
Lionel Landwerlin [Mon, 24 Jan 2022 09:49:19 +0000 (11:49 +0200)]
anv: verify that the format supports multisampling
We tightened the requirements for multisampling on Gfx7 but didn't
format that at the Vulkan level.
This will break more conformance tests on Gfx7, but we weren't
conformant anyway.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes:
531b1b7511af ("intel/isl: Strengthen MCS SINT format restriction")
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14679>
Jordan Justen [Sun, 23 Jan 2022 09:28:52 +0000 (01:28 -0800)]
intel/dev: Add device ids for ADL-N
Ref: https://cgit.freedesktop.org/drm/drm-tip/commit/?id=
7e28d0b26759846485978ada860ef4a427e06c8f
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14666>
Jordan Justen [Sun, 23 Jan 2022 08:58:18 +0000 (00:58 -0800)]
intel/dev: Add DG1 PCI id 0x4909
Ref: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?id=
5f0d4214938db66969a50d4b1262307e39f4f2b2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14665>
Iago Toral Quiroga [Fri, 21 Jan 2022 12:31:19 +0000 (13:31 +0100)]
v3dv: support VK_KHR_8bit_storage
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Fri, 21 Jan 2022 12:30:22 +0000 (13:30 +0100)]
broadcom/compiler: update comment on load_uniform fast-path
The comment for 16-bit applies to 8-bit uniforms as well.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Fri, 21 Jan 2022 12:10:55 +0000 (13:10 +0100)]
broadcom/compiler: allow vectorization to larger scalar type
Allow to vectorize operations from a smaller bit-size into
scalar operations of a larger bit-size. This allows us to
turn 2x8-bit into a equivalent scalar 16-bit load/store.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Fri, 21 Jan 2022 12:08:28 +0000 (13:08 +0100)]
broadcom/compiler: support 8-bit loads via ldunifa
This generalizes the support we added for 16-bit to also handle
8-bit loads via ldunifa. The story is the same: we align the address
to 32-bit downwards and we skip any bytes that are not of interest.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Fri, 21 Jan 2022 11:05:15 +0000 (12:05 +0100)]
broadcom/compiler: handle to/from 8-bit integer conversions
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Fri, 21 Jan 2022 11:04:11 +0000 (12:04 +0100)]
broadcom/compiler: support 8-bit general store access
Just like with 16-bit, this mode only supports scalar access, but
we are already lowering all non 32-bit accesses to scalar.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Wed, 19 Jan 2022 11:33:10 +0000 (12:33 +0100)]
v3dv: expose storagePushConstant16 feature from VK_KHR_16bit_storage
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Wed, 19 Jan 2022 11:32:42 +0000 (12:32 +0100)]
broadcom/compiler: support 16-bit uniforms
Since ldunif is a 32-bit instruction we need to demote these to
UBO loads, like we do for indirect indexing, with the exception
of scalar 16bit uniforms with an offset that is 32-bit aligned.
For the exception where we can use lfdunif we read a 32-bit slot
from memory where the uniform data is in the lower 16-bit and we
will read garbage in the upper 16-bit which we won't use anyway.
It should be noted that by using ldunif, we are consuming
32-bit from the uniform stream, but this is fine because
if there is valid uniform data in the upper 16-bit (i.e.
we had a ivec2 uniform aligned to a 32-bit address), since
we scalarize 16-bit loads, we would see another load uniform
with an unaligned offset for the second component, which we
will demote to UBO.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Tue, 18 Jan 2022 10:17:29 +0000 (11:17 +0100)]
v3dv: support VK_KHR_16_bit_storage
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Thu, 20 Jan 2022 13:44:05 +0000 (14:44 +0100)]
broadcom/compiler: support f32 to f16 RTZ and RTE rounding modes
These are required by VK_KHR_16bit_storage. Our hardware, however,
doesn't provide any mechanism to decide on the rounding mode of
the conversion and it seems to be using RTE, so we implement
RTZ in software.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Tue, 18 Jan 2022 10:15:45 +0000 (11:15 +0100)]
broadcom/compiler: implement 32-bit/16-bit conversion opcodes
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Tue, 18 Jan 2022 11:02:36 +0000 (12:02 +0100)]
broadcom/compiler: use ldunifa with unaligned constant offset
If we know we have a load with a constant offset, then even if it
is not aligned to 32-bit we can still produce an aligned offset
and then skip over the bytes we don't need.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Tue, 18 Jan 2022 10:13:56 +0000 (11:13 +0100)]
broadcom/compiler: support ldunifa with some 16-bit loads
Even though ldunifa is strictly 32-bit we may be able to use it
to load 16-bit values that sit at 32-bit aligned addresses.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Wed, 19 Jan 2022 08:48:49 +0000 (09:48 +0100)]
broadcom/compiler: lower packing after vectorization
The vectorization pass can inject 32_2x16 (un)packing opcodes
upon successful vectorization of 16-bit operations into 32-bit
counterparts, so make sure we lower these to something our
backend can handle.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Tue, 18 Jan 2022 10:06:50 +0000 (11:06 +0100)]
broadcom/compiler: implement TMU general 16-bit load/store
This allows us to implement 16-bit access on uniform and
storage buffers.
Notice that V3D hardware can only do general access on scalar
16-bit elements, which we currently enforce by running a lowering
pass during shader compile.
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Wed, 19 Jan 2022 08:36:49 +0000 (09:36 +0100)]
broadcom/compiler: better document vectorization implications
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Iago Toral Quiroga [Tue, 18 Jan 2022 09:59:42 +0000 (10:59 +0100)]
broadcom/compiler: add lowering pass to scalarize non 32-bit general load/store
V3D hardware doesn't support vector access for general TMU load/store
operations like the ones we use for UBO and SSBO, so we need to split
these to scalar operations.
It should be noted that we also have a vectorization pass (which runs
later, during optimization), that may reconstruct some of these into
32-bit operations when possible (i.e. when the resulting operation
is 32-bit aligned).
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14648>
Tapani Pälli [Wed, 19 Jan 2022 07:51:30 +0000 (09:51 +0200)]
mesa: change GetProgramiv name length queries to use program resources
Program resource queries provide equivalent code, gl_resource_name
introduced by commit
dea558cbd29 takes care of ARB_gl_spirv special
case where name information is not available.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14636>
Tapani Pälli [Thu, 20 Jan 2022 10:18:24 +0000 (12:18 +0200)]
mesa: move GetProgramInterfaceiv as a shader_query function
This matches how _mesa_get_program_resourceiv was done and this
makes it possible to skip some validation and shader program lookup
when calling it from glGetProgramiv.
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14636>
Emma Anholt [Tue, 28 Dec 2021 18:03:35 +0000 (10:03 -0800)]
nir/lower_locals_to_regs: Do an ad-hoc copy propagate on our generated MOV.
I noticed the inefficiency in NIR-to-TGSI output while trying to debug a
failure handling some arrays in r600. While this makes reading CTS
shaders easier, the effect in the real world is pretty limited. From
softpipe shader-db:
total instructions in shared programs: 2929840 -> 2929836 (<.01%)
instructions in affected programs: 118 -> 114 (-3.39%)
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14321>
Chia-I Wu [Tue, 25 Jan 2022 01:30:23 +0000 (17:30 -0800)]
freedreno/drm, turnip: set DRM_RDWR for exported dma-bufs
This allows the exported fds to be mapped for writing. My use case is
for virtio-gpu blob resources where the fds are mapped rw and mappings
are added to the guests using KVM_SET_USER_MEMORY_REGION.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14699>