docs: do not generate redirects on error

The build-finished event is also triggered when there's an error. I
somehow got the second argument wrong, and ended up ignoring the case.
This can lead to new exceptions being thrown due to missing files, that
ends up hiding the real problem.

Fixes: 64a4ba9e1ce ("docs: add an extension to generate redirects")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10407>

zink: only emit ImageBuffer cap if needed

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>

zink: emit cap early

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>

zink: emit sample-shading cap early

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>

zink: remove needless shader-info from context

There's no longer any code reading this, so let's get rid of it. It
always rubbed me a bit the wrong way, because this repeated some
information already present in the context.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>

zink: emit cap early

We have enough information to emit this cap early, so let's do that.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>

zink: do not check for varying output for fragment shaders

This will make us emit these caps needlessly, possibly on implementations
not supporting the enabling features.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>

zink: always enable fixed shader-caps

This is required for a bunch of stuff that can occur in any Vulkan
shader stage, not just these few. So let's always emit this cap.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10371>

intel/decoder: add gen4/5 geometry state decode

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642>

intel/decoder: fixup batch decoder for binding tables on gen4/5

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10642>

radv: expose 2/3rd of total memory as VRAM and 1/3rd as GTT on APUs

A bunch of games complain when the VRAM size is too small. The most
compatible solution seems to return memory heaps like a dGPU.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3423
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9774>

radv: adjust the computation of the total usage of memory used

internal_usage is the memory allocated by the current process (intent)
while system_usage is the memory allocated globally (actual).

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9774>

gallium/u_threaded: don't set resource pointers to NULL after driver calls

The pointers won't be used at that point. Just decrement the refcounts.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>

gallium/u_threaded: rewrite slot layout to reduce wasted space

A lot of space was wasted due to 16-byte alignment for slots. This new
layout tries to match glthread. Highlights:

- the slot size changed to 8 bytes (was 16), so less padding
- the header size changed to 4 bytes (was 8), so some calls can use
  the remaining 4 bytes in the slot for parameters
- draw merging merges up to 307 draws (was 256) due to space savings
- parameters in structures are sorted based on implicit type alignment
  (uint8_t first, pointers last) to make it easier to utilize the 4 bytes
  after the header and to remove holes
- some structures use smaller types for parameters than pipe_context where
  it's safe (e.g. clear uses float instead of double for depth)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>

gallium/u_threaded: handle sampler views == NULL better

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>

gallium/u_threaded: move base_valid_buffer_range to transfer where it belongs

This saves 8 bytes per resource.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>

Revert "gallium/u_threaded: align batches and call slots to 16 bytes"

This reverts commit 3b1ce49bc1e5aff87805b0bab255885c84bf5052.

It will be completely rewritten, but let's revert this first.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.eric.pelloux-prayer@amd.com>
Acked-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10606>

gallium: Reset attachments to ST_ATTACHMENT_INVALID when revalidating

It is *super* *confusing* to leave this initialized to zero, i.e.
ST_ATTACHMENT_FRONT_LEFT.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10491>

mesa: Ignore the depth buffer when computing framebuffer floatness

Not that Z32F is especially common, but we shouldn't consider it to
imply that the color buffers are also float, which is what floatMode
is meant to mean.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10491>

mesa: Remove unused _mesa_{create,destroy}_visual

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10491>

util/math: change ROUND_DOWN_TO to return a uint64_t

For 32-bit builds.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10622>

intel/genxml: fix raster op fields on gen4/5

These should be unsigned integers

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>

intel/gemxml: move blitter command to render on gen4/5

The blitter commands don't show up in INTEL_DEBUG=bat, but on
gen4/5 they are emitted on the render engine ring so just change
the XML to reflect that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>

intel/genxml: rewrite the prefilterop xml to be more consistent.

This uses a prefix at Ken's suggestion and aligns it across gens

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>

intel/genxml: align gen4/5 xml for store data immediate

Just align with the gen6 and later xml

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>

intel: fix MI builder for pre-gen7

MI_LOAD_REGISTER_MEM is only available on gen7+, so avoid build errors
on earlier generations.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10636>

zink: export PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

zink: implement sparse buffer creation/mapping

sparse buffers are not cpu-readable, so any mapping requires that they
use a staging buffer, either the stream uploader for writes or a manual
copy for readback

future work here should attempt to resolve two perf issues:
* sparse allocations should be allocated dynamically using a suballocator
  or some other, more useful strategy
* readback shouldn't allocate a huge staging buffer

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

zink: add a pipe_context::resource_commit hook

so many structs

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

zink: use new ctx device lost checker function

make this handling more consistent

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

zink: add a ctx function for handling device lost resets

ensure the reset function is only called once when the screen flag is set

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

zink: use zink_screen_handle_vkresult() for fence and timeline waiting

more consistent handling and some code size reduction

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

zink: add a screen util function for handling VkResults

enforce device lost status always

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

zink: minor refactoring of buffer map for read case

make this a little more flexible for the non-DONTBLOCK case

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10509>

pan/bi: Use nir_lower_to_bit_size

Last holdout of the backend algebraic pass. Delete it.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Switch to 1-bit bools

In prep for FP16.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Don't swizzle scalars

Pointless, already replicated.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Track scalarness of 16-bit ALU

Needed for optimal swizzle lowering.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Handle b2i8/16

Missing from the algebraic rules, get it right this time.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Handle b2f ourselves

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Handle ineg

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Handle integer min/max ourselves

total instructions in shared programs: 158197 -> 158181 (-0.01%)
instructions in affected programs: 169 -> 153 (-9.47%)
helped: 3
HURT: 0

total nops in shared programs: 116393 -> 116397 (<.01%)
nops in affected programs: 60 -> 64 (6.67%)
helped: 0
HURT: 2

total clauses in shared programs: 28628 -> 28627 (<.01%)
clauses in affected programs: 10 -> 9 (-10.00%)
helped: 1
HURT: 0

total quadwords in shared programs: 124146 -> 124140 (<.01%)
quadwords in affected programs: 127 -> 121 (-4.72%)
helped: 3

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

pan/bi: Add imm_uintN helper

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10627>

zink: support PIPE_CAP_QUERY_MEMORY_INFO

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10511>

zink: hook up VK_EXT_memory_budget

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10511>

zink: grab GetPhysicalDeviceMemoryProperties2 from instance

Acked-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10511>

ci/freedreno: Mark a5xx texture gather as flaky.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10633>

nir/builder: Move clamp helpers to nir_builder.h

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10631>

vulkan/device_select: avoid segfault on Wayland if wl_drm is unavailable

On Wayland, if the wl_drm interface is not available, for example if the
compositor is using the proprietary NVIDIA driver along with their egl-wayland
library, the device_select layer will fail to initialize. However, the failure
path will unconditionally call wl_drm_destroy even though info.wl_drm would be
NULL in that case. This can cause a segfault in libwayland-client.so.

To fix this, check if info.wl_drm is NULL before calling wl_drm_destroy. This
way, initialization will fail gracefully even if that interface is not present.

Signed-off-by: Erik Kurzinger <ekurzinger@nvidia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10598>

nir: Move shared_memory_explicit_layout bit into common shader_info

Move it out of the "cs" sub-struct, since the bit can be used for
other shader stages in the future.

This also removes a subtle issue in spirv_to_nir:
info.cs.shared_memory_explicit_layout was used without checking for
the CS shader stage.  It ended up being "harmless" since the effects
also depended on presence of shared variables.

Fixes: 5de6c5973a6 ("spirv: Implement SPV_KHR_workgroup_memory_explicit_layout")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10529>

tunrip: Add support for VK_EXT_separate_stencil_usage.

We were implictly including it in exposing VK 1.2, but we weren't making
use of the supplied struct.  Actually enabling it gives us a chance to do
slightly better at Z/S UBWC, and means we won't lose the separate usage
test coverage when switching back to exposing VK 1.1.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10594>

zink: cache SpvId for aggregate glsl_types

This should reduce the amount of types we re-emit while producing
SPIR-V.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10372>

zink: handle matrix-types after vectors

This makes us handle all non-aggregate types before we handle aggregate
types. This is going to matter in the next commit.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10372>

pan/mdg: Don't print zero

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Reduced printed parens

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Don't print mem addr brackets

Already comma separated.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Don't print explicit .rte

Default round mode.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Suppress most attribute tables

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Don't print zero shifts

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: More concise RMU name

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/mdg: Hide units behind MIDGARD_MESA_DEBUG=verbose

Not usually interesting unless debugging bundling.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Key blend shaders to the input types

On Bifrost, fragment shaders might output either FP16 or FP32. The blend
shader will access the output as-is within the register, so depending on
the precision of the blend shader's logic, it may need to insert a
f2f16 or f2f32 conversion. This requires expanding the blend shader key.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/blend: Emit explicit conversions for all types

Needed so we can mix and match.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/lower_framebufffer: Don't use i2imp

Fails when converting from i2i8, which is possible.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Assume lower_fragcolor has been called

Allows us to clean up quite a bit.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Call nir_lower_fragcolor based on key

We only want it to trigger if MRT is actually in use. This is a cheap
key (only require multiple variants for an obscure edge case) and avoids
the perf regression of using this pass which is needed for conformance.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Prepare for lower_fragcolor

FRAG_RESULT_COLOR means something a bit different.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Distribute to_c_factor

Easier to understand, I think.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Workaround a v7 implementation-detail

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost/blend: Fix outdated comments

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/lower_blend: Rename is_bifrost->scalar

Don't leak ISA details.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/lower_blend: Use NIR helpers

Deletes a bunch of indentations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/lower_blend: Clean up type size handling

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Don't clobber RT0 if RTn is disabled

Fixes: a124c47b9f9 ("panfrost: Fix NULL derefs in pan_cmdstream.c")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Minor cleanup of blend CSO

No need to cast.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Support alpha_to_one

Gets rid of a bogus assert in the blend CSO create.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

panfrost: Make comment less confusing

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Lower 8-bit fragment input

Same reasons/technique as fragment output lowering, just need the NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Handle swizzles in i2i8

Otherwise they get copypropped away.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Add single-component 8-bit mkvec lowering

So we can implement scalar i2i8.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Handle different sizes of LD_TILE

v2: Fix overflow.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

pan/bi: Track dual-src blend type

Will be needed for fp16 outputs. I am acutely aware dual-src blending is
broken on Bifrost right now anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10393>

venus: query extended resource info from gralloc

Creating Android swapchain image from gralloc buffer requires to use
VkImageDrmFormatModifierExplicitCreateInfoEXT. To fill the struct info,
we need to query extended resource info from gralloc.

With the queried modifier from gralloc, we can ask the driver for the
plane count of the given format and modifier pair.

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10553>

tgsi: Mark the tgsi_exec_channel and tgsi_double_channel ALIGN16.

We allocate them all align16, so mark the unions (and their container
structs) that way so the compiler can do aligned SSE load/stores.

glmark2 -b loop FPS +0.197265% +/- 0.117633% (n=1906)

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10604>

radv: Add a STONEY baseline for dEQP.

See:
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9286188
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297109
  https://gitlab.freedesktop.org/tanty/mesa-valve-ci/-/jobs/9297110

v2.
  - Clarify that the dEQP-VK.texture.explicit_lod.2d tests are skipped
  due to slow APU-based STONEY test devices.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10559>

v3d: choose a larger CSD supergroup size if possible

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

broadcom/common: move CSD supergroup sizing to a common helper

We want to use this in GL too.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

v3dv: limit supergroup size in presence of TSY barriers

When a TSY barrier is hit, the entire supergroup will be synchronized.
If the supergoup is large and uses all available QPU threads it would
mean that we would sychronize and stall all running threads until all
of them reach the barrier, which may be inefficient.

This patch makes it so that if the compute shader has any such barriers
we limit the supergroup size so each supergroup only takes half of the
QPU threads available at most, so that if one supergroup hits a
barrier we have at least one other supergroup we can run, reducing
idle QPU time.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

broadcom/compiler: track if a shader has control barriers in prog_data

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

v3dv: choose a larger CSD supergroup size if possible

Each supergroup executes a number batches. Each batch has 16 elements
(one per QPU lane), except possibly the last batch which might be
incomplete. Until now, we packed a single workgroup in each supergroup,
which can lead to more incomplete batches and less efficient use
of the QPUs depending on the configuration of workgroups being dispatched.

This patch computes a number of workgroups per supergroup so that
we reduce or completely eliminate incomplete batches if possible.

It should be noted however, that TSY barriers act on supergroups,
so larger supergroups lead to larger syncpoints on barriers too.
A follow-up patch will try to find a good balance for compute shaders
that use such barriers.

This improves performance of the Sascha Willem's computecloth demo
by ~13%.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

compiler/nir: add a divergence analysis option for non-uniform workgroup id

The V3D hardware allows us to pack multiple workgroups together to avoid
wasting execution lanes in shader cores.

For example, if we dispatch 16 workgroups with a local size of 1 element, we
can pack all 16 workgroups in a single 16-wide dispatch where each lane
executes a different workgroup, instead of 16 1-wide dispatches.

When we do this, we don't have a uniform workgroup id any more.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10541>

intel/compiler: Remove unused exported functions

Now that all drivers are using brw_cs_get_dispatch_info() we can
remove one function (which is now unused) and reduce the scope of the
other.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

i965: Use brw_cs_get_dispatch_info()

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

anv: Use brw_cs_get_dispatch_info()

And since right_mask is already provided as part of dispatch_info,
just use that instead of storing it.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

iris: Use brw_cs_get_dispatch_info()

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

intel/compiler: Add common function for CS dispatch info

We have this small calculations repeated in each Intel driver, so move
them to a single place to be reused.  Also includes "right_mask" since
is always used in the same context and depends on the dispatch info
values.

Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10504>

nir: Remove now unnecessary conditions from emit_load/store helpers

The mode one was used before 0bc5a829dd6 ("nir: Remove shared support from
lower_io").

The others were used before 5f7c7c9a7f7 ("nir: add src and dest types
to all IO loads and stores for mediump").

All conditions now are always true, so drop them.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10533>

panfrost/ci: Run the full deqp-gles3 testsuite

We recently added 5 more VIM3s to the lavalab, this should be more than
enough to run the full GLES 3.0 testsuite on G52.

Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10614>

docs: update gallium doxygen docs

Gallium's background as a Tungstend Graphics technology is no longer
significant; it's a historical detail. Besides, since Tungsten Graphics
were acquired by VMware more than a decade ago, the website no longer
exists.

While we're at it, replace the docs link with a link to the mesa docs,
and point to archive.org copy of the Tungsten Graphics paper.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2770
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10452>

nir/opt_algebraic: optimizations for add umax/umin with zero

For unsigned comparisons with zero these ops can be eliminated.

v2: Add comparison optimizations with -1 (Rhys Perry)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net> (v1)
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10583>