Jin Kyu Song [Thu, 19 Dec 2013 06:01:14 +0000 (22:01 -0800)]
nosplit: Generate index-only EA only when a multiplier is used.
[nosplit eax] has been encoded as [eax*1+0] since 0.98.34.
But this seems like unexpected behavior.
So only when a register is multiplied, that will be treated
as an index. ([nosplit eax*1] -> [eax*1+0])
Document is updated accordingly.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 19 Dec 2013 05:31:51 +0000 (21:31 -0800)]
mpx: Clean up instruction data
Cleaned up unneccessary size specifiers in the instruction data.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 19 Dec 2013 05:28:41 +0000 (21:28 -0800)]
nosplit: Limit the effect of NOSPLIT
[nosplit eax+eax] was encoded [eax*2] previously but
this seems against the user's intention.
So in this case, nosplit is ignored now and [eax+eax] will be
generated.
Document is also updated accordingly.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 19 Dec 2013 05:28:17 +0000 (21:28 -0800)]
mib: Avoid RIP-relative addressing in mib
Using RIP relative for mib operands causes #UD exception.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Cyrill Gorcunov [Fri, 13 Dec 2013 06:59:39 +0000 (10:59 +0400)]
insns: Mark LOADALL, LOADALL286 with ND flag
Otherwise disassembler treat syscall, sysret incorrectly.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Wed, 11 Dec 2013 00:24:45 +0000 (16:24 -0800)]
mib: Handle MIB EA in a different way from regular EA's
In mib operands, users' intention should be preserved.
e.g.) [eax + eax*1] and [eax*2] must be distinguished and encoded differently.
So a new EA flag EAF_MIB for mib operands is added.
And a new EA hint EAH_SUMMED for the case of [eax+eax*4] being parsed
as [eax*5] is also added.
NOSPLIT specifier does not have an effect in mib, so [nosplit eax + eax*1]
will be encoded as [eax, eax] rather than [eax*2] as in a regular EA.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Wed, 11 Dec 2013 20:09:09 +0000 (12:09 -0800)]
misc/release: Generate manpages
asciidoc/xmlto are not tools we require every users to have, so each
tarball should contain them. That means the release script needs to
know about them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cyrill Gorcunov [Tue, 10 Dec 2013 07:09:49 +0000 (11:09 +0400)]
iflag: Don't use c99 array initialization
It's sad but not all compilers support c99 features, so drop
off IFLAG_INIT helper.
Reported-by: H. Peter Anvin <hpa@zytor.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 7 Dec 2013 12:15:03 +0000 (16:15 +0400)]
insns-iflags: Drop occasionally introduced \Tab's
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 7 Dec 2013 12:14:00 +0000 (16:14 +0400)]
iflag: \Tabs -> \Space
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 7 Dec 2013 12:12:07 +0000 (16:12 +0400)]
iflag: Introduce IFLAG_INIT helper
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Thu, 5 Dec 2013 08:06:45 +0000 (00:06 -0800)]
NASM 2.11rc4
Jin Kyu Song [Thu, 5 Dec 2013 04:51:13 +0000 (20:51 -0800)]
doc: Update nasmdoc
Added bnd warning and nobnd prefix. DEFAULT directive section
has got more description about BND-related settings.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 5 Dec 2013 04:05:55 +0000 (20:05 -0800)]
bnd: Add a new nobnd prefix
bnd and nobnd prifixes can be used for each instruction line to
direct whether bnd registers should be preserved or not.
And those are also added as options for DEFAULT directive.
Once bnd is set with default, DEFAULT BND, all bnd-prefix
available instructions are prefixed with bnd. To override it,
nobnd prefix can be used.
In the other way, DEFAULT NOBND can disable DEFAULT BND and
have nasm encode in the normal way.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 29 Nov 2013 08:38:29 +0000 (00:38 -0800)]
bnd: Show warning when bnd prefix is dropped
When bnd prefix is dropped as jmp is encoded as jmp short,
nasm shows a warning message, which can be suppressed with a new
command line option, -w-bnd.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Sun, 1 Dec 2013 00:38:42 +0000 (16:38 -0800)]
pfmask: Limit the preferred mask to the vendor specific flags
In ndisasm, the priority follows the order of instructions in insns.dat.
Other iflags could affect this mechanism when a proper instruction form
had a higher iflag bit set.
The preferred mask bits are now limited to vendor flags (Cyrix and AMD)
and other flags do not affect disassembler any more.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 29 Nov 2013 05:26:26 +0000 (21:26 -0800)]
doc: Make the bit about mib operands a bit clearer
Clean up the text about what a mib is.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Fri, 29 Nov 2013 05:24:09 +0000 (21:24 -0800)]
doc: Clean up changelog for 2.11
- We don't need to list internal infrastructure improvements.
- We don't list rc releases separately.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Thu, 28 Nov 2013 20:22:05 +0000 (12:22 -0800)]
NASM 2.11rc3
H. Peter Anvin [Thu, 28 Nov 2013 20:11:24 +0000 (12:11 -0800)]
Add {vex3} and {vex2} prefixes by analogy with {evex}
Allow specifying {vex3} or {vex2} (the latter is currently always
redundant, unless we end up with instructions at some point can be
specified with legacy prefixes or VEX) to select a specific encoding
of VEX-encoded instructions.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
H. Peter Anvin [Thu, 28 Nov 2013 19:36:26 +0000 (11:36 -0800)]
NASM 2.11rc2
H. Peter Anvin [Thu, 28 Nov 2013 19:33:28 +0000 (11:33 -0800)]
Remove "high 16" register class macros for xmm/ymm/zmm
The "high 16" register class macros were actually incorrect, as they
simply aliased the corresponding whole set class. In oder to keep
someone from getting confused and making mistakes, remove them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Jin Kyu Song [Thu, 28 Nov 2013 04:52:22 +0000 (20:52 -0800)]
testcase: Remove escape characters - '\'
Since the multi-line macro preprocessor is modified to expand
grouped parameter with braces. The escape character is not needed
any more.
The testcase converter script is also modified not to generate '\'.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 28 Nov 2013 04:52:16 +0000 (20:52 -0800)]
preproc: Handle curly braces in multi-line macro parameters
Multi-line macro uses curly braces for enclosing a parameter
containing comma(s). Passing curly braces as a part of a parameter
which is already enclosed with braces confuses the macro expander.
The number of braces in a group parameter is counted and any brace
in the outmost enclosing braces is treated as a part of parameter.
e.g.) mmacro {1,2,3}, {4,{5,6}}
mmacro gets 2 parameters of '1,2,3' and '4,{5,6}'
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 28 Nov 2013 04:23:53 +0000 (20:23 -0800)]
Revert "AVX-512: Handle curly braces in multi-line macro parameters"
This reverts commit
a800aed7b75d56114f2e1e4928cbc48ecf96a4a0.
As recommended by the community, braces inside a group parameter
of multi-line macro should be parsed without a need of a leading
escape character such as "\{ab,c\}".
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 27 Nov 2013 22:10:40 +0000 (14:10 -0800)]
stdscan: Rework curly brace parsing routines
As recommended by the community, a comma-separated decorators ({k1,z})
and nested braces ({{k1},{z}}) are dropped out. So only standard syntax
is supported from now.
This rework made source code neat and easy to maintain. Most of the codes
for handling corner cases are removed.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 27 Nov 2013 01:27:48 +0000 (17:27 -0800)]
iflags: Add IF_EVEX for checking {evex} availability
For checking the availability of {evex} prefix, AVX512 iflag
has been used. But this is a flag for an instruction set
not for an encoding scheme. And there are some AVX512 instructions
encoded with VEX prefix.
So a new instruction flag (IF_EVEX) is added for the instructions
which are actually encoded with EVEX prefix.
This flag is automatically added by insns.pl, so no need to add manually
in insns.dat.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 27 Nov 2013 01:14:07 +0000 (17:14 -0800)]
opflags: Separate vector registers into low-16 and high-16
Since only EVEX supports all 32 vector registers encoding for now,
VEX/REX encoded instructions should not take high-16 registers as operands.
This filtering had been done using instruction flag so far, but
using the opflags makes more sense.
[XYZ]MMREG operands used for non-EVEX instructions are automatically
converted to [XYZ]MM_L16 in insns.pl
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Tue, 26 Nov 2013 01:59:25 +0000 (17:59 -0800)]
doc: Update the change history and nasmdoc
Added the list of features added since 2.10 release.
Nasmdoc is also updated with those new features.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Wed, 27 Nov 2013 21:43:45 +0000 (13:43 -0800)]
disasm: Don't rely on iflag_cmp() returning +/-1
It is safer to just rely on the sign, for future options.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
H. Peter Anvin [Wed, 27 Nov 2013 21:41:50 +0000 (13:41 -0800)]
iflag: Do the equality test in iflag_cmp() first
The equality test indicates how long we spin, so do that first.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
H. Peter Anvin [Tue, 26 Nov 2013 23:21:15 +0000 (15:21 -0800)]
iflag: In iflag_cmp() scan from the most significant word down
In order for iflag_cmp() to return an ordering that makes sense, we
need to scan from the most significant word downward. That way the
bits with the higher index consistently are the more significant.
This fixes the disassembler vendor selection algorithm. While we are
doing that, make that dependency more explicit in the comments.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Mon, 25 Nov 2013 01:14:34 +0000 (17:14 -0800)]
iflag: Drop the use of double underscores
Double underscores are reserved for the implementation, i.e. the C
compiler and its libraries. NASM is an application and should not use
this namespace.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Mon, 25 Nov 2013 01:13:20 +0000 (17:13 -0800)]
iflag: Make the insns_flags array const
Make the insns_flags array const, and change the helper functions to
match.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Mon, 25 Nov 2013 01:07:33 +0000 (17:07 -0800)]
insns.dat: Fix a typo in a comment
isnsn-iflags.pl not insns-iflag.pl.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Sun, 24 Nov 2013 19:52:32 +0000 (11:52 -0800)]
iflag: Move instruction flag comment
Move the instruction flag comment to the Perl file where they are
defined.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Sun, 24 Nov 2013 19:49:24 +0000 (11:49 -0800)]
iflag: remove C99 constructs, don't hardcode the number of words
Avoid using C99 constructs when not necessary. Don't hardcode the
number of words when we can autodiscover them.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Sun, 24 Nov 2013 19:18:50 +0000 (11:18 -0800)]
"make alldeps"
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Sun, 24 Nov 2013 19:13:10 +0000 (11:13 -0800)]
iflag: Fix dependencies, factor out static components of iflag.h
Multi-dependencies don't work as expected, especially not across Make
versions, this is why we don't use them and read the instructions list
multiple times.
iflag.h has a lot of static content, so factor out the static content.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Sun, 24 Nov 2013 18:56:49 +0000 (10:56 -0800)]
"make alldeps"
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Cyrill Gorcunov [Sun, 10 Nov 2013 07:45:24 +0000 (11:45 +0400)]
insns: Restore back MMX,FPU flags
In commit
9bb987d8e0330429afba42015b1fc7c7ca0d1b16
we had to drop some flags due to flags type used
in nasm code.
Since now flags internal structure is reworked, we
can restore them back.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 18:28:52 +0000 (22:28 +0400)]
Update .gitignore
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 18:28:05 +0000 (22:28 +0400)]
make: Update deps
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 18:16:11 +0000 (22:16 +0400)]
iflag: Start using new instruction flags engine
Here we start using instruction flags generator.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sat, 26 Oct 2013 21:20:42 +0000 (01:20 +0400)]
insns: Introduce insns-flags.pl
It been found that 64 bits for instruction flags is too small,
so instead we start using indirect addressing scheme to keep
instruction flags in bitvectors instead.
Using one bitvector per instruction template entry is wastefull
(especially if vector grow in future, at moment it's 128 bit length),
so we use indirect addressing, which is generated as follow
- read instruction flags from insns.dat
- flag sequence sorted and joined into one key string
- this key string become a hash index
- all hash entries are compacted into one array
- every instruction template uses array offset instead
of flags bitfield
Just for info, at moment we have 195 unique flags combination,
but since instruction template will use index as unsigned
integer, we can use a way more wider combination of flags
in future.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 24 Nov 2013 08:26:35 +0000 (12:26 +0400)]
make: Add 'golden' target
We've 'test' target in toplevel Makefile, lets be
complete and allow to generate "golden" tests from
toplevel as well.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 22 Nov 2013 03:40:42 +0000 (19:40 -0800)]
bnd: Drop bnd prefix for relaxed short jmp instructions
Reverted the redundant branch instruction patterns for bnd prefix.
And when a relaxed jmp instruction becomes a short (Jb) form,
bnd prefix is not needed because it does not initialize bnd registers.
So in that case, bnd prefix is silently dropped.
BND JMP foo -> drops bnd prefix
BND JMP short foo -> shows an explicit error
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 20 Nov 2013 23:32:52 +0000 (15:32 -0800)]
disp8: Consolidate a logic to get compressed displacement
Consolidated two separate but similar functions in nasm and ndisasm
into a commonly linked source code.
To encode and decode the compressed displacement (disp8*N) for EVEX,
N value should be derived using various conditions.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 20 Nov 2013 02:44:13 +0000 (18:44 -0800)]
disasm: Add suport for bnd registers
MPX uses a new bnd registers and a new mib syntax.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 20 Nov 2013 02:43:04 +0000 (18:43 -0800)]
disasm: Add EVEX decorator syntax
Broadcasting, opmask, embedded rounding and SAE decorators
are not added at proper position.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 15 Nov 2013 21:20:55 +0000 (13:20 -0800)]
disasm: Add ZMM vsib
ZMM registers can be used for vsib index and the number of registers
has been increased to 32.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 15 Nov 2013 21:18:32 +0000 (13:18 -0800)]
disasm: Support EVEX compressed displacement
When tuple type is indicated in the bytecode, disp8 is
treated as a compressed disp and gets calculated back to disp8*N.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Mon, 11 Nov 2013 19:49:10 +0000 (11:49 -0800)]
disasm: Add basic AVX512 support
Disassembler can translate EVEX prefix, count up to 32 vector registers
and recognize new ZMM / opmask registers.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Sat, 9 Nov 2013 01:22:24 +0000 (17:22 -0800)]
disasm: style cleanup
Fix indentation.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 30 Oct 2013 10:12:45 +0000 (03:12 -0700)]
match: Check the number of elements in broadcasting operands
The broadcasting decorator {1to##} must describe exactly how many times
the memory element is repeated in order to clearly match the correct
instruction format.
For example,
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to8} ; good
vaddpd zmm30,zmm29,QWORD [rdx+0x3f8]{1to16} ; fail qword * 16 = 1024b
vaddps zmm30,zmm29,DWORD [rcx]{1to16} ; good
vaddps zmm30,zmm29,DWORD [rcx]{1to8} ; fail dword * 8 = 256b
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 30 Oct 2013 10:00:12 +0000 (03:00 -0700)]
match: Improve broadcast opsize matching
Broadcasting operand size is different from the original
operand size because 32b or 64b element is repeated to form a vector.
So when matching a broadcasting operand, opsize should be treated
differently.
The broadcasting element size is specified in the decorator information.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Tue, 29 Oct 2013 00:07:57 +0000 (17:07 -0700)]
Build: Suppress warning messages
Giving a correct printf format specifier supresses the warning message.
And a local pointer variable is initialized with NULL.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Sat, 26 Oct 2013 02:29:53 +0000 (19:29 -0700)]
AVX-512: Add {evex} instruction prefix
For instructions that can be encoded either in VEX or EVEX,
{evex} forces nasm to encode in EVEX.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Thu, 24 Oct 2013 01:39:03 +0000 (18:39 -0700)]
PREFETCHWT1: Add a new instruction flag
PREFETCHWT1 instruction's CPUID was TBD before.
Now it has its new CPUID bit : PREFETCHWT1
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 18 Oct 2013 03:37:26 +0000 (20:37 -0700)]
AVX512: Update instruction group
CPUID bit for vptestnm[dq] changed.
vptestnm[dq]: AVX512CD -> AVX512F
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 8 Nov 2013 21:31:58 +0000 (13:31 -0800)]
MPX: Move BND prefix indication from bytecode to iflags
As BND prefix validity check conflicts with jcc8 prefix,
IF_BND is added for the instruction templates which can have
bnd prefix for preserving the content of bound register.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Fri, 8 Nov 2013 19:41:12 +0000 (11:41 -0800)]
MPX: Adapt GAS's mib syntax with an index reg only
GAS uses *1 multiplier for explicitly marking an index register in mib operand.
e.g.) [rdx * 1 + 3] is equivalent to [3, rdx] in NASM's split EA format
So only for mib operands, this is encoded same as gas does.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:59:10 +0000 (19:59 -0700)]
iflags: Use UINT64_C() for 64bit values
UINT64_C() macro is used for iflags as it becomes 64bit.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 03:49:54 +0000 (20:49 -0700)]
SHA: SHA test cases
32bit and 64bit test asm files.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:44:03 +0000 (19:44 -0700)]
SHA: Add SHA instructions
New instruction extensions of SHA family are added.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:42:41 +0000 (19:42 -0700)]
MPX: Add test cases for MPX
MPX test asm files are added. These include all three different styles of
mib syntax (NASM, ICC and gas).
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:38:51 +0000 (19:38 -0700)]
MPX: Add BND prefix for branch instructions
BND prefix is used for adding bounds checking protection
across flow control changes such as call, ret, jmp and jcc calls.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Wed, 16 Oct 2013 02:10:13 +0000 (19:10 -0700)]
MPX: Add MPX instructions
Added MPX instructions and corresponding parser and encoder.
ICC style mib - base + disp and index are separate - is supported.
E.g. bndstx [ebx+3], bnd2, edx -> ebx+3 : base+disp, edx : index
As a supplement to NASM style mib - split EA - parser,
omitted base+disp is now treated as 0 displacement.
E.g. bndstx [,edx], bnd2 -> bndstx [0,edx], bnd2
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 23:53:51 +0000 (16:53 -0700)]
disasm: add support for emitting split EA format
Add support for emitting split EA format in the disassembler,
indicated by the MIB instruction flag.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 23:39:16 +0000 (16:39 -0700)]
parser: support split base,index effective address
Mostly intended for the "mib" expressions in BNDLDX/BNDSTX.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 00:28:39 +0000 (17:28 -0700)]
parse: factor out mref parsing
Factor out the parsing of an mref from parse_line(). In order to
support the [base,index] syntax we need to be able to parse an mref in
two steps.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
H. Peter Anvin [Fri, 27 Sep 2013 00:23:08 +0000 (17:23 -0700)]
parser: simplify code by keeping a pointer to the current operand
There is an awful lot of syntax-heavy "result->oprs[operand]" going
on; simplify by making a pointer to the current operand.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Jin Kyu Song [Sat, 21 Sep 2013 03:52:11 +0000 (20:52 -0700)]
AVX-512: Add perfomtest-compliant headers to test cases
test/avx512*.asm files are now tested by using perfomtest.pl
Refer to pefomtest help message for the usage.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Cyrill Gorcunov [Sat, 9 Nov 2013 08:02:15 +0000 (12:02 +0400)]
BR3392270: preproc: Handle all token chains in mmacro params range
A typical example is
|
| %macro m0 0-*
| %rep %0
| m0 arg is %1
| %rotate 1
| %endrep
| %endmacro
|
| %macro m1 0-*
| m0 %{1:-1}
| %endmacro
|
| m1 a=b, c=d
If passed with nasm -E the output must be like
m0 arg is a=b
m0 arg is c=d
http://bugzilla.nasm.us/show_bug.cgi?id=3392270
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Fri, 8 Nov 2013 23:28:19 +0000 (15:28 -0800)]
Add (redundant) parentheses around bit tests mixed with &&
It is easy to get confused when mixing & and &&, so add redundant
parenteses for clarity.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Jin Kyu Song [Fri, 8 Nov 2013 09:14:39 +0000 (01:14 -0800)]
REX: Set REX bits in accordance with 32-register environment
REX.RXB bits were set for high-8 registers previously.
Since high-16 zmm registers are newly added, those bits should
be set as one bit of binary number of register value.
Similarly EVEX.R'/V'/X should be set in the same manner.
Authored-by: H. Peter Anvin <hpa@linux.intel.com>
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Cyrill Gorcunov [Mon, 28 Oct 2013 07:35:55 +0000 (11:35 +0400)]
Revert "make: Remove generated files on clean target"
This reverts commit
b6c7291b3d1f904b20955c3f9829b8cc92801227.
We already have this cleanup stage in "cleaner" target, I managed
to miss it.
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Cyrill Gorcunov [Sun, 27 Oct 2013 17:15:47 +0000 (21:15 +0400)]
make: Remove generated files on clean target
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Thu, 24 Oct 2013 13:17:23 +0000 (14:17 +0100)]
Merge remote-tracking branch 'origin/master'
H. Peter Anvin [Thu, 24 Oct 2013 12:57:57 +0000 (13:57 +0100)]
Makefile.in: always run "make alldeps" when "make dist"
"make dist" (tarball generation) really should include "make alldeps"
so the Makefile dependencies are correct.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Thu, 24 Oct 2013 12:45:06 +0000 (13:45 +0100)]
Run "make alldeps" to update dependencies
H. Peter Anvin [Thu, 24 Oct 2013 12:25:51 +0000 (13:25 +0100)]
Makefile.in: generate manpages for "make dist"
Make sure the "dist" target generates the man pages.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Thu, 24 Oct 2013 12:22:19 +0000 (13:22 +0100)]
Revert "build: Include pregenerated nasm manpages"
This reverts commit
99427bdb6c85c812665f6d7b36ac520a631c5b23.
We don't include generated files in the repository, instead we should
pregenerate them for the tarball generation, just as we do for the
Perl-generated files.
Signed-off-by: H. Peter Anvin <hpa@zytor.com>
H. Peter Anvin [Sat, 19 Oct 2013 19:20:28 +0000 (12:20 -0700)]
macros.pl: Remove superfluous whitespace
Squeeze multiple whitespace characters together, since they have no
semantic function.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Jin Kyu Song [Mon, 7 Oct 2013 21:51:09 +0000 (14:51 -0700)]
iflags: Eliminate perl smart match operator
As smart match operator reuiqres perl version 5.10.1 or later,
it is replaced with grep function.
This part of code is going to be completely removed once iflags
renovataion is done. This commit is a quick fix for a build error.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Cyrill Gorcunov [Thu, 3 Oct 2013 13:21:39 +0000 (17:21 +0400)]
Merge branch 'nasm-2.10.xx'
* nasm-2.10.xx:
coff: Better handling of section redefinition
Marat Dukhan [Thu, 19 Sep 2013 23:19:52 +0000 (19:19 -0400)]
coff: Better handling of section redefinition
Currently, if we try to define an already defined section and specify
section flags, NASM will output "warning: section attributes ignored
on redeclaration of section %SECTIONNAME%".
The patch modifies this behaviour:
1. If the previous section definition differs only in alignment flags,
no warning is generated
2. If the new definition implies larger alignment, it overrides the
previous section alignment
3. If the new definition specifies any section alignment, the content of
the section will be aligned on the new boundary (i.e. the effect is the
same as if there was ALIGN macro)
Signed-off-by: Marat Dukhan <maratek@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
H. Peter Anvin [Thu, 3 Oct 2013 01:25:19 +0000 (18:25 -0700)]
Add support for DZ and RESZ, document the ZWORD keyword
Add the DZ and RESZ pseudoinstructions and add ZWORD to the
documentation.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
H. Peter Anvin [Wed, 2 Oct 2013 21:58:19 +0000 (14:58 -0700)]
NASM 2.11rc1
H. Peter Anvin [Wed, 2 Oct 2013 21:58:02 +0000 (14:58 -0700)]
NASM 2.10rc1
H. Peter Anvin [Wed, 2 Oct 2013 21:28:09 +0000 (14:28 -0700)]
Merge branch 'avx512'
AVX512 is ready enough that it will realistically be in version 2.11.
Add AVX512 to the master branch; for legacy branch maintenance use the
nasm-2.10.xx branch.
Signed-off-by: H. Peter Anvin <hpa@linux.intel.com>
Cyrill Gorcunov [Sat, 21 Sep 2013 09:14:15 +0000 (13:14 +0400)]
strfunc: Tabs to spaces conversion
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Marat Dukhan [Fri, 20 Sep 2013 22:54:49 +0000 (18:54 -0400)]
coff: Support for section names longer than 8 bytes
http://bugzilla.nasm.us/show_bug.cgi?id=3392233
Signed-off-by: Marat Dukhan <maratek@gmail.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 21 Sep 2013 03:36:19 +0000 (20:36 -0700)]
AVX-512: Fix bugs related to uninitialized variables
Initialized disp8 to avoid a case that disp8 encoded
instead of the actual offset value.
Added a checking routine for basereg value before using it
as an index of array.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 13 Sep 2013 21:12:57 +0000 (14:12 -0700)]
AVX-512: Added AVX-512PF instructions
Added Prefetch (AVX-512PF) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512PF[bit 26] = 1.
CPUID feature flag for PREFETCHWT1 is TBD
but PREFETCHWT1 is included in this commit.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 13 Sep 2013 21:12:56 +0000 (14:12 -0700)]
AVX-512: Add AVX-512ER instructions
Added Exponential and Reciprocal (AVX-512ER) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512ER[bit 27] = 1.
IF_AVX512 is now shared by all AVX-512* instructions as a bit mask.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Fri, 13 Sep 2013 21:12:55 +0000 (14:12 -0700)]
AVX-512: Add AVX-512CD instructions
Added Conflict Detection (AVX-512CD) instructions.
These instructions are supported
if CPUID.(EAX=07H, ECX=0):EBX.AVX512CD[bit 28] = 1.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 7 Sep 2013 04:22:18 +0000 (21:22 -0700)]
AVX-512: Add Pseudo-ops for CMP instructions
Added three-operand pseudo-ops for VCMPPD, VPCMPD and so on.
Test case is also updated to validate them.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 31 Aug 2013 01:10:36 +0000 (18:10 -0700)]
AVX-512: Reorder instructions in insns.dat
Within a same instruction mnemonic, instructions are reordered
in order of opcode byte value.
Therefore when there are two possible opcode candidates, smaller
opcode is picked now.
e.g.) vmovapd zmm30, zmm29 -> now 28h is used. 29h previously
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>
Jin Kyu Song [Sat, 31 Aug 2013 01:10:35 +0000 (18:10 -0700)]
AVX-512: Fix rounding mode value in EVEX prefix with SAE
If SAE is set, VL(vector length) is implied to be 512.
EVEX.L'L (=EVEX.RC) is set to 00b by default.
Signed-off-by: Jin Kyu Song <jin.kyu.song@intel.com>
Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com>