Andrey Grodzovsky [Wed, 14 Oct 2020 17:10:06 +0000 (13:10 -0400)]
drm/amd/display: Revert "drm/amd/display: Fix a list corruption"
This fixes regression on device unplug and/or driver unload.
[ 65.681501 < 0.000004>] BUG: kernel NULL pointer dereference, address:
0000000000000008
[ 65.681504 < 0.000003>] #PF: supervisor write access in kernel mode
[ 65.681506 < 0.000002>] #PF: error_code(0x0002) - not-present page
[ 65.681507 < 0.000001>] PGD
7c9437067 P4D
7c9437067 PUD
7c9db7067 PMD 0
[ 65.681511 < 0.000004>] Oops: 0002 [#1] SMP NOPTI
[ 65.681512 < 0.000001>] CPU: 8 PID: 127 Comm: kworker/8:1 Tainted: G W O 5.9.0-rc2-dev+ #59
[ 65.681514 < 0.000002>] Hardware name: System manufacturer System Product Name/PRIME X470-PRO, BIOS 4406 02/28/2019
[ 65.681525 < 0.000011>] Workqueue: events drm_connector_free_work_fn [drm]
[ 65.681535 < 0.000010>] RIP: 0010:drm_atomic_private_obj_fini+0x11/0x60 [drm]
[ 65.681537 < 0.000002>] Code: de 4c 89 e7 e8 70 f2 ba f8 48 8d 65 d8 5b 41 5c 41 5d 41 5e 41 5f 5d c3 90 0f 1f 44 00 00 48 8b 47 08 48 8b 17 55 48 89 e5 53 <48> 89 42 08 48 89 10 48 b8 00 01 00 00 00 00 ad de 48 89 fb 48 89
[ 65.681541 < 0.000004>] RSP: 0018:
ffffa5fa805efdd8 EFLAGS:
00010246
[ 65.681542 < 0.000001>] RAX:
0000000000000000 RBX:
ffff9a4b094654d8 RCX:
0000000000000000
[ 65.681544 < 0.000002>] RDX:
0000000000000000 RSI:
ffffffffba197bc2 RDI:
ffff9a4b094654d8
[ 65.681545 < 0.000001>] RBP:
ffffa5fa805efde0 R08:
ffffffffba197b82 R09:
0000000000000040
[ 65.681547 < 0.000002>] R10:
ffffa5fa805efdc8 R11:
000000000000007f R12:
ffff9a4b09465888
[ 65.681549 < 0.000002>] R13:
ffff9a4b36f20010 R14:
ffff9a4b36f20290 R15:
ffff9a4b3a692840
[ 65.681551 < 0.000002>] FS:
0000000000000000(0000) GS:
ffff9a4b3ea00000(0000) knlGS:
0000000000000000
[ 65.681553 < 0.000002>] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 65.681554 < 0.000001>] CR2:
0000000000000008 CR3:
00000007c9c82000 CR4:
00000000003506e0
[ 65.681556 < 0.000002>] Call Trace:
[ 65.681561 < 0.000005>] drm_dp_mst_topology_mgr_destroy+0xc4/0xe0 [drm_kms_helper]
[ 65.681612 < 0.000051>] amdgpu_dm_connector_destroy+0x3d/0x110 [amdgpu]
[ 65.681622 < 0.000010>] drm_connector_free_work_fn+0x78/0x90 [drm]
[ 65.681624 < 0.000002>] process_one_work+0x164/0x410
[ 65.681626 < 0.000002>] worker_thread+0x4d/0x450
[ 65.681628 < 0.000002>] ? rescuer_thread+0x390/0x390
[ 65.681630 < 0.000002>] kthread+0x10a/0x140
[ 65.681632 < 0.000002>] ? kthread_unpark+0x70/0x70
[ 65.681634 < 0.000002>] ret_from_fork+0x22/0x30
This reverts commit
1545fbf97eafc1dbdc2923e58b4186b16a834784.
Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Fri, 16 Oct 2020 12:43:06 +0000 (20:43 +0800)]
drm/amd/pm: drop navy_flounder hardcode of using soft pptable
Drop navy_flounder hardcode of using soft pptable, so that it
can use pptable from vbios when available.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mihir Bhogilal Patel [Thu, 15 Oct 2020 12:27:26 +0000 (17:57 +0530)]
drm/amdgpu: add a list in VM for BOs in the done state
Add a new list in VM for done state i.e. BOs which are
invalidated and updated in PTEs.
Signed-off-by: Mihir Bhogilal Patel <Mihir.Patel@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Thu, 15 Oct 2020 02:48:15 +0000 (10:48 +0800)]
drm/amdgpu: update golden setting for sienna_cichlid
Update golden setting for sienna_cichlid.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Fri, 16 Oct 2020 03:07:47 +0000 (11:07 +0800)]
drm/amd/swsmu: add missing feature map for sienna_cichlid
it will cause smu sysfs node of "pp_features" show error.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kevin Wang [Wed, 14 Oct 2020 12:09:57 +0000 (20:09 +0800)]
drm/amdgpu: remove gfxhub_v1_1_funcs set
remove duplicate gfxhub v1.1 function set.
put function of gfxhub_v1_1_get_xgmi_info to gfxhub v1_0 function set.
Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Tue, 13 Oct 2020 04:18:27 +0000 (12:18 +0800)]
drm/amd/amdgpu: set the default value of noretry to 1 for some dGPUs
noretry = 0 cause some dGPU's kfd page fault tests fail,
so set noretry to 1 for these special ASICs:
vega20/navi10/navi14
v2: merge raven and default case due to the same setting
v3: remove ARCTURUS
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Acked-by: Felix Kuhling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 15 Oct 2020 02:59:40 +0000 (10:59 +0800)]
drm/amdgpu/display: enable display ip block for vangogh
This patch is to enable display IP block for vangogh platforms.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Thu, 15 Oct 2020 07:12:23 +0000 (15:12 +0800)]
drm/amdgpu/display: fix the NULL pointer reference on dmucb on dcn301
DCN301 needs to use dmub create abm instance instead of dce.
[ 1138.854204] BUG: kernel NULL pointer dereference, address:
0000000000000000
[ 1138.854206] #PF: supervisor instruction fetch in kernel mode
[ 1138.854207] #PF: error_code(0x0010) - not-present page
[ 1138.854208] PGD 0 P4D 0
[ 1138.854212] Oops: 0010 [#1] SMP NOPTI
[ 1138.854216] CPU: 6 PID: 1240 Comm: modprobe Tainted: G W OE 5.9.0-rc2-custom #1
[ 1138.854217] Hardware name: AMD Chachani-VN/Chachani-VN, BIOS BAerithA104 10/01/2020
[ 1138.854221] RIP: 0010:0x0
[ 1138.854224] Code: Bad RIP value.
[ 1138.854226] RSP: 0018:
ffffc90001c4f638 EFLAGS:
00010286
[ 1138.854228] RAX:
0000000000000000 RBX:
ffff88804f2b2800 RCX:
ffffc90001c4f740
[ 1138.854229] RDX:
00000000000000e8 RSI:
ffffc90001c4f640 RDI:
ffff88805816f300
[ 1138.854230] RBP:
ffffc90001c4f850 R08:
ffffc90001c4f644 R09:
ffffc90001c4f654
[ 1138.854231] R10:
ffffc90001c4f72c R11:
ffffc90001c4f740 R12:
ffffc90001c4f640
[ 1138.854232] R13:
ffffc90001c4f728 R14:
0000000000000000 R15:
ffff888007296381
[ 1138.854235] FS:
00007f5f44d84540(0000) GS:
ffff88805e380000(0000) knlGS:
0000000000000000
[ 1138.854236] CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
[ 1138.854237] CR2:
ffffffffffffffd6 CR3:
00000000194f4000 CR4:
0000000000050ee0
[ 1138.854239] Call Trace:
[ 1138.854447] dmub_init_abm_config+0x220/0x267 [amdgpu]
[ 1138.854654] dm_late_init+0x197/0x1ad [amdgpu]
[ 1138.854846] ? dm_late_init+0x197/0x1ad [amdgpu]
[ 1138.854999] amdgpu_device_ip_late_init+0x6f/0x21b [amdgpu]
[ 1138.855148] amdgpu_device_init+0x1b7f/0x1cfb [amdgpu]
[ 1138.855293] amdgpu_driver_load_kms+0x2c/0x26e [amdgpu]
[ 1138.855437] amdgpu_pci_probe+0x1c7/0x249 [amdgpu]
[ 1138.920489] local_pci_probe+0x48/0x80
[ 1138.920492] pci_device_probe+0x10f/0x1c0
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Fri, 17 Jul 2020 08:28:46 +0000 (16:28 +0800)]
drm/amd/display: add S/G support for Renoir
S/G (scatter/gather) display support for display
buffers in system memory.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Yifan Zhang [Mon, 31 Aug 2020 07:56:24 +0000 (15:56 +0800)]
drm/amd/display: setup system context in dm_init
[why]
display S/G mode fails in Renoir
[how]
Setup system context in dm init.
Signed-off-by: Yifan Zhang <yifan1.zhang@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mihir Bhogilal Patel [Thu, 8 Oct 2020 10:16:38 +0000 (15:46 +0530)]
drm/amdgpu: Add debugfs entry for printing VM info
Create new debugfs entry to print memory info using VM buffer
objects.
V2: Added Common function for printing BO info.
Dump more VM lists for evicted, moved, relocated, invalidated.
Removed dumping VM mapped BOs.
V3: Fixed coding style comments, renamed print API and variables.
V4: Fixed coding style comments.
Signed-off-by: Mihir Bhogilal Patel <Mihir.Patel@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Thu, 15 Oct 2020 06:57:46 +0000 (14:57 +0800)]
drm/amdgpu: correct the gpu reset handling for job != NULL case
Current code wrongly treat all cases as job == NULL.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-and-tested-by: Jane Jian <Jane.Jian@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 30 Sep 2020 06:34:08 +0000 (14:34 +0800)]
drm/amdgpu: add rlc iram and dram firmware support
Support to load RLC iram and dram ucode when RLC firmware struct use v2.2
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Likun Gao [Wed, 14 Oct 2020 06:05:18 +0000 (14:05 +0800)]
drm/amdgpu: add function to program pbb mode for sienna cichlid
Add function for sienna_cichlid to force PBB workload mode to zero by
checking whether there have SE been harvested.
Signed-off-by: Likun Gao <Likun.Gao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jiansong Chen [Thu, 15 Oct 2020 02:42:58 +0000 (10:42 +0800)]
Revert "drm/amdgpu: disable gfxoff temporarily for navy_flounder"
This reverts commit
39ad082459373facaa255b0791595d018597a164.
TDR issue has been resovled by pmfw update.
Signed-off-by: Jiansong Chen <Jiansong.Chen@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 13 Oct 2020 06:17:29 +0000 (14:17 +0800)]
drm/amd/pm: properly setting GPO feature on UMD pstate entering/exiting
Disable/enable the GPO feature on UMD pstate entering/exiting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 09:58:06 +0000 (17:58 +0800)]
drm/amdgpu: fulfill Navi gfx and pcie settings on umd pstate switching(V2)
Fulfill Navi gfx and pcie settings on umd pstate switching.
V2: temporarily skip the pcie ASPM setting considering the ASPM function
is not fully enabled yet
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 09:10:48 +0000 (17:10 +0800)]
drm/amdgpu: add interface for setting MGCG perfmon
Enable Navi1X MGCG perfmon setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 08:50:44 +0000 (16:50 +0800)]
drm/amdgpu: add interface for setting ASPM
Support NAVI10 ASPM setting.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Tue, 18 Aug 2020 04:43:25 +0000 (12:43 +0800)]
drm/amd/pm: correct gfx and pcie settings on umd pstate switching(V2)
For entering UMD stable Pstate, the operations to enter rlc_safe
mode, disable mgcg_perfmon and disable PCIE aspm are needed. And
the opposite operations should be performed on UMD stable Pstate
exiting.
V2: take those ASICs(CI/SI/VI) which may not support this into
consideration
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Sat, 10 Oct 2020 01:58:41 +0000 (09:58 +0800)]
drm/amd/pm: populate Arcturus PCIE link state
Populate current link speed, width and clock domain frequency.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Sat, 10 Oct 2020 01:36:02 +0000 (09:36 +0800)]
drm/amd/pm: populate the bootup LCLK frequency
As for other clock domains.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Wed, 14 Oct 2020 14:12:02 +0000 (22:12 +0800)]
drm/amdgpu: disable gpa mode for direct loading
This patch fixes the gfx hang while use firmware direct loading mode.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tom Rix [Wed, 14 Oct 2020 21:18:06 +0000 (14:18 -0700)]
drm/amdgpu: add missing newline at eof
Representative checkpatch.pl warning
WARNING: adding a line without newline at end of file
30: FILE: drivers/gpu/drm/amd/pm/swsmu/smu11/vangogh_ppt.h:30:
+#endif
Signed-off-by: Tom Rix <trix@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Wed, 14 Oct 2020 17:39:39 +0000 (13:39 -0400)]
drm/amdgpu/display: DRM_AMD_DC_DCN3_02 depends on DRM_AMD_DC_DCN3_01
Fix this to avoid build problems if DRM_AMD_DC_DCN3_02 is defined, but
DRM_AMD_DC_DCN3_01 is not.
Fixes:
36d26912e8d854 ("drm/amd/display: Add support for DCN302 (v2)")
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Reported-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Kent Russell [Wed, 14 Oct 2020 11:47:32 +0000 (07:47 -0400)]
drm/amdkfd: Use kvfree in destroy_crat_image
Now that we use kvmalloc for the crat_image, we need to use kvfree when
we destroy this.
Fixes:
d0e63b343e575e ("drm/amdkfd: Use kvmalloc instead of kmalloc for VCRAT")
Reported-by: Morris Zhang <shiwu.zhang@amd.clm>
Signed-off-by: Kent Russell <kent.russell@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Veerabadhran G [Thu, 8 Oct 2020 17:00:02 +0000 (22:30 +0530)]
drm/amdgpu: vcn and jpeg ring synchronization
Synchronize the ring usage for vcn1 and jpeg1 to workaround a hardware bug.
Signed-off-by: Veerabadhran Gopalakrishnan <veerabadhran.gopalakrishnan@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Hawking Zhang [Wed, 30 Sep 2020 15:13:28 +0000 (23:13 +0800)]
drm/amdgpu: enable GDDR6 save-restore support for dimgrey_cavefish
add mp0 11_0_12 for dimgrey_cavefish to the mem training
supported list, otherwise the modeprobe would fail
on dimgrey_cavefish with latest vbios.
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Huang Rui [Tue, 13 Oct 2020 11:19:31 +0000 (19:19 +0800)]
drm/amdgpu: fix the issue that apu has no smu firmware binary
The driver needn't load smu binary on APU platforms.
Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Madhav Chauhan <madhav.chauhan@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 2 Sep 2020 08:10:10 +0000 (16:10 +0800)]
drm/amd/pm: increase mclk switch threshold to 200 us
To avoid underflow seen on Polaris10 with some 3440x1440
144Hz displays. As the threshold of 190 us cuts too close
to minVBlankTime of 192 us.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Tue, 13 Oct 2020 11:54:20 +0000 (13:54 +0200)]
docs: amdgpu: fix a warning when building the documentation
As reported by Sphinx:
Documentation/gpu/amdgpu.rst:200: WARNING: Inline emphasis start-string without end-string.
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Mauro Carvalho Chehab [Tue, 13 Oct 2020 11:54:27 +0000 (13:54 +0200)]
drm/amd/display: kernel-doc: document force_timing_sync
As warned when running "make htmldocs":
./drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.h:345: warning: Function parameter or member 'force_timing_sync' not described in 'amdgpu_display_manager'
This new struct member was not documented at kernel-doc markup.
Fixes:
3d4e52d0cf24 ("drm/amd/display: Add debugfs for forcing stream timing sync")
Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bernard Zhao [Mon, 12 Oct 2020 11:46:16 +0000 (04:46 -0700)]
drm/amd/display: remove no need return value
Functions (disable_all_writeback_pipes_for_stream &
dc_enable_stereo & dc_post_update_surfaces_to_stream)
always return true, there is no need to keep the return value.
This change is to make the code a bit more readable.
Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
kernel test robot [Mon, 12 Oct 2020 21:20:49 +0000 (05:20 +0800)]
drm/amdgpu: fix semicolon.cocci warnings
drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.c:608:2-3: Unneeded semicolon
Remove unneeded semicolon.
Generated by: scripts/coccinelle/misc/semicolon.cocci
Fixes:
b4a7db71ea06 ("drm/amdgpu: add per device user friendly xgmi events for vega20")
CC: Jonathan Kim <jonathan.kim@amd.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Mon, 12 Oct 2020 14:12:28 +0000 (10:12 -0400)]
drm/amdgpu/swsmu: init the baco mutex in early_init
GPU reset might get called during init time, before
sw_init has been called.
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Thu, 8 Oct 2020 17:32:47 +0000 (13:32 -0400)]
drm/amd/display: Add green_sardine support to DM
Display Manager support for green_sardine
Signed-off-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Roman Li [Thu, 8 Oct 2020 17:28:41 +0000 (13:28 -0400)]
drm/amd/display: Add green_sardine support to DC
Display Core support for green_sardine
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Sat, 10 Oct 2020 07:45:35 +0000 (15:45 +0800)]
drm/amdgpu: add DM block for dimgrey_cavefish
Add DM block support for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Sat, 10 Oct 2020 07:42:46 +0000 (15:42 +0800)]
drm/amdgpu: remove ASD ucode init for dimgrey_cavefish
dimgrey_cavefish has no ASD ucode currently, remove its initialization.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jack Gui <Jack.Gui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Fri, 25 Sep 2020 18:00:24 +0000 (14:00 -0400)]
drm/amd/display: Add DCN302 support in amdgpu_dm (v2)
Handle CAVE_DIMGREY_CAVEFISH in amdgpu_dm
v2: fix rebase typo (Alex)
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Tue, 29 Sep 2020 18:52:09 +0000 (14:52 -0400)]
drm/amd/display: Add support for DCN302 (v2)
- add DCN302 resource, irq service, dmub loader,
- handle DC_VERSION_DCN_3_02
- define DCN302 power gating functions
- handle DCN302 in GPIO files
- define I2C regs
- add CONFIG_DRM_AMD_DC_DCN3_02 guard
v2: rebase fixes (Alex)
Signed-off-by: Joshua Aberback <joshua.aberback@amd.com>
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Sun, 27 Sep 2020 08:25:27 +0000 (16:25 +0800)]
drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish
Per PMFW 59.7.0.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 9 Oct 2020 22:39:48 +0000 (18:39 -0400)]
drm/amdgpu: remove gpu_info fw support for dimgrey_cavefish
Remove gpu_info fw support for dimgrey_cavefish, gpu info can be got
from ip discovery.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 10 Aug 2020 09:48:34 +0000 (17:48 +0800)]
drm/amdgpu: enable ih CG for dimgrey_cavefish
Set ih CG flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 10 Aug 2020 09:46:17 +0000 (17:46 +0800)]
drm/amdgpu: enable hdp CG and LS for dimgrey_cavefish
Set hdp CG and LS flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 4 Jun 2020 07:20:39 +0000 (15:20 +0800)]
drm/amdgpu: add psp and smu block for dimgrey_cavefish
Add psp and smu block for dimgrey_cavefish with psp firmware load type.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by:Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 17:54:34 +0000 (13:54 -0400)]
drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish(v2)
Per PMFW 59.5.0.
v2: refine subject and commit message, fix typo
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 17:53:49 +0000 (13:53 -0400)]
drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish
Update driver if version from 0x5 to 0x6 for dimgrey_cavefish, per PMFW 59.04.0.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Thu, 23 Jul 2020 16:58:12 +0000 (12:58 -0400)]
drm/amdgpu: enable jpeg3.0 for dimgrey_cavefish
Enable jpeg3.0 ip block for dimgrey_cavefish.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Thu, 23 Jul 2020 16:55:54 +0000 (12:55 -0400)]
drm/amdgpu: enable vcn3.0 for dimgrey_cavefish
Enable vcn3.0 ip block for dimgrey_cavefish.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 17:52:47 +0000 (13:52 -0400)]
drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish
Update driver if version from 0x4 to 0x5 for dimgrey_cavefish, per PMFW 59.02.0.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 10 Aug 2020 09:38:47 +0000 (17:38 +0800)]
drm/amdgpu: enable athub/mmhub PG for dimgrey_cavefish
Set athub/mmhub PG flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 10 Aug 2020 09:34:30 +0000 (17:34 +0800)]
drm/amdgpu: enable mc CG and LS for dimgrey_cavefish
Set mc CG and LS flag for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 10 Aug 2020 09:15:23 +0000 (17:15 +0800)]
drm/amdgpu: enable GFX clock gating for dimgrey_cavefish
Enable GFX MGCG, CGCG and 3DCG for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 16:24:26 +0000 (12:24 -0400)]
drm/amdgpu/swsmu: update driver if version for dimgrey_cavefish
Update driver if version according to PMFW with version 0x003B0100.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Sun, 9 Aug 2020 01:12:49 +0000 (09:12 +0800)]
drm/amdgpu: support athub cg setting for dimgrey_cavefish
Same as navy_flounder, the athub ip of dimgrey_cavefish is v2.1.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 16:23:07 +0000 (12:23 -0400)]
drm/amdgpu: enable front door loading for dimgrey_cavefish
Support both back and front door loading for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Wed, 5 Aug 2020 21:59:09 +0000 (17:59 -0400)]
drm/amdgpu: enable jpeg3.0 PG and CG for dimgrey_cavefish
Enable JPEG3.0 PG and CG for dimgrey_cavefish.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Wed, 5 Aug 2020 21:54:21 +0000 (17:54 -0400)]
drm/amdgpu: enable VCN3.0 PG and CG for dimgrey_cavefish
Enable VCN3.0 PG and CG for dimgrey_cavefish
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Kenneth Feng <kenneth.feng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Fri, 2 Oct 2020 16:22:13 +0000 (12:22 -0400)]
drm/amdkfd: Add kfd2kgd_funcs for dimgrey_cavefish kfd support
Add KFD support.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Chengming Gui [Fri, 2 Oct 2020 16:20:32 +0000 (12:20 -0400)]
drm/amdkfd: Support dimgrey_cavefish KFD (v2)
Add KFD support for dimgrey cavefish.
v2: rebase (Alex)
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Tao Zhou <tao.zhou1@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 16:04:08 +0000 (12:04 -0400)]
drm/amdgpu: add gc golden setting for dimgrey_cavefish
Add gc golden setting for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Tested-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 16:00:54 +0000 (12:00 -0400)]
drm/amdgpu: support cp_fw_write_wait for dimgrey_cavefish
Same as sienna_cichlid, dimgrey_cavefish supports WAIT_REG_MEM packet.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 28 Jul 2020 05:53:48 +0000 (13:53 +0800)]
drm/amdgpu: skip reroute ih for some ASICs
Add check before reroute ih setting, it's not supported by some ASICs.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:56:29 +0000 (11:56 -0400)]
drm/amdgpu: add psp support for dimgrey_cavefish(v2)
General psp support for dimgrey_cavefish.
v2: remove the checks for asd load and reroute ih.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 23 Jul 2020 11:14:00 +0000 (19:14 +0800)]
drm/amdgpu: increase size of psp fw_name string(v2)
Increase fw_name string size so longer chip name can be stored.
v2: define macro for the length of psp fw name.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:51:04 +0000 (11:51 -0400)]
drm/amdgpu/swsmu: add smu support for dimgrey_cavefish(v2)
Reuse sienna_cichlid pp table for dimgrey_cavefish.
v2: update related comment.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 23 Jul 2020 10:16:53 +0000 (18:16 +0800)]
drm/amdgpu/swsmu: increase size for smu fw_name string
A longer chip name needs more space.
v2: define macro for the length of smu fw name
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Thu, 23 Jul 2020 10:10:20 +0000 (18:10 +0800)]
drm/amdgpu: add gmc cg support for dimgrey_cavefish
The athub version for dimgrey_cavefish is v2.1.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Thu, 23 Jul 2020 16:44:51 +0000 (12:44 -0400)]
drm/amdgpu/vcn: enable VCN DPG mode for dimgrey_cavefish
Enable VCN DPG mode for dimgrey_cavefish.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
James Zhu [Fri, 2 Oct 2020 15:47:20 +0000 (11:47 -0400)]
drm/amdgpu/vcn: add firmware support for dimgrey_cavefish
Add firmware support for dimgrey_cavefish.
Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:45:39 +0000 (11:45 -0400)]
drm/amdgpu: force pa_sc_tile_steering_override to 0 for dimgrey_cavefish
pa_sc_tile_steering_override is only programmable for gfx10.0/10.1/10.2, the same as sienna_cichlid.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Wed, 11 Mar 2020 04:09:57 +0000 (12:09 +0800)]
drm/amdgpu: add virtual display support for dimgrey_cavefish
Add virtual ip block for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:44:16 +0000 (11:44 -0400)]
drm/amdgpu: configure dimgrey_cavefish gfx according to gfx 10.3's definition
The gfx version of dimgrey_cavefish is 10.3, identical to sienna_cichlid, follow the way
of sienna_cichlid.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:42:31 +0000 (11:42 -0400)]
drm/amdgpu: add sdma ip block for dimgrey_cavefish
Enable sdma block for dimgrey_cavefish, same as sienna_cichlid.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:40:44 +0000 (11:40 -0400)]
drm/amdgpu: add gfx ip block for dimgrey_cavefish
Enable gfx block for dimgrey_cavefish, same as navy_flounder.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:39:28 +0000 (11:39 -0400)]
drm/amdgpu: add ih ip block for dimgrey_cavefish
Enable ih block for dimgrey_cavefish, same as navy_flounder.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:38:30 +0000 (11:38 -0400)]
drm/amdgpu: add gmc ip block for dimgrey_cavefish
Enable gmc block for dimgrey_cavefish, same as sienna_cichlid.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:35:47 +0000 (11:35 -0400)]
drm/amdgpu: add common ip block for dimgrey_cavefish
Same as navy_flounder.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Tue, 10 Mar 2020 08:30:28 +0000 (16:30 +0800)]
drm/amdgpu: add mmhub support for dimgrey_cavefish
Same as navy_flounder.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:34:02 +0000 (11:34 -0400)]
drm/amdgpu: initialize IP offset for dimgrey_cavefish
Add ip offset definition for dimgrey_cavefish and initialize it.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:30:54 +0000 (11:30 -0400)]
drm/amdgpu: add common support for dimgrey_cavefish
Add external id and set clock gating for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:29:43 +0000 (11:29 -0400)]
drm/amdgpu: add gfx clock gating support for dimgrey_cavefish
Set gfx clock gating for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:28:43 +0000 (11:28 -0400)]
drm/amdgpu: add gmc support for dimgrey_cavefish
Same as navy_flounder.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:26:17 +0000 (11:26 -0400)]
drm/amdgpu: add support for dimgrey_cavefish firmware
Add support for dimgrey_cavefish cp/rlc firmware.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:24:30 +0000 (11:24 -0400)]
drm/amdgpu: set asic family and ip blocks for dimgrey_cavefish
Same as navi series.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Mon, 9 Mar 2020 12:00:59 +0000 (20:00 +0800)]
drm/amdgpu: set fw load type for dimgrey_cavefish
Use direct load for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 9 Oct 2020 22:38:30 +0000 (18:38 -0400)]
drm/amdgpu: add dimgrey_cavefish gpu info firmware
Load gpu info firmware for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tao Zhou [Fri, 2 Oct 2020 15:21:47 +0000 (11:21 -0400)]
drm/amdgpu: add dimgrey_cavefish asic type
Add chip type for dimgrey_cavefish.
Signed-off-by: Tao Zhou <tao.zhou1@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Jiansong Chen <Jiansong.Chen@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Rodrigo Siqueira [Fri, 9 Oct 2020 13:36:01 +0000 (09:36 -0400)]
drm/amd/display: Fix module load hangs when connected to an eDP
It was recently introduced a change that enables driver to disable
streams if pixel clock changes. Consequently, the code path executed in
the disable vbios function expanded to an encoder verification part.
The encoder loop is nested inside the pipe count loop, and both loops
share the 'i' variable in control of their flow. This situation may lead
to an infinite loop because the encoder loop constantly updates the `i`
variable, making the first loop always positive. As a result, we can see
a soft hang during the module load (modprobe amdgpu) and a series of
dmesg log that looks like this:
kernel:[ 124.538727] watchdog: BUG: soft lockup - CPU#2 stuck for 22s!
[modprobe:1000]
RSP: 0018:
ffffabbf419bf0e8 EFLAGS:
00000282
RAX:
ffffffffc0809de0 RBX:
ffff93b35ccc0000 RCX:
ffff93b366c21800
RDX:
0000000000000000 RSI:
0000000000000141 RDI:
ffff93b35ccc0000
RBP:
ffffabbf419bf108 R08:
ffffabbf419bf164 R09:
0000000000000001
R10:
0000000000000003 R11:
0000000000000003 R12:
0000000008677d40
R13:
0000000000000141 R14:
ffff93b35cfc0000 R15:
ffff93b35abc0000
FS:
00007f1400717540(0000) GS:
ffff93b37f680000(0000)
knlGS:
0000000000000000
CS: 0010 DS: 0000 ES: 0000 CR0:
0000000080050033
CR2:
00005649b66b0968 CR3:
00000003e0fec000 CR4:
0000000000350ee0
Call Trace:
amdgpu_device_rreg+0x17/0x20 [amdgpu]
amdgpu_cgs_read_register+0x14/0x20 [amdgpu]
dm_read_reg_func+0x3a/0xb0 [amdgpu]
get_pixel_clk_frequency_100hz+0x30/0x50 [amdgpu]
dc_commit_state+0x8f1/0xae0 [amdgpu]
? drm_calc_timestamping_constants+0x101/0x160 [drm]
amdgpu_dm_atomic_commit_tail+0x39d/0x21a0 [amdgpu]
? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu]
? kfree+0xc3/0x390
? dcn21_validate_bandwidth+0xe5/0x290 [amdgpu]
...
RSP: 002b:
00007fff26009bd8 EFLAGS:
00000246 ORIG_RAX:
0000000000000139
RAX:
ffffffffffffffda RBX:
000055a8025bea50 RCX:
00007f140085c89d
RDX:
0000000000000000 RSI:
000055a8025b8290 RDI:
000000000000000c
RBP:
0000000000040000 R08:
0000000000000000 R09:
0000000000000000
R10:
000000000000000c R11:
0000000000000246 R12:
000055a8025b8290
R13:
0000000000000000 R14:
000055a8025bead0 R15:
000055a8025bea50
This issue was fixed by introducing a second variable for the internal
loop.
Fixes:
8353d30e747f4e ("drm/amd/display: disable stream if pixel clock changed with link active")
Reviewed-by: Roman Li <Roman.Li@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Bhawanpreet Lakha [Mon, 5 Oct 2020 18:07:02 +0000 (14:07 -0400)]
drm/amd/display: Add missing function pointers for dcn3
These function pointers are missing from dcn30_init
.calc_vupdate_position : Used to help avoid cursor stuttering
.set_pipe : Needed for setting ABM
So add them
Signed-off-by: Bhawanpreet Lakha <Bhawanpreet.Lakha@amd.com>
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ye Bin [Fri, 9 Oct 2020 07:47:58 +0000 (15:47 +0800)]
drm/amdgpu: Fix inconsistent of format with argument type in amdgpu_xgmi.c
Fix follow warning:
[drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.c:249]: (warning) %d in format
string (no. 1) requires 'int' but the argument type is 'unsigned int'.
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ye Bin [Fri, 9 Oct 2020 07:42:18 +0000 (15:42 +0800)]
drm/amdgpu: Fix invalid number of character '{' in amdgpu_acpi_init
Fix follow warning:
Checking drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c...
[drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:770]: (error) Invalid number
of character '{' when these macros are defined: ''.
Checking drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c: CONFIG_ACPI...
[drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:770]: (error) Invalid number
of character '{' when these macros are defined: 'CONFIG_ACPI'.
......
Checking drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c: CONFIG_X86...
[drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:770]: (error) Invalid number
of character '{' when these macros are defined: 'CONFIG_X86'.
Checking drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c: _X86_...
[drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:770]: (error) Invalid number
of character '{' when these macros are defined: '_X86_'.
Checking drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c: __linux__...
[drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.c:770]: (error) Invalid number
of character '{' when these macros are defined: '__linux__'.
Fixes:
97d798b276e9 ("drm/amdgpu: simplify ATIF backlight handling")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Ye Bin <yebin10@huawei.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Alex Deucher [Thu, 1 Oct 2020 05:06:24 +0000 (01:06 -0400)]
drm/amdgpu/swsmu: clean up a bunch of stale interfaces
These were leftover from the initial implementation, but
never used. Drop them.
Reviewed-by: Evan Quan <evan.quan@amd.com>
Noticed-by: Ryan Taylor <ryan.taylor@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Evan Quan [Wed, 30 Sep 2020 03:54:01 +0000 (11:54 +0800)]
drm/amd/pm: setup APU dpm clock table in SMU HW initialization
As the dpm clock table is needed during DC HW initialization.
And that (DC HW initialization) comes before smu_late_init()
where current APU dpm clock table setup is performed. So, NULL
pointer dereference will be triggered. By moving APU dpm clock
table setup to smu_hw_init(), this can be avoided.
Fixes:
02cf91c113ea ("drm/amd/powerplay: postpone operations not required for hw setup to late_init")
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reported-by: Dirk Gouders <dirk@gouders.net>
Acked-by: Nirmoy Das <nirmoy.das@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Changfeng [Fri, 9 Oct 2020 04:42:06 +0000 (12:42 +0800)]
drm/amdgpu: modify cp_flags to pg_flags in gfx_v10_cntl_power_gating
It needs to use adev->pg_flags other than adev->cg_glags in
gfx_v10_cntl_power_gating
Signed-off-by: Changfeng <Changfeng.Zhu@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Emily.Deng [Thu, 8 Oct 2020 00:53:59 +0000 (08:53 +0800)]
drm/amdgpu: Remove warning for virtual_display
Remove the virtual_display warning in drm_crtc_vblank_off when
dev->num_crtcs is null.
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Emily.Deng <Emily.Deng@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
kernel test robot [Wed, 23 Sep 2020 02:28:28 +0000 (10:28 +0800)]
drm/amdgpu: kfd_initialized can be static
Fixes:
c7651b73586600 ("drm/amdgpu: Fix handling of KFD initialization failures")
Signed-off-by: kernel test robot <lkp@intel.com>
Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Gustavo A. R. Silva [Thu, 8 Oct 2020 14:34:50 +0000 (09:34 -0500)]
amd/amdgpu_ctx: Use struct_size() helper and kmalloc() (v2)
Make use of the new struct_size() helper instead of the offsetof() idiom.
Also, use kmalloc() instead of kcalloc().
v2: squash in kzalloc fix
Signed-off-by: Gustavo A. R. Silva <gustavoars@kernel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>