spirv_to_nir: Cast RelaxedPrecision ALU op dests to mediump.

This is controlled by spirv_to_nir_options.relaxed_precision_alu, because
some drivers don't want it.

This gets us mostly 16-bit math on turnip in vk-5-normal.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465>

spirv: Use nir_vec_scalars() to simplify matrix transpose.

This should emit fewer instructions that need to be copy-propagated away.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465>

freedreno/ir3: Fix 16-bit bit_count.

No need to do the 16-bit lowering if it already is.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16465>

u_trace/anv/iris: drop cs argument for recording traces

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16605>

docs/u_trace: document u_trace usage

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16579>

svga: fix aa point

Use in_prim from current geometry shader to check for point prim type
when determine if aa point is enabled or not.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16598>

svga: add need_texcoord_semantic to tgsi_add_point_sprite & tgsi_add_aa_point

Since PIPE_CAP_TGSI_TEXCOORD is now set in SVGA vgpu10 driver,
we need to add a new parameter need_texcoord_semantic to
tgsi_add_point_sprite and tgsi_add_aa_point
to allow setting texcoords using tgsi texcoord semantic.

Reviewed-by: Neha Bhende <bhenden@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16598>

intel/ds: fix compilation

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6518
Fixes: efc2782f970c ("intel/perf: store a copy of devinfo")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16601>

docs: Add calendar entries for 22.1 release.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610>

relnotes: Add sha256sum and fix minor formatting issues

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610>

docs: add release notes for 22.1.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610>

docs: update calendar and link releases notes for 22.1.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16610>

pan/va: Use ^ instead of ` to indicate last-use

This syncs the ISA syntax with other Valhall ISA users. It's also somewhat
easier to read.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/va: Remove DISCARD.f32 destination

It doesn't actually write anything. This is a pointless divergence from Bifrost.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/va: Handle 2-src blend in lower_split_src

Fixes assertion fail in shaders/dolphin/smg.1.shader_test

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Validate vector widths

Now that our IR is much more strongly typed, and RA code quality depends on
correct typing, add a validation pass to make sure we didn't screw it up. This
pass found a massive number of bugs in early versions of this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Validate preload constraints are satisfied

We tightened the rules around preloading substantially and take advantage of the
rules in RA. The safe helpers it introduced should ensure the rules are
followed, but just in case, add a validation pass to check our work. This pass
found (multiple) bugs in early versions of this series.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: See through splits for var_tex fusion

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Optimize split of collect

Required to get decent codegen from UBO pushing.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Don't propagate discard

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Remove liveness metadata tracking

We don't use it for anything, and with no pass infrastructure it's just an
accident waiting to happen.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Simplify register precolouring in the IR

In the current IR, any register may be preloaded by reading it anywhere, and any
register may be precoloured by writing it anywhere. This is convenient for
instruction selection, but requires the register allocator to do considerable
gymnastics to ensure it doesn't clobber precoloured registers. It also breaks
the purity of our SSA representation, which complicates optimization passes
(e.g. copyprop).

Let's trade some instruction selection complexity for simplifying register
allocation by constraining how register precolouring works. Under the new model:

* Registers may only be preloaded at the start of the program.
* Precoloured destinations are handled explicitly by RA.

Internally, a stronger invariant is placed for preloading: registers may only be
preloaded by MOV.i32 instructions at the beginning of the block, and these moves
must be unique. These invariants ensure RA can trivially coalesce the moves.

A bi_preload helper is added as a safe version of bi_register respecting these
invariants, allowing a smooth transition for instruction selection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Remove bi_word and bi_word_node

They are no longer used, as offsets are no longer used for normal values (only for
FAU). Keep it like that.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Scalarize copyprop

Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Scalarize modifier propagation

Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Scalarize bi_opt_cse

Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Scalarize bi_lower_swizzle

Reduces memory footprint.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/va: Don't use bi_word in FAU unit test

It will be removed shortly, as the FAU construction helper should be used
instead.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/va: Use split for 64-bit lowering

Written in this way, this pass looks pretty silly...

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Emit collect and split

..Rather than using offsets during instruction selection.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Simplfy BLEND emit

We don't need to collect anything, now that Valhall handles this case correctly.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Lift split/collect cache from AGX

Design based on ACO (and fruitful discussions with Daniel).

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Create COLLECT during isel

This transitions us away from the fake SSA we currently use for vectors.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Expand MAX_DESTS to 4

For splits.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Fix mov and pack_32_2x16

Move can take in a vector and write a scalar, depending on the swizzle. We need
to handle this case. Split out mov and pack_32_2x16 so we can specify correct
behaviour for both. Also drop unused 1-bit boolean stuff which obscured the fix.

Fixes: 76cea8e27b3 ("panfrost: Fix pack_32_2x16 implementation")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Lower split/collect before RA

For transitioning to the new scalarized IR.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Add bi_before_block cursor

Useful for preloading.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Add collect and split instructions

These move-like instructions will be generated during instruction selection and
lowered before/after register allocation.

These need special printer support until we get dynamic sources/destinations.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Add source/destination counts

In preparation for dynamic allocation, as needed for phi nodes and parallel
copies. For now, it just serves to simplify the semantics of splits and
collects.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Use value-based interference with LCRA

"Revisiting Out-of-SSA Translation for Correctness, Code Quality, and
Efficiency" discusses "value-based interference": two variables interfere if and
only if there exists a point in the program where they are both live *with
different values*. In particular, the source and destination of a move do not
interfere a priori, because they have the same value at that point in the
program. (If a later instruction overwrites one, the required interference will
be added there).

We can use this idea to avoid some extra interferences, avoiding a regression in
moves from split/collect.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Lower phis to scalar

If we don't lower phis to scalar, when we go out of SSA, we can get vector
nir_registers. In particular, we can get code like:

   r0 = vec2 r0.y, r0.x

This code looks like a move, but is in fact a swap. The trivial lowering of vec2
would not work -- the following fails to swap correctly:

   r0.x = r0.y
   r0.y = r0.x

Currently, we generate temporaries to handle these cases. It's easy to move the
complexity to NIR, though, and we'll want to scalarize phis for SSA-based RA
anyway.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: +JUMP can't read same-cycle temp

Minor ISA detail missed in the Bifrost scheduler. I hit this in an early version
of this series (where a move feeding into a blend shader return was not
coalesced). Let's get it fixed in the scheduler.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/va: Use 64-bit lowering for texturing

Texture instructions on Valhall take 64-bit sources. Now that we have
infrastructure to handle this properly, we don't need to use a non-SSA node to
hack around the optimization.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/va: Lower split 64-bit sources

This ensures Valhall 64-bit constraints are respected in a simple way. It's not
the most efficient, though. Optimization is deferred until full Valhall support
is upstreamed and the RA is overhauled.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/va: Mark more source sizes

This source size information will be consumed by the 64-bit lowering pass, so
ensure it's accurate. That means marking 32-bit and 64-bit sources explicitly on
message passing where it wouldn't match up with the type size suffix of the
instruction.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

pan/bi: Update bi_count_write_registers for Valhall

We add some new instructions on Valhall with special register requirements
(texturing, atomics). Handle these appropriately so we can do RA on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16585>

vulkan: Fall back to raw data objects when deserializing if ops == NULL

This can happen if an object is serialized whose object type isn't in
the pipeline cache import ops.  In this case, we generate a raw data
object and plan to turn it into the right object type later.

Fixes: d35e78bb8536 ("vulkan/pipeline_cache: Implement deserialize for raw objects")
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16584>

radv: validate shaders after linking passes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

radv: add missing NIR_PASS() and switch from NIR_PASS_V()

Unlike NIR_PASS_V(), NIR_PASS() can skip printing the shader when
NIR_DEBUG=print.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5244
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

radv: call nir_metadata_preserve in various lowering passes

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

nir: call nir_metadata_preserve in nir_lower_memory_model

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

nir: call nir_metadata_preserve in nir_vectorize_tess_levels

This is necessary to use this pass with the NIR_PASS() macro.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

nir: call nir_metadata_preserve in nir_io_add_const_offset_to_base

This is necessary to use this pass with the NIR_PASS() macro.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

nir: print file when validation fails

This should make it clear whether a validation failure happens in RADV or
zink.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

nir: allow NIR_PASS(_, )

If a user wants to skip printing the shader if no changes were made
without declaring a dummy variable for the progress.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12448>

radeonsi: wait for PS idle in si_set_framebuffer_state

This is needed to avoid write-after-read hazards in
texture -> render transitions.

This fixes fbo-depth tests that were flaky on GPUs (at
least sienna_cichlid and vega20).

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16561>

amd: rename fishes to Navi21, Navi22, Navi23, Navi24, and Rembrandt

Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16604>

mesa/st: clear color buffers using color from a constant buffer

v2: fixed GLCTS failures (mareko)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>

mesa/st: add nir shader to clear color buffers using constant value

v2: use load_uniform instead of load_ubo to fix vc4

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>

gallium/u_blitter: clear color buffers using color from a constant buffer

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>

radeonsi: save the fs constant buffer to the util blitter context

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15318>

Revert "ci: Disable jobs to the Collabora lab"

This reverts commit 224544dc33c60b933b379eef067058ad31ef7bae.

Work has finished and the lab is up and running.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16600>

util/u_trace: Add json output

If we want to load the u_trace output somewhere for analysis it's much
easier to deal with json than to parse strings.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16475>

aco: remove unnecessary intrinsics that are lowered at the ABI level

Fixes: f553076eaf1 ("aco: Remove now-superfluous intrinsics.")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16577>

r300: keep negation if w is an inline constant

(in dataflow swizzles pass)

helps with:
dEQP-GLES2.functional.shaders.random.conditionals.combined.73
on r300 and r400

Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16559>

nir/i915g/r300/nv30: skip marking varyings as flat in some drivers

Some older drivers don't support GLSL versions with the concept of flat
varyings and also don't support integers. Here we add a new setting to
make sure we don't use the optimisation that sets varyings to flat.
This setting helps us avoid marking varyings as flat and therefore
potentially having them changed to ints via varying packing.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6500
Fixes: 7647023f3bb5 ("glsl: enable the use of the nir based varying linker")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16573>

v3dv: Loosen an assert in copy_buffer_to_image_shader

In f99ac7f2de19 ("v3dv: Don't use color aspects for depth/stencil
images"), we stopped using color aspects for depth/stencil images in a
bunch of cases.  This causes us to trigger an assert in
copy_buffer_to_image_shader where it assumes 16-bit is always color but
now it can also be D16_UNORM.  The assert isn't protecting us from
anything we weren't already doing before so we can just loosen it a bit.

Fixes: f99ac7f2de19 ("v3dv: Don't use color aspects for depth/stencil images")
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16592>

ci/crosvm: Terminate the previous crosvm after a deqp-runner timeout.

When deqp-runner times out, it kills the deqp process, which in our case
is the previous invocation of our shell script, so the crosvm and socat
cleanup never happened.  crosvm has a way to cleanly shut down a previous
crosvm invocation, so let's just use that and do our cleanup when we need
to.

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16485>

ci/crosvm: Rename VSOCK_TEMP_DIR -> VM_TEMP_DIR.

It doesn't contain anything about the vsocks, just files shared between
the host and the guest.

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16485>

ci/crosvm: Simplify the CID setup.

Now that deqp-runner tells us which thread we are, we don't need to go
probing for a spare directory to use.

Reviewed-by: Cristian Ciocaltea <cristian.ciocaltea@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16485>

dzn: Add new parameter to vk_image_view_init call

Fixes: fc8d2543 ("vulkan,v3dv: Add a driver_internal flag to vk_image_view_init/create")
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16589>

d3d12: MSVC warning around operator precedence causing uint32_t==bool

Fixes: b171a6ba ("d3d12: Add video encode implementation of pipe_video_codec")
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16588>

d3d12: Don't use VLAs

Fixes: 739283da ("d3d12: Improve planar resource support to handle video requirements")
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16588>

d3d12: Include windows.h on Windows before dxgicommon.h

The dxgicommon.h header uses UINT types without including windows.h itself.

Fixes: 6dbe05ff ("d3d12: Add util video functions to d3d12_format")
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16588>

radv: init states from pRasterizationState at only one place

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16552>

radv: init states from pViewportState at only one place

Except the viewport/scissor arrays to avoid useless array copies.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16552>

radv: init states from pTessellationState at only one place

It's part of the pre-rasterization state of graphics pipeline libs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16552>

tu: Implement VK_EXT_pipeline_creation_cache_control

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16562>

tu: Implement VK_EXT_pipeline_creation_feedback

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16562>

tu: Zero-initialize compute driver key

Fixes: 05329d7 ("tu: Implement pipeline caching with shared Vulkan cache")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16562>

drirc: Set limit_trig_input_range option for glmark2

This fixes jellyfish rendering issues in glmark2 on Intel.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6479
Signed-off-by: Vadym Shovkoplias <vadym.shovkoplias@globallogic.com>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16525>

freedreno/a6xx: Add EARLYPREAMBLE flag to all a6xx_sp_xs_ctrl_reg0

Each shader stage has its own "early preamble" flag.

Early preamble is likely an optimization to hide some of latency
when loading UBOs into consts in the preamble.

Early preamble has the following limitations:
- Only shared, a1, and consts regs could be used
  (accessing other regs would result in GPU fault);
- No cat5/cat6, only stc/ldc variants are working;
- Values writen to shared regs are not accessible by the rest
  of the shader;
- Instructions before shps are also considered to be a part of
  early preamble.

Note, for all shaders from d3d11 games blob produced preambles
compatible with early preamble mode.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15901>

Revert "st/mesa: Transcode ASTC to BC7 (BPTC) where possible"

This reverts commit 68ef895674b176b4faf875a4d7f4d787b330d4d9.

When trying out transcode_astc=true with BPTC on Asphalt 9, we observed
very poor image quality - to the point that basic UI icons were blocky,
and buttons with a black border had smeared pixels on the edges.  Using
DXT5 had no such issues.

I originally suspected there was a bug in the BPTC encoder, but I now
believe the issue is deeper than that.  The commit that introduced the
encoder, 17cde55c538009764207bd29b78a909d2c5d14b4, says:

   "The compressor is written from scratch and takes a very simple
    approach.  It always uses a single mode of the BPTC format (4 for
    unorm and 3 for half-floats) and picks the two endpoints by dividing
    the texels into those which have more or less than the average
    luminance of the block and then calculating an average color of the
    texels within each division.

    It's probably not really sensible to try to use BPTC compression at
    runtime because for example with the Nvidia offline compression tool
    it can take in the order of an hour to compress a full-screen image.
    With that in mind I don't think it's worth having a proper compressor
    in Mesa and this approach gives reasonable results for a usage that
    is basically a corner case."

In other words, the reason our BPTC compressor was so fast is that it
only implements one of the modes and does a low quality approximation.
This honestly should probably be improved somewhat, but the original
use case was for online-compression, the uncommon but mandatory OpenGL
feature where you can supply uncompressed data and trust the driver to
compress it for you (at unknown and uncontrolled quality and speed).

Unfortunately, the compressor as it stands is simply not usable for
transcoding ASTC data where we want to preserve the underlying image
quality as much as possible.

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16566>

radeonsi: fix glTexBuffer max size handling

The spec says the number of texels must be clamped to the value of
GL_MAX_TEXTURE_BUFFER_SIZE.

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Mihai Preda <mhpreda@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16480>

docs: update extensions for V3D and VC4

Mark some extensions that are already supported by V3D and VC4.

Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16528>

radv: add new pipeline helpers for NIR->ASM compilation

It walks backwards to compile, looks cleaner to me.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16553>

radv: do not try to dump the NIR of the trap handler shader

There is no NIR at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16553>

radv: rename shader compile functions to spirv_to_nir/nir_to_asm

For better clarity.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16553>

radv/ci: enable the experimental support for mesh shaders

The experimental support has been merged for months already, but has
been left unexercised in CI even though dEQP has a mesh_shader.nv
category.

This commit enables the experimental support, which should bring
additional testing \o/.

Suggested-by: Timur Kristóf <timur.kristof@gmail.com>
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16550>

ci: Disable jobs to the Collabora lab

In anticipation of infrastructure work.

This commit is to be reverted later in the day.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16576>

vulkan/pipeline_cache: Implement deserialize for raw objects

When caching NIR, it's cached as a raw object because we cache the
serialized NIR.  When it's then loaded from the disk cache later, we
fail to deserialize it because raw objects are a special case.  There
are two callers of vk_pipeline_cache_object_deserialize(), one of which
has a special case for raw objects and the other is called only when
we've checked that it isn't a raw object.  The special cases are
pointless; raw objects should deserialize themselves.

Fixes: 591da9877900 ("vulkan: Add a common VkPipelineCache implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16281>

zink: add ZINK_DEBUG=sync

this is great for debugging

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16544>

zink: add c++ guards for zink_screen.h

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16544>

zink: fix non-dynamic vertex stride update flagging

without dynamic vertex input, pipeline vertex state must be recalculated
if buffer strides change or the enabled buffer mask changes in order
to accurately handle dynamic state stride VUs

cc: mesa-stable

fixes:
spec@!opengl 1.1@array-stride

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16563>

zink: handle PIPE_BUFFER sparse texture queries

this is legal but was never handled

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16563>

zink: clamp 1D_ARRAY sparse textures to 2D as needed

forgot to handle this case

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16563>

zink: force render target usage for sampler-only resources

these might hit u_blitter later, which will require rt usage
to handle texture views, so add rt usage now to avoid failing later

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16563>

zink: fix surface/bufferview cache comparisons

these caches ignore pNext from the create info since the pNext cannot
affect the eventual object that is created, so comparing it will break
the hash table

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16563>

zink: add extended usage and retry if resource creation fails

this is one of those cases where some bizarro format is being created
for sampling only, but gallium blasts out all the bind flags at once

trust that we're not going to do anything too crazy and let surface
usage pruning handle the rest

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16563>

zink: remove input attachment usage when pruning surface usage

if the format doesn't support color attachment, it doesn't need to
be an input attachment

cc: mesa-stable

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16563>