radv: do not abort if SPM isn't supported for the current GPU

In a mixed GFX9/GFX10 setup, this would crash for the GFX9 logical
device. Just print a message intead of aborting.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17292>

radv: use LOAD_CONTEXT_REG to load the opaque buffer size on GFX10+

For unknown reasons, COPY_DATA can hang on GFX10+ while it doesn't
hang on GFX9. Adding PFP_SYNC_ME before/after the COPY_DATA doesn't
fix the hang either.

Using a LOAD_CONTEXT_REG_INDEX packet shouldn't be needed unless the
driver supports preemption (shadow memory) which RADV doesn't support.

I don't have a real explanation but PFP_SYNC_ME+LOAD_CONTEXT_REG_INDEX
fixes a GPU hang with Space Engineers (game uses a bunch of consecutive
calls to vkCmdDrawIndirectByteCountEXT without anything in-between).

Gitlab: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5838
Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17290>

st/glsl: fix broken vertex attrib mapping

Here we move the nir_get_single_slot_attribs_mask() call that sets the
inputs_read mask after NIR optimisations have finished and after
st_nir_assign_vs_in_locations() has been called.

Besides fixing a bug where the mappings would be missaligned if
further NIR optimisations resulted in less inputs being read, it
also allows us to drop an additional nir gather info call.

Fixes: 0909a57b631f ("radeonsi/nir: Set vs_inputs_dual_locations and let NIR do the remap")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6240

Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17326>

freedreno/a6xx: Initialize VFD_FETCH[n].SIZE to zero

Avoid inheriting VBOs from other processes/submits (ie. anywhere it
might not be an actual valid iova).

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6763
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>

freedreno/a6xx: Split VFD_FETCH[] if needed

Avoid overflowing max pkt4 size by splitting VFD_FETCH[] emit.
Otherwise the maximum size of 32 VBOs would overflow and wrap to
zero.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>

freedreno/registers: Small cleanup

Whitespace fix plus move a couple regs that ended split apart from the
rest of the VFD regs.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>

freedreno: Add pkt4 assert

Add assert to catch places where we overflow max PKT4 size

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17317>

freedreno/registers: add missing varset="chip" for new enum values

Fixes: de8c769d1168 ("freedreno/registers: add a7xx registers for drm/msm kernel driver")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6788
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17351>

etnaviv: rework resource status tracking (again)

While a resource might be shared across different contexts all synchronization
of commands is the resposibility of the user (OpenGL spec Chapter 5 "Shared
Objects and Multiple Contexts").

Currently etnaviv tries to be extremely helpful by flushing foreign contexts
when using a resource that is still pending there. This introduces a lot of
issues, as context flushes can now happen at basically any time and also
introduces a lot of overhead due to the needed tracking and locking. Get rid
of all this cross-context tracking and flushing.

The only real requirement here is that we need to track pending resources
without mutating the state of the etna_resource, as this might be shared
across multiple contexts and thus be used by multiple threads concurrently.
Introduce a hash table to track the current pending resources and their
states in the local context.

A side-effect of this change is that we don't need to keep all used
resources referenced until context flush time, as we don't need to mutate
them anymore to track the status. This allows to free some of them a bit
earlier. Note that this introduces a small possibility of a new resource
matching the key of a already destroyed resource still in the
pending_resources hashtable, but even if we get such a collision the worst
outcome is a not strictly necessary flush of the local context being
performed, which is acceptable if it doesn't happen very often.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14466>

etnaviv: add function to get resource status

Don't access the status member of etna_resource directly, as this
go away to get rid of shared mutable state. Add a wrapper function
that allows to plug in the new status lookup.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14466>

etnaviv: drm: rename etna_drm_table_lock

This lock is used to serialize much more than just the lookup tables. In
fact it's used for all device global state including the bo cache. Rename
it to better reflect its real usage.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14466>

etnaviv: drm: make etna_bo_map thread safe

This might be called from multiple threads at the same time. To avoid
taking a global lock just to guard against the fairly low chance of
multiple threads calling this on the same BO at the same time, we allow
for the threads to race. All threads will set up a mapping, but only
the first thread is able to set the map member of the etna_bo, all other
threads just roll back and use the mapping set up by the winning thread.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14466>

etnaviv: drm: don't cache mmap offset

The mmap offset is the only information we currently get from
DRM_ETNAVIV_GEM_INFO and there is no point in storing this
offset after the mapping has been established. Reduce the
shared mutable state on the etna_bo by inlining fetching the
offset into etna_bo_map.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14466>

etnaviv: drm: always use hash to track BO index

Currently the buffer index hash is only used if the BO is used in
multiple streams and the current index is cached on the BO. This
introduces some shared state on the BO, which necessitates the use
of a lock to keep this state consistent across threads, which
negates some of the benefits of caching the index.

Always use the hash to keep track of the submit BOs, to get rid
of the shared state and simplify the code.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14466>

etnaviv: allow mapped buffers during execution

Etnaviv has no restrictions on buffers being mapped during execution. In
fact most buffers are already always mapped during their lifetime as the
unmap is a no-op. Let the frontend know that it doesn't need to bother
with unmapping buffers.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17343>

etnaviv: expose real map buffer alignment

As we do not suballocate any buffers, the real map buffer alignment
is determined by the GEM BO map alignment, which is at least 4KB.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17343>

radv/ci: do not reboot on soft-recovered hangs, just warn

The job will still fail, but it will at least go through until the end.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>

radv/ci: allow specifying a warning pattern

This will be used to detect soft resets without aborting the run, but
still make the job fail.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>

radv/ci: add CI lists for LLVM on NAVI21

Copied and adjusted from the ACO lists.

v2: Martin Roukala
 - add an extra test in the list of timeouts
 - add an extra test in the list of flakes
 - remove a fail

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>

radv/ci: test the llvm backend on navi21

The LLVM backend is not officially supported by the RADV developers,
but it has been useful early during bring-up, or later when users are
experiencing what looks like a compiler bug. It is thus beneficial to
keep it working.

However, maintaining the vkcts expectations for every platform requires
more work and machine time than what we would like to commit to. This
is why we agreed that we would only keep LLVM tested on the latest
family of Radeon GPUs.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16841>

gallium/util: Move u_dl and u_pointer to src/util

Reviewed-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17327>

etnaviv: async shader compile

Passes following piglit:
 - spec@khr_parallel_shader_compile@basic

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16172>

etnaviv: factor out shader screen related init/deint

This is a prep step for the next changes.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16172>

ci/x86: update to llvm 13

Most CI tests are currently running on LLVM 11 (released over 2 years
ago), which predates some of the GPUs we have in CI and prevents
testing RADV's LLVM backend.

LLVM 13 is known to work for RADV, released almost 8 months ago, and
is already available in most distributions. Fedora 36 is even already
on LLVM 14.

So this commit updates x86 testing on llvm 13.

v2:
 - store the llvm apt repo key locally (Michel Dänzer)

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Timur Kristóf <timur.kristof@gmail.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17188>

radv: Use NIR optimization to move discards to the top.

Fossil stats on Sienna Cichlid:

Totals from 1988 (1.55% of 128653) affected shaders:
VGPRs: 68096 -> 67928 (-0.25%); split: -0.61%, +0.36%
CodeSize: 5391936 -> 5391312 (-0.01%); split: -0.11%, +0.10%
MaxWaves: 53020 -> 52946 (-0.14%); split: +0.05%, -0.19%
Instrs: 992413 -> 992509 (+0.01%); split: -0.10%, +0.11%
Latency: 8643141 -> 8789295 (+1.69%); split: -0.31%, +2.00%
InvThroughput: 1680195 -> 1680605 (+0.02%); split: -0.04%, +0.07%
SClause: 50886 -> 51318 (+0.85%); split: -0.73%, +1.57%
Copies: 57017 -> 56741 (-0.48%); split: -1.28%, +0.80%
PreSGPRs: 66766 -> 67048 (+0.42%); split: -0.24%, +0.66%
PreVGPRs: 56832 -> 56935 (+0.18%); split: -0.44%, +0.62%

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13037>

venus: swizzle the chroma channels for YVU420 to match the VkFormat

Test:
- testVP8EncodeDecodeVideoFromBufferToSurface
- android.media.cts.DecodeAccuracyTest

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17323>

radv: Add CULL_PRIMITIVE to special output mask.

It isn't compiled to an output param, so can be safely ignored
from the param assignment.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>

radv: Don't assign driver locations to mesh shader outputs.

Set all driver locations to zero.
These are ignored by ac_nir_lower_ngg anyway.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>

ac/nir/ngg: Ignore driver location for mesh shader outputs.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17244>

ci/radv: enable vkcts testing on kabini

It seems like the hangs have been resolved on kabini, so let's allow
developers to run their tests on kabini, if they are *very* patient
(~10h).

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17129>

ci/freedreno: disable SpecOps trace, each run flaky

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17336>

freedreno/registers: add a7xx registers for drm/msm kernel driver

Most of this is taken directly from the downstream kernel driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15602>

dzn: Support Vulkan loader interface v5

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17321>

radv: Use two bools for ahit_status

This avoids using a VGPR and uses two SGPRs
instead since we only need to store 2 bits.

Quake II RTX:

Totals from 7 (0.46% of 1513) affected shaders:
CodeSize: 229364 -> 229148 (-0.09%); split: -0.12%, +0.02%
Instrs: 41937 -> 41879 (-0.14%)
Latency: 977374 -> 976723 (-0.07%)
InvThroughput: 651582 -> 651148 (-0.07%)
Copies: 5064 -> 5033 (-0.61%)
PreSGPRs: 430 -> 433 (+0.70%)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17293>

ci/freedreno: disable Stellaris trace

Revert when it gets fixed on CI runner (works on OnePlus 6T with
5.18 kernel).

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>

ci/freedreno: temporary disable AmnesiaTDD

Revert when https://gitlab.freedesktop.org/mesa/mesa/-/issues/6763 get fixed.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>

ci/freedreno: add more restricted traces

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17167>

nir/opt_shrink_vectors: fix re-using of components for vecN

Cc: mesa-stable
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17276>

ir3: Use NIR's info.writes_memory to detect when when to force late-z

Better than maintaining our old checks.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16818>

v3dv: fix pool descriptor count for inline uniform buffers

Fixes VK_ERROR_OUT_OF_POOL_MEMORY in the inlineuniformblocks
sample from Sascha Willems.

Fixes: ea3223e7a46 ('v3dv: implement VK_EXT_inline_uniform_block')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17311>

vulkan/wsi: Disable dma-buf sync file if ENOSYS is returned

ENOSYS is commented as "Invalid system call number". This is returned
by qemu-user for unbridged ioctls.

Fixes: 30b57f10b36d ("vulkan/wsi: Signal semaphores and fences from the dma-buf")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17325>

dzn: Mark transition barriers as executed when we execute barriers

It was previously done dzn_cmd_buffer_flush_transition_barriers(),
leaving the queue+flush case unhandled. Let's fix that by moving
this piece of code to dzn_cmd_buffer_exec_transition_barriers().

Fixes: 35356b1173e ("dzn: Cache and pack transition barriers")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17314>

broadcom/rpi4-skips: drop duplicated lines

Signed-off-by: Eric Engestrom <eric@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17312>

glsl: drop non-nir path for atan in builtin functions

All drivers now use NIR. Here we drop the non NIR path and rename
the NIR path to drop the extra "_op" chars from the function names.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17308>

intel/fs: Opportunistically split SEND message payloads

While we've taken advantage of split-sends in select situations, there
are many other cases (such as sampler messages, framebuffer writes, and
URB writes) that have never received that treatment, and continued to
use monolithic send payloads.

This commit introduces a new optimization pass which detects SEND
messages with a single payload, finds an adjacent LOAD_PAYLOAD that
produces that payload, splits it two, and updates the SEND to use both
of the new smaller payloads.

In places where we manually used split SENDS, we rely on underlying
knowledge of the message to determine a natural split point.  For
example, header and data, or address and value.

In this pass, we instead infer a natural split point by looking at the
source registers.  Often times, consecutive LOAD_PAYLOAD sources may
already be grouped together in a contiguous block, such as a texture
coordinate.  Then, there is another bit of data, such as a LOD, that
may come from elsewhere.  We look for the point where the source list
switches VGRFs, and split it there.  (If there is a message header, we
choose to split there, as it will naturally come from elsewhere.)

This not only reduces the payload sizes, alleviating register pressure,
but it means that we may be able to eliminate some payload construction
altogether, if we have a contiguous block already and some extra data
being tacked on to one side or the other.

shader-db results for Icelake are:

   total instructions in shared programs: 19602513 -> 19369255 (-1.19%)
   instructions in affected programs: 6085404 -> 5852146 (-3.83%)
   helped: 23650 / HURT: 15
   helped stats (abs) min: 1 max: 1344 x̄: 9.87 x̃: 3
   helped stats (rel) min: 0.03% max: 35.71% x̄: 3.78% x̃: 2.15%
   HURT stats (abs)   min: 1 max: 44 x̄: 7.20 x̃: 2
   HURT stats (rel)   min: 1.04% max: 20.00% x̄: 4.13% x̃: 2.00%
   95% mean confidence interval for instructions value: -10.16 -9.55
   95% mean confidence interval for instructions %-change: -3.84% -3.72%
   Instructions are helped.

   total cycles in shared programs: 848180368 -> 842208063 (-0.70%)
   cycles in affected programs: 599931746 -> 593959441 (-1.00%)
   helped: 22114 / HURT: 13053
   helped stats (abs) min: 1 max: 482486 x̄: 580.94 x̃: 22
   helped stats (rel) min: <.01% max: 78.92% x̄: 4.76% x̃: 0.75%
   HURT stats (abs)   min: 1 max: 94022 x̄: 526.67 x̃: 22
   HURT stats (rel)   min: <.01% max: 188.99% x̄: 4.52% x̃: 0.61%
   95% mean confidence interval for cycles value: -222.87 -116.79
   95% mean confidence interval for cycles %-change: -1.44% -1.20%
   Cycles are helped.

   total spills in shared programs: 8387 -> 6569 (-21.68%)
   spills in affected programs: 5110 -> 3292 (-35.58%)
   helped: 359 / HURT: 3

   total fills in shared programs: 11833 -> 8218 (-30.55%)
   fills in affected programs: 8635 -> 5020 (-41.86%)
   helped: 358 / HURT: 3

   LOST:   1 SIMD16 shader, 659 SIMD32 shaders
   GAINED: 65 SIMD16 shaders, 959 SIMD32 shaders

   Total CPU time (seconds): 1505.48 -> 1474.08 (-2.09%)

Examining these results: the few shaders where spills/fills increased
were already spilling significantly, and were only slightly hurt.  The
applications affected were also helped in countless other shaders, and
other shaders stopped spilling altogether or had 50% reductions.  Many
SIMD16 shaders were gained, and overall we gain more SIMD32, though many
close to the register pressure line go back and forth.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17018>

intel/compiler: Handle split-sends in EOT high-register pinning case

SEND messages with EOT need to use g112-g127 for their sources so that
the hardware is able to launch new threads while old ones are finishing
without worrying about register overlap when pushing payloads.  For the
newer split-send messages, this applies to both source registers.

Our special case for this in the register allocator was only considering
the first source.  This wasn't a problem because we hadn't ever tried to
use split-sends with EOT before.  However, my new optimization pass is
going to introduce some shortly, so we'll need to handle them properly.

Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17018>

aco: drop radv_shader.h include

This shouldn't be used anymore

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

aco/radv: provide a vs prolog callback from aco to radv.

Avoid building the radv binary in aco, just callback with the
necessary info.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

aco/radv: provide a callback from aco shader building to build binary

This moves the radv specific code into radv, and calls back from
aco into radv.

This should allow easier radeonsi integration later.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

aco: refactor the radv binary builder out of the core aco fn.

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16445>

intel/compiler: Convert brw_eu.cpp back to brw_eu.c

Now that we've removed the thread_local lookup tables using
pointer-to-member C++ features, this can go back to being a standard
C file, like it was in the past.  We just need to annotate a couple
of things with "struct".

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Remove use of thread_local for opcode tables

We had been using thread_local index -> opcode_desc tables to avoid
plumbing through a storage location throughout all the code.  But now
we have done so with the new brw_isa_info structure.  So we can just
store the tables there, and initialize it with the compiler.

This fixes crashes in gtk4-demo on iris, and should help with some
programs on zink as well.  Something was going wrong with the
thread_local variables not being set up correctly.  While we might be
able to work around that issue, there's really no advantage to storing
these lookup tables in TLS (beyond it being simpler to do originally).
So let's simply stop doing so.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6728
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6229
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Introduce a new brw_isa_info structure

This structure will contain the opcode mapping tables in the next
commit.  For now, this is the mechanical change to plumb it into all
the necessary places, and it continues simply holding devinfo.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Move opcode_desc handling to a separate header

This patch creates a new header file, brw_isa_info.h, which will
contains all the functions related to opcode encoding on various
generations.  Opcode numbers may have different meanings on different
hardware, so we remap them between an enum we can easily work with
and the hardware encoding.

We move the brw_inst setters and getters to brw_inst.h.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/tools: Stop malloc'ing device info in i965_disasm

There's not really any point, a stack allocated struct works fine.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Split 3DPRIM_* defines out to a separate header.

These clash with genxml and will become a problem shortly.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Fix brw_gfx_ver_enum.h to be a proper header file

This header file didn't include normal guards against being included
multiple times.  It also defined a function in a header file without
marking it static inline.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

intel/compiler: Stop including src/mesa/main/config.h

src/mesa/main includes are for Mesa's OpenGL implementation, and the
compiler is used in Vulkan drivers and other tools.  We really only
needed one #define, which is that we offer 32 samplers.  It probably
makes more sense to have our own defined limit for that rather than
importing a project-wide value which theoretically could be adjusted,
so swap MAX_SAMPLERS for a new BRW_MAX_SAMPLERS and call it a day.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

crocus: Use PIPE_* defines rather than ones from main/config.h

Gallium drivers shouldn't be including src/mesa/main headers, but we're
picking up a rogue main/config.h via the compiler, so this code I ported
over from i965 kept compiling.  Use the PIPE_* defines instead so that
we can stop including that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

iris: Use PIPE_* defines rather than ones from main/config.h

Gallium drivers shouldn't be including src/mesa/main headers, but we're
picking up a rogue main/config.h via the compiler, so this code I ported
over from i965 kept compiling.  Use the PIPE_* defines instead so that
we can stop including that.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17309>

zink: enforce viewport depth clamping

VUID-VkViewport-minDepth-01234 specifies that depth must be in the range [0.0, 1.0],
so the viewport must always be clamped to this range

this affects texture clears using u_blitter, as this expects to be able
to use the GL range of [-1.0, 1.0], so pass the depth value as though it's
been de-converted back to a GL z coordinate to account for viewport transform

cc: mesa-stable

fixes #6757

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17319>

lavapipe: don't remove xfb outputs

cc: mesa-stable

fixes:
dEQP-VK.transform_feedback.simple.multiquery_omit_write_1
dEQP-VK.transform_feedback.simple.multiquery_omit_write_3
dEQP-VK.transform_feedback.simple.query_omit_write_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_4_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_4_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_250_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_124_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_248_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_4_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_list_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_line_strip_with_adjacency_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_fan_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_249_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_507_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_246_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_504_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_list_with_adjacency_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_127_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_251_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_509_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_61_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_0_6_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_126_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_250_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_508_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_60_64bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_32bits
dEQP-VK.transform_feedback.simple.query_omit_write_triangle_strip_with_adjacency_0_6_64bits

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17299>

zink: disable turnip traces temporarily

this needs a libX11 update

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17313>

venus: use narrow range to match up with mesa EGL

This matches up with the native gl drivers as well as the media stack.

Test: android.graphics.cts.MediaVulkanGpuTest
Test: android.media.cts.EncodeDecodeTest

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Ryan Neph <ryanneph@google.com>
Reviewed-by: Chad Versace <chadversary@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17306>

radv/ci: re-enable vega10 fossils testing

Should work now.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>

aco/ra: update register file when updating phi definition

update_renames() fills in the wrong temp id.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Fixes: 302cb5c9001 ("aco/ra: remove some redundant code")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17295>

docs: update calendar and link releases notes for 22.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17318>

docs: add sah256sum for mesa 22.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17318>

docs: add release notes for 22.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17318>

ci: Remove the trailing "when: never"s from rules.

This avoids the risks of concatenating our rulesets missing out on some
file list because of a "never" in the middle.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/zink: Simplify lavapipe rules setup, and clarify what the rules are for.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/zink: Reuse anv-rules.

This makes it so that we respect collabora farm disables.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/freedreno: Filter when we run test jobs for VK or GL changes.

Not only runs less testing when only one driver is impacted, but also
makes sure zink+turnip is turned off when the farm is.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Split core GL from core VK-or-GL rules.

Now editing src/glx won't rerun Vulkan testing.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Simplify vulkan rules using !references.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci/freedreno: Use !references to clean up restricted traces rules.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Pull common zink frontend rules to a shared rule list.

This drops the mesa/gallium lists from some build rules, since zink common
rules brings them in already.  If we do more driver common rules, we might
end up with those core lists appearing in the yaml multiple times, but
that seems like a small price to pay for not being able to forget some.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Pull out farm disables to a reused rule.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

ci: Use "!references" to manage scheduled pipeline rules.

Because !references merging happens after yaml parsing, this lets us
remove a duplicated definition between .test-source-dep.yml and
.gitlab-ci.yml.

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Acked-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17287>

dozen: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

microsoft: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

intel: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

d3d12: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

nir: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

radv: Use nir_test_mask instead of i2b(iand)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

nir: Add a nir_test_mask helper

nir_ine_imm(b, nir_iand_imm(b, x, mask), 0) and
nir_i2b(b, nir_iand_imm(b, x, mask)) are common
patterns which become quite messy when they are
part of a larger expression. Clang-format does
not improve things either and we can end up with
some rather interesting looking code.
(RADV ray tracing pipeline and query lowering)

Signed-off-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17242>

radv: reorder some NIR passes

Totals from 6171 (4.57% of 134913) affected shaders: (GFX10.3)
CodeSize: 61916968 -> 61916676 (-0.00%); split: -0.01%, +0.01%
Instrs: 11473620 -> 11473797 (+0.00%); split: -0.01%, +0.01%
Latency: 161997216 -> 161997029 (-0.00%); split: -0.00%, +0.00%
InvThroughput: 29075944 -> 29075862 (-0.00%); split: -0.00%, +0.00%
VClause: 199793 -> 199790 (-0.00%); split: -0.01%, +0.00%
SClause: 418180 -> 418013 (-0.04%)
Copies: 786921 -> 786884 (-0.00%); split: -0.06%, +0.06%
Branches: 348058 -> 348106 (+0.01%); split: -0.04%, +0.06%
PreSGPRs: 604400 -> 604396 (-0.00%)
PreVGPRs: 469415 -> 469430 (+0.00%)

Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17279>

radv: fix swizzles after nir_opt_algebraic_late

Fixes: 2e895f8b0496f9f15359a5d98ef722d3d9753bc4 ('radv: vectorize nir_op_fabs')
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17279>

ac/nir/ngg: Refactor LDS instructions in NGG GS vertex emit and export.

Change NGG GS emit vertex code to emit combined shared stores,
also change the export vertex code to emit combined shared loads.
This results in more optimal code generation, ie. fewer LDS
instructions are generated.

GS vertices are stored using an odd stride to minimize the chance
of bank conflicts, which means that unfortunately
we still can't use an alignment higher than 4 here,
so the best we can get are some ds_read2_b32 instructions.

Fossil DB stats on Navi 21 (formerly Sienna Cichlid):

Totals from 135 (0.10% of 128653) affected shaders:
VGPRs: 6416 -> 6512 (+1.50%)
CodeSize: 529436 -> 503792 (-4.84%)
MaxWaves: 2952 -> 2924 (-0.95%)
Instrs: 93384 -> 90176 (-3.44%)
Latency: 290283 -> 293611 (+1.15%); split: -0.36%, +1.50%
InvThroughput: 81218 -> 82598 (+1.70%)
Copies: 6603 -> 6606 (+0.05%)
PreVGPRs: 5037 -> 5076 (+0.77%)

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11425>

zink: don't increment screen->num_contexts for copy context

this otherwise may trigger unwanted perf regressions

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17315>

zink: store context flags

Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17315>

nv50/ir/ra: Fix copying compound for moves

In order to reduce moves when coalescing multiple registers into a
larger register, RA will try to coalesce MERGE instructions with their
definitions. For example, for something like this in GLSL:

uint a = ...;
uint b = ...;
uint64 x = packUint2x32(a, b);

The compiler will try to coalesce x with a and b, in the same way as
something like:

uint a = ...;
uint b = ...;
...
uint x = phi(a, b);

with the crucial difference that the definitions of a and b only clobber
part of the register, instead of the whole thing. This information is
carried through the compound flag and compMask bitmask. If compound is
set, then the value has been coalesced in such a way that not all the
defs clobber the entire register. The compMask bitmask describes which
subregister each def clobbers, although it does it in a slightly
convoluted way. It's an invariant that once compound is set on one def,
it must be set for all the defs in a given coalesced value.

In more detail, the constraints pass will first create extra moves:

uint a = ...;
uint b = ...;
uint a' = a;
uint b' = b;
uint64 x = packUint2x32(a', b');

and then RA will merge values involved in MERGE/SPLIT instructions,
merging x with a' and b' and making the combined value compound -- this
is relatively simple, and will always succeed since we just created a'
and b', so they never interfere with x, and x has no other definitions,
since we haven't started coalescing moves yet. Basically, we just replaced
the MERGE instruction with an equivalent sequence of partial writes to the
destination. The tricky part comes when we try to merge a' with a
and b' with b. We need to transfer the compound information from a' to a
and b' to b, which copyCompound() does, but we also need to transfer it
to any defs coalesced with a and b, which the code failed to do. Similarly,
if x is the argument to a phi instruction, then when we try to merge it
with other arguments to the same phi by coalescing moves, we'd have
problems guaranteeing that all the other merged defs stay up-to-date.

One tricky part of fixing this is that in order to properly propagate
the information from a' to a, we need to do it before the defs for a and
a' are merged in coalesceValues(), since we need to know which defs are
merged with a but not a' -- after coalesceValues() returns, all the defs
have been combined, so we don't know which is which. I took the approach
of calling copyCompound() inside coalesceValues(), instead of
afterwards.

v2: (mhenning) This now loops over mergedDefs in copyCompound, to update
    it for changes made in bcf6a9ec

Cc: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: Karol Herbst <kherbst@redhat.com>
Tested-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: M Henning <drawoc@darkrefraction.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17115>

zink: remove the workaround for depth_clip_enable on turnip

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>

turnip: keep the depth_clip_disable state at the pipeline builder.

So we could later decide whether to enable Z_CLIP_DISABLE on not.

Closes: #6732

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>

freedreno,ir3: rename Z_CLAMP_ENABLE to Z_CLIP_DISABLE

UNK5 of GRAS_CL_CNTL is still unclear though.

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17248>

nir/types: fix glsl_matrix_type_is_row_major() assert

interface blocks can have row_major set

cc: mesa-stable

affects (zink):
dEQP-GLES2.functional.shaders*

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17238>

zink: workaround depth sampler border color when z24 is z32

If there is a z24 unorm depth buffer, but it's the hw is using
a z32, the border color needs to be clamped appropriately.

This creates a second sampler with the clamped border color,
and uses it if needed. The checks might need some tightening up.

Fixes: zink on radv
dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth
dEQP-GLES31.functional.texture.border_clamp.range_clamp.nearest_unorm_depth_uint_stencil_sample_depth

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17305>

ci: Remove -Wno-error=maybe-uninitialized

It is not needed anymore.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17121>

svga: Clear query before usage

Fixes the following compiler warning:
  svga_pipe_query.c:1295:17: warning: 'result.u64' may be used uninitialized [-Werror=maybe-uninitialized]

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17121>

r600: Switch to unreachable(..)

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17121>