Christian Kohlschütter [Mon, 17 Oct 2022 19:02:36 +0000 (19:02 +0000)]
arm: dts: rockchip: rk3399: nanopi-r4s: Provide smbios sysinfo
Provide human-readable manufacturer and product names for the
FriendlyELEC NanoPi R4S.
Enable CONFIG_SYSINFO and CONFIG_SYSINFO_SMBIOS by default.
Signed-off-by: Christian Kohlschütter <christian@kohlschutter.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tom Rini [Mon, 27 Feb 2023 22:18:36 +0000 (17:18 -0500)]
Prepare v2023.04-rc3
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 27 Feb 2023 14:11:57 +0000 (09:11 -0500)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Thu, 23 Feb 2023 22:32:22 +0000 (17:32 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-tegra
Tom Rini [Thu, 23 Feb 2023 22:30:49 +0000 (17:30 -0500)]
Merge branch '2023-02-23-assorted-fixes'
- btrfs bugfix, silence a bunch of gcc-12.2 linker warnings finally,
relax one of the trace test time requirements (so CI doesn't fail due
to test being slightly slow, but still correct), and correct env on
MMC and checking for where GPT can be
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:38 +0000 (19:35 +0200)]
ARM: tegra20: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypt BCT.
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Ramin Khonsari [Tue, 14 Feb 2023 17:35:37 +0000 (19:35 +0200)]
ARM: tegra30: implement BCT patching
This function allows updating bootloader from u-boot
on production devices without need in host PC.
Be aware! It works only with re-crypted BCT.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Ramin Khonsari <raminterex@yahoo.com>
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:36 +0000 (19:35 +0200)]
ARM: tegra: crypto: extend crypto functional
Add support for encryption, decryption and signinig with
non-zero key saving backward compatibility.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:35 +0000 (19:35 +0200)]
ARM: tegra: expose crypto module for all Tegra SoCs
Move crypto module from T20 only into common Tegra dir.
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:34 +0000 (19:35 +0200)]
board: tegra30: switch to updated pre-dm i2c write
Configure PMIC voltages for early stages using updated
early i2c write.
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:33 +0000 (19:35 +0200)]
board: tegra124: switch to updated pre-dm i2c write
Configure PMIC for early stages using updated i2c write.
Tested-by: Thierry Reding <treding@nvidia.com> # Jetson TK1 T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:32 +0000 (19:35 +0200)]
ARM: tegra: create common pre-dm i2c write
This implementation allows pwr i2c writing on early SPL
stages when DM is not yet setup.
Such writing is needed to configure main voltages of PMIC
on early SPL for bootloader to boot properly.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:31 +0000 (19:35 +0200)]
ARM: tegra: add late init support
Late init function allows passing values like identifiers and
perform device specific configurations of pre-boot stage.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Maxim Schwalm [Tue, 14 Feb 2023 17:35:30 +0000 (19:35 +0200)]
ARM: tegra: provide default USB gadget setup
All Nvidia boards use the same manufacturer, vendor ID and product ID
for the gadgets. Make them the defaults to remove some boilerplate from
the defconfigs.
Inspired by commit
e02687bda96c ("sunxi: provide default USB gadget
setup") which did the same for Allwinner boards.
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Maxim Schwalm <maxim.schwalm@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:29 +0000 (19:35 +0200)]
spi: tegra20_slink: accept any word length
Original t20 slink could work with commands only
fully divisible by 8. This patch removes such
restriction, so commands of any bitlength now
can be passed and processed.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF600T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:28 +0000 (19:35 +0200)]
ARM: tegra: Fix Tegra PWM parent clock
Default parent clock for the PWM on Tegra is a 32kHz clock and
is unable to support the requested PWM period.
Fix PWM support on Tegra20, Tegra30, Tegra114, Tegra124 and Tegra210 by
updating the parent clock for the PWM to be the PLL_P.
This commit is equivalent to Linux kernel commit:
https://lore.kernel.org/all/
20221010100046.6477-1-jonathanh@nvidia.com/
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # ASUS TF201 T30
Tested-by: Thierry Reding <treding@nvidia.com> # T30 and T124
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:27 +0000 (19:35 +0200)]
ARM: tegra30: add PLLD to pll setup
On T30 unlike T20 dsi panels are wider used on devices
and PLLD is used as DISP1 parent more often, so lets
enable it as well for this cases.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF700T T30
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:26 +0000 (19:35 +0200)]
ARM: tegra: clock: add clock_decode_pair helper
Get periph clock id and its parent from device tree.
This works by looking up the peripheral's 'clocks' node and
reading out the second and fourth cells, which are the
peripheral and PLL clock numbers.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:25 +0000 (19:35 +0200)]
ARM: tegra: clock: add clk_id_to_pll_id helper
This function allows to convert a device tree clock ID to PLL ID.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # HTC One X
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:24 +0000 (19:35 +0200)]
ARM: t20/t30: swap host1x and disp1 clock parents
According to mainline clock tables and TRM HOST1X
parent is PLLC, while DISP1 usually uses PLLP as
parent clock.
Tested-by: Andreas Westman Dorcsak <hedmoo@yahoo.com> # ASUS TF T30
Tested-by: Robert Eckelmann <longnoserob@gmail.com> # ASUS TF101 T20
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Tested-by: Thierry Reding <treding@nvidia.com> # Beaver T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Signed-off-by: Tom <twarren@nvidia.com>
Svyatoslav Ryhel [Tue, 14 Feb 2023 17:35:23 +0000 (19:35 +0200)]
tegra30: clock: add EXTPERIPH
This mappings were missing for some reason.
Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # LG P895 T30
Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom <twarren@nvidia.com>
Marek Vasut [Thu, 9 Feb 2023 12:30:10 +0000 (13:30 +0100)]
env: mmc: Apply GPT only on eMMC user HW partition
Apply the GPT U-Boot environment GUID type look up only on eMMC user
HW partition, do not apply the look up on eMMC boot HW partitions as
mmc_offset_try_partition() assumes either SD partitions or eMMC user
HW partition.
This fixes environment operation on systems where CONFIG_SYS_MMC_ENV_PART
is non-zero and CONFIG_SYS_REDUNDAND_ENVIRONMENT is set.
Fixes:
80105d8fd52 ("env: mmc: select GPT env partition by type guid")
Signed-off-by: Marek Vasut <marex@denx.de>
Reviewed-by: Tom Rini <trini@konsulko.com>
Simon Glass [Fri, 17 Feb 2023 22:45:16 +0000 (15:45 -0700)]
trace: Relax test requirements
We expect the profile and bootstage to agree on timing, but when
running on slow machines there can be a larger descrepency. Increase the
tolerance to fix this.
Fixes:
9cea4797aeb ("trace: Add a test")
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 14 Feb 2023 20:09:32 +0000 (15:09 -0500)]
x86: Pass -z execstack for EFI payload flags
To match how we link EFI executables elsewhere, and to silence a linker
warning, pass -z execstack here as well.
Cc: Bin Meng <bmeng.cn@gmail.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Tue, 14 Feb 2023 20:09:31 +0000 (15:09 -0500)]
Makefile: Link with -z noexectack
When moving to gcc-12.2 we started trying to quiet some of the new
linker warnings, that are not relevant to us. However, a
misunderstanding of the mechanics at play meant that I intentionally
omitted passing -z noexecstack to the linker, when we do need to. Add
this flag and in turn remove warnings from the linker.
Fixes:
1e1c51f8ace8 ("Makefile: link with --no-warn-rwx-segments")
Signed-off-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Qu Wenruo [Mon, 13 Feb 2023 00:37:59 +0000 (08:37 +0800)]
fs: btrfs: limit the mapped length to the original length
[BUG]
There is a bug report that btrfs driver caused hang during file read:
This breaks btrfs on the HiFive Unmatched.
=> pci enum
PCIE-0: Link up (Gen1-x8, Bus0)
=> nvme scan
=> load nvme 0:2 0x8c000000 /boot/dtb/sifive/hifive-unmatched-a00.dtb
[hangs]
[CAUSE]
The reporter provided some debug output:
read_extent_data: cur=
615817216, orig_len=16384, cur_len=16384
read_extent_data: btrfs_map_block: cur_len=
479944704; ret=0
read_extent_data: ret=0
read_extent_data: cur=
615833600, orig_len=4096, cur_len=4096
read_extent_data: btrfs_map_block: cur_len=
479928320; ret=0
Note the second and the last line, the @cur_len is 450+MiB, which is
almost a chunk size.
And inside __btrfs_map_block(), we limits the returned value to stripe
length, but that's depending on the chunk type:
if (map->type & (BTRFS_BLOCK_GROUP_RAID0 | BTRFS_BLOCK_GROUP_RAID1 |
BTRFS_BLOCK_GROUP_RAID1C3 | BTRFS_BLOCK_GROUP_RAID1C4 |
BTRFS_BLOCK_GROUP_RAID5 | BTRFS_BLOCK_GROUP_RAID6 |
BTRFS_BLOCK_GROUP_RAID10 |
BTRFS_BLOCK_GROUP_DUP)) {
/* we limit the length of each bio to what fits in a stripe */
*length = min_t(u64, ce->size - offset,
map->stripe_len - stripe_offset);
} else {
*length = ce->size - offset;
}
This means, if the chunk is SINGLE profile, then we don't limit the
returned length at all, and even for other profiles, we can still return
a length much larger than the requested one.
[FIX]
Properly clamp the returned length, preventing it from returning a much
larger range than expected.
Reported-by: Andreas Schwab <schwab@linux-m68k.org>
Signed-off-by: Qu Wenruo <wqu@suse.com>
Tom Rini [Wed, 22 Feb 2023 18:36:29 +0000 (13:36 -0500)]
Merge branch 'master' of https://source.denx.de/u-boot/custodians/u-boot-usb
- DWC3 bugfix
Tom Rini [Wed, 22 Feb 2023 14:28:03 +0000 (09:28 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-socfpga
- chameleonv3 updates
Paweł Anikiel [Tue, 21 Feb 2023 15:17:06 +0000 (16:17 +0100)]
chameleonv3: Convert CONFIG_SPL_MAX_SIZE to Kconfig
This file was missed during the conversion process. Add the symbol to
defconfig.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Tue, 21 Feb 2023 15:17:05 +0000 (16:17 +0100)]
arm: dts: chameleonv3: Add 270-2 variant
Add devicetree for chameleonv3 with the 270-2I2-D11E variant of the
Mercury+ AA1 module
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Tue, 21 Feb 2023 15:17:04 +0000 (16:17 +0100)]
arm: dts: chameleonv3: Rename chameleonv3.dts to .dtsi
This file is included by the different chameleonv3 variants. Change the
name to .dtsi.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Tue, 21 Feb 2023 15:17:03 +0000 (16:17 +0100)]
arm: dts: chameleonv3: Override chameleonv3 bitstream names
Set the bitstream name per Chameleon variant. This allows the same
boot filesystem with all bitstream variants to be used on different
boards.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Tue, 21 Feb 2023 15:17:02 +0000 (16:17 +0100)]
socfpga: chameleonv3: Move environment to a text file
Move the environment to an easily editable text file in the boot
partition
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Paweł Anikiel [Tue, 21 Feb 2023 15:17:01 +0000 (16:17 +0100)]
socfpga: chameleonv3: Enable ext4 in SPL
Allow SPL to boot from an ext4 filesystem.
Signed-off-by: Paweł Anikiel <pan@semihalf.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Venkatesh Yadav Abbarapu [Fri, 13 Jan 2023 05:12:02 +0000 (10:42 +0530)]
usb: dwc3: Use the devm_gpiod_get_optional() API for reset gpio
As the "reset-gpios" property is optional, don't return the
error and just skip the gpio reset sequence.
Signed-off-by: Venkatesh Yadav Abbarapu <venkatesh.abbarapu@amd.com>
Tom Rini [Sun, 19 Feb 2023 22:03:30 +0000 (17:03 -0500)]
Merge tag 'efi-2023-04-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-04-rc3
Documentation
* Add a document for the RISC-V architecture
* Move gateworks and bcm7xxx documentation to HTML
UEFI
* measure the loaded device-tree
* make CapsuleMax configurable and provide sensible default
Heinrich Schuchardt [Sun, 19 Feb 2023 20:26:24 +0000 (21:26 +0100)]
doc: remove superfluous warning
We have been using Sphinx >=3 since 2020. We don't expect issues.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Etienne Carriere [Thu, 16 Feb 2023 17:21:41 +0000 (18:21 +0100)]
efi_loader: set CapsuleMax from CONFIG_EFI_CAPSULE_MAX
Adds CONFIG_EFI_CAPSULE_MAX to configure the max index value used in
EFI capsule reports. Prior to this change is the hard coded value was
65535 which would exceed available storage for variables. Now the
default value is 15 which should work fine with most systems.
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Etienne Carriere [Thu, 16 Feb 2023 16:29:48 +0000 (17:29 +0100)]
efi_loader: Measure the loaded DTB
Measures the DTB passed to the EFI application upon new boolean config
switch CONFIG_EFI_TCG2_PROTOCOL_MEASURE_DTB. For platforms where the
content of the DTB passed to the OS can change across reboots, there is
not point measuring it hence the config switch to allow platform to not
embed this feature.
Co-developed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Signed-off-by: Etienne Carriere <etienne.carriere@linaro.org>
Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Masahisa Kojima [Wed, 15 Feb 2023 02:32:17 +0000 (11:32 +0900)]
efi_loader: fix wrong attribute check for QueryVariableInfo
QueryVariableInfo with EFI_VARIABLE_HARDWARE_ERROR_RECORD is
accepted, remove wrong attribute check.
Fixes:
454a9442fbce ("efi_loader: update attribute check for QueryVariableInfo()")
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Mon, 13 Feb 2023 18:22:33 +0000 (19:22 +0100)]
efi_loader: avoid buffer overrun in efi_var_mem_compare
We should not scan beyond the end of string name.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Yu Chien Peter Lin [Tue, 14 Feb 2023 10:18:51 +0000 (18:18 +0800)]
doc: arch: Add document for RISC-V architecture
This patch adds a brief introduction to the RISC-V architecture and
the typical boot process used on a variety of RISC-V platforms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tim Harvey [Mon, 13 Feb 2023 17:44:27 +0000 (09:44 -0800)]
board: gateworks: venice: move README to RST
Move board/gateworks/venice/README to RST documentation.
Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Thomas Fitzsimmons [Mon, 13 Feb 2023 16:21:27 +0000 (11:21 -0500)]
doc: board: bcm7xxx: Convert to reStructuredText format
Convert the documentation for the Broadcom BCM7445 and BCM7260 boards
to reStructuredText format and add the new filename to
doc/board/broadcom/index.rst.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Yu Chien Peter Lin [Sun, 12 Feb 2023 07:09:51 +0000 (15:09 +0800)]
doc: devicetree: dt_qemu.rst: Fix the typo and space
Fix typo and whitespace in the document.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Fri, 17 Feb 2023 19:18:46 +0000 (14:18 -0500)]
Merge branch '2023-02-17-assorted-fixes'
- avb_verify bugfix, and cpsw_mdio bugfix
Ivan Khoronzhuk [Fri, 27 Jan 2023 20:02:14 +0000 (22:02 +0200)]
common: avb_verify: prevent opening incorrect session
The arg->session is not valid if arg->ret != NULL, so can't be
assigned, correct this.
Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@globallogic.com>
Reviewed-by: Jens Wiklander <jens.wiklander@linaro.org>
Ulf Samuelsson [Tue, 7 Feb 2023 08:25:27 +0000 (09:25 +0100)]
cpsw_mdio.c: Use correct reg in cpsw_mdio_get_alive
cpsw_mdio_get_alive reads the wrong register.
See page 2316 in SPRUH73Q AM335x TRM
Signed-off-by: Ulf Samuelsson <ulf@emagii.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Ramon Fried <rfried.dev@gmail.com>
Reviewed-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Tom Rini [Fri, 17 Feb 2023 14:58:06 +0000 (09:58 -0500)]
configs: Resync with savedefconfig
Rsync all defconfig files using moveconfig.py
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Fri, 17 Feb 2023 14:03:35 +0000 (09:03 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-riscv
- binman: Add help message if opensbi is absent when building u-boot SPL
- AndesTech: rename cpu and board name to 'andesv5' and 'ae350'
- Clean up cache operation for Andes ae350 platform
Rick Chen [Fri, 17 Feb 2023 08:57:01 +0000 (16:57 +0800)]
riscv: binman: Add help message for missing blobs
Add the 'missing-msg' for more detailed output
on missing system firmware.
Signed-off-by: Rick Chen <rick@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Leo Yu-Chi Liang [Tue, 14 Feb 2023 12:42:50 +0000 (20:42 +0800)]
riscv: ae350: Adjust the memory layout of ae350
Adjust the initial stack pointer address to 0x10000000(256M)
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Leo Yu-Chi Liang [Tue, 14 Feb 2023 12:42:49 +0000 (20:42 +0800)]
riscv: Rename Andes cpu and board names
The current ae350-related defconfigs could also
support newer Andes CPU IP, so modify the names of CPU
from ax25 to andesv5, and board name from ax25-ae350 to ae350.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:53 +0000 (16:10 +0800)]
driver: cache-v5l2: Fix type casting warning on RV32
This patch fixes following warning for the riscv32 toolchain.
drivers/cache/cache-v5l2.c:122:16: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
122 | regs = (struct l2cache *)dev_read_addr(dev);
| ^
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:52 +0000 (16:10 +0800)]
configs: ae350: Display CPU and board info for AE350 platforms
Display information about CPU and board during start up.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:51 +0000 (16:10 +0800)]
configs: ae350: Increase maximum retry count for AE350 platforms
Loading an image via TFTP is often interrupted when retrying more than
10 times, increase the number of retries so that it does not simply stop
the transfer.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:50 +0000 (16:10 +0800)]
configs: ae350: Enable v5l2 cache for AE350 platforms in SPL
To reduce the code size, CONFIG_V5L2_CACHE was disabled since commit:
ca06444aac2c643db3a3f2eb37afc60fae15177e
Turing on does not significantly increase the size of u-boot-spl.bin,
so we enable it by default to improve performance.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:49 +0000 (16:10 +0800)]
riscv: ax25: cache.c: Cleanups to L1/L2 cache function used in SPL
This patch refines L1 cache enable/disable and v5l2-cache enable
functions.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:48 +0000 (16:10 +0800)]
riscv: ae350: dts: Update L2 cache compatible string
Update the compatible string of L2 cache.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:47 +0000 (16:10 +0800)]
riscv: cpu: ax25: Simplify cache enabling logic in harts_early_init()
As the OpenSBI v1.2 does not enable the cache [0], we enable
the i/d-cache in harts_early_init() and do not disable in
cleanup_before_linux(). This patch also simplifies the logic
and moves the CSR encoding to include/asm/arch-andes/csr.h.
[0] https://github.com/riscv-software-src/opensbi/commit/
bd7ef4139829da5c30fa980f7498d385124408fa
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:46 +0000 (16:10 +0800)]
driver: cache: cache-v5l2: Update memory-mapped scheme to support Gen2 platform
The L2C configuration register has MAP field to indicate its version
is v0 (Gen1) or v1 (Gen2) L2-cache. This patch makes the driver
compatible with both memory-mapped scheme.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 08:10:45 +0000 (16:10 +0800)]
board: AndesTech: ax25-ae350.c: Enable v5l2-cache in spl_board_init()
The L2-cache is not enabled currently, the enbale_caches() will call
the v5l2_enable() callback to enable it in SPL.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Leo Yu-Chi Liang [Mon, 6 Feb 2023 08:10:44 +0000 (16:10 +0800)]
riscv: Remove redundant Kconfig "RISCV_NDS_CACHE"
There is no need for RISCV_NDS_CACHE config to control cache switches.
Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Yu Chien Peter Lin [Mon, 6 Feb 2023 02:06:29 +0000 (10:06 +0800)]
riscv: global_data.h: Correct the comment for PLICSW
PLIC is used for external interrupt, while PLICSW is an Andes-specific
design for software interrupt.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Tom Rini [Mon, 13 Feb 2023 23:39:15 +0000 (18:39 -0500)]
Prepare v2023.04-rc2
Signed-off-by: Tom Rini <trini@konsulko.com>
Sumit Garg [Mon, 13 Feb 2023 04:49:09 +0000 (10:19 +0530)]
clocks: qcs404: Add support for I2C clocks
Co-developed-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Mike Worsfold <mworsfold@impinj.com>
Signed-off-by: Sumit Garg <sumit.garg@linaro.org>
Tom Rini [Mon, 13 Feb 2023 14:57:35 +0000 (09:57 -0500)]
Merge tag 'i2c-updates-for-v2023.04' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c updates for v2023.04
- add new i2c driver ast2600 from Ryan Chen
- i2c-cdns: make read fifo-depth configurable through device tree
from Pei Yue Ho
- mxc i2c driver: print base address in hex, not in decimal
from Fabio
Tom Rini [Mon, 13 Feb 2023 14:39:15 +0000 (09:39 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Support for 2 new Armada 385 boards (Tony)
- mvebu: Minor misc board enhancements (Tony)
- kirkwood: Serial driver fixes (Kconfig & dtsi) (Tony)
- cmd: return code when tlv_eeprom incorrectly called (Heinrich)
Tony Dinh [Fri, 10 Feb 2023 21:08:17 +0000 (13:08 -0800)]
arm: kirkwood: Enable uart0 dm-pre-reloc for Pogoplug V4 board
When DM_SERIAL is enabled, the device-tree tag u-boot,dm-pre-reloc is
required for this board to boot over UART with kwboot. Enable this in
kirkwood-pogoplug-series-4-u-boot.dtsi.
Added by Stefan while applying:
Please note that it's not fully understood, why this property really
is needed. Here a link to the discussion about this:
https://lore.kernel.org/r/
20230201080210.ypz4nrj4y2igwxz3@pali/
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Thu, 9 Feb 2023 22:00:03 +0000 (14:00 -0800)]
arm: mvebu: Add support for Synology DS116 (Armada 385)
Synology DS116 is a NAS based on Marvell Armada 385 SoC.
Board Specification:
- Marvel MV88F6820 Dual Core at 1.8GHz
- 1 GiB DDR3 RAM
- 8MB Macronix mx25l6405d SPI flash
- I2C
- 2x USB 3.0
- 1x GBE LAN port (PHY: Marvell 88E1510)
- 1x SATA (6 Gbps)
- 3x LED
- PIC16F1829 (connected to uart1)
- GPIO fan
- serial console
Note that this patch depends on the add-support for Thecus N2350 patch:
https://patchwork.ozlabs.org/project/uboot/patch/
20230201231306.7010-1-mibodhi@gmail.com/
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Tony Dinh [Tue, 7 Feb 2023 01:00:11 +0000 (17:00 -0800)]
arm: mvebu: Power up 2nd SATA port for Thecus N2350
Currently, only the 1st SATA port is powered up (by GPIO1 12).
Add GPIO1 13 in board initialization to power up the 2nd SATA port.
Note that this patch depends on the initial add-support patch:
https://patchwork.ozlabs.org/project/uboot/patch/
20230201231306.7010-1-mibodhi@gmail.com/
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Thu, 2 Feb 2023 22:16:53 +0000 (14:16 -0800)]
arm: kirkwood: sheevaplug: reduce u-boot image size
Sheevaplug board has 512K CONFIG_BOARD_SIZE_LIMIT. Recently, DM_SERIAL has
pushed the image size a few hundred bytes over that limit. So explicitly
deselect some configs that are unrelated to this board
(and gain back a bit over 2K).
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Tony Dinh [Wed, 1 Feb 2023 23:13:05 +0000 (15:13 -0800)]
arm: mvebu: Add support for Thecus N2350 (Armada 385) board
Thecus N2350 is a NAS based on Marvell Armada 385 SoC.
Specification:
- Processor: Marvel MV88F6820 Dual Core at 1GHz
- 1 GiB DDR4 RAM
- 4MB Macronix mx25l3205d SPI flash
- 512MB Hynix H27U4G8F2DTR-BC NAND flash
- I2C
- 2x USB 3.0
- 1x GBE LAN port (PHY: Marvell 88E1510)
- 2x SATA (hot swap slots)
- 3x buttons
- 10x LEDS
- serial console
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tony Dinh [Tue, 31 Jan 2023 22:06:54 +0000 (14:06 -0800)]
arm: kirkwood: Use CONFIG_SYS_NS16550 with DM_SERIAL for Kirkwood boards
CONFIG_SYS_NS16550 is required when DM_SERIAL is enabled for
Kirkwood boards.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Heinrich Schuchardt [Fri, 27 Jan 2023 21:49:10 +0000 (22:49 +0100)]
cmd: return code when tlv_eeprom incorrectly called
A command called with incorrect parameters should set $? to 1 (false).
Instead of calling cmd_usage(cmdtp) and then returning 0 just return
CMD_RET_FAILURE.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Acked-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Stefan Roese <sr@denx.de>
Pei Yue Ho [Mon, 13 Feb 2023 08:02:41 +0000 (00:02 -0800)]
i2c: i2c-cdns.c: Update driver to read fifo-depth from device tree
Enable driver to fetch the optional parameter (fifo-depth) from device
tree. If the parameter is not found in the device tree, it will use
the default value declared in the driver.
Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Pei Yue Ho [Mon, 13 Feb 2023 08:02:40 +0000 (00:02 -0800)]
dt-bindings: i2c: i2c-cdns.txt: Add description for an optional parameter, fifo-depth
Add description for fifo-depth parameter that can be used
in the device tree.
Signed-off-by: Pei Yue Ho <peiyue.ho@starfivetech.com>
Reviewed-by: Wei Liang Lim <weiliang.lim@starfivetech.com>
Reviewed-by: Eng Lee Teh <englee.teh@starfivetech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Ryan Chen [Mon, 30 Jan 2023 06:19:25 +0000 (14:19 +0800)]
arm: aspeed: dtsi: add reg for i2c
The i2c driver have global register that i2c bus use
ofnode_get_parent to get parent register address.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Ryan Chen [Mon, 30 Jan 2023 06:19:24 +0000 (14:19 +0800)]
i2c:aspeed:support ast2600 i2c new register mode driver
Add i2c new register mode driver to support AST2600 i2c
new register mode. AST2600 i2c controller have legacy and
new register mode. The new register mode have global register
support 4 base clock for scl clock selection, and new clock
divider mode.
Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Fabio Estevam [Tue, 3 Jan 2023 19:03:44 +0000 (16:03 -0300)]
i2c: mxc_i2c: Use hex notation for the base address
Printing the I2C controller base address in decimal notation
is not helpful.
Change it to hex notation, which is the standard format found
in the Reference Manual and devicetree.
Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Dhruva Gole <d-gole@ti.com>
Reviewed-by: Heiko Schocher <hs@denx.de>
Tom Rini [Mon, 13 Feb 2023 01:11:22 +0000 (20:11 -0500)]
Merge tag 'dm-pull-12feb23' of https://source.denx.de/u-boot/custodians/u-boot-dm
minor changes to fdt command and binman
Andre Przywara [Fri, 10 Feb 2023 11:02:12 +0000 (11:02 +0000)]
cmd: fdt: allow standalone "fdt move"
At the moment every subcommand of "fdt", except "addr" itself, requires
the DT address to be set first. We explicitly check for that before even
comparing against the subcommands' string.
This early bailout also affects the "move" subcommand, even though that
does not require or rely on a previous call to "fdt addr". In fact it
even sets the FDT address to the target of the move command, so is a
perfect beginning for a sequence of fdt commands.
Move the check for a previously set FDT address to after we handle the
"move" command also, so we don't need a dummy call to "fdt addr" first,
before being able to move the devicetree.
This skips one pointless "fdt addr" call in scripts which aim to alter
the control DT, but need to copy it to a safe location first (for
instance to $fdt_addr_r).
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Andre Przywara [Fri, 10 Feb 2023 11:02:11 +0000 (11:02 +0000)]
cmd: fdt: move: Use map_sysmem to convert pointers
The "fdt move" subcommand was using the provided DTB addresses directly,
without trying to "map" them into U-Boot's address space. This happened
to work since on the vast majority of "real" platforms there is a simple
1:1 mapping of VA to PAs, so either value works fine.
However this is not true on the sandbox, so the "fdt move" command fails
there miserably:
=> fdt addr $fdtcontroladdr
=> cp.l $fdtcontroladdr $fdt_addr_r 40 # simple memcpy works
=> fdt move $fdtcontroladdr $fdt_addr_r
Segmentation fault
Use the proper "map_sysmem" call to convert PAs to VAs, to make this
more robust in general and to enable operation in the sandbox.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 7 Feb 2023 21:34:18 +0000 (14:34 -0700)]
binman: Show the image name for the top-level section
At present we show 'main section' as the top-level section name. It may
be more helpful to show the actual image name. This is tricky because
Image is a parent class of Entry_section, so there is no distinction
between an image and a section.
Update it to show the image name.
Signed-off-by: Simon Glass <sjg@chromium.org>
Jade Lovelace [Sat, 11 Feb 2023 01:15:26 +0000 (17:15 -0800)]
socfpga: fix the serial console on DE1-SoC
Previously, the TX LED would flash but nothing would appear on the
serial port, and the board would appear dead with a build of the
socfpga_cyclone5_defconfig. I have verified that adding the frequency to
the uart will fix the serial console on my board.
Thanks to @ehoffman on the Rocketboards forum:
https://forum.rocketboards.org/t/cyclonev-programming-fpga-from-u-boot/2230/30
Signed-off-by: Jade Lovelace <lists@jade.fyi>
Reviewed-by: Marek Vasut <marex@denx.de>
Tom Rini [Sun, 12 Feb 2023 20:25:32 +0000 (15:25 -0500)]
Merge tag 'clk-2023.04-rc1' of https://source.denx.de/u-boot/custodians/u-boot-clk
Clock changes for 2023.04-rc1
This contains various fixes and small features. I've included a reset patch as
well since it was in the same series as a clock patch.
Tom Rini [Sun, 12 Feb 2023 20:25:09 +0000 (15:25 -0500)]
Merge branch 'for-2023.04' of https://source.denx.de/u-boot/custodians/u-boot-mpc8xx
- A fix for a long standing bug that has been exposed by commit
50128aeb0f8 ("cyclic: get rid of cyclic_init()") preventing 8xx boards
from booting since u-boot 2023.01
- A GPIO driver for powerpc 8xx chip
- Fixup for powerpc 8xx SPI driver
- A new powerpc 8xx board
- The two devices having that board.
Samuel Holland [Sun, 22 Jan 2023 00:02:52 +0000 (18:02 -0600)]
reset: Allow reset_get_by_name() with NULL name
This allows devm_reset_control_get(dev, NULL) to work and get the first
reset control, which is common in code ported from Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-2-samuel@sholland.org
Samuel Holland [Sun, 22 Jan 2023 00:02:51 +0000 (18:02 -0600)]
clk: Allow clk_get_by_name() with NULL name
This allows devm_clock_get(dev, NULL) to work and get the first clock,
which is common in code ported from Linux.
Signed-off-by: Samuel Holland <samuel@sholland.org>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Link: https://lore.kernel.org/r/20230122000252.53642-1-samuel@sholland.org
Patrick Delaunay [Tue, 13 Dec 2022 13:57:10 +0000 (14:57 +0100)]
cmd: clk: probe the clock before dump them
The clock UCLASS need to be probed to allow availability of the
private data (struct clk *), get in show_clks() with dev_get_clk_ptr()
before use them.
Without this patch the clock dump can cause crash because all the
private data are not available before calling the API clk_get_rate().
It is the case for the SCMI clocks, priv->channel is needed for
scmi_clk_get_rate() and it is initialized only in scmi_clk_probe().
This issue causes a crash for "clk dump" command on STM32MP135F-DK board
for SCMI clock not yet probed.
Fixes:
1a725e229096 ("clk: fix clock tree dump to properly dump out every registered clock")
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Reviewed-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221213145708.v2.1.Ia0bc6b272f1e2e3f37873c61d79138c2663c4055@changeid
Dario Binacchi [Mon, 19 Dec 2022 11:31:26 +0000 (12:31 +0100)]
clk: imx8mn: fix imx8mn_enet_phy_sels clocks list
[backport from linux commit
2626cf67f20b28446dfc3a5b9493dd535cdb747b]
According to the "Clock Root" table of the reference manual (document
IMX8MNRM Rev 2, 07/2022):
Clock Root offset Source Select (CCM_TARGET_ROOTn[MUX])
... ... ...
ENET_PHY_REF_CLK_ROOT 0xAA80 000 - 24M_REF_CLK
001 - SYSTEM_PLL2_DIV20
010 - SYSTEM_PLL2_DIV8
011 - SYSTEM_PLL2_DIV5
100 - SYSTEM_PLL2_DIV2
101 - AUDIO_PLL1_CLK
110 - VIDEO_PLL_CLK
111 - AUDIO_PLL2_CLK
... ... ...
while the imx8mn_enet_phy_sels list didn't contained audio_pll1_out for
source select bits 101b.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-4-dario.binacchi@amarulasolutions.com
Dario Binacchi [Mon, 19 Dec 2022 11:31:25 +0000 (12:31 +0100)]
clk: imx: rename video_pll1 to video_pll
[backport from linux commit
bedcf9d1dcf88ed38731f0ac9620e5a421e1e9d6]
Unlike audio_pll1 and audio_pll2, there is no video_pll2. Further, the
name used in the RM is video_pll. So, let's rename "video_pll1" to
"video_pll" to be consistent with the RM and avoid misunderstandings.
No functional changes intended.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-3-dario.binacchi@amarulasolutions.com
Dario Binacchi [Mon, 19 Dec 2022 11:31:24 +0000 (12:31 +0100)]
clk: imx8mn: rename vpu_pll to m7_alt_pll
[backport from linux commit
a429c60baefd95ab43a2ce7f25d5b2d7a2e431df]
The IMX8MN platform does not have any video processing unit (VPU), and
indeed in the reference manual (document IMX8MNRM Rev 2, 07/2022) there
is no occurrence of its pll. From an analysis of the code and the RM
itself, I think vpu pll is used instead of m7 alternate pll, probably
for copy and paste of code taken from modules of similar architectures.
Signed-off-by: Dario Binacchi <dario.binacchi@amarulasolutions.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221219113127.528282-2-dario.binacchi@amarulasolutions.com
Jim Liu [Mon, 21 Nov 2022 09:15:28 +0000 (17:15 +0800)]
clk: nuvoton: fix bug for calculate pll clock
Fix bug for npcm7xx bmc calculate pll clock.
PLLCON1 need to divide by 2.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com>
Acked-by: Sean Anderson <seanga2@gmail.com>
Link: https://lore.kernel.org/r/20221121091528.1351-1-JJLIU0@nuvoton.com
Sjoerd Simons [Sun, 12 Feb 2023 15:07:05 +0000 (16:07 +0100)]
lmb: Treat a region which is a subset as equal
In various cases logical memory blocks are coalesced; As a result doing
a strict check whether memory blocks are the same doesn't necessarily
work as a previous addition of a given block might have been merged into
a bigger block.
Fix this by considering a block is already registered if it's a pure
subset of one of the existing blocks.
Signed-off-by: Sjoerd Simons <sjoerd@collabora.com>
Tom Rini [Sun, 12 Feb 2023 15:56:54 +0000 (10:56 -0500)]
Merge branch '2023-02-10-update-trace-feature-to-work-with-trace-cmd'
To quote the author:
Since U-Boot's tracing feature was originally written, quite a few changes
have taken place in this domain. The original text format used by tracing
is still emitted by Linux, but a new trace-cmd tool has invented a binary
format which is now used by new tools, such as kernelshark.
With recent distributions and the move to Python 3, the old pybootchart
tool does not build or run. Unfortunately there is no 1:1 replacement for
the features that were provided by pybootchart, or at least it is not
obvious. Still, it makes sense to keep with the times.
This series updates proftool to use the new binary format, adding support
for function and funcgraph tracing, so that U-Boot's trace records can be
examined by trace-cmd and kernelshark.
This series also adds support for a flamegraph, which provides a visual
way to see which functions are called a lot, as well as which ones consume
the most time.
Some minor updates to the trace implementation within U-Boot are included,
to provide a little more information and to fix a few problems.
No unit tests are provided by proftool, but a functional test ensures that
sandbox can emit traces which can be processed by proftool, then parsed by
trace-cmd and that the timing of the various formats looks consistent.
Tom Rini [Tue, 7 Feb 2023 17:32:19 +0000 (12:32 -0500)]
CI, Docker: Update to Jammy 2023016 tag
Move to the latest tag for "Jammy" and rebuild the containers.
Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Sun, 15 Jan 2023 21:16:01 +0000 (14:16 -0700)]
trace: Update documentation
Revamp the documentation for the new features, including a description of
the new features and documentation for the trace command.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 15 Jan 2023 21:16:00 +0000 (14:16 -0700)]
trace: Add a test
Add a test which runs sandbox, collects a trace and makes sure it can
be processed by trace-cmd. This should ensure that this feature continues
to work as U-Boot and trace-cmd evolve.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sun, 15 Jan 2023 21:15:59 +0000 (14:15 -0700)]
Docker: Support trace-cmd
Build trace-cmd as part of the docker image, so that trace tests can be
used. Unfortunately the version provided by distributions is a little old
and has bugs. It also does not support specifying the time base for the
trace, which is required to convert microseconds to nanaseconds.
Signed-off-by: Simon Glass <sjg@chromium.org>