Simon Glass [Sun, 6 Sep 2020 16:35:31 +0000 (10:35 -0600)]
x86: Use multiple images
We already use binman's 'multiple-images' feature with Chrome OS and we
want to use it for Edison. There is no real down-side.
Adjust x86 to always use multiple-images.
Signed-off-by: Simon Glass <sjg@chromium.org>
Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Simon Glass [Wed, 23 Sep 2020 03:16:40 +0000 (21:16 -0600)]
x86: video: Show information about each video device
At present the 'bdinfo' command shows the framebuffer address, but not the
address of the copy framebuffer, if present. Add support for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 20:54:51 +0000 (14:54 -0600)]
x86: Add support for more than 8 MTRRs
At present the mtrr command only support 8 MTRRs. Some SoCs have more than
that. Update the implementation to support up to 10. Read the number of
MTRRs dynamically instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 20:54:50 +0000 (14:54 -0600)]
x86: Allow showing details about a HOB entry
Some HOBs include information that can be decoded. Add a -v option to the
hob command, to allow this to be displayed. Add the ability to decode a
resource descriptor.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 20:54:49 +0000 (14:54 -0600)]
x86: hob: Try to show a name instead of a GUID
GUIDs are one of the seven evils of the computer world. They obfuscate the
meaning and require people to look up long hex strings to decode it.
Luckily only a miniscule fraction of the 10^38 possible GUIDs are in use.
Add a way to decode the GUIDs known to U-Boot. Add a few more to the list
for good measure.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 20:54:48 +0000 (14:54 -0600)]
x86: hob: Add way to show a single hob entry
The 'hob' command currently lists all HOB entries. Add way to list a
single entry, by index.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:44 +0000 (12:45 -0600)]
acpi: Use I2cSerialBusV2() instead of I2cSerialBus()
Use the correct name of the ACPI structure being created.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:43 +0000 (12:45 -0600)]
acpi: Add more documentation for struct acpi_gpio
Add some documentation provided by Andy Shevchenko to describe how to
use struct acpi_gpio.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:42 +0000 (12:45 -0600)]
x86: coral: Update config and device tree for ACPI
Enable new features and provide require device-tree config so that U-Boot
produces the correct ACPI tables on Coral.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:41 +0000 (12:45 -0600)]
x86: Move include of bitops out of ACPI region
At present linux/bitops.h is included in ACPI code. This is not needed and
can cause a problem in fls64.h since BITS_PER_LONG is not defined. Move
the #include into the part not used by ACPI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:40 +0000 (12:45 -0600)]
x86: Add a way to add to the e820 memory table
Some boards want to reserve extra regions of memory. Add a 'chosen'
property to support this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:39 +0000 (12:45 -0600)]
acpi: Use defines for field lengths
A few fields have an open-coded length. Use the defines for this purpose
instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:38 +0000 (12:45 -0600)]
x86: fsp: Show FSP-S or FSP-M address in fsp_get_header()
At present this function only supports FSP-M but it is also used to read
FSP-S, in which case FSP-M may be zero. Add support for showing whichever
address is present in the FSP binary.
Also change the debug() statements to log_debug() while here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:37 +0000 (12:45 -0600)]
x86: fsp: Add more debugging for silicon init
If locating the FSP header hangs for whatever reason it is useful to see
where it got stuck. Add a debug print. Also show the address of the FSP-S
entry point as a sanity check.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:36 +0000 (12:45 -0600)]
x86: apl: Check low-level init in FSP-S pre-init
If U-Boot is not running FSP-S it should not do the pre-init either. Add a
condition to handle this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:35 +0000 (12:45 -0600)]
x86: coral: Add audio descriptor files
Add files describing the various audio configurations supported on coral.
These are passed to Linux in the ACPI tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:34 +0000 (12:45 -0600)]
x86: acpi: Set the log category for x86 table generation
This file doesn't currently have a log category. Add one so that items
are logged correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:33 +0000 (12:45 -0600)]
acpi: tpm: Add a TPM1 table
This provides information about a v1 TPM in the system. Generate this
table if the TPM is present.
Add a required new bloblist type and correct the header order of one
header file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:32 +0000 (12:45 -0600)]
acpi: tpm: Add a TPM2 table
This provides information about a v2 TPM in the system. Generate this
table if the TPM is present.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:31 +0000 (12:45 -0600)]
x86: Correct handling of MADT table CPUs
At present if hyperthreading is disabled the CPU numbering is not
sequential. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:30 +0000 (12:45 -0600)]
x86: Add a header guard to asm/acpi_table.h
This file cannot currently be included in ASL files. Add a header guard
to permit this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:29 +0000 (12:45 -0600)]
x86: Correct the assembly guard in e820.h
This is currently in the wrong place, so including the file in the device
tree fails. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:28 +0000 (12:45 -0600)]
x86: Notify the FSP of the 'end firmware' event
Send this notification when U-Boot is about to boot into Linux, as
requested by the FSP.
Currently this causes a crash with the APL FSP, so leave it disabled for
now.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:27 +0000 (12:45 -0600)]
x86: Sort the MTRR table
At present the MTRR registers are programmed with the list the U-Boot
builds up in the same order. In some cases this list may be out of order.
It looks better in Linux to have the registers in order, so sort them,
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:26 +0000 (12:45 -0600)]
x86: cpu: Report address width from cpu_get_info()
Add support for this new field in the common code used by most x86 CPU
drivers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:25 +0000 (12:45 -0600)]
x86: fsp: Update the FSP API with the end-firmware method
This new method is intended to be called when UEFI shuts down the 'boot
services', i.e. any lingering code in the boot loader that might be used
by the OS.
Add a definition for this new method and update the comments a little.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:45:24 +0000 (12:45 -0600)]
tpm: cr50: Add ACPI support
Generate ACPI information for this device so that Linux can use it
correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:23 +0000 (12:45 -0600)]
x86: apl: Drop unnecessary code in PMC driver
We don't have CONFIG_PCI in TPL but it is present in SPL, etc. So this
code is not needed. Drop it, and fix a code-style nit just above.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:22 +0000 (12:45 -0600)]
x86: apl: Generate ACPI table for LPC
Add an ACPI table for the LPC on Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:21 +0000 (12:45 -0600)]
x86: apl: Generate CPU tables
Add ACPI generation to the APL CPU driver.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:20 +0000 (12:45 -0600)]
x86: apl: Add support for hostbridge ACPI generation
Support generating a DMAR table and add a few helper routines as well.
Also set up NHLT so that audio works.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:19 +0000 (12:45 -0600)]
x86: apl: Generate required ACPI tables
Add support for generating various ACPI tables for Apollo Lake. Add a few
S3 definitions that are needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:18 +0000 (12:45 -0600)]
p2sb: Add some definitions used for ACPI
Allow this header to be included in ASL files by adding a header guard and
a few definitions that are needed.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:17 +0000 (12:45 -0600)]
x86: apl: Allow reading hostbridge base addresses
Add a few functions to permit reading of various useful base addresses
provided by the hostbridge.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:16 +0000 (12:45 -0600)]
x86: acpi: Add support for additional Intel tables
Apollo Lake needs to generate a few more table types used on Intel SoCs.
Add support for these into the x86 ACPI code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:15 +0000 (12:45 -0600)]
x86: Support Atom SoCs using SWSMISCI rather than the SWSCI
Some Atom SoCs use SWSMISCI for SMI control. Add a Kconfig to select this.
It is used on Apollo Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:14 +0000 (12:45 -0600)]
x86: acpi: Add common Intel ACPI tables
Add various tables that are common to Intel CPUs. These functions can be
used by arch-specific CPU code.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:13 +0000 (12:45 -0600)]
acpi: Add more support for generating processor tables
This adds tables relating to P-States and C-States.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:12 +0000 (12:45 -0600)]
x86: acpi: Add PCT and PTC tables
These are needed for the CPU tables. Add them into an x86-specific file
since we do not support them on sandbox, or include tests.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:11 +0000 (12:45 -0600)]
acpi: Add support for generating processor tables
ACPI has a number of CPU-related tables. Add utility functions to write
out the basic packages.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:10 +0000 (12:45 -0600)]
x86: acpi: Support generation of the DBG2 table
Add an implementation of the DBG2 (Debug Port Table 2) ACPI table.
Adjust one of the header includes to be in the correct order, before
adding more.
Note that the DBG2 table is generic but the PCI UART is x86-specific at
present since it assumes an ns16550 UART. It can be generalised later
if necessary.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:09 +0000 (12:45 -0600)]
x86: acpi: Support generation of the HPET table
Add an implementation of the HPET (High Precision Event Timer) ACPI
table. Since this is x86-specific, put it in an x86-specific file
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:08 +0000 (12:45 -0600)]
x86: Add a few common Intel CPU functions
Add functions to query CPU information, needed for ACPI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:07 +0000 (12:45 -0600)]
x86: apl: Update iomap for ACPI
Add some more definitions to the iomap. These will be used by
ACPI-generation code as well as the device tree.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:06 +0000 (12:45 -0600)]
x86: apl: Add power-management definitions
Add SCI and power-state definitions required by ACPI tables. Fix the
license to match the original source file.
Als update the guard on acpi_pmc.h to avoid an error when buiding ASL.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:05 +0000 (12:45 -0600)]
x86: Add some definitions for SMM
U-Boot does not support SMM (System Management Mode) at present, but needs
a few definitions to correctly set up the ACPI table. Add these.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:04 +0000 (12:45 -0600)]
x86: acpi: Add a common routine to write WiFi info
Intel WiFi chips can use a common routine to write the information needed
by linux. Add an implementation of this.
Enable it for coral.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:03 +0000 (12:45 -0600)]
x86: apl: Support writing the IntelGraphicsMem table
This table is needed by the Linux graphics driver to handle graphics
correctly. Write it to ACPI.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:02 +0000 (12:45 -0600)]
x86: Add wake sources for the acpi_gpe driver
Some devices can wake the system from sleep, e.g opening the lid on a
clamshell or moving a USB mouse.
Add a wake to specify this for USB devices and add the settings for Apollo
Lake.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:45:01 +0000 (12:45 -0600)]
i2c: Add a generic driver to generate ACPI info
Many I2C devices produce roughly the same ACPI data with just things like
the GPIO/interrupt information being different.
This can be handled by a generic driver along with some information in the
device tree.
Add a generic i2c driver for this purpose.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Heiko Schocher <hs@denx.de>
Simon Glass [Tue, 22 Sep 2020 18:45:00 +0000 (12:45 -0600)]
x86: link: Allow more space for U-Boot
The extra ACPI code increases U-Boot above it current size limit. Move
the start earlier to provide space.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:44:59 +0000 (12:44 -0600)]
dm: acpi: Use correct GPIO polarity type in acpi_dp_add_gpio()
This function currently accepts the IRQ-polarity type. Fix it to use the
GPIO type instead.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:58 +0000 (12:44 -0600)]
acpi: Support generating a multi-function _DSM for devices
Add a function to generate ACPI code for a _DSM method for a device.
This includes functions for starting and ending each part of the _DSM.
Signed-off-by: Simon Glass <sjg@chromium.org>
[bmeng: fix the "new blank line at EOF" git warning]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:44:57 +0000 (12:44 -0600)]
acpi: Add support for conditions and return values
Add functions to support generating ACPI code for condition checks and
return values.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:56 +0000 (12:44 -0600)]
acpi: Add support for writing a _PRW
A 'Power Resource for Wake' list the resources a device depends on for
wake. Add a function to generate this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:55 +0000 (12:44 -0600)]
x86: coral: Add ACPI tables for coral
This device has a large set of ACPI tables. Bring these in from coreboot
so that full functionality is available (apart from SMI).
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:54 +0000 (12:44 -0600)]
x86: acpi: Expand the GNVS
Expand this to 4KB so that it is possible to add custom information to it.
On Chromebooks this is used to pass verified-boot information.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:53 +0000 (12:44 -0600)]
x86: acpi: Support external GNVS tables
At present U-Boot puts a magic number in the ASL for the GNVS table and
searches for it later.
Add a Kconfig option to use a different approach, where the ASL files
declare the table as an external symbol. U-Boot can then put it wherever
it likes, without any magic numbers or searching.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:52 +0000 (12:44 -0600)]
x86: Add a common global NVS structure
Add the definition of this structure common to Intel devices. It includes
some optional Chrome OS pieces which are used when vboot is integrated.
Drop the APL version as it is basically the same.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:51 +0000 (12:44 -0600)]
x86: Add a config for the systemagent PCIEX regions size
Add a way to specify the required size for this region. This is used when
generating ACPI tables.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:50 +0000 (12:44 -0600)]
x86: apl: Correct PCIE_ECAM_BASE
This value is incorrect and causes problems booting Linux. Fix it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Tue, 22 Sep 2020 18:44:49 +0000 (12:44 -0600)]
x86: acpi: Add DPTF asl files
Add common DPTF (Intel Dynamic Performance and Thermal Framework) files,
taken from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:48 +0000 (12:44 -0600)]
x86: acpi: apl: Add asl files for Apollo Lake
Add Apollo Lake ASL files, taken from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Tue, 22 Sep 2020 18:44:47 +0000 (12:44 -0600)]
x86: acpi: Add base asl files for common x86 devices
Add common x86 ASL files, taken from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Simon Glass [Tue, 22 Sep 2020 18:44:46 +0000 (12:44 -0600)]
x86: acpi: Add cros_ec tables
Add ASL files for the Chrome OS EC, taken from coreboot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Sat, 5 Sep 2020 20:50:53 +0000 (14:50 -0600)]
cros: Add information about booting Chrome OS on x86
Recent versions of Chrome OS do not have a kernel in the root disk, to
save space.
With the improvements to the 'zboot' command it is fairly easy to load
the kernel from the raw partition. Add instructions on how to do this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:52 +0000 (14:50 -0600)]
cros: Update chromium documentation
A few things have changed since this was written about 18 months ago.
Update the README.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:51 +0000 (14:50 -0600)]
x86: zboot: Allow overriding the command line
When booting Chrome OS images the command line is stored separately
from the kernel. Add a way to specify this address so that images boot
correctly.
Also add comments to the zimage.h header.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 8 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:50 +0000 (14:50 -0600)]
x86: zboot: Add an option to dump the setup information
There is a lot of information in the setup block and it is quite hard to
decode manually. Add a 'zboot dump' command to decode it into a
human-readable format.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:49 +0000 (14:50 -0600)]
x86: zboot: Allow setting a separate setup base address
At present the setup block is always obtained from the image
automatically. In some cases it can be useful to use a setup block
obtained elsewhere, e.g. if the image has already been unpacked. Add an
argument to support this and update the logic to use it if provided.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust maxargs to 7 for 'zboot start']
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:48 +0000 (14:50 -0600)]
x86: zboot: Set environment variables for image locations
At present it is not possible to tell from a script where the setup block
is, or where the image was loaded to. Add environment variables for this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:47 +0000 (14:50 -0600)]
x86: zboot: Add an 'setup' subcommand
Add a subcommand that sets up the kernel ready for execution.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:46 +0000 (14:50 -0600)]
x86: zboot: Add an 'load' subcommand
Add a subcommand that loads the kernel into the right places in memory.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: adjust ZBOOT_STATE_INFO value to match the command order]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:45 +0000 (14:50 -0600)]
x86: zboot: Add an 'info' subcommand
Add a little subcommand that prints out where the kernel was loaded and
its setup pointer. Run it by default in the normal boot.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:44 +0000 (14:50 -0600)]
x86: zboot: Add a 'go' subcommand
Split out the code that actually boots linux into a separate sub-command.
Add base_ptr to the state to support this.
Show an error if the boot fails, since this should not happen.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:43 +0000 (14:50 -0600)]
x86: zboot: Set up a sub-command structure
Add subcommands to zboot. At present there is only one called 'start'
which does the whole boot. It is the default command so is optional.
Change the 's' string variable to const while we are here.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: reduce maxargs to 6 of 'zboot start' subcommand]
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:42 +0000 (14:50 -0600)]
x86: zimage: Disable interrupts just before booting
At present if an error occurs while setting up the boot, interrupts are
left disabled. Move this call later in the sequence to avoid this problem.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:41 +0000 (14:50 -0600)]
x86: zboot: Correct image type
At present U-Boot sets a loader type of 8 which means LILO version 8,
according to the spec. Update it to 0x80, which means U-Boot with no
particular version.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:40 +0000 (14:50 -0600)]
x86: zboot: Move kernel-version code into a function
To help reduce the size and complexity of load_zimage(), move the code
that reads the kernel version into a separate function. Update
get_boot_protocol() to allow printing the 'Magic signature' message only
once, under control of its callers.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:39 +0000 (14:50 -0600)]
x86: zimage: Avoid using #ifdef
Use IS_ENABLED() instead of #ifdef in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:38 +0000 (14:50 -0600)]
x86: zimage: Use a state struct to hold the state
At present the 'zboot' command does everything in one go. It would be
better if it supported sub-commands like bootm, so it is possible to
examine what will be booted before actually booting it.
In preparation for this, move the 'state' of the command into a struct.
This will allow it to be shared among multiple functions in this file.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Sat, 5 Sep 2020 20:50:37 +0000 (14:50 -0600)]
x86: Update the bootparam header
This header is missing a few of the newer features from the specification.
Add these as well as a link to the spec. Also use the BIT() macros where
appropriate.
Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Tom Rini [Thu, 24 Sep 2020 12:30:25 +0000 (08:30 -0400)]
Merge branch 'mpc85xx-for-v2021.01' into next
- Add DM_SPI, DM_SPI_FLASH support for powerpc platforms
- Add DM_ETH support on P1010RDB, P1020RDB, P2020RDB
- Remove some un-maintained powerpc platforms
- Add USB_STORAGE support in config
Ran Wang [Tue, 30 Jun 2020 05:08:34 +0000 (13:08 +0800)]
configs: powerpc: add usb (host) mass storage support
commit
0cfccb54014b ("configs: Resync with savedefconfig")
removed CONFIG_USB_STORAGE from some powerpc platforms' defconfig
files, whicih would block the use case of system loading rootfs
from USB drives, add them back.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com>
Reviewed-by: Tom Rini <trini@konsulko.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:45 +0000 (11:56 +0530)]
configs: Remove P5040DS secure boot configs
Remove NXP powerpc P5040DS secure boot configs as they are
no longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:44 +0000 (11:56 +0530)]
board/freescale: Remove P5020DS board support
Remove NXP powerpc P5020DS board support as it is no
longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:43 +0000 (11:56 +0530)]
powerpc:Remove P4080DS secure boot configs
Remove NXP powerpc P4080DS secure boot configs as they are
no longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:42 +0000 (11:56 +0530)]
configs: Remove P3041DS secure boot configs
Remove NXP powerpc P3041DS secure boot configs as they are
no longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:41 +0000 (11:56 +0530)]
board/freescale: Remove P1024RDB board support
Remove NXP powerpc P1024RDB board support as it is no
longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 10:06:25 +0000 (15:36 +0530)]
board/freescale: Remove P1021RDB board support
Remove NXP powerpc P1021RDB board support as it is no
longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:39 +0000 (11:56 +0530)]
board/freescale: Remove P1020MBG board support
Remove NXP powerpc P1020MBG board support as it is no
longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:38 +0000 (11:56 +0530)]
board/freescale: Remove P1020UTM board support
Remove NXP powerpc P1020UTM board support as it is no
longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 10:05:16 +0000 (15:35 +0530)]
board/freescale: Remove P1025RDB board support
Remove NXP powerpc P1025RDB board support as it is no
longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:36 +0000 (11:56 +0530)]
configs: Remove P1010RDB secure boot configs
Remove NXP powerpc P1010RDB secure boot configs as they are
no longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Priyanka Jain [Mon, 21 Sep 2020 06:26:35 +0000 (11:56 +0530)]
board/freescale: Remove p1023rdb board support
Remove NXP powerpc p1023rdb board support as it is no
longer maintained.
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Hou Zhiqiang [Thu, 16 Jul 2020 10:09:25 +0000 (18:09 +0800)]
configs: P2020RDB: Enable DM_ETH config
Enable the DM_ETH and DM_MDIO config.
On P2020RDB, the eTSEC1 is connecting with a switch VSC7385,
so also enable the fixed PHY support.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Hou Zhiqiang [Mon, 21 Sep 2020 09:46:23 +0000 (15:16 +0530)]
dts: powerpc: p2020rdb: Add eTSEC DT nodes
P2020RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII switch VSC7385
eTSEC2: Connected to SGMII PHY VSC8221
eTSEC3: Connected to SGMII PHY AR8021
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Hou Zhiqiang [Thu, 16 Jul 2020 10:09:23 +0000 (18:09 +0800)]
configs: P1010RDB: Enable DM_ETH config
Enable the DM_ETH and DM_MDIO config.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Hou Zhiqiang [Mon, 21 Sep 2020 09:45:04 +0000 (15:15 +0530)]
p1010rdb: Don't compile board_eth_init() for DM_ETH
The board_eth_init() is only used by legacy ethernet driver framework,
so do not compile it when DM_ETH config has been selected.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Hou Zhiqiang [Mon, 21 Sep 2020 09:43:22 +0000 (15:13 +0530)]
dts: powerpc: p1010rdb: Add eTSEC DT nodes
P1010RDB implements 3 enhanced three-speed Ethernet controllers,
and the connection is shown below:
eTSEC1: Connected to RGMII PHY AR8033
eTSEC2: Connected to SGMII PHY AR8033
eTSEC3: Connected to SGMII PHY AR8033
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Rebased]
Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
projects / platform / kernel / u-boot.git / log