Konstantin Seurer [Tue, 15 Aug 2023 12:55:10 +0000 (14:55 +0200)]
aco/spill: Make sure that offset stays in bounds
If a shader spills a lot, the offset can be above the HW limit.
cc: mesa-stable
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24652>
Rob Clark [Thu, 21 Sep 2023 21:27:44 +0000 (14:27 -0700)]
freedreno/fence: Hold a strong ref to batch
We don't want a unflushed fence to outlive it's batch, otherwise we run
into trouble when it comes time to wait on the fence. For ex:
1. Create a fence before framebuffer state is set, with the
PIPE_FLUSH_DEFERRED flags. This creates a new batch, to which the
ctx holds the only reference (unless the fence also holds a ref)
2. set_framebuffer_state() creates a new batch and drops the ctx->batch
reference.
3. Later something tries to wait on the fence
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8621
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25337>
Rob Clark [Thu, 21 Sep 2023 21:27:09 +0000 (14:27 -0700)]
freedreno: Add reformatting commits to .git-blame-ignore-revs
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25337>
Timothy Arceri [Thu, 21 Sep 2023 06:55:49 +0000 (16:55 +1000)]
glsl: remove unused validate_first_and_last_interface_explicit_locations()
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Timothy Arceri [Thu, 21 Sep 2023 06:50:21 +0000 (16:50 +1000)]
glsl: switch to nir validate_first_and_last_interface_explicit_locations()
Use the new nir version. The glsl ir version will be removed in the
following patch.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Timothy Arceri [Wed, 13 Sep 2023 02:23:11 +0000 (12:23 +1000)]
glsl: add nir version of validate_first_and_last_interface_explicit_locations()
The glsl ir version will be removed in a following commit.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Timothy Arceri [Thu, 21 Sep 2023 06:48:22 +0000 (16:48 +1000)]
glsl: move get_varying_type() declaration earlier
Required for the following patch to keep this file somewhat organised.
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25318>
Jordan Justen [Tue, 28 Jun 2022 21:31:11 +0000 (14:31 -0700)]
intel/isl: Build for Xe2
This is only *build* support in isl for Xe2. Before adding LNL PCI
IDs, subsequent patches will fill in ISL updates for Xe2.
Rework:
* Rohan: Update isl_genX_declare_get_func
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
Jordan Justen [Tue, 28 Jun 2022 19:04:51 +0000 (12:04 -0700)]
intel/genxml: Build with gen20.xml
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Sagar Ghuge <sagar.ghuge@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25253>
Martin Roukala (né Peres) [Thu, 21 Sep 2023 10:32:39 +0000 (13:32 +0300)]
radv/ci: add more tests to the navi10 vkcts flake list
Since I had to aggregate the results of a lot of run, this commit also
ends up ordering some of the flakes to fit the alphabetical order.
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>
Martin Roukala (né Peres) [Mon, 18 Sep 2023 13:23:52 +0000 (16:23 +0300)]
radv/ci: move vkcts-navi10 testing to KWS
We now have 2 more navi10 DUTs at KWS, so let's use them to speed
up vkcts testing!
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25324>
Ian Romanick [Mon, 5 Dec 2022 22:18:33 +0000 (14:18 -0800)]
nir/rematerialize: Rematerialize ALUs used only by compares with zero
This was 4th on the list of things to try in
3ee2e84c608 ("nir:
Rematerialize compare instructions"). This is implemented as a separate
subpass that tries to find ALU instructions (with restrictions) that are
only used by comparisons with zero that are in turn only used as
conditions for bcsel or if-statements.
There are two restrictions implemented. One of the sources must be a
constant. This is done in an attempt to prevent increasing register
pressure. Additionally, the opcode of the instruction must be one that
has a high probablility of getting a conditional modifier on Intel
GPUs. Not all instructions can have a conditional modifiers (e.g., min
and max), so I don't think there is any benefit to moving these
instructions.
v2: Rebase on many, many recent NIR infrastructure changes.
v3: Make data in commit message more clear. Suggested by Matt. Rebase on
b5d6b7c402a ("nir: Drop most uses if nir_instr_rewrite_src()").
All of the affected shaders on ILK and G45 are in CS:GO. There is some
brief analysis of the changes in the MR.
Reviewed-by: Matt Tuner <mattst88@gmail.com>
Shader-db results:
DG2
total instructions in shared programs:
22824637 ->
22824258 (<.01%)
instructions in affected programs: 365742 -> 365363 (-0.10%)
helped: 190 / HURT: 97
total cycles in shared programs:
832186193 ->
832157290 (<.01%)
cycles in affected programs:
41245259 ->
41216356 (-0.07%)
helped: 208 / HURT: 117
total spills in shared programs: 4072 -> 4060 (-0.29%)
spills in affected programs: 366 -> 354 (-3.28%)
helped: 4 / HURT: 2
total fills in shared programs: 3601 -> 3607 (0.17%)
fills in affected programs: 708 -> 714 (0.85%)
helped: 4 / HURT: 2
LOST: 0
GAINED: 1
Tiger Lake and Ice Lake had similar results. (Ice Lake shown)
total instructions in shared programs:
20320934 ->
20320689 (<.01%)
instructions in affected programs: 236592 -> 236347 (-0.10%)
helped: 176 / HURT: 29
total cycles in shared programs:
849846341 ->
849843856 (<.01%)
cycles in affected programs:
41277336 ->
41274851 (<.01%)
helped: 195 / HURT: 110
LOST: 0
GAINED: 1
Skylake
total instructions in shared programs:
18550811 ->
18550470 (<.01%)
instructions in affected programs: 233908 -> 233567 (-0.15%)
helped: 182 / HURT: 25
total cycles in shared programs:
835910983 ->
835889167 (<.01%)
cycles in affected programs:
38764359 ->
38742543 (-0.06%)
helped: 207/ HURT: 94
total spills in shared programs: 4522 -> 4506 (-0.35%)
spills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0
total fills in shared programs: 5296 -> 5280 (-0.30%)
fills in affected programs: 324 -> 308 (-4.94%)
helped: 4 / HURT: 0
LOST: 0
GAINED: 1
Broadwell
total instructions in shared programs:
18199130 ->
18197920 (<.01%)
instructions in affected programs: 214664 -> 213454 (-0.56%)
helped: 191 / HURT: 0
total cycles in shared programs:
935131908 ->
934870248 (-0.03%)
cycles in affected programs:
75770568 ->
75508908 (-0.35%)
helped: 203 / HURT: 84
total spills in shared programs: 13896 -> 13734 (-1.17%)
spills in affected programs: 162 -> 0
helped: 3 / HURT: 0
total fills in shared programs: 16989 -> 16761 (-1.34%)
fills in affected programs: 228 -> 0
helped: 3 / HURT: 0
Haswell
total instructions in shared programs:
16969502 ->
16969085 (<.01%)
instructions in affected programs: 185498 -> 185081 (-0.22%)
helped: 121 / HURT: 1
total cycles in shared programs:
925290863 ->
924806827 (-0.05%)
cycles in affected programs:
30200863 ->
29716827 (-1.60%)
helped: 100 / HURT: 85
total spills in shared programs: 13565 -> 13533 (-0.24%)
spills in affected programs: 736 -> 704 (-4.35%)
helped: 8 / HURT: 0
total fills in shared programs: 15468 -> 15436 (-0.21%)
fills in affected programs: 740 -> 708 (-4.32%)
helped: 8 / HURT: 0
LOST: 0
GAINED: 1
Ivy Bridge
total instructions in shared programs:
15839127 ->
15838947 (<.01%)
instructions in affected programs: 77776 -> 77596 (-0.23%)
helped: 58 / HURT: 0
total cycles in shared programs:
459852774 ->
459739770 (-0.02%)
cycles in affected programs:
11970210 ->
11857206 (-0.94%)
helped: 79 / HURT: 53
Sandy Bridge
total instructions in shared programs:
14106847 ->
14106831 (<.01%)
instructions in affected programs: 1611 -> 1595 (-0.99%)
helped: 10 / HURT: 0
total cycles in shared programs:
775004024 ->
775007516 (<.01%)
cycles in affected programs: 2530686 -> 2534178 (0.14%)
helped: 55 / HURT: 48
Iron Lake
total cycles in shared programs:
257753356 ->
257754900 (<.01%)
cycles in affected programs: 2977374 -> 2978918 (0.05%)
helped: 12 / HURT: 106
GM45
total cycles in shared programs:
169711382 ->
169712816 (<.01%)
cycles in affected programs: 2402070 -> 2403504 (0.06%)
helped: 12 / HURT: 57
Fossil-db results:
All Intel platforms had similar results. (DG2 shown)
Totals:
Instrs:
193884596 ->
193465896 (-0.22%); split: -0.25%, +0.03%
Cycles:
14050193354 ->
14048194826 (-0.01%); split: -0.34%, +0.33%
Spill count: 114944 -> 100449 (-12.61%); split: -13.59%, +0.98%
Fill count: 201525 -> 179534 (-10.91%); split: -11.22%, +0.31%
Scratch Memory Size:
10028032 -> 8468480 (-15.55%)
Totals from 16912 (2.59% of 653124) affected shaders:
Instrs:
34173709 ->
33755009 (-1.23%); split: -1.41%, +0.19%
Cycles:
2945969110 ->
2943970582 (-0.07%); split: -1.62%, +1.55%
Spill count: 97753 -> 83258 (-14.83%); split: -15.98%, +1.15%
Fill count: 176355 -> 154364 (-12.47%); split: -12.82%, +0.35%
Scratch Memory Size: 8619008 -> 7059456 (-18.09%)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20176>
Pierre-Eric Pelloux-Prayer [Thu, 21 Sep 2023 07:42:53 +0000 (09:42 +0200)]
radeonsi: emit framebuffer state after allocating cmask
tex->cmask_base_address_reg and tex->cb_color_info are used in
si_emit_framebuffer_state so we have to re-emit the state when
they're modified.
It's not done in si_alloc_separate_cmask because it cannot
update framebuffer.dirty_cbufs.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9830
Cc: mesa-stable
Reviewed-by: Yogesh Mohan Marimuthu <yogesh.mohanmarimuthu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25317>
Emma Anholt [Wed, 20 Sep 2023 18:40:17 +0000 (11:40 -0700)]
ci/fastboot: Use a case insensitive match for a fastboot line.
Newer boards like the RB5 have a capital F, so this will make the script
more reusable for drm ci.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25311>
David Rosca [Tue, 19 Sep 2023 09:00:12 +0000 (11:00 +0200)]
radeonsi/vcn: Implement destroy_fence vfunc
Now that fences are correctly cleaned up in frontend, we can store
the fence reference in picture->fence again.
The encoder also needs to implement this vfunc because if a surface
from decoder is used directly as encode input it's now up to encoder
to destroy the fence.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9834
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
David Rosca [Tue, 19 Sep 2023 08:53:21 +0000 (10:53 +0200)]
frontends/va: Destroy fences when destroying surface or context
It is valid to destroy VASurface after destroying VAContext, so we need
to destroy fences of all surfaces that are currently being tracked by a
context when deleting this context.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
David Rosca [Tue, 19 Sep 2023 08:51:10 +0000 (10:51 +0200)]
frontends/va: Track surfaces in context
This will be needed to correctly cleanup fences.
Reviewed-by: Sil Vilerino <sivileri@microsoft.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25296>
Roman Stratiienko [Sat, 9 Sep 2023 10:57:29 +0000 (13:57 +0300)]
u_gralloc: Add a function that returns gralloc type
This is needed by some drivers to reject the fallback gralloc.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Roman Stratiienko [Wed, 20 Sep 2023 21:06:15 +0000 (00:06 +0300)]
Revert "util: Add NONNULL macro"
We agreed in [1] not to use it since it has little value,
but making a code less readable.
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256
This reverts commit
21dcde096f351f83a2df7aa9f42a7276b5454c81.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Roman Stratiienko [Wed, 20 Sep 2023 21:01:19 +0000 (00:01 +0300)]
u_gralloc: Remove usage of NONNULL macro
We agreed in [1] not to use it since it has little value,
but making a code less readable.
[1]: https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Roman Stratiienko [Fri, 15 Sep 2023 22:26:33 +0000 (01:26 +0300)]
u_gralloc: Remove inline modifiers from the functions
Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Chia-I Wu <olvaffe@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25256>
Eric Engestrom [Thu, 21 Sep 2023 09:25:02 +0000 (10:25 +0100)]
docs: drop outdated and redundant note about the minimum meson version
The documentation we've been keeping up to date is in `docs/meson.rst`.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25322>
Georg Lehmann [Fri, 8 Sep 2023 09:01:34 +0000 (11:01 +0200)]
aco: simplify masked swizzle dpp selection by removing or_mask first
and_mask and xor_mask alone can represent all patterns without or_mask
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25115>
Eric Engestrom [Fri, 1 Sep 2023 12:28:36 +0000 (13:28 +0100)]
ci: limit build jobs to 30min so that they can retry when they go wrong
Build jobs should never take more than 1-3 minutes.
These jobs are never slow, either they finish within reasonable time or
something has gone wrong and the job will never terminate, so we should
instead timeout and retry.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24995>
Karol Herbst [Tue, 19 Sep 2023 16:07:27 +0000 (18:07 +0200)]
rusticl/kernel: skip adding global id offsets if not used
This allows us to shrink the kernel input buffer quite significantly as
the offset is a vec aligned size_t3 value.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
Karol Herbst [Wed, 20 Sep 2023 10:46:13 +0000 (12:46 +0200)]
rusticl/mesa: fix `set_constant_buffer` when passing an empty buffer
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25303>
Jordan Justen [Thu, 13 Apr 2023 22:55:07 +0000 (15:55 -0700)]
intel/fs: Update SSBO & shared uniform block loads for Xe2
Note: lower_lsc_block_logical_send() most likely stills needs some
related updates.
Ref:
a358b97c586 ("intel/fs: optimize uniform SSBO & shared loads")
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Thu, 2 Mar 2023 00:28:29 +0000 (16:28 -0800)]
intel/compiler: Update RT stack_id access for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Sat, 18 Feb 2023 00:08:26 +0000 (16:08 -0800)]
intel/compiler: Update ray-tracing intrinsic lowering for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Wed, 1 Feb 2023 18:32:38 +0000 (10:32 -0800)]
intel/compiler: Update lower_trace_ray_logical_send() for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Wed, 1 Feb 2023 18:32:10 +0000 (10:32 -0800)]
intel/compiler: Update emit_rt_lsc_fence() for Xe2
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Tue, 19 Sep 2023 18:09:09 +0000 (11:09 -0700)]
intel/compiler: Update opt_split_sends() for Xe2 reg size
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Jordan Justen [Wed, 1 Feb 2023 00:01:26 +0000 (16:01 -0800)]
intel/compiler/fs: Support Xe2 reg size in assign_curb_setup
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 11 Jan 2023 08:20:36 +0000 (00:20 -0800)]
intel/xe2+: Round up size to reg_unit() in fs_reg_alloc::alloc_spill_reg().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Tue, 11 Oct 2022 01:05:13 +0000 (18:05 -0700)]
intel/fs/xe2+: Fix calculation of spill message width for Xe2 regs.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 29 Sep 2022 00:37:18 +0000 (17:37 -0700)]
intel/fs/xe2+: Fix execution width of SHADER_OPCODE_GET_BUFFER_SIZE for SIMD16 EU.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Fri, 30 Sep 2022 01:04:56 +0000 (18:04 -0700)]
intel/fs/xe2+: Update regioning lowering offset alignment checks for Xe2 regs.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 11 Aug 2022 00:31:58 +0000 (17:31 -0700)]
intel/fs: Lower unsupported regioning with non-trivial 2D regions on FIXED_GRFs.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Sun, 11 Sep 2022 08:01:17 +0000 (01:01 -0700)]
intel/fs/xe2+: Update TASK/MESH payload setup for Xe2 reg size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Sun, 11 Sep 2022 07:57:26 +0000 (00:57 -0700)]
intel/fs/xe2+: Update BS payload setup for Xe2 reg size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 7 Sep 2022 21:11:05 +0000 (14:11 -0700)]
intel/fs/xe2+: Update TES payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 7 Sep 2022 21:09:04 +0000 (14:09 -0700)]
intel/fs/xe2+: Update TCS payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 8 Sep 2022 00:52:18 +0000 (17:52 -0700)]
intel/fs/xe2+: Update GS payload setup for Xe2 reg size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Fri, 2 Sep 2022 00:13:57 +0000 (17:13 -0700)]
intel/compiler/xe2: Account for reg_unit() in TES intrinsics
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Caio Oliveira [Wed, 7 Sep 2022 07:22:13 +0000 (00:22 -0700)]
intel/compiler/xe2: Account for reg_unit() in TCS intrinsics
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 24 Aug 2022 18:46:45 +0000 (11:46 -0700)]
intel/fs/xe2+: Fix payload layout of sampler messages for Xe2 reg size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Ian Romanick [Tue, 23 Aug 2022 01:00:09 +0000 (18:00 -0700)]
intel/compiler/xe2: TXD is lowered to SIMD16 in SIMD32 mode
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Ian Romanick [Tue, 23 Aug 2022 00:35:53 +0000 (17:35 -0700)]
intel/compiler/xe2: Use SIMD16 for nir_intrinsic_image_size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Ian Romanick [Mon, 1 Aug 2022 23:42:57 +0000 (16:42 -0700)]
intel/compiler/xe2: Update fs_visitor::setup_vs_payload to account for Xe2 reg size
[ Francisco Jerez: Simplify. ]
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Rohan Garg [Mon, 1 Aug 2022 14:45:30 +0000 (16:45 +0200)]
intel/compiler: Adjust barrier emission for Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 3 Aug 2022 23:51:43 +0000 (16:51 -0700)]
intel/fs/xe2+: Scale BRW_MAX_MSG_LENGTH by native register size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Rohan Garg [Fri, 22 Jul 2022 11:33:17 +0000 (13:33 +0200)]
intel/compiler: Adjust fence message lengths for new register width on Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Rohan Garg [Fri, 22 Jul 2022 11:32:08 +0000 (13:32 +0200)]
intel/compiler: Adjust CS payload registers for new register width on Xe2+
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 21 Jul 2022 18:38:03 +0000 (11:38 -0700)]
intel/fs/xe2+: Round up fs_builder::vgrf() size calculation to HW register unit.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 23 Jul 2022 00:36:26 +0000 (17:36 -0700)]
intel/fs/xe2+: Update encoding of FB write message payload.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Tue, 19 Jul 2022 23:44:26 +0000 (16:44 -0700)]
intel/compiler/xe2+: Represent dispatch_grf_start_reg in native GRF units.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 23 Jul 2022 00:30:30 +0000 (17:30 -0700)]
intel/fs/xe2+: Allow increased SIMD width for various get_fpu_lowered_simd_width() restrictions.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 16 Jul 2022 02:11:04 +0000 (19:11 -0700)]
intel/eu/xe2+: Update validation of GRF region size to account for Xe2 reg size
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 23 Jul 2022 00:28:47 +0000 (17:28 -0700)]
intel/fs/xe2+: Scale MAX_SAMPLER_MESSAGE_SIZE by native register size.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 21:43:05 +0000 (14:43 -0700)]
intel/fs/xe2+: Fixes for increased accumulator register width.
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 21:03:49 +0000 (14:03 -0700)]
intel/fs/xe2+: Fix grf_count in post-RA scheduling for updated register file size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 21:01:29 +0000 (14:01 -0700)]
intel/fs/xe2+: Fix payload node live range calculations for change in register size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 08:12:24 +0000 (01:12 -0700)]
intel/fs: Fix signedness of payload_node_count argument of calculate_payload_ranges().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Thu, 7 Jul 2022 08:00:19 +0000 (01:00 -0700)]
intel/eu/xe2+: Fix encoding of various message descriptors for change in register size.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Wed, 29 Jun 2022 00:49:38 +0000 (17:49 -0700)]
intel/fs/ra/xe2: Scale up register allocation granularity by 2x on Xe2+ platforms.
v2: Fix spill register allocation. Switch to brw_reg::nr
representation in fake 256b units.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Tue, 22 Feb 2022 05:42:05 +0000 (21:42 -0800)]
intel/compiler: Make MAX_VGRF_SIZE macro depend on devinfo and update it for Xe2.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 19 Feb 2022 06:28:58 +0000 (22:28 -0800)]
intel/vec4/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.
Rework:
* Jordan: 16=>20 following
d33aff783d9 ("intel/fs: add support for
sparse accesses")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Francisco Jerez [Sat, 19 Feb 2022 06:25:58 +0000 (22:25 -0800)]
intel/fs/ra: Define REG_CLASS_COUNT constant specifying the number of register classes.
Rework:
* Jordan: 16=>20 following
d33aff783d9 ("intel/fs: add support for
sparse accesses")
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25020>
Eric Engestrom [Wed, 20 Sep 2023 17:25:12 +0000 (18:25 +0100)]
docs: add another 23.1.x
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>
Eric Engestrom [Wed, 20 Sep 2023 17:24:06 +0000 (18:24 +0100)]
docs: update calendar for 23.1.8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>
Eric Engestrom [Wed, 20 Sep 2023 17:24:00 +0000 (18:24 +0100)]
docs: add sha256sum for 23.1.8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>
Eric Engestrom [Wed, 20 Sep 2023 17:15:21 +0000 (18:15 +0100)]
docs: add release notes for 23.1.8
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25310>
Connor Abbott [Fri, 1 Feb 2019 11:36:56 +0000 (12:36 +0100)]
amd: Use inverse ballot intrinsic if available
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>
Connor Abbott [Fri, 1 Feb 2019 10:37:50 +0000 (11:37 +0100)]
nir/spirv: Add inverse_ballot intrinsic
This is actually a no-op on AMD, so we really don't want to lower it to
something more complicated. There may be a more efficient way to do
this on Intel too. In addition, in the future we'll want to use this for
lowering boolean reduce operations, where the inverse ballot will
operate on the backend's "natural" ballot type as indicated by
options->ballot_bit_size, instead of uvec4 as produced by SPIR-V. In
total, there are now three possible lowerings we may have to perform:
- inverse_ballot with source type of uvec4 from SPIR-V to inverse_ballot
with natural source type, when the backend supports inverse_ballot
natively.
- inverse_ballot with source type of uvec4 from SPIR-V to arithmetic,
when the backend doesn't support inverse_ballot.
- inverse_ballot with natural source type from reduce operation, when
the backend doesn't support inverse_ballot.
Previously we just did the second lowering unconditionally in vtn, but
it's just a combination of the first and third. We add support here for
the first and third lowerings in nir_lower_subgroups, instead of simply
moving the second lowering, to avoid unnecessary churn.
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>
Connor Abbott [Fri, 1 Feb 2019 10:01:31 +0000 (11:01 +0100)]
nir/lower_subgroups: Don't do multiple lowerings at once
Since using nir_shader_lower_instructions(), instructions get revisited
before proceeding with the next one. This already guarantees that any
subsequent lowerings of those instructions happen during the same pass
of nir_lower_subgroups().
v2: use nir_shader_lower_instructions() instead of setting the cursor.
Co-authored-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25123>
Sviatoslav Peleshko [Wed, 20 Sep 2023 13:31:57 +0000 (16:31 +0300)]
zink: Store zink_vertex_elements_hw_state::b.strides by binding id
Currently, we store strides by vertex buffer id, which means that we have
to map the binding index to the vertex buffer index every time we want to
get a stride for a given binding. This also creates an order mismatch when
we pass strides directly to CmdBindVertexBuffers2EXT. Instead of converting
strides for CmdBindVertexBuffers2EXT too, we can just store strides by
binding id, and drop the mapping in other places.
Fixes:
76725452 ("gallium: move vertex stride to CSO")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9817
Signed-off-by: Sviatoslav Peleshko <sviatoslav.peleshko@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25305>
Konstantin Seurer [Sun, 17 Sep 2023 14:35:33 +0000 (16:35 +0200)]
radv/rt: Skip cull_mask handling if it is FF
Totals from 9 (1.32% of 680) affected shaders:
Instrs: 609329 -> 609057 (-0.04%)
CodeSize: 3267328 -> 3265664 (-0.05%)
Latency: 8289582 -> 8275874 (-0.17%)
InvThroughput: 2166498 -> 2163147 (-0.15%)
VClause: 23581 -> 23583 (+0.01%)
Copies: 51076 -> 51028 (-0.09%)
Branches: 24637 -> 24603 (-0.14%)
PreVGPRs: 996 -> 986 (-1.00%)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25268>
Konstantin Seurer [Sat, 16 Sep 2023 17:35:21 +0000 (19:35 +0200)]
radv/ray_queries: Skip cull_mask handling if it is FF
Stats for Metro Exodus:
Totals from 26 (0.99% of 2627) affected shaders:
Instrs: 14586 -> 14232 (-2.43%)
CodeSize: 77024 -> 75192 (-2.38%)
VGPRs: 1408 -> 1208 (-14.20%)
Latency: 315076 -> 309898 (-1.64%)
InvThroughput: 42345 -> 41677 (-1.58%)
VClause: 366 -> 374 (+2.19%)
Copies: 2840 -> 2800 (-1.41%); split: -1.48%, +0.07%
Branches: 587 -> 561 (-4.43%)
PreSGPRs: 897 -> 853 (-4.91%)
PreVGPRs: 1290 -> 1122 (-13.02%)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25268>
Konstantin Seurer [Sat, 16 Sep 2023 14:35:00 +0000 (16:35 +0200)]
radv/bvh: Treat instances with mask == 0 as inactive
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25268>
Tapani Pälli [Tue, 19 Sep 2023 06:35:16 +0000 (09:35 +0300)]
anv: refactor to fix pipe control debugging
While earlier changes to pipe control emission allowed debug dump of
each pipe control, they also changed debug output to almost always print
same reason/function for each pc. These changes fix the output so that
we print the original function name where pc is emitted.
As example:
pc: emit PC=( +depth_flush +rt_flush +pb_stall +depth_stall ) reason: gfx11_batch_emit_pipe_control_write
pc: emit PC=( ) reason: gfx11_batch_emit_pipe_control_write
changes back to:
pc: emit PC=( +depth_flush +rt_flush +pb_stall +depth_stall ) reason: gfx11_emit_apply_pipe_flushes
pc: emit PC=( ) reason: cmd_buffer_emit_depth_stencil
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25282>
Iago Toral Quiroga [Tue, 19 Sep 2023 12:13:25 +0000 (14:13 +0200)]
v3dv: we can sample from 1D array too
Fixes:
95f881ad ('v3dv: add support for sampling simple 2D linear textures')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25286>
Rob Clark [Tue, 19 Sep 2023 14:58:09 +0000 (07:58 -0700)]
freedreno/a6xx: Add L8_SRGB
Avoids a tragic slow-path with CS:GO
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25298>
Emma Anholt [Tue, 19 Sep 2023 19:25:37 +0000 (12:25 -0700)]
ci/zink: Add a few updates for anv/tgl from the nightly runs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25301>
Emma Anholt [Tue, 19 Sep 2023 19:15:05 +0000 (12:15 -0700)]
ci/virgl: Disable virgl-iris-traces.
It's been failing with "No virgl contexts available on hostlibEGL warning:
egl: failed to create dri2 screen" for ages, and nobody seems to care.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25301>
Emma Anholt [Tue, 19 Sep 2023 19:09:20 +0000 (12:09 -0700)]
ci/intel: Add various updates from our nightly runs.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25301>
Jose Maria Casanova Crespo [Wed, 7 Jun 2023 22:57:15 +0000 (00:57 +0200)]
vc4: mark buffers as initialized at vc4_texture_subdata
This fixes several tests when the initially uploaded buffer
from CPU was being ignored because vc4_texture_subdata was not
marking the resource as written/initialized.
The usage flags management available at vc4_resource_transfer_map
is generalized into vc4_map_usage_prep and reused at
vc4_resource_transfer_map. This makes vc4 implementation more similar
to v3d.
This fixes 7 text in the following subgroups:
-dEQP-GLES2.functional.fbo.render.texsubimage.*
-dEQP-GLES2.functional.texture.specification.basic_copytexsubimage2d.*
-spec@arb_clear_texture@arb_clear_texture-*
Cc: mesa-stable
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25297>
Paulo Zanoni [Fri, 8 Sep 2023 21:50:17 +0000 (14:50 -0700)]
iris: assert(bo->deps) after realloc()
Iris in general doesn't really like checking the return value of its
allocations, but in some places it does assert that those pointers are
non-NULL. We've recently investigated a bug that could have been
coming from a failed bo->deps realloc(), so add the assert() here to
help give us more confidence over things the next time we're debugging
issues.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25236>
Paulo Zanoni [Fri, 8 Sep 2023 21:29:51 +0000 (14:29 -0700)]
iris: avoid stack overflow in iris_bo_wait_syncobj()
Keep most cases using the stack as it's cheaper, but fall back to the
heap when the size gets too big.
This should fix a stack overflow reported by @rhezashan for a case
where we had lots of iris_screens.
Credits to Matt Turner and José Roberto de Souza for their work on
this issue, which led us to find its root cause.
Cc: mesa-stable
Reported-by: rheza shandikri (@rhezashan in gitlab)
Credits-to: José Roberto de Souza <jose.souza@intel.com>
Credits-to: Matt Turner <mattst88@gmail.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25236>
Paulo Zanoni [Fri, 8 Sep 2023 00:48:05 +0000 (17:48 -0700)]
iris: assert bufmgr->bo_deps_lock is held
This is the only place that touches bo->deps but does not explicitly
lock it and is not a setup/teardown function where locking won't help
anything.
I'm confident we won't hit this assertion, but I've recently had this
lock as the suspect of a bug and had to check the callers to see if we
could be calling from any unlocked place. Having the assert helps
increasing our confidence.
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Paulo Zanoni <paulo.r.zanoni@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25236>
Pavel Ondračka [Tue, 29 Aug 2023 06:46:17 +0000 (08:46 +0200)]
nir/move_vec_src_uses_to_dest: allow to skip reuse of constant sources
And enable this for r300 and intel-vec4
crocus HSW (mostly helps few doplhin ubershaders):
total instructions in shared programs: 1576736 -> 1576589 (<.01%)
instructions in affected programs: 38235 -> 38088 (-0.38%)
helped: 12
HURT: 0
total cycles in shared programs:
111025838 ->
110944796 (-0.07%)
cycles in affected programs: 5646582 -> 5565540 (-1.44%)
helped: 15
HURT: 6
total spills in shared programs: 447 -> 432 (-3.36%)
spills in affected programs: 186 -> 171 (-8.06%)
helped: 12
HURT: 0
total fills in shared programs: 792 -> 774 (-2.27%)
fills in affected programs: 291 -> 273 (-6.19%)
helped: 12
HURT: 0
r300 RV530:
total instructions in shared programs: 96655 -> 96304 (-0.36%)
instructions in affected programs: 15020 -> 14669 (-2.34%)
helped: 79
HURT: 18
total temps in shared programs: 13027 -> 12952 (-0.58%)
temps in affected programs: 677 -> 602 (-11.08%)
helped: 41
HURT: 9
total cycles in shared programs: 147745 -> 147314 (-0.29%)
cycles in affected programs: 21831 -> 21400 (-1.97%)
helped: 84
HURT: 19
r300 RV370:
total instructions in shared programs: 63678 -> 63669 (-0.01%)
instructions in affected programs: 931 -> 922 (-0.97%)
helped: 12
HURT: 6
total temps in shared programs: 10028 -> 10013 (-0.15%)
temps in affected programs: 339 -> 324 (-4.42%)
helped: 33
HURT: 10
total cycles in shared programs: 101118 -> 101087 (-0.03%)
cycles in affected programs: 2659 -> 2628 (-1.17%)
helped: 22
HURT: 6
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24932>
Pavel Ondračka [Tue, 29 Aug 2023 06:06:24 +0000 (08:06 +0200)]
nir/move_vec_src_uses_to_dest: skip reuse if vec is used only once in store_output
lima and etnaviv show no change in shader-db.
crocus HSW:
total instructions in shared programs: 1576762 -> 1576736 (<.01%)
instructions in affected programs: 485 -> 459 (-5.36%)
helped: 28
HURT: 1
total cycles in shared programs:
111025898 ->
111025838 (<.01%)
cycles in affected programs: 1248 -> 1188 (-4.81%)
helped: 29
HURT: 0
RV370:
total instructions in shared programs: 63889 -> 63558 (-0.52%)
instructions in affected programs: 9116 -> 8785 (-3.63%)
helped: 129
HURT: 0
total temps in shared programs: 10071 -> 10016 (-0.55%)
temps in affected programs: 285 -> 230 (-19.30%)
helped: 51
HURT: 0
total cycles in shared programs: 101344 -> 100997 (-0.34%)
cycles in affected programs: 9326 -> 8979 (-3.72%)
helped: 129
HURT: 0
RV530:
total instructions in shared programs: 93597 -> 93267 (-0.35%)
instructions in affected programs: 10309 -> 9979 (-3.20%)
helped: 166
HURT: 0
total temps in shared programs: 13019 -> 12955 (-0.49%)
temps in affected programs: 337 -> 273 (-18.99%)
helped: 61
HURT: 1
total cycles in shared programs: 144506 -> 144159 (-0.24%)
cycles in affected programs: 10662 -> 10315 (-3.25%)
helped: 165
HURT: 0
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24932>
Pavel Ondračka [Tue, 29 Aug 2023 06:03:05 +0000 (08:03 +0200)]
r300: enable nir_move_vec_src_uses_to_dest
We want to do this in general, right now the stats are not that good but
that will be taken care of in the next commits.
RV530:
total instructions in shared programs: 93561 -> 93597 (0.04%)
instructions in affected programs: 39015 -> 39051 (0.09%)
helped: 207
HURT: 212
total temps in shared programs: 12864 -> 13019 (1.20%)
temps in affected programs: 2010 -> 2165 (7.71%)
helped: 57
HURT: 181
total cycles in shared programs: 144639 -> 144506 (-0.09%)
cycles in affected programs: 54524 -> 54391 (-0.24%)
helped: 191
HURT: 234
RV370:
total instructions in shared programs: 63692 -> 63811 (0.19%)
instructions in affected programs: 16851 -> 16970 (0.71%)
helped: 121
HURT: 141
total temps in shared programs: 9966 -> 10050 (0.84%)
temps in affected programs: 969 -> 1053 (8.67%)
helped: 33
HURT: 126
total cycles in shared programs: 101042 -> 101205 (0.16%)
cycles in affected programs: 20606 -> 20769 (0.79%)
helped: 121
HURT: 155
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24932>
lorn10 [Thu, 2 Mar 2023 11:51:27 +0000 (11:51 +0000)]
docs: Update Clover's env variable documentation
Fixes:
981bc603b46c ("clover: implement CLOVER_DEVICE_TYPE like RUSTICL_DEVICE_TYPE")
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21657>
Rohan Garg [Thu, 31 Aug 2023 12:53:10 +0000 (14:53 +0200)]
anv: define clear color localy within can_fast_clear_color_att
We can drop a extra function argument this way.
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24972>
Iago Toral Quiroga [Tue, 19 Sep 2023 07:50:54 +0000 (09:50 +0200)]
v3dv: only handle Android Hardware Buffer on Android
Fixes:
733909a6 ('v3dv/android: Add AHardwareBuffer support')
Fixes the following CTS regression on Linux:
dEQP-VK.api.external.memory.android_hardware_buffer.dedicated.image.info
dEQP-VK.api.external.memory.android_hardware_buffer.suballocated.image.info
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25283>
Samuel Pitoiset [Wed, 13 Sep 2023 06:37:22 +0000 (08:37 +0200)]
radv: remove absolute_depth_bias workaround
This was only used with Path of Exile and the game bug seems fixed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25198>
Samuel Pitoiset [Wed, 13 Sep 2023 06:34:26 +0000 (08:34 +0200)]
radv: remove drirc workarounds for Path Of Exile
According to https://gitlab.freedesktop.org/mesa/mesa/-/issues/9798,
all game bugs should have been fixed.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9798
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25198>
Samuel Pitoiset [Wed, 13 Sep 2023 06:35:08 +0000 (08:35 +0200)]
drirc: remove Path of Exile workarounds
According to https://gitlab.freedesktop.org/mesa/mesa/-/issues/9798,
all game bugs should have been fixed.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25198>
Samuel Pitoiset [Fri, 15 Sep 2023 10:31:56 +0000 (12:31 +0200)]
ac/perfcounter: add GFX11 groups
Source from PAL.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25245>
Samuel Pitoiset [Fri, 15 Sep 2023 10:31:41 +0000 (12:31 +0200)]
ac/perfcounter: add SG_WQP group for GFX11
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25245>