Francisco Jerez [Thu, 19 Mar 2015 16:25:30 +0000 (18:25 +0200)]
i965/vec4: Fix broken saturate mask check in copy propagation.
try_copy_propagate() was checking the bit of the saturate mask for the
arg-th component of the source to decide whether the whole source
should be saturated (WTF?). We need to swizzle the original saturate
mask and check that for all enabled channels the saturate flag is
either set or unset, as we cannot saturate a subset of destination
components only.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Francisco Jerez [Wed, 18 Mar 2015 13:45:16 +0000 (15:45 +0200)]
i965/vec4: Don't lose copy propagation saturate bits for not written components.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Francisco Jerez [Wed, 18 Mar 2015 13:39:03 +0000 (15:39 +0200)]
Revert "i965/vec4: Don't lose the saturate modifier in copy propagation."
This reverts commit
0dfec59a2785cf7a87ee5128889ecebe810b611b. The
change prevented propagation of copies with the saturate flag set,
making the whole saturate mask tracking completely useless. A proper
fix follows.
Reviewed-by: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Francisco Jerez [Wed, 18 Mar 2015 13:40:25 +0000 (15:40 +0200)]
i965/vec4: Remove unused method definition.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 19:19:28 +0000 (21:19 +0200)]
i965/vec4: Some more trivial swizzle clean-up.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 13:27:58 +0000 (15:27 +0200)]
i965/vec4: Improve src_reg/dst_reg conversion constructors.
This simplifies the src_reg/dst_reg conversion constructors using the
swizzle utils introduced in a previous patch. It also makes them more
useful by changing their semantics slightly: dst_reg(src_reg) used to
set the writemask to XYZW if the src_reg swizzle was anything other
than XXXX, which was almost certainly not what the caller intended if
the swizzle was non-trivial. After this patch the same components
that are present in the swizzle will be enabled in the resulting
writemask.
src_reg(dst_reg) used to set the first components of the swizzle to
the enabled components of the writemask and then replicate the last
enabled component to fill the swizzle, which, in cases where the
writemask didn't have exactly the first n components set, would in
general not be compatible with the original dst_reg. E.g.:
| ADD(tmp, src_reg(tmp), src_reg(1));
would *not* do what one would expect (add one to each of the enabled
components of tmp) if tmp didn't have a writemask of the described
form (e.g. YZ, YW, XZW would all fail). This pattern actually occurs
in many different places in the VEC4 back-end, it's a wonder that it
hasn't caused piglit failures until now. After this patch
src_reg(dst_reg) will construct a swizzle with each enabled component
at its natural position (e.g. Y at the second position, Z at the
third, and so on). The resulting swizzle will behave like the
identity when used in any instruction with the original writemask.
I've manually verified that *none* of the callers of both conversion
constructors were relying on the previous broken semantics. There are
no piglit regressions on any generation.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 13:21:20 +0000 (15:21 +0200)]
i965/vec4: Pass argument by reference to src_reg/dst_reg conversion constructors.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 19:18:08 +0000 (21:18 +0200)]
i965/vec4: Remove swizzle_for_size() in favour of brw_swizzle_for_size().
It could be objected that swizzle_for_size() is "faster" than
brw_swizzle_for_size(). It's not measurably better in any reasonable
CPU-bound benchmark on VLV according to the Finnish benchmarking
system (including the SynMark2 DrvShComp shader compilation
benchmark).
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 13:26:10 +0000 (15:26 +0200)]
i965/vec4: Remove broken vector size deduction in setup_builtin_uniform_values().
This seemed to be trying to deduce the number of uniform vector
components from the parameter swizzle, but the algorithm would always
give 4 as result. Instead grab the correct number of components from
the GLSL type.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 19:15:05 +0000 (21:15 +0200)]
i965/vec4: Simplify visitor handling of swizzles using the swizzle utils.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 19:11:20 +0000 (21:11 +0200)]
i965/vec4: Simplify opt_register_coalesce() using the swizzle utils.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 19:09:51 +0000 (21:09 +0200)]
i965/vec4: Simplify reswizzle() using the swizzle utils.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 19:08:52 +0000 (21:08 +0200)]
i965/vec4: Simplify opt_reduce_swizzle() using the swizzle utils.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Thu, 19 Mar 2015 14:03:57 +0000 (16:03 +0200)]
i965: Fix signedness of backend_reg::reg_offset.
And make it 16-bit so it packs nicely with the previous field.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 13:24:06 +0000 (15:24 +0200)]
i965/vec4: Fix signedness of dst_reg::writemask.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 13:22:52 +0000 (15:22 +0200)]
i965/vec4: Don't use GL types in the IR data structures.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 12:32:37 +0000 (14:32 +0200)]
i965/vec4: Fix signedness of brw_is_single_value_swizzle() argument.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Francisco Jerez [Wed, 18 Mar 2015 12:34:51 +0000 (14:34 +0200)]
i965: Define some useful swizzle helper functions.
This defines helper functions implementing some common swizzle
transformations that are usually open-coded in the compiler back-end,
causing a lot of clutter. Some optimization passes will become almost
trivial implemented in terms of these functions (e.g.
vec4_visitor::opt_reduce_swizzle()).
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tapani Pälli [Mon, 23 Mar 2015 07:12:35 +0000 (09:12 +0200)]
glsl: fix names in lower_constant_arrays_to_uniforms
Patch changes lowering pass to use unique name for each uniform
so that arrays from different stages cannot end up having same
name.
v2: instead of global counter, use pointer to achieve
unique name (Kenneth Graunke)
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89590
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Cc: 10.5 10.4 <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Wed, 18 Mar 2015 02:57:59 +0000 (19:57 -0700)]
i965/nir: Use signed integer type for booleans
FS instructions with NIR on i965:
total instructions in shared programs: 2663561 -> 2619051 (-1.67%)
instructions in affected programs: 1612965 -> 1568455 (-2.76%)
helped: 5455
HURT: 12
FS instructions with NIR on g4x:
total instructions in shared programs: 2352633 -> 2307908 (-1.90%)
instructions in affected programs: 1441842 -> 1397117 (-3.10%)
helped: 5463
HURT: 11
FS instructions with NIR on ilk:
total instructions in shared programs: 3997305 -> 3934278 (-1.58%)
instructions in affected programs: 2189409 -> 2126382 (-2.88%)
helped: 8969
HURT: 22
FS instructions with NIR on hsw (snb and ivb were similar):
total instructions in shared programs: 4109389 -> 4109242 (-0.00%)
instructions in affected programs: 109869 -> 109722 (-0.13%)
helped: 339
HURT: 190
No SIMD16 programs were gained or lost on any platform
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Tue, 17 Mar 2015 18:49:04 +0000 (11:49 -0700)]
i965/nir: Do boolean resolves on GEN <= 5
v2: A couple comment clean-ups from Matt
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Tue, 17 Mar 2015 18:29:01 +0000 (11:29 -0700)]
i965: Add a NIR analysis pass for determining when a boolean resolve is needed
v2: Fix the spelling of analyze and re-arrange code for better readability
as per Connor's comments.
v3: Make the naming of things more consistent and add a pile of comments
v4: Stop trying to avoid vectors
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Tue, 17 Mar 2015 20:43:10 +0000 (13:43 -0700)]
i965/nir: Properly set the predicate on the SEL used in min/max
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Tue, 17 Mar 2015 20:10:19 +0000 (13:10 -0700)]
i965/nir: Use NIR lowering for ffma for gen < 6
Reviewed-by: Matt Turner <mattst88@gmail.com>
Jason Ekstrand [Tue, 17 Mar 2015 18:37:09 +0000 (11:37 -0700)]
i965/nir: Use emit_lrp for emitting flrp
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jason Ekstrand [Tue, 17 Mar 2015 18:36:10 +0000 (11:36 -0700)]
i965/fs: Make emit_lrp return an fs_inst
Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Dave Airlie [Sun, 22 Mar 2015 23:54:52 +0000 (09:54 +1000)]
i965: define I915_PARAM_REVISION
we are broken against the libdrm 2.4.60 minimum specified,
so fix it for now.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Jose Fonseca [Fri, 20 Mar 2015 12:02:42 +0000 (12:02 +0000)]
gallivm: Silence unused variable warnings on release builds.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Fri, 20 Mar 2015 12:01:23 +0000 (12:01 +0000)]
scons: Silence conversion from 'size_t' to 'type', possible loss of data on MSVC.
Most cases seem harmless, though that might not always be the case. Maybe
one day we can get gcc to complain about these and fix them throughout
the code, but until then let's silence them.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Fri, 20 Mar 2015 06:53:09 +0000 (06:53 +0000)]
scons: Ensure inttypes.h is always pre-included on MSVC.
It's a bit hackish couldn't find another solution. See code comment
for details. The warning is useful, so universally disabling doesn't
sound a good idea.
Fixes
warning C4005: 'xxx' : macro redefinition
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 22:22:26 +0000 (22:22 +0000)]
scons: Silence MSVC C4351 warning.
It warns about change in MSVC behavior -- array initialisation used to
be non-standard, but is standard now, assuming I understand correctly
http://en.cppreference.com/w/cpp/language/zero_initialization .
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 22:09:20 +0000 (22:09 +0000)]
scons: Match some of LLVM warning options.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 13:35:18 +0000 (13:35 +0000)]
scons: Cleanup flex/bison settings specification.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 13:30:19 +0000 (13:30 +0000)]
scons: Prefer winflexbison, and use --wincompat when available.
This avoids MSVC the warning
warning C4013: 'isatty' undefined; assuming extern returning int
with certain versions of flex.
Reviewed-by: Brian Paul <brianp@vmware.com>
v2: Add win flex-bison link to docs/install.html.
Jose Fonseca [Thu, 19 Mar 2015 11:53:36 +0000 (11:53 +0000)]
scons: Define YY_USE_CONST on MSVC.
This prevents the MSVC from
warning C4090: 'function' : different 'const' qualifiers
when compiling flex generated lexers.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Fri, 20 Mar 2015 06:27:59 +0000 (06:27 +0000)]
scons: Tell MSVC STL library to not use exceptions.
MSVC defaults to no exceptions unless /EH option is passed (which we don't), while
MSVC's STL defaults to use exceptions unless _HAS_EXCEPTIONS=0 is defined,
which we didn't.
This fixes
warning C4530: C++ exception handler used, but unwind semantics are not enabled. Specify /EHsc
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 13:31:37 +0000 (13:31 +0000)]
scons: Ensure git_sha1.h's directory exists.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 13:38:52 +0000 (13:38 +0000)]
configure: Bail out with MinGW targets.
We only support native Windows builds with SCons.
Tested with:
./configure --host=i686-w64-mingw32
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 11:51:08 +0000 (11:51 +0000)]
include: Ensure float.h is included for DBL_MAX.
I didn't actually hit the issue in practice, but just happen to notice
while looking at the code.
Reviewed-by: Brian Paul <brianp@vmware.com>
Jose Fonseca [Thu, 19 Mar 2015 13:14:41 +0000 (13:14 +0000)]
st/vdpau: Avoid constness cast warnings.
Fixes MSVC
warning C4090: '=' : different 'const' qualifiers
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Jose Fonseca [Thu, 19 Mar 2015 22:24:20 +0000 (22:24 +0000)]
glsl: Disable MSVC switch warning on a per-file basis.
This addresses
...\glsl_parser.cpp(...) : warning C4065: switch statement contains 'default' but no 'case' labels
This is on code generated by bison, which we have little control.
It seems useful to have this warning otherwise enabled.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Jose Fonseca [Wed, 18 Mar 2015 14:21:15 +0000 (14:21 +0000)]
glsl: Avoid GLboolean vs bool arithmetic MSVC warnings.
Note that GLboolean is an alias for unsigned char, which lacks the
implicit true/false semantics that C++/C99 bool have.
Reviewed-by: Brian Paul <brianp@vmware.com>
v2: Change gl_shader::IsES and gl_shader_program::IsES to be bool as
recommended by Ian Romanick.
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Emil Velikov [Sat, 21 Mar 2015 22:30:52 +0000 (22:30 +0000)]
galahad: actually remove the driver
Should have been part of
429a4355259(galahad: remove driver). Seems like
I've erroneously committed the trimmed patch.
Reported-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Thu, 19 Mar 2015 01:36:08 +0000 (01:36 +0000)]
egl: cut down static storage size for {Version,ClientAPI}String
Both seems to be excessively long, namely:
ClientAPIString can get up-to 47 based on current code, while the name
of the driver can dictate the length of the VersionString, currently it
is around 11. Let's pad each to 100, rather than the current 1000.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Emil Velikov [Sat, 21 Mar 2015 17:21:21 +0000 (17:21 +0000)]
docs: note the removal of gbm_gallium, galahad and identity
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sat, 14 Mar 2015 22:36:31 +0000 (22:36 +0000)]
galahad: remove driver
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 14 Mar 2015 22:36:30 +0000 (22:36 +0000)]
gallium/docs: remove information about identity driver
Removed from tree.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 14 Mar 2015 22:36:29 +0000 (22:36 +0000)]
docs: update the egl_platforms list
Add the missing wayland, null, android and haiku platforms.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 14 Mar 2015 22:36:28 +0000 (22:36 +0000)]
egl/main: drop platform fbdev specific code
st/egl was the only one which had support for this platform.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 14 Mar 2015 22:36:27 +0000 (22:36 +0000)]
winsys/sw/fbdev: remove unused software winsys
st/egl was its only user.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 14 Mar 2015 22:36:26 +0000 (22:36 +0000)]
winsys/sw/wayland: remove unused winsys
st/egl was its only user.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Emil Velikov [Sat, 14 Mar 2015 22:36:25 +0000 (22:36 +0000)]
st/gbm: remove state-tracker
st/egl was its only user.
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Acked-by: Matt Turner <mattst88@gmail.com>
Roland Scheidegger [Sat, 21 Mar 2015 00:13:54 +0000 (01:13 +0100)]
llvmpipe: use global llvm context for PIPE_SUBSYSTEM_EMBEDDED
There's 2 reasons why we'd want to use the global context:
1) There still seems to be one memory "leak" left when using multiple llvm
contexts (it is not a true leak as the memory disappears into some still
addressable pool but nevertheless the memory consumption grows). See
http://cgit.freedesktop.org/~jrfonseca/llvm-jitstress/
2) These contexts get kinda big - even when disposing modules etc. after
compiling a shader the LLVMContext can easily be over 100kB. So when there's
lots of llvm contexts arounds it adds up.
The downside is that at least right now this is absolutely not thread safe,
so this only works safely in environments where multiple pipe contexts are not
used concurrently.
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Emil Velikov [Sat, 21 Mar 2015 00:54:14 +0000 (00:54 +0000)]
docs: add news item and link release notes for mesa 10.4.7
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Emil Velikov [Sat, 21 Mar 2015 00:50:13 +0000 (00:50 +0000)]
docs: Add sha256 sums for the 10.4.7 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
cb154bb22116910c462f7a83f4401bd01e15c34d)
Emil Velikov [Sat, 21 Mar 2015 00:26:27 +0000 (00:26 +0000)]
Add release notes for the 10.4.7 release
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
(cherry picked from commit
d26f3c1f860e267964d2bd74a86235ae702af3f4)
Dave Airlie [Fri, 20 Mar 2015 07:25:15 +0000 (17:25 +1000)]
mesa: reorder gl_light_attrib
reduces from 2664->2656.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 07:21:57 +0000 (17:21 +1000)]
mesa: reorder gl_framebuffer
this reduces it from 1088 -> 1080 bytes
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 07:13:03 +0000 (17:13 +1000)]
mesa: fix hole in vertex_array_object
this just removes 4 bytes from this object.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 07:10:57 +0000 (17:10 +1000)]
mesa: repack gl_texture_attrib.
This removes a hole, and puts the large allocation at the end,
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 07:05:40 +0000 (17:05 +1000)]
mesa: reduce gl_colorbuffer_attrib and gl_fog_attrib
These 392->388 and 72->68.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 07:01:55 +0000 (17:01 +1000)]
mesa: reorder gl_image_unit
reduces 40->32
but reduces use in context from 7680->6144.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 06:54:40 +0000 (16:54 +1000)]
mesa: reorder gl_program, gl_shader, gl_shader_program
gl_program : 1344->1336
gl_shader: 488->472
gl_shader_program: 352->344.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 06:52:44 +0000 (16:52 +1000)]
mesa: reorder gl_transform_feedback_object
Reduces size from 184 to 176 bytes.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 06:26:59 +0000 (16:26 +1000)]
mesa: reorder prog_instruction
reduces size from 64 to 56 bytes.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 06:07:24 +0000 (16:07 +1000)]
mesa: reorder gl_array_attrib
drops 80 bytes to 72.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 06:02:46 +0000 (16:02 +1000)]
mesa: reorder gl_client_array
drops from 56 to 48 bytes,
drops gl_vertex_array_object from 4584 to 4320 bytes
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 06:00:10 +0000 (16:00 +1000)]
mesa: reorder gl_texture_unit
drops size from 520 -> 512 bytes,
which then makes gl_texture_attrib go from 99984 to 98440.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 05:59:01 +0000 (15:59 +1000)]
mesa: reorder gl_point_attrib
this drops the size from 52 bytes to 48 bytes.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Fri, 20 Mar 2015 05:58:09 +0000 (15:58 +1000)]
mesa: reorder gl_multisample_attrib
drops size from 28 bytes to 20.
Acked-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Alex Deucher alexander.deucher@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Ian Romanick [Thu, 19 Mar 2015 23:44:14 +0000 (16:44 -0700)]
i965/fs: Use correct null destination register in cmod tests
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89670
Reviewed-by: Matt Turner <mattst88@gmail.com>
Cc: Vinson Lee <vlee@freedesktop.org>
Connor Abbott [Fri, 20 Mar 2015 00:58:58 +0000 (20:58 -0400)]
i965/fs: bail on move-to-flag in sel peephole
Fixes a piglit regression
(shaders/glsl-fs-vec4-indexing-temp-dst-in-nested-loop-combined) with
my series for GVN.
Reviewed-by: Matt Turner <mattst88@gmail.com>
Signed-off-by: Connor Abbott <cwabbott0@gmail.com>
Francisco Jerez [Thu, 26 Feb 2015 11:58:21 +0000 (13:58 +0200)]
i965: Mask out unused Align16 components in brw_untyped_atomic.
This is currently not a problem because the vec4 visitor happens to
mask out unused components from the destination, but it might become
an issue when we start using atomics without writeback message. In
any case it seems sensible to set it again here because the
consequences of setting the wrong writemask (random graphics memory
corruption) are difficult to debug and can easily go unnoticed.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 26 Feb 2015 10:56:19 +0000 (12:56 +0200)]
i965: Pass number of components explicitly to brw_untyped_atomic and _surface_read.
And calculate the message response size based on the number of
components rather than the other way around. This simplifies their
interface somewhat and allows the caller to request a writeback
message with more than one vector component in SIMD4x2 mode.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 26 Feb 2015 15:24:03 +0000 (17:24 +0200)]
i965: Don't disable exec masking for sampler message sends.
This was telling the sampler to do texture fetches for *all* channels
in the non-constant surface index case, what could have reduced
throughput unnecessarily when some of the channels were disabled by
control flow.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 19 Mar 2015 13:44:24 +0000 (15:44 +0200)]
i965: Factor out logic to build a send message instruction with indirect descriptor.
This is going to be useful because the Gen7+ uniform and varying pull
constant, texturing, typed and untyped surface read, write, and atomic
generation code on the vec4 and fs back-end all require the same logic
to handle conditionally indirect surface indices. In pseudocode:
| if (surface.file == BRW_IMMEDIATE_VALUE) {
| inst = brw_SEND(p, dst, payload);
| set_descriptor_control_bits(inst, surface, ...);
| } else {
| inst = brw_OR(p, addr, surface, 0);
| set_descriptor_control_bits(inst, ...);
| inst = brw_SEND(p, dst, payload);
| set_indirect_send_descriptor(inst, addr);
| }
This patch abstracts out this frequently recurring pattern so we can
now write:
| inst = brw_send_indirect_message(p, sfid, dst, payload, surface)
| set_descriptor_control_bits(inst, ...);
without worrying about handling the immediate and indirect surface
index cases explicitly.
v2: Rebase. Improve documentatation and commit message. (Topi)
Preserve UW destination type cargo-cult. (Topi, Ken, Matt)
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 22 Jan 2015 15:08:23 +0000 (17:08 +0200)]
i965: Set nr_params to the number of uniform components in the VS/GS path.
Both do_vs_prog and do_gs_prog initialize brw_stage_prog_data::nr_params to
the number of uniform *vectors* required by the shader rather than the number
of uniform components, contradicting the comment. This is inconsistent with
what the state upload code and scalar path expect but it happens to work until
Gen8 because vec4_visitor interprets it as a number of vectors on construction
and later on overwrites its original value with the number of uniform
components referenced by the shader.
Also there's no need to add the number of samplers, they're not actually
passed in as uniforms.
Fixes a memory corruption issue on BDW with SIMD8 VS.
Cc: "10.5" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Wed, 4 Mar 2015 20:53:45 +0000 (12:53 -0800)]
i965/skl: Break down SIMD16 3-source instructions when required.
Several steppings of Skylake fail when using SIMD16 with 3-source
instructions (such as MAD).
This implements WaDisableSIMD16On3SrcInstr and fixes ~190 Piglit
tests.
Based on a patch by Neil Roberts.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Neil Roberts <neil@linux.intel.com>
Neil Roberts [Thu, 19 Mar 2015 18:18:49 +0000 (18:18 +0000)]
i965: Refactor SIMD16-to-2xSIMD8 checks.
The places that were checking whether 3-source instructions are
supported have now been combined into a small helper function. This
will be used in the next patch to add an additonal restriction.
Based on a patch by Kenneth Graunke.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Neil Roberts [Wed, 4 Mar 2015 14:13:40 +0000 (14:13 +0000)]
i965: Store the GPU revision number in brw_context
brwContextInit now queries the GPU revision number via a new parameter
for DRM_I915_GETPARAM. This new parameter requires a kernel patch and
a patch to libdrm. If the kernel doesn't support it then it will
continue but set the revision number to -1. The intention is to use
this to implement workarounds that are only needed on certain
steppings of the GPU.
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Fredrik Höglund [Thu, 19 Mar 2015 18:44:57 +0000 (19:44 +0100)]
mesa: Make sure the buffer exists in _mesa_lookup_bufferobj_err
Generate GL_INVALID_OPERATION and return NULL when the buffer object
hasn't been created. All callers expect this.
v2: Use a more concise error message.
Cc: Laura Ekstrand <laura@jlekstrand.net>
Reviewed-by: Laura Ekstrand <laura@jlekstrand.net>
Dave Airlie [Wed, 18 Mar 2015 01:46:45 +0000 (11:46 +1000)]
u_primconvert: add primitive restart support
This add primitive restart support to the prim conversion.
This involves changing the API for the translate functions
as we need to pass the prim restart index and the original
number of indices into the translate functions.
primitive restart is support for quads, quad strips
and polygons.
This deal with the case where the actual number of output
primitives is less than the initially calculated number,
by filling the rest of the output primitives with the restart
index, the other option is to reduce the output prim number,
but that will make the generator code a bit messier.
Reviewed-by: Brian Paul <brianp@vmware.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Kenneth Graunke [Tue, 24 Feb 2015 20:48:56 +0000 (12:48 -0800)]
i965/fp: Emit discard jumps.
This should improve the performance of any shaders using the KIL
instruction. I'm a bit surprised we missed this.
Unfortunately, I have not been able to measure any performance
improvements from this patch. It does make ARB_fragment_program
behave similarly to GLSL code.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Kenneth Graunke [Thu, 5 Mar 2015 23:48:39 +0000 (15:48 -0800)]
i965/fs: Make an emit_discard_jump() function to reduce duplication.
This is already copied in two places, and I want to copy it to a third
place.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Carl Worth <cworth@cworth.org>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Laura Ekstrand [Tue, 17 Mar 2015 19:55:41 +0000 (12:55 -0700)]
main: Add TEXTURE_CUBE_MAP support in CopyTextureSubImage3D.
So it turns out that this doesn't actually fix any bugs or add any features,
stictly speaking. However, it does avoid a lot of kludginess. Previously, if
you called
glCopyTextureSubImage3D(texcube, 0, 0, 0, zoffset = 3, ...
it would grab the texture image object for face = 0 in teximage.c instead of
the desired face = 3. But Line 274 of brw_blorp_blit.cpp would correct for
this by updating the slice to 3.
This commit does the correct thing before calling any drivers,
which should make the functionality much more robust and uniform across all
drivers.
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Laura Ekstrand [Thu, 19 Mar 2015 17:43:17 +0000 (10:43 -0700)]
main: Simplify debug messages for CopyTex*SubImage*D.
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Ian Romanick [Mon, 16 Mar 2015 19:14:10 +0000 (12:14 -0700)]
glsl: Annotate as_foo functions that the this pointer cannot be NULL
We use the idiom
ir_foo *x = y->as_foo();
if (x == NULL)
return;
all over the place. GCC generates some quite lovely code for this.
One such example:
340a5b: 83 7d 18 04 cmpl $0x4,0x18(%rbp)
340a5f: 0f 85 06 04 00 00 jne 340e6b
340a65: 48 85 ed test %rbp,%rbp
340a68: 0f 84 fd 03 00 00 je 340e6b
This case used as_expression() (ir_type_expression is 4). Note that it
checks the ir_type, then checks that the pointer isn't NULL. There is
some disconnect in GCC around the condition in the as_foo functions.
return ir_type == ir_type_##TYPE ? (ir_##TYPE *) this : NULL; \
It believes "this" could be NULL, so it emits check outside the function
just for fun.
This patch uses assume() to tell GCC that it need not bother with extra
NULL checking of the pointer returned by the as_foo functions.
text data bss dec hex filename
4836430 158688 26248 5021366 4c9eb6 i965_dri-before.so
4836173 158688 26248 5021109 4c9db5 i965_dri-after.so
v2: Replace 'if (this == NULL) unreachable("this cannot be NULL")' with
assume(this != NULL). Suggested by Ilia Mirkin.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Paul Berry [Fri, 10 Jan 2014 14:48:11 +0000 (06:48 -0800)]
main: Change the type argument of use_shader_program() to gl_shader_stage.
This allows it to be called from a loop.
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Paul Berry [Fri, 10 Jan 2014 14:35:09 +0000 (06:35 -0800)]
main: Clean up a strange construction in use_shader_program().
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Jason Ekstrand [Wed, 18 Mar 2015 22:18:54 +0000 (15:18 -0700)]
i965/nir: Sort uniforms direct-first and use two different uniform registers
Previously, we put all the uniforms into one big array. The problem with
this approach is that, as soon as there was one indirect array acces, the
backend would decide that the entire large array should be pull constants.
This commit splits the array in half: first direct-only uniforms and then
potentially-indirect uniforms. This may not be optimal, but it does let
the backend promote things to push constants.
Shader-db results on HSW:
total instructions in shared programs: 4114840 -> 4112172 (-0.06%)
instructions in affected programs: 43316 -> 40648 (-6.16%)
helped: 116
HURT: 0
v2: Set param_size[num_direct_uniforms] only if we have indirect uniforms.
This caused a bug that, strangely enough, only showed up on Broadwell
vertex shaders.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 18 Mar 2015 22:05:28 +0000 (15:05 -0700)]
nir/lower_io: Add a assign_locations function that sorts by [in]direct use
v2: Delete the set of indirectly accessed variables when we're done with it
v3: Rename from _packed to _scalar
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 18 Mar 2015 22:04:15 +0000 (15:04 -0700)]
nir/lower_io: Make variable location assignment a manual operation
Previously, we just assigned variable locations in nir_lower_io. Now, we
force the user to assign variable locations for us. This gives the backend
a bit more control over where variables are placed.
v2: Rename from _packed to _scalar
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Jason Ekstrand [Wed, 18 Mar 2015 19:34:09 +0000 (12:34 -0700)]
nir: Use a list instead of a hash_table for inputs, outputs, and uniforms
We never did a single hash table lookup in the entire NIR code base that I
found so there was no real benifit to doing it that way. I suppose that
for linking, we'll probably want to be able to lookup by name but we can
leave building that hash table to the linker. In the mean time this was
causing problems with GLSL IR -> NIR because GLSL IR doesn't guarantee us
unique names of uniforms, etc. This was causing massive rendering isues in
the unreal4 Sun Temple demo.
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Brian Paul [Thu, 19 Mar 2015 14:48:56 +0000 (08:48 -0600)]
gallivm: remove unused 'builder' variable
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Brian Paul [Thu, 19 Mar 2015 14:10:19 +0000 (08:10 -0600)]
mesa: use more descriptive error messages for glUniform errors
Different errors for type mismatches, size mismatches and matrix/
non-matrix mismatches. Use a common format of "uniformName"@location
in the messags.
Reviewed-by: Martin Peres <martin.peres@linux.intel.com>
Matt Turner [Mon, 16 Mar 2015 19:18:31 +0000 (12:18 -0700)]
i965/fs: Print spills:fills and number of promoted constants.
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
Reviewed-by: Chris Forbes <chrisf@ijw.co.nz>
Ian Romanick [Sat, 24 Jan 2015 01:31:12 +0000 (17:31 -0800)]
i965/fs: Emit better b2f of an expression on GEN4 and GEN5
On platforms that do not natively generate 0u and ~0u for Boolean
results, b2f expressions that look like
f = b2f(expr cmp 0)
will generate better code by pretending the expression is
f = ir_triop_sel(0.0, 1.0, expr cmp 0)
This is because the last instruction of "expr" can generate the
condition code for the "cmp 0". This avoids having to do the "-(b & 1)"
trick to generate 0u or ~0u for the Boolean result. This means code like
mov(16) g16<1>F 1F
mul.ge.f0(16) null g6<8,8,1>F g14<8,8,1>F
(+f0) sel(16) m6<1>F g16<8,8,1>F 0F
will be generated instead of
mul(16) g2<1>F g12<8,8,1>F g4<8,8,1>F
cmp.ge.f0(16) g2<1>D g4<8,8,1>F 0F
and(16) g4<1>D g2<8,8,1>D 1D
and(16) m6<1>D -g4<8,8,1>D 0x3f800000UD
v2: When the comparison is either == 0.0 or != 0.0 use the knowledge
that the true (or false) case already results in zero would allow better
code generation by possibly avoiding a load-immediate instruction.
v3: Apply the optimization even when neither comparitor is zero.
Shader-db results:
GM45 (0x2A42):
total instructions in shared programs: 3551002 -> 3550829 (-0.00%)
instructions in affected programs: 33269 -> 33096 (-0.52%)
helped: 121
Iron Lake (0x0046):
total instructions in shared programs: 4993327 -> 4993146 (-0.00%)
instructions in affected programs: 34199 -> 34018 (-0.53%)
helped: 129
No change on other platforms.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Tapani Palli <tapani.palli@intel.com>
Matt Turner [Wed, 18 Mar 2015 21:23:41 +0000 (14:23 -0700)]
util: Optimize _mesa_roundeven with SSE 4.1.
The SSE 4.1 ROUND instructions let us implement roundeven directly.
Otherwise we assume that the rounding mode has not been modified (as we
do in the rest of Mesa) and use rint().
glibc uses the ROUND instruction in rint() after a cpuid check. This
patch just lets us inline it directly when we're already building for
SSE 4.1.
Reviewed-by: Carl Worth <cworth@cworth.org>
Matt Turner [Thu, 12 Mar 2015 18:34:05 +0000 (11:34 -0700)]
util: Add a roundeven test.
Reviewed-by: Carl Worth <cworth@cworth.org>
Matt Turner [Wed, 11 Mar 2015 00:55:21 +0000 (17:55 -0700)]
mesa: Replace _mesa_round_to_even() with _mesa_roundeven().
Eric's initial patch adding constant expression evaluation for
ir_unop_round_even used nearbyint. The open-coded _mesa_round_to_even
implementation came about without much explanation after a reviewer
asked whether nearbyint depended on the application not modifying the
rounding mode. Of course (as Eric commented) we rely on the application
not changing the rounding mode from its default (round-to-nearest) in
many other places, including the IROUND function used by
_mesa_round_to_even!
Worse, IROUND() is implemented using the trunc(x + 0.5) trick which
fails for x = nextafterf(0.5, 0.0).
Still worse, _mesa_round_to_even unexpectedly returns an int. I suspect
that could cause problems when rounding large integral values not
representable as an int in ir_constant_expression.cpp's
ir_unop_round_even evaluation. Its use of _mesa_round_to_even is clearly
broken for doubles (as noted during review).
The constant expression evaluation code for the packing built-in
functions also mistakenly assumed that _mesa_round_to_even returned a
float, as can be seen by the cast through a signed integer type to an
unsigned (since negative float -> unsigned conversions are undefined).
rint() and nearbyint() implement the round-half-to-even behavior we want
when the rounding mode is set to the default round-to-nearest. The only
difference between them is that nearbyint() raises the inexact
exception.
This patch implements _mesa_roundeven{f,}, a function similar to the
roundeven function added by a yet unimplemented technical specification
(ISO/IEC TS 18661-1:2014), with a small difference in behavior -- we
don't bother raising the inexact exception, which I don't think we care
about anyway.
At least recent Intel CPUs can quickly change a subset of the bits in
the x87 floating-point control register, but the exception mask bits are
not included. rint() does not need to change these bits, but nearbyint()
does (twice: save old, set new, and restore old) in order to raise the
inexact exception, which would incur some penalty.
Reviewed-by: Carl Worth <cworth@cworth.org>