anv/video: fix to set U/V offset correctly.

Fixes: 98c58a16ef1a ("anv: add initial video decode support for h264.")

Closes: mesa/mesa#9227

Signed-off-by: Hyunjun Ko <zzoon@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23819>

glsl: call nir_opt_find_array_copies() when linking

shader-db results IRIS (BDW):

total instructions in shared programs: 17883388 -> 17859658 (-0.13%)
instructions in affected programs: 48100 -> 24370 (-49.33%)
helped: 6
HURT: 0
helped stats (abs) min: 1450 max: 7028 x̄: 3955.00 x̃: 3387
helped stats (rel) min: 40.31% max: 51.92% x̄: 47.07% x̃: 48.96%
95% mean confidence interval for instructions value: -6613.28 -1296.72
95% mean confidence interval for instructions %-change: -52.73% -41.40%
Instructions are helped.

total cycles in shared programs: 866961809 -> 863521521 (-0.40%)
cycles in affected programs: 9179396 -> 5739108 (-37.48%)
helped: 6
HURT: 0
helped stats (abs) min: 252584 max: 972430 x̄: 573381.33 x̃: 495130
helped stats (rel) min: 21.80% max: 48.65% x̄: 35.01% x̃: 34.58%
95% mean confidence interval for cycles value: -917157.00 -229605.67
95% mean confidence interval for cycles %-change: -47.61% -22.40%
Cycles are helped.

total spills in shared programs: 20417 -> 15521 (-23.98%)
spills in affected programs: 6966 -> 2070 (-70.28%)
helped: 6
HURT: 0

total fills in shared programs: 25151 -> 21005 (-16.48%)
fills in affected programs: 4374 -> 228 (-94.79%)
helped: 6
HURT: 0

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9055
Fixes: d75a36a9eeb1 ("glsl: remove do_copy_propagation_elements() optimisation pass")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23737>

nir/load_libclc: run some opt passes for everybody

Cuts down serialized size from 2850288 to 1377780 bytes.

Reduces clinfo with Rusticl time by 40% for debug builds.

(Old data, but the point stands)

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15996>

rusticl/device: create helper context before loading libclc

Some drivers (llvmpipe) postpone some screen initialization until the
first context is created.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15996>

venus: Fix detection of push descriptor set

- Fix null deref. VkPipelineLayoutCreateInfo::pSetLayouts is allowed to
  contain VK_NULL_HANDLE.
- The loop 'break' was misplaced.

Fixes crash in
dEQP-VK.pipeline.pipeline_library.graphics_library.fast.0_00_11_11 after
VK_EXT_graphics_pipeline_library is enabled in a later patch.

Fixes: 91966f2eff1 ("venus: extend lifetime of push descriptor set layout")
Signed-off-by: Lina Versace <linyaa@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Dawn Han <dawnhan@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23810>

nir/opt_if: Use block_ends_in_jump

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23782>

nir: Remove integer and 64-bit modifiers

Now that Intel and R600 both do their own modifier propagation, the only
backends that still lower modifiers in NIR are:

* nir-to-tgsi
* lima
* etnaviv
* a2xx

The latter 3 backends do not support integers, and certainly do not support
fp64. So they don't use these.

TGSI in theory supports integer negate modifiers but NTT doesn't use them, so
they're unused there too.

Since they're unused, we remove NIR support for integer and 64-bit modifiers,
leaving only 16/32-bit float modifiers. This will reduce the scope needed for a
replacement to NIR modifiers, being pursued in !23089.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23782>

venus: Advertise 1.3 in ICD file

It was still advertising 1.2.

Signed-off-by: Lina Versace <linyaa@google.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23808>

venus: suballocate feedback slot with feedback buffer alignment

Venus sync feedback design relies on concurrent host device resource
access. To avoid device flush overwriting host writes, we must
suballocate the slots with a minimum size of the buffer alignment.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23633>

docs: update calendar for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

docs/relnotes: add sha256sum for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

docs: add release notes for 23.1.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23805>

anv: align buffers to a cache line

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9217
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23794>

r300: add partial CMP support on R5xx

VE_COND_MUX_GTE4 is a nice match for the TGSI CMP opcode, however
there is a big limitation due to the general shortcoming of the
vertex shader engine that any instruction can read only two different
temporary registers. So we still have to lower in some cases.

Shader-db RV530:
total instructions in shared programs: 130872 -> 130333 (-0.41%)
instructions in affected programs: 29854 -> 29315 (-1.81%)
helped: 294
HURT: 83
total temps in shared programs: 16747 -> 16775 (0.17%)
temps in affected programs: 407 -> 435 (6.88%)
helped: 10
HURT: 38

Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23691>

radv: pre-init surface info

this is costly to do at render time, so avoid it when possible

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23770>

ci/etnaviv: update ci expectation

I have been running ci stress tests during the last few days
and nights and this is what I needed to get a pass rate > 80%.
There are still many flakes but I think this is a good starting
point to make better use of the ci.

Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23797>

Revert "amd/ci: temporarily disable some manual jobs that take a long time to run"

This reverts commit 4031ed5c8a0bbda910f22aec5ee3263b8137936a.

Signed-off-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23798>

rusticl: stop linking with libgalliumvl

it's not needed.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23778>

rusticl: specify which symbols to export

Drops release binary size from 31MB to 29MB

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23778>

rusticl: add ld_args_gc_sections

This drops release file size from 33MB to 31MB on my system.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23778>

meson: Guard the glsl tests that only working when OpenGL ES2 is enabled

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

mapi: Fixes non-constant-expression cannot be narrowed from type 'unsigned long' to 'unsigned int' in initializer list with clang

error is:
../src/mapi/glapi/tests/check_table.cpp:563:19: error: non-constant-expression cannot be narrowed from type 'unsigned long' to 'unsigned int' in initializer list [-Wc++11-narrowing]
   { "glNewList", _O(NewList) },

This is just a test and only with clang, and can be disabled by compiler option, so there is no need to back ported

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

meson: Use consistence disabled/enabled comment for shared-glapi option

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

mapi: Fixes check_table.cpp for DrawArraysInstancedARB and DrawElementsInstancedARB

The compile error when compiled with "-Dglx=xlib -D shared-glapi=disabled":
check_table.cpp:1133:37: error: ‘struct _glapi_table’ has no member named ‘DrawArraysInstancedARB’; did you mean ‘DrawArraysInstanced’?
 1133 |    { "glDrawArraysInstancedARB", _O(DrawArraysInstancedARB) },

Fixes: 5679ef99b82 ("glapi: remove EXT and ARB suffixes from Draw functions")

Reviewed-by: Eric Engestrom <eric@igalia.com>
Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23793>

rusticl: experimental support for cl_khr_fp16

Hidden behind `RUSTICL_ENABLE=fp16` for now as the OpenCL CTS doesn't have
enough fp16 tests at the moment. There has been a lot of work on it though,
so hopefully we can enable and verify it soon.

Additionally libclc also misses a bunch of fp16 functionality, so most of
the tests would also just crash.

However this flag is useful for development as it already wires up most of
the code needed.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23788>

rusticl/device: rename doubles to fp64 and long to int64

They are obviously the better names.

Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Nora Allen <blackcatgames@protonmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23788>

ci/panfrost: switch panfrost-g52-piglit-gles2 from X to XWayland

Runtime reduced approx. by 3 minutes (~ 11 to 8 minutes).

 - Add spec@ext_image_dma_buf_import@ext_image_dma_buf_import-transcode-nv12-as-r8-gr88 crash
 - drop useless `.piglit-test` extend

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23785>

zink/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

radeonsi/get: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

r600/pipe: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

iris/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

crocus/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

sofpipe/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

llvmpipe/screen: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

gallium: add PIPE_CAP_TIMER_RESOLUTION

Reviewed by Marek Olšák

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23703>

radeonsi: clean up #includes

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: declare compiler[] and nir_options as pointers to reduce #includes

so that we don't have to include the structure definitions.
(ac_llvm_compiler includes LLVM, and nir_options includes NIR)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: clean up query functions, make them static, remove forward decls

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for compute by buffering reg writes

This is the compute portion of the work. It uses a separate buffer
for compute SH registers in si_context.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: use SET_SH_REG_PAIRS_PACKED for gfx by buffering reg writes

Instead of writing SH registers into the command buffer, push them into
an array in si_context. Before a draw, take all buffered register writes
and create a single SET_SH_REG_PAIRS_PACKED packet for them.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: reorder compute code to prepare for packed SET_SH_REG packets

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: enable register shadowing by default

required by SET_SH_REG_PAIRS_PACKED*

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: fix GLCTS with register shadowing by keeping the CS preamble

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: remove uses_reg_shadowing parameter from si_init_gfx_preamble_state

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: remove radeon_winsys::cs_set_preamble

It only does radeon_emit_array and it's not possible to do anything better.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: use si_pm4_create_sized for the shadowing preamble

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: don't do BREAK_BATCH for context regs with only 1 context per batch

because it has no effect

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: keep pipeline statistics disabled when they are not used

so that we don't always disable/enable pipeline stats around blits
when there are no pipeline stat queries

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: determine si_pm4_state::reg_va_low_idx automatically

The existing code doesn't work with the packed SET packets, so si_pm4_state
needs to find reg_va_low_idx after the whole packet is built.

Remove si_pm4_set_reg_va and do the same thing for SET_SH_REG.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi/gfx11: use SET_*_REG_PAIRS_PACKED packets for pm4 states

It can generate all PACKED packets, but only SET_CONTEXT_REG_PAIRS_PACKED
is generated because register shadowing is required by
SET_SH_REG_PAIRS_PACKED*.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: eliminate redundant TCS user data and RSRC2 register changes

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: move the only tcs_out_lds_offsets field to vs_state_bits

This removes 1 user data SGPR.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: replace tcs_out_lds_layout with nearly identical tes_offchip_addr

tcs_out_lds_layout is basically renamed to tes_offchip_addr in TCS, using
the same variable as TES and also using the same bit layout. The only
difference in the bit layout was that TCS had to mask out the low bits,
which this also removes.

The enums are renamed to *_SGPR_TCS_OFFCHIP_ADDR so as not to conflict
with *_SGPR_TES_OFFCHIP_ADDR, which are in different user data SGPRs.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

radeonsi: move TCS.gl_PatchVerticesIn into the tcs_offchip_layout SGPR

we'll be able to remove 1 TCS user data SGPR thanks to this

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23517>

zink/ci: remove 3 tests from the fails list

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

amd/ci: temporarily disable some manual jobs that take a long time to run

We are trying to re-enable the valve CI... but doing so runs all the
jobs, including the manual ones.

Since some can take over an hour to run, let's disable them, and
re-enable them in another MR by reverting this commit.

Sorry for the noise!

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

Revert "ci: mark the valve farm as down"

Fixed by rebooting the gateway. A post-mortem analysis will be
performed to figure out what happened!

This reverts commit 2089fc8188635ed0ee72e2ddc009e7a775210bb7.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23789>

nir_opt_algebraic: don't use i32csel without native integer support

Otherwise nir_lower_int_to_float (or specifically nir_gather_ssa_types)
will fail to recognize we already have float constants and converts them
again.

Example from spec/glsl-1.10/execution/vs-loop-array-index-unroll.shader_test
with r300 driver (after enabling has_fused_comp_and_csel).

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x3e800000, 0x3f800000) = (0.000000, 0.250000, 1.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x3f000000, 0x3f800000) = (0.000000, 0.500000, 1.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x3f400000, 0x3f800000) = (0.000000, 0.750000, 1.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x3f800000) = (0.000000, 1.000000)
        vec1 32 ssa_6 = load_const (0x3f800000 = 1.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x00000001, 0x00000002, 0x00000003) = (0.000000, 0.000000, 0.000000, 0.000000)
        vec4  1 ssa_9 = ilt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_15 = i32csel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_15.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

and after nir_lower_int_to_float

impl main {
        block block_0:
        /* preds: */
        vec1 32 ssa_0 = load_const (0x00000000 = 0.000000)
        vec4 32 ssa_1 = intrinsic load_input (ssa_0) (base=0, component=0, dest_type=float32, io location=VERT_ATTRIB_POS slots=1)      /* gl_Vertex */
        vec3 32 ssa_2 = load_const (0x00000000, 0x4e7a0000, 0x4e7e0000) = (0.000000, 1048576000.000000, 1065353216.000000)
        vec3 32 ssa_3 = load_const (0x00000000, 0x4e7c0000, 0x4e7e0000) = (0.000000, 1056964608.000000, 1065353216.000000)
        vec3 32 ssa_4 = load_const (0x00000000, 0x4e7d0000, 0x4e7e0000) = (0.000000, 1061158912.000000, 1065353216.000000)
        vec2 32 ssa_5 = load_const (0x00000000, 0x4e7e0000) = (0.000000, 1065353216.000000)
        vec1 32 ssa_6 = load_const (0x4e7e0000 = 1065353216.000000)
        vec1 32 ssa_7 = intrinsic load_ubo_vec4 (ssa_0, ssa_0) (access=0, base=0, component=0)
        vec4 32 ssa_8 = load_const (0x00000000, 0x3f800000, 0x40000000, 0x40400000) = (0.000000, 1.000000, 2.000000, 3.000000)
        vec4  1 ssa_9 = flt ssa_8, ssa_7.xxxx
        vec3 32 ssa_10 = bcsel ssa_9.www, ssa_5.xyy, ssa_4
        vec3 32 ssa_11 = bcsel ssa_9.zzz, ssa_10, ssa_3
        vec3 32 ssa_12 = bcsel ssa_9.yyy, ssa_11, ssa_2
        vec3 32 ssa_13 = fcsel_gt ssa_7.xxx, ssa_12, ssa_6.xxx
        vec4 32 ssa_14 = fsat ssa_13.xyxz
        intrinsic store_output (ssa_14, ssa_0) (base=1, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_COL0 slots=1, xfb(), xfb2())       /* gl_FrontColor */
        intrinsic store_output (ssa_1, ssa_0) (base=0, wrmask=xyzw, component=0, src_type=float32, io location=VARYING_SLOT_POS slots=1, xfb(), xfb2()) /* gl_Position */
        /* succs: block_1 */
        block block_1:
}

Reviewed-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23704>

docs/ci: fix command to disable/re-enable farms

Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23780>

r600/sfn: Add source mod propagation also to fp64 ops

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>

r600/sfn: Implement fsat for 64 bit ops

Because a plain mov with the fsat modifier doesn't do a proper 64 bit fsat
we either have to propagate the op as modifier to the instruction that
creates the value, or we add a fake op that applies the fsat op, i.e. we
implement the mov as an add_64 with zero as the second value.

Fixes:  0ff3c4bef21e6768a53610337c39d1e306b3869e
    r600/sfn: drop use of nir source mods

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23754>

anv: update conformanceVersion

The Vulkan CTS started generating the list of valid versions the driver
can report as conformant against based on the active branches, and the
1.3.0 branch we were reporting up to now is no longer valid.

Fixes dEQP-VK.api.driver_properties.conformance_version

Reviewed-by: Mark Janes <markjanes@swizzler.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23784>

dzn: Align placed footprints used when copying linear <-> optimal for BC formats

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23662>

ci: move .microsoft-farm-container-rules to test-source-dep.yml

farm rules are placed on test-source-dep.yml, so move it there.

This is also useful when trying to re-use the container/gitlab-ci.yml to
other workflows without running the jobs.

Signed-off-by: Helen Koike <helen.koike@collabora.com>
Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23731>

nir/lower_tex: ignore saturate for txf ops

saturate is used for GL_CLAMP emulation, and GL_CLAMP cannot be used
with txf

ref #9226

cc: mesa-stable

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23750>

zink: add fastpaths for no-op sampler/view rebinds

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: check sampler views pointer before loop

this doesn't need to be checked in every loop iteration

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: don't update tc info directly from cso binds

this somehow becomes expensive at extremely high fps, so defer
until rp begin to check layout change state

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: track and apply ds3 states only on change

drivers don't do their own state tracking, so ensure the calls are only
made when necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: use local screen var in blend state bind

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: clean up rp update tracking on dsa bind

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: specialize invalidate_descriptor_state hook for compact mode

the constant flag check here has perf implications at high fps,
so avoid it when possible

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: make invalidate_descriptor_state a ctx hook

this will allow for specialization

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: force inlining for a bunch of functions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

zink: no-op redundant samplemask changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23758>

dzn: Fix multisample counts in device limits

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

dzn: Remove dynamic check for block-compressed support

None of this is optional in D3D

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

dzn: Use common GetPhysicalDeviceFeatures2

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

dzn: Inline D3D12 device creation in physical device creation

This was effectively happening *anyway* because WSI init was calling
functions that needed a D3D12 device around to be able to answer.
Just remove the whole song and dance of maybe not having a device.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23658>

util: reinstate ENUM_PACKED

gets rid of warning: 'gcc_struct' attribute ignored [-Wattributes] introduced by !23338

Fixes: 86532fa21de ("util: Use the gcc_struct attribute for packed structures in mingw")
Reviewed-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23478>

egl/haiku: Fix potential crash if double buffering is disabled

* Don't assume the existence of the back buffer in swap_buffers

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23556>

ci: mark the valve farm as down

docker daemon is down on mupuf-gfx10-vangogh-{1..3}

Signed-off-by: Eric Engestrom <eric@igalia.com>

intel/fs: Add missing newline

Emacs will add a newline to the end of this file whether I've edited
that line or not. It was driving me up the wall, so... yeah.

Trivial.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23777>

radv: inline radv_can_enable_dual_src()

this is unexpectedly heavy

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>

radv: remove redundant intermediate variable in radv_is_mrt0_dual_src()

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23601>

dzn: Ignore export access parameters

D3D requires these to just be GENERIC_ALL. Fixes some sharing tests.

Fixes: c64f1b66 ("dzn: Hook up win32 semaphore import/export")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23772>

asahi: drop unnecessary DRM_FORMAT_MOD_{LINEAR,INVALID} fallbacks

Since afe134a49c ("asahi: Drop macOS backend"), `drm_fourcc.h` is
unconditionally included, meaning these defines are now dead code.

Fixes: afe134a49c5ef79ca612 ("asahi: Drop macOS backend")
Signed-off-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23773>

aco: don't set exec_hi for wave32 scan reductions

fossil-db (wave32):
Totals from 21 (0.02% of 133428) affected shaders:
Instrs: 10778 -> 10712 (-0.61%)
CodeSize: 56604 -> 56208 (-0.70%)
Latency: 168293 -> 168251 (-0.02%)
InvThroughput: 25256 -> 25253 (-0.01%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Georg Lehmann <dadschoorse@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23745>

pvr: Fix csb control stream extension

Previously we reserved space for a stream link and whenever we ran
out of space in the current bo, allocated a new one, and emitted a
link to it. This is problematic as stream links can only be emitted
at state update boundaries so the handling could have produced a
corrupted control stream.

That's fixed by using a `relocation_mark` set by the driver to
indicate where a state update was last started, so csb can relocate
the whole update into the new bo and link to it.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23520>

intel/fs: Constant propagate into SHADER_OPCODE_SHUFFLE

Code already exists to convert SHADER_OPCODE_SHUFFLE into a simple MOV
when either source is constant. However... the constants have to
actually get into those sources!

On a shader that I'm working on that multiplies very large matrices using
lots of subgroup operations,

-SIMD8 shader: 1378 instructions. 3 loops. 793896 cycles. 0:0 spills:fills, 23 sends, scheduled with mode non-lifo. Promoted 0 constants. Compacted 22048 to 21664 bytes (2%)
+SIMD8 shader: 346 instructions. 3 loops. 61742 cycles. 0:0 spills:fills, 23 sends, scheduled with mode top-down. Promoted 0 constants. Compacted 5536 to 5216 bytes (6%)

No changes in shader-db or fossil-db on any Intel platform.

v2: Merge a bunch of identical cases. Suggested by Ken.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> [v1]
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23609>

pvr: Fix dynamic offset patching

Previously the set of dynamic offsets were being reused per each
binding. That's now fixed, by using an offset to determine where
each binding's dynamic offsets reside.

Tests fixed:
  dEQP-VK.binding_model.descriptor_copy.{compute,graphics}
    .{uniform,storage}_buffer_dynamic_0

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Fixes: aa791961a82e ("pvr: Add support for dynamic buffers descriptors")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23587>

pvr: Fix barrier insertion on merged subpasses

The driver can merge subpasses within a render pass into a single
hw render. While doing so it makes the assumption that the subpasses
in an hw render will all be submitted in a single job.

On vkCmdPipelineBarrier() the driver was previously incorrectly
inserting an event sub-cmd on a merged subpass, breaking that
assumption leading to incorrect values for input attachments.

Signed-off-by: Soroush Kashani <soroush.kashani@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Fixes: 6d672e033683 ("pvr: Add initial vkCmdPipelineBarrier skeleton.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23693>

pvr: Fix seg fault on empty descriptor set

Vulkan allows empty descriptor sets to be created. When we setup
the descriptor set addresses table we fill in the address of the
`bo` for each valid/currently bound desc set. For empty desc sets
there is no `bo` which was causing a seg fault. Now skip them,
leaving their address set to `~0`.

Reported-by: Simon Perretta <simon.perretta@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Fixes: ce67f5ac944 ("pvr: Write descriptor set addrs table dev addr into shareds")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23692>

radv: Move most of DB_SHADER_CONTROL to PS, more precise GFX11 blend WA

Move most of the DB_SHADER_CONTROL fields from the pipeline to the pixel
shader for preparation for shader objects.

Also, the GFX11 export conflict bug workaround doesn't need to be enabled
for non-1x sample counts or if blending is not enabled, so make the
application of DB_SHADER_CONTROL consider the current sample count and
blending state even if they're dynamic.

Having access to the exact sample count in DB_SHADER_CONTROL setup is also
necessary for good performance in SampleInterlock execution modes of
fragment shader interlock, for configuration of POPS_OVERLAP_NUM_SAMPLES
(GFX9-10.3) or OVERRIDE_INTRINSIC_RATE (GFX11), as PixelInterlock is
massively slower with multisampling due to overlap between adjacent
polygons sharing covered pixels among the common edge.

The name of the dynamic state controlling DB_SHADER_CONTROL is now
unambiguous - previously line rasterization mode had effect on attachment
feedback loop state emission.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Vitaliy Triang3l Kuzmin <triang3l@yandex.ru>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23474>

isl: add surface creation reporting mechanism

We have a number of users reporting surface creation issues with
modifiers etc...

This makes Anv & Iris printout the reason of the failure with
INTEL_DEBUG=isl Failure example in Iris :

MESA: debug: ISL surface failed: ../src/intel/isl/isl.c:1729: requested row pitch (42B) less than minimum alignment requirement (1024B) extent=160x160x1 dim=2d msaa=1x levels=1 rpitch=42 fmt=B8G8R8X8_UNORM usage=+rt+tex+disp

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

isl: assert on gfx8 condition that should not be met

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

isl: assert on gfx7 condition that should not be met

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

isl: assert on gfx6 condition that should not be met

Those 2 cases should have been handled earlier.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14039>

zink: radv vangogh ci updates

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23729>

zink: always clamp NUM_QUERIES to 500

this avoids ooming on some weaker GPUs with big query energy

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23729>