Asahi Lina [Fri, 1 Sep 2023 09:52:14 +0000 (18:52 +0900)]
asahi: Allow no16 flag for disk cache
The debug flags are already plumbed into driver_flags for the disk
cache, so we just need to actually allow some flags instead of bailing
out of the disk cache init.
We only care about no16 for production right now, and it's probably a
good idea to disable disk caching during most debug sessions, so
allowlist only that one.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:42:48 +0000 (15:42 +0900)]
driconf: Disable fp16 for browsers
There are way too many broken WebGL apps using the wrong precision
qualifiers, which causes anything from jittery geometry to complete
breakage (e.g. QuakeJS and other games).
In addition, a Firefox bug is breaking basic canvas rendering for the
same reason (mozilla bug #1845309).
Let's just disable fp16 for browsers. There is no hope of getting all
this broken stuff fixed.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:42:04 +0000 (15:42 +0900)]
asahi: Add and support the no_fp16 driconf flag
This is the driconf equivalent of our debug no16 flag, which disables
fp16 support to work around apps using bad GLSL precision qualifiers.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 30 Aug 2023 06:40:27 +0000 (15:40 +0900)]
asahi: Add scaffolding for supporting driconf options
It's time to start using some of these, so add the required scaffolding
to be able to have driver-specific driconf handling for us.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Eric Engestrom <eric@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:39:19 +0000 (21:39 +0900)]
asahi: Fix VDM pipeline field width
The lower bits have a special meaning, like on the other pipelines.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:36:43 +0000 (21:36 +0900)]
asahi: decode: Do not assert on buffer overruns
This kills the hypervisor, let's just print and return.
Also flush after decoding, so that if something else goes wrong at least
we get the logs up to that point.
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:33:18 +0000 (21:33 +0900)]
asahi: decode: Implement VDM call/ret
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Wed, 16 Aug 2023 12:32:44 +0000 (21:32 +0900)]
asahi: cmdbuf: Identify call/ret bits
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Asahi Lina [Fri, 1 Sep 2023 10:42:50 +0000 (19:42 +0900)]
asahi: Allocate staging resources as staging
We were never setting the flag, which made these resources
write-combine...
Signed-off-by: Asahi Lina <lina@asahilina.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sat, 15 Apr 2023 23:49:47 +0000 (19:49 -0400)]
agx: Schedule for register pressure
Since we register allocate in SSA, the number of registers required (register
demand) equals to the maximum number of simultaneous live values (register
pressure). So if we can reduce register pressure, we are guaranteed to reduce
register demand. Even an ineffective heuristic like randomly swapping
instructions can only reduce pressure as long as it's conservative.
This implements one such heuristic: in each block, schedule backwards, selecting
the free instruction that looks like it will reduce liveness the most. In other
words, the greedy algorithm to reduce register pressure. At the end of the
block, if we haven't actually reduced pressure, we bail. This isn't optimal, but
it's well-motivated and optimally handles special cases (like 0-source
instructions).
This is based on the scheduler I originally wrote for Mali.
In my Dolphin ubershader branch, this improved performance at native 4K by 10fps
(105fps->115fps) when I measured together with some other optimizations. On top
of my current next (which notably includes nir_opt_sink improvements), this
commit alone goes (53fps->54fps) which is considerably less impressive :-p
shader-db results are a win, but not as large as we might hope. Instruction
count win seems to be from the smaller live ranges being easier on RA (fewer
swaps / moves). The two shaders affected for thread count are from fifa mobile,
which go from 640 threads ->
1024 (full occupancy). In other words... this heuristic does an excellent job in
a small subset of shaders. The Dolphin ubershader win was real, though :~)
Note these shader-db wins are on top of a branch with the nir_opt_sink
improvements. Without that, the stats are much better... The schedulers have
some overlap, but they're better together.
total instructions in shared programs: 1766635 -> 1763496 (-0.18%)
instructions in affected programs: 445855 -> 442716 (-0.70%)
helped: 1963
HURT: 350
Instructions are helped.
total bytes in shared programs:
11597648 ->
11586924 (-0.09%)
bytes in affected programs: 3106230 -> 3095506 (-0.35%)
helped: 2003
HURT: 374
Bytes are helped.
total halfregs in shared programs: 504609 -> 481980 (-4.48%)
halfregs in affected programs: 138322 -> 115693 (-16.36%)
helped: 3405
HURT: 311
Halfregs are helped.
total threads in shared programs:
18839936 ->
18840704 (<.01%)
threads in affected programs: 1280 -> 2048 (60.00%)
helped: 2
HURT: 0
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:12:46 +0000 (19:12 -0400)]
agx: Include schedule class in the opcode info
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:19:07 +0000 (19:19 -0400)]
agx: Add schedule-specialized get_sr variants
Some special registers imply scheduling constraints. We want to have a single
scheduling class per instruction in the IR, so fork off various get_sr variants
depending on what kind of SR we're reading, and validate that we use the right
kind.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 23:05:47 +0000 (19:05 -0400)]
agx: Annotate opcodes with a scheduling class
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 20 Aug 2023 17:43:38 +0000 (13:43 -0400)]
agx/validate: Print to stderr
Otherwise unusable.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Sun, 20 Aug 2023 17:10:43 +0000 (13:10 -0400)]
agx: Fix jmp_exec_none encoding
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Alyssa Rosenzweig [Thu, 24 Aug 2023 20:01:24 +0000 (16:01 -0400)]
asahi: Fixes for clang-warnings
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Christian Gmeiner [Thu, 24 Aug 2023 15:49:16 +0000 (17:49 +0200)]
agx/lower_address: Remove not used has_offset
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Christian Gmeiner [Thu, 24 Aug 2023 09:01:10 +0000 (11:01 +0200)]
agx/lower_address: Use intrinsics_pass
Signed-off-by: Christian Gmeiner <cgmeiner@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Neal Gompa [Wed, 23 Aug 2023 17:02:37 +0000 (13:02 -0400)]
asahi: Fix 32-bit x86 build with correct data type for overflow error message
Currently, when building on 32-bit x86, we get compilation errors
due to data type mis-matches in the format string.
This should fix the issue.
Signed-off-by: Neal Gompa <neal@gompa.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Wed, 30 Aug 2023 09:13:56 +0000 (11:13 +0200)]
rusticl: enable asahi
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 10:21:33 +0000 (12:21 +0200)]
rusticl/memory: fallback if allocating linear images fails
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 09:57:02 +0000 (11:57 +0200)]
asahi: handle images in is_format_supported
Some frontends differentiate between textures and images more explicitly
than st/mesa. So we might end up with PIPE_BIND_SHADER_IMAGE but not
PIPE_BIND_SAMPLER_VIEW in is_format_supported.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 1 Sep 2023 09:52:50 +0000 (11:52 +0200)]
asahi: gracefully handle allocating linear images
Frontends might try to allocate linear textures or images, we should
gracefully return NULL so frontends can do fallback paths.
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Wed, 30 Aug 2023 09:21:13 +0000 (11:21 +0200)]
asahi: implement clear_buffer
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 3 Feb 2023 17:42:50 +0000 (18:42 +0100)]
asahi: implement set_global_binding
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 12:53:56 +0000 (14:53 +0200)]
asahi: implement get_compute_state_info
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 18:33:42 +0000 (20:33 +0200)]
asahi: handle load_global_invocation_id_zero_base
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 15:09:14 +0000 (17:09 +0200)]
asahi: handle load_workgroup_size
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 13:02:41 +0000 (15:02 +0200)]
asahi: handle kernels
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Tue, 29 Aug 2023 22:51:11 +0000 (00:51 +0200)]
asahi: lower hadd
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Karol Herbst [Fri, 3 Feb 2023 17:42:36 +0000 (18:42 +0100)]
asahi: fetch available system memory
Signed-off-by: Karol Herbst <git@karolherbst.de>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25052>
Connor Abbott [Fri, 25 Aug 2023 10:47:29 +0000 (12:47 +0200)]
vk/graphics_state: Fix copying MS locations pipeline state
Copying the state below overwrote the ms.sample_locations we set,
so our new_sample_locations was never actually used and we were
accidentally doing a shallow copy. Turnip passes a stack-allocated
old_state, so this resulted in invalid stack pointers.
Fixes:
f497cc9d56e ("vk/graphics_state: Add helpers for pre-baking state")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25031>
Eric Engestrom [Mon, 4 Sep 2023 11:40:18 +0000 (12:40 +0100)]
ci: skip containers & build jobs when disabling a farm
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25032>
Danylo Piliaiev [Fri, 14 Jul 2023 14:41:48 +0000 (16:41 +0200)]
tu/a7xx: Disable LRZ
Even with GMEM disabled LRZ is still interacted with in some cases.
So it has to be completely disabled until it is fixed.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 10 Jul 2023 13:07:39 +0000 (15:07 +0200)]
tu/a7xx: Fix CmdDrawIndirectByteCountEXT
On a7xx DI_SRC_SEL_AUTO_INDEX is used instead of DI_SRC_SEL_AUTO_XFB.
On a7xx the counter value and offset are shifted right by 2, so
the vertexStride should also be in units of dwords.
CTS doesn't test this though.
Fixes:
dEQP-VK.transform_feedback.simple.draw_indirect_*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 4 Jul 2023 13:11:58 +0000 (15:11 +0200)]
tu/a7xx: Fix 3d blits after multiview usage
Fixes cts tests:
dEQP-VK.dynamic_rendering.primary_cmd_buff.random.seed*
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Thu, 22 Jun 2023 10:30:42 +0000 (12:30 +0200)]
tu/a7xx: Fix occlusion query
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Mark Collins [Tue, 6 Jun 2023 10:27:20 +0000 (10:27 +0000)]
tu/a7xx: Adapt r3d blits for A7xx
As r3d_ops emits sysmem draws directly, it needs to be manually
updated to emit the A7XX commands instead of A6XX.
VK-CTS tests success on A630 + A740:
dEQP-VK.api.copy_and_blit.core.blit_image.*
Signed-off-by: Mark Collins <mark@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 31 May 2023 12:29:41 +0000 (14:29 +0200)]
tu/a7xx: Fix flat shading
dEQP-VK.rasterization.flatshading.* are passing.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 30 May 2023 13:03:23 +0000 (15:03 +0200)]
tu/a7xx: Fix multiview
dEQP-VK.multiview.* mostly works, fails seem to be caused by lack of
3d blits.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 30 May 2023 13:02:28 +0000 (15:02 +0200)]
tu/a7xx: Fix tesselation shaders
dEQP-VK.tessellation.* are passing now.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 30 May 2023 13:00:43 +0000 (15:00 +0200)]
tu/a7xx: Fix geometry shaders
dEQP-VK.geometry.* are passing now
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 23 May 2023 16:44:58 +0000 (18:44 +0200)]
freedreno/fdl: Set LOSSLESSCOMPEN for image when ubwc is enabled on a7xx
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 19 Apr 2023 17:18:13 +0000 (19:18 +0200)]
tu: Basic a7xx support
Works:
- sysmem rendering
Doesn't work:
- gmem rendering
- 3d blits
- TESS and GS
Wild Life Extreme benchmarks runs without issues, most Sascha Willems
Vulkan demos are working.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 19 Apr 2023 17:05:00 +0000 (19:05 +0200)]
tu/common: Generalize TU_GENX macro
Now it doesn't require generated macro.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:32:20 +0000 (19:32 +0200)]
ir3/a7xx: Disable shared consts for a7xx
a7xx introduced a new way to upload shared consts with old one
becoming unavailable, use fallback mechanism until we implement
the new shared consts.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:27:45 +0000 (19:27 +0200)]
ir3/a7xx: Use ccinv for data synchronization
Fixes a lot of tests in dEQP-VK.memory_model.* e.g.:
dEQP-VK.memory_model.message_passing.core11.u32.coherent.fence_fence.atomicwrite.device.payload_local.buffer.guard_local.buffer.comp
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:25:06 +0000 (19:25 +0200)]
ir3/a7xx: Add ccinv instruction
_Presumably_ invalidates workgroup-wide cache for image/buffer data access.
so while "fence" is enough to synchronize data access inside a workgroup,
for cross-workgroup synchronization we have to invalidate that cache.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 24 Apr 2023 14:39:44 +0000 (16:39 +0200)]
ir3/a7xx: insert lock/unlock at the end of every compute shader
Add (ss)(sy) in all cases until.
TODO: Set sync flags depending on real need.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 19 Apr 2023 17:08:00 +0000 (19:08 +0200)]
ir3/a7xx: Don't multiply global mem instruction's offset by 4
a7xx global memory instructions don't have implied shift.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Wed, 3 May 2023 17:39:46 +0000 (19:39 +0200)]
ir3/a7xx: cat5 mode1 has swapped tex/samp ids
Though blob is not seen to even use mode1 on a740, it uses
S2EN variant instead.
Fixes:
dEQP-VK.binding_model.descriptor_buffer.multiple.*
dEQP-VK.binding_model.descriptor_buffer.embedded_imm_samplers.*
dEQP-VK.pipeline.monolithic.descriptor_limits.compute_shader.*
Adapted from Jonathan Marek's changes.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 9 Jun 2023 10:58:55 +0000 (12:58 +0200)]
isaspec: Make possible to obtain gpu_id in <expr> blocks
Done with ISA_GPU_ID() macro. This makes possible to use
gpu generation in to select between overrides.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 17 Apr 2023 13:39:09 +0000 (15:39 +0200)]
freedreno/computerator: Fix remaining issues with A7XX
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 4 Sep 2023 15:53:09 +0000 (17:53 +0200)]
ir3/tests: Use fd_dev_info to infer GPU generation
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Mon, 17 Apr 2023 13:38:00 +0000 (15:38 +0200)]
freedreno: Fully define a730 and a740 device properties
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Tue, 2 May 2023 11:26:06 +0000 (13:26 +0200)]
freedreno: Add a list of raw magic regs
The set of magic regs is different between generations and even
sub-gens. Adding a new one and/or emitting one on specific generation
takes much more code than necessary. Doing this in a single place is
much nicer.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 11 Aug 2023 13:30:47 +0000 (15:30 +0200)]
freedreno/registers: Generate python files with reg offsets
This would allow us to use register names in python scripts.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Danylo Piliaiev [Fri, 11 Aug 2023 13:10:59 +0000 (15:10 +0200)]
freedreno/registers: Refactor gen_header.py to allow more options
We want it to also generate .py files with reg definitions.
Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23217>
Lionel Landwerlin [Sat, 2 Sep 2023 15:53:13 +0000 (18:53 +0300)]
intel/nir: rerun lower_tex if it lowers something
nir_lower_tex can lower tg4 coords into tg4 offset which on DG2+ we
also need to lower into constant offsets.
Unfortunately the nir_lower_tex pass is not able to lower the
instructions it itself generates, so the easy fix for when
nir_lower_tex lowers tg4 coords into tg4 offsets is to rerun the pass.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9735
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25015>
Vlad Schiller [Mon, 21 Aug 2023 05:34:36 +0000 (06:34 +0100)]
pvr: Implement VK_KHR_format_feature_flags2
This commit will implement and set VK_KHR_format_feature_flags2
instead of the old ones.
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24929>
Samuel Pitoiset [Wed, 30 Aug 2023 12:08:09 +0000 (14:08 +0200)]
radv/amdgpu: do not copy the original chain link for IBs
Otherwise, if a secondary CS is grown and then executed without IB2,
the INDIRECT_BUFFER packet would have been copied but it shouldn't.
This fixes a regression that introduced GPU hangs with
gl_vk_meshlet_cadscene on RDNA2.
Fixes:
df0c742543d ("radv/amdgpu: rework growing a CS with the chained IB path slightly")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
Samuel Pitoiset [Fri, 25 Aug 2023 15:26:30 +0000 (17:26 +0200)]
radv/amdgpu: fix executing secondaries without IB2
If a secondary cmdbuf has been grown and is executed without IB2
(eg. on compute queue or when it's not allowed), the ib size ptr
contains chaining info, which means the IB size was wrong.
This fixes CPU crashes when running gl_vk_meshlet_cadscene.
Fixes:
277b2afd708 ("radv/amdgpu: add support for executing DGC cmdbuf with RADV_DEBUG=noibs")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24891>
Lionel Landwerlin [Fri, 11 Aug 2023 09:19:28 +0000 (12:19 +0300)]
intel/measure: track batch buffer sizes
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Lionel Landwerlin [Fri, 11 Aug 2023 09:14:32 +0000 (12:14 +0300)]
anv: reuse cmd_buffer::total_batch_size
This was left unused after
624ac55721 ("anv: move total_batch_size to
anv_batch"). We're now going to use it to store the total amount of
commands written in a command buffer.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Lionel Landwerlin [Fri, 11 Aug 2023 09:04:18 +0000 (12:04 +0300)]
anv: rename total_batch_size
This name is confusing, the real thing it represents is the allocated
amount of batch space.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24628>
Chris Spencer [Tue, 29 Aug 2023 19:26:20 +0000 (20:26 +0100)]
anv/android: Enable shared presentable image support
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
Chris Spencer [Tue, 29 Aug 2023 21:16:45 +0000 (22:16 +0100)]
android: Add explanatory comment to u_gralloc
Signed-off-by: Chris Spencer <spencercw@gmail.com>
Reviewed-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24941>
Dmitry Osipenko [Fri, 1 Sep 2023 00:36:15 +0000 (03:36 +0300)]
util/cache_test: Add test for get/put() with disabled cache
The disk_cache_create() now always returns valid cache even when disk
cache is disabled. In a case of disabled cache, the disk cache is NO-OP.
Test whether get/put() work as expected for the disabled cache.
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dmitry Osipenko [Fri, 1 Sep 2023 00:13:11 +0000 (03:13 +0300)]
util/cache_test: Fix disabled cache test using SHADER_CACHE_DISABLE_BY_DEFAULT
Previous commit decoupled EGL_ANDROID_blob_cache from the disk cache
and haven't updated the SHADER_CACHE_DISABLE_BY_DEFAULT test-case that
is failing because now cache is always created even if disk cache is
disabled, such cache is NO-OP in this case. Fix the failing test.
Fixes:
39f26642 ("util: Decouple disk cache from EGL_ANDROID_blob_cache")
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dmitry Osipenko [Fri, 1 Sep 2023 00:03:22 +0000 (03:03 +0300)]
util/cache_test: Re-add test for disabled cache
Test for disabled cache was removed when we decoupled
EGL_ANDROID_blob_cache from the disk cache because test was failing
since it became outdated. Add the updated test.
Fixes:
39f26642 ("util: Decouple disk cache from EGL_ANDROID_blob_cache")
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Dmitry Osipenko <dmitry.osipenko@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24985>
Dave Airlie [Wed, 30 Aug 2023 01:56:56 +0000 (11:56 +1000)]
llvmpipe/cs: further cleanups after tgsi removal.
These was still a few more places that could be polished better.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25045>
Mike Blumenkrantz [Fri, 1 Sep 2023 17:23:32 +0000 (13:23 -0400)]
zink: fix linear modifier dmabuf imports
these are disguised as INVALID modifiers, but really they're LINEAR
cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25002>
Alyssa Rosenzweig [Wed, 30 Aug 2023 22:10:28 +0000 (18:10 -0400)]
nir/opt_if: Simplify if's with general conditions
Dolphin ubershaders have a pattern:
if (x && y) {
} else {
discard;
}
The current code to simplify if's will bail on this pattern, since the condition
is not a comparison. However, if that check is dropped and we allow NIR to
invert this, we get:
if (!(x && y)) {
discard;
} else {
}
which is now in a form for nir_opt_conditional_discard to turn into it
discard_if(!(x && y))
which may be substantially cheaper than the original code.
In general, I see no reason to restrict to conditionals. Assuming the backend is
clever enough to delete empty else blocks (I think most are), then this patch is
a strict win as long as inot instructions are cheaper than empty else blocks.
This matches my intuition for typical GPUs, where simple ALU instructions are
cheaper than control flow. Furthermore, it may be possible in practice for
backends to fold the inot into a richer set of instructions. For example, most
GPUs have a NAND instructions which would fold in the inot in the above code.
So just drop the check, simplify the pass, get the win.
---
Also, to avoid inflating register pressure, make sure we put the inot right
before the if. Android shader-db on is uninspiring due to terrible
coalescing decisions in the current RA. But it does fix the Dolphin smell.
total instructions in shared programs: 1756571 -> 1756568 (<.01%)
instructions in affected programs: 1600 -> 1597 (-0.19%)
helped: 1
HURT: 4
Inconclusive result (value mean confidence interval includes 0).
total bytes in shared programs:
11521172 ->
11521156 (<.01%)
bytes in affected programs: 10080 -> 10064 (-0.16%)
helped: 1
HURT: 4
Inconclusive result (value mean confidence interval includes 0).
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24965>
Mike Blumenkrantz [Wed, 30 Aug 2023 13:49:30 +0000 (09:49 -0400)]
lavapipe: fix pipeline stride propagation
this is on the cso now
affects dEQP-VK.pipeline.fast_linked_library.extended_dynamic_state.before_good_static.large_stride
Fixes:
76725452239 ("gallium: move vertex stride to CSO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24954>
Mike Blumenkrantz [Wed, 30 Aug 2023 13:38:54 +0000 (09:38 -0400)]
lavapipe: update vbo indices before propagating stride
the vbo index is used to set the stride, so it needs to be updated
affects dEQP-VK.pipeline.pipeline_library.bind_buffers_2.single.stride_0_4_offset_1_0.count_2
Fixes:
76725452239 ("gallium: move vertex stride to CSO")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24954>
Mike Blumenkrantz [Thu, 24 Aug 2023 12:26:10 +0000 (08:26 -0400)]
zink: don't block reordering during ref updates in unordered blits
unordered blits handle all the reorder mechanics already, so any changes
here end up unnecessarily blocking further reordering
test case KHR-GLES3.packed_pixels.varied_rectangle.rgb
ref #9016
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24934>
Mike Blumenkrantz [Wed, 30 Aug 2023 10:54:37 +0000 (06:54 -0400)]
zink: be more precise about flagging rp changes around unordered u_blitter
failing to update rp attachments as needed after unordered blits results in
broken (depth) rendering
Fixes:
3a9f7d70383 ("zink: implement unordered u_blitter calls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24934>
Leo Liu [Fri, 1 Sep 2023 22:26:43 +0000 (18:26 -0400)]
radeonsi/vcn: fix the incorrect dt_size
Issue: For texture with multiple planes, the planes will point to the
same BO with the total size, so current vcn dt_size is incorrect.
(gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[0]))
...
buf = 0x5555558daa30,
gpu_address = 0xffff800101000000,
bo_size = 0xa2000,
...
}
(gdb) p/x *((struct si_resource *)(((struct vl_video_buffer *)out_surf)->resources[1]))
...
buf = 0x5555558daa30,
gpu_address = 0xffff800101000000,
bo_size = 0xa2000,
...
}
This is because: in function static struct si_texture *si_texture_create_object(),
if (plane0) {
/* The buffer is shared with the first plane. */
resource->bo_size = plane0->buffer.bo_size;
...
radeon_bo_reference(sscreen->ws, &resource->buf, plane0->buffer.buf);
resource->gpu_address = plane0->buffer.gpu_address;
}
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/9728
Cc: mesa-stable
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Ruijing Dong <ruijing.dong@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25013>
Tapani Pälli [Mon, 21 Aug 2023 10:29:43 +0000 (13:29 +0300)]
iris: implement Wa_14018912822
When MSAA is enabled, instead of using BLENDFACTOR_ZERO use CONST_COLOR,
CONST_ALPHA and supply zero by using blend constants.
We need info on blend state entries in the CSO so that we can set them
up properly.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24714>
Tapani Pälli [Wed, 16 Aug 2023 05:20:12 +0000 (08:20 +0300)]
anv: implement Wa_14018912822
When MSAA is enabled, instead of using BLENDFACTOR_ZERO use CONST_COLOR,
CONST_ALPHA and supply zero by using blend constants.
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24714>
Samuel Pitoiset [Mon, 4 Sep 2023 08:34:06 +0000 (10:34 +0200)]
ci: do not fail vkd3d-proton job when the expectations match
When the list of expected failures match, the job shouldn't fail.
This also adjusts the first error check to catch segfaults.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25025>
Samuel Pitoiset [Mon, 4 Sep 2023 06:44:51 +0000 (08:44 +0200)]
radv/ci: re-enable vkd3d-polaris10-valve
Like the vkcts job, this was disabled a while ago but it seems to be
working well again.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25025>
Pavel Ondračka [Wed, 23 Aug 2023 11:55:48 +0000 (13:55 +0200)]
r300: use w channel for scalar opcodes if possible
The opcodes write to w by default so using anything else means we can't
schedule anything in the rbg slot anyway becasue we have to replicate the
result from w. We already attempt to do this during the scheduling, but
at that point it is more tricky, so doing it early leads to much better
code. Performance++
RV530 benchmarks:
Lightsmark, 1280x800, fullscreen
before:
N Min Max Median Avg Stddev
x 5 27.32 27.36 27.34 27.34 0.
015811388
after:
N Min Max Median Avg Stddev
x 5 27.53 27.61 27.59 27.576 0.
034351128
Unigine Sanctuary, 1280x800, fullscreen, medium shaders
before:
N Min Max Median Avg Stddev
x 5 10.1211 10.1238 10.1214 10.12192 0.
0011211601
after:
N Min Max Median Avg Stddev
x 5 10.4607 10.4637 10.4619 10.46206 0.
0012441865
RV530 shader-db:
total instructions in shared programs: 129643 -> 128038 (-1.24%)
instructions in affected programs: 45415 -> 43810 (-3.53%)
helped: 514
HURT: 43
total presub in shared programs: 4912 -> 5201 (5.88%)
presub in affected programs: 752 -> 1041 (38.43%)
helped: 40
HURT: 30
total omod in shared programs: 381 -> 383 (0.52%)
omod in affected programs: 6 -> 8 (33.33%)
helped: 1
HURT: 3
total temps in shared programs: 16904 -> 16841 (-0.37%)
temps in affected programs: 1377 -> 1314 (-4.58%)
helped: 81
HURT: 52
total lits in shared programs: 3555 -> 3550 (-0.14%)
lits in affected programs: 294 -> 289 (-1.70%)
helped: 13
HURT: 11
total cycles in shared programs: 194771 -> 193734 (-0.53%)
cycles in affected programs: 79079 -> 78042 (-1.31%)
helped: 452
HURT: 84
GAINED: shaders/glamor/82.shader_test FS
RV370 shader-db:
total instructions in shared programs: 82116 -> 81600 (-0.63%)
instructions in affected programs: 11888 -> 11372 (-4.34%)
helped: 273
HURT: 40
total temps in shared programs: 12438 -> 12441 (0.02%)
temps in affected programs: 692 -> 695 (0.43%)
helped: 36
HURT: 39
total cycles in shared programs: 128140 -> 127630 (-0.40%)
cycles in affected programs: 25838 -> 25328 (-1.97%)
helped: 266
HURT: 41
GAINED: shaders/0ad/12.shader_test FS
GAINED: shaders/CC3-tiberium-wars/314.shader_test FS
GAINED: shaders/lightsmark/16.shader_test FS
GAINED: shaders/sanctuary/159.shader_test FS
GAINED: shaders/sanctuary/162.shader_test FS
GAINED: shaders/sanctuary/51.shader_test FS
GAINED: shaders/sanctuary/54.shader_test FS
GAINED: shaders/trine/fp-422.shader_test FS
Partial fix for: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6661
Reviewed-by: Filip Gawin <filip.gawin@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24889>
Vlad Schiller [Thu, 10 Aug 2023 07:39:17 +0000 (08:39 +0100)]
pvr: Add 'info' PVR_DEBUG flag
This commit will add a new PVR_DEBUG flag that, when used,
it will display information about the display and render
devices in the common code (without adding dependencies)
Signed-off-by: Vlad Schiller <vlad-radu.schiller@imgtec.com>
Reviewed-by: Luigi Santivetti <luigi.santivetti@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24931>
Carsten Haitzler [Mon, 4 Sep 2023 08:55:34 +0000 (09:55 +0100)]
kmsro: Add hdlcd DPU
Arm hdlcd display units do exist on Juno SoC's. This is the
first time Mesa has had to deal with panfrost working on these SoC's,
thus have to add hdlcd support.
Signed-off-by: Carsten Haitzler <carsten.haitzler@foss.arm.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25027>
David Heidelberg [Mon, 4 Sep 2023 10:55:24 +0000 (16:25 +0530)]
ci: disable Google Freedreno farm, currently timeouting on all jobs
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25030>
Roman Stratiienko [Sat, 2 Sep 2023 19:00:32 +0000 (22:00 +0300)]
v3dv/android: Skip swapchain binding
ANV functionality was used as a reference. As stated in anv_BindImageMemory2:
Ignore this struct on Android, we cannot access swapchain
structures there.
Fixes 2 failing VTS test:
dEQP-VK.wsi.android.swapchain.create#image_swapchain_create_info
dEQP-VK.wsi.android.swapchain.simulate_oom#image_swapchain_create_info
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Roman Stratiienko [Sat, 2 Sep 2023 18:01:33 +0000 (21:01 +0300)]
v3dv: Migrate to vk_device_memory
It allows the reuse of some generic code, especially AHB logic.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Roman Stratiienko [Sat, 2 Sep 2023 15:35:09 +0000 (18:35 +0300)]
v3dv/android: Enable shared presentable image support
Functionality ensures gralloc won't allocate compressed buffer
incompatible with shared presentable image support.
Broadcom does not support compressed buffers and we can just enable the
feature without additional logic. Despite that, we add the logic here
so it can be replaced with the generic code someday.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Roman Stratiienko [Sat, 2 Sep 2023 15:18:50 +0000 (18:18 +0300)]
v3dv/android: Use u_gralloc code
Use generic u_gralloc logic instead of custom.
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25028>
Samuel Pitoiset [Fri, 1 Sep 2023 11:52:28 +0000 (13:52 +0200)]
radv: fix capturing indirect dispatches with SQTT
Looks like indirect dispatches require an event marker instead of an
event marker with dims. That makes sense somehow given the blocks size
is not known at record time with indirect dispatches.
This allows RGP to report correct block sizes.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24994>
Qiang Yu [Fri, 1 Sep 2023 07:21:11 +0000 (15:21 +0800)]
aco,radv,radeonsi: rename is_monolithic to merged_shader_compiled_separately
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24990>
Alexander Orzechowski [Sun, 3 Sep 2023 20:28:11 +0000 (16:28 -0400)]
radeonsi: Set PIPE_CONTEXT_LOSE_CONTEXT_ON_RESET for auxiliary contexts
This fixes a regression with context loss hardened compositors such as
wlroots or kwin where instead of continuing execution in a reset
situation, the process would be aborted. Although these applications set
their notification strategy to lose context on reset, radeonsi also
creates auxiliary contexts for its own use observed when
`egl_init_display` and `gbm_create_device` are called from these
compositors. Fix this by allowing a context loss on reset for these
auxiliary contexts.
Note: It seems this has been attempted before for another call site
creating auxiliary contexts, but this location was missed, hence the
fixed commit hash below.
Fixes: #9672
Fixes:
591aaea6486fca44feb65e46ba09aaa708315b50
Signed-off-by: Alexander Orzechowski <alex@ozal.ski>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/25023>
Dave Airlie [Thu, 31 Aug 2023 02:07:33 +0000 (12:07 +1000)]
nir/gather: add support for fbfetch and bindless image loads.
If a driver calls gather after lowering the uses_fbfetch_output
needs to be set properly if we have bindless image loads.
Fixes a regression seen calling gather info later in some llvmpipe
work.
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24987>
Timur Kristóf [Mon, 7 Aug 2023 09:19:49 +0000 (11:19 +0200)]
ac/nir/ngg: Extract nogs_export_vertex_params function.
Just for better code readability. No functional changes.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 20:39:22 +0000 (22:39 +0200)]
ac/nir/ngg: Wait for attribute ring stores in mesh shaders.
Make sure that both per-vertex and per-primitive attribute
ring stores are finished before position or primitive export
instructions are executed.
This is necessary because we need to ensure that mesh shader
waves work correctly when they have either vertex-only or
primitive-only waves.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 20:28:43 +0000 (22:28 +0200)]
ac/nir/ngg: Refactor mesh shader primitive export.
Cleanup the code that generates the two channels of the
primitive export instruction, and move storing the built-in
per-primitive outputs out to match how vertex attributes work.
Prepares the mesh shader lowering for a workaround that
affect export instructions.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 19:51:43 +0000 (21:51 +0200)]
ac/nir/ngg: Wait for attribute stores before VS/TES/GS pos0 export.
This is a HW bug workaround for some (all?) GFX11 chips.
On these chips, rasterization can start before the attribute ring
stores are finished, which can cause issues.
As a workaround, wait for attribute ring stores to finish
before doing the position export.
Mesh shaders will be taken care of in another commit.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 19:30:05 +0000 (21:30 +0200)]
ac/nir: Slightly refactor how pos0 exports are added when missing.
Prepares for a workaround. Makes it possible for this function
to not emit the pos0 export at all so that it can be emitted
by a subsequent call to the function later.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
Timur Kristóf [Tue, 22 Aug 2023 18:22:32 +0000 (20:22 +0200)]
ac/nir: Add done arg to ac_nir_export_position.
This prepares for a workaround where we won't need to add
the done flag to the last export in this function, because
it will be added in a subsequent call to the same function.
Cc: mesa-stable
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Qiang Yu <yuq825@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24574>
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