Michal Simek [Thu, 2 Nov 2017 09:21:08 +0000 (10:21 +0100)]
arm64: zynqmp: Use revision in dts file description
Trivial change.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jyotheeswar Reddy Mutthareddyvari [Mon, 2 Jan 2017 09:04:51 +0000 (14:34 +0530)]
arm64: zynqmp: PM: Specify power domains for DP related nodes
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is
causing genpd to trigger a power down request for DP domain, making all DP related
peripherals unusable. So assign power domains for all DP related nodes to enable
proper accounting of DP power domain usage.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Naga Sureshkumar Relli [Thu, 9 Mar 2017 14:30:13 +0000 (20:00 +0530)]
arm64: zynqmp: disable smmu
This patch disables the smmu and also removes the mmu-masters
Signed-off-by: Naga Sureshkumar Relli <nagasure@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nava kishore Manne [Fri, 27 Jan 2017 12:50:14 +0000 (18:20 +0530)]
arm64: zynqmp: rtc: Add calibration
This patch adds the calibration property with required value,
calculated based on rtc input crystal oscillator frequency (32.768Khz).
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Anurag Kumar Vulisha [Tue, 4 Jul 2017 14:33:42 +0000 (20:03 +0530)]
arm64: zynqmp: Add SMMU support for SATA IP
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below
SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0]
Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so
SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]
Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values
Read ID/ Write ID for Non-Data Port0 transfers = 0
Read ID/ Write ID for Data Port0 transfers = 1
Read ID/ Write ID for Non-Data Port1 transfers = 2
Read ID/ Write ID for Data Port1 transfers = 3
Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rob Herring [Wed, 22 Mar 2017 02:03:13 +0000 (21:03 -0500)]
arm64: dts: xilinx: fix PCI bus dtc warnings
dtc recently added PCI bus checks. Fix these warnings.
Signed-off-by: Rob Herring <robh@kernel.org>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: "Sören Brinkmann" <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 30 Aug 2017 06:06:11 +0000 (08:06 +0200)]
arm64: zynqmp: Add missing gpio property to dtsi
All gpio controllers should contain this property.
This property is not checked by the code that's why this issue wasn't
found earlier.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Hyun Kwon [Tue, 22 Aug 2017 01:54:29 +0000 (18:54 -0700)]
arm64: zynqmp: Update the GPU address size
The correct register size is 0x10000, otherwise
it overlaps with other register space.
Signed-off-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Madhurkiran Harikrishnan [Fri, 17 Feb 2017 12:14:45 +0000 (04:14 -0800)]
arm64: zynqmp: Add clock name for GPU
This patch will add names to the clocks used by GPU.
Signed-off-by: Madhurkiran Harikrishnan <madhurki@xilinx.com>
Reviewed-by: Hyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nava kishore Manne [Mon, 22 May 2017 06:35:17 +0000 (12:05 +0530)]
arm64: zynqmp: Label whole PL part as fpga_full region
This will simplify dt overlay structure for the whole PL.
Signed-off-by: Nava kishore Manne <navam@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 9 Feb 2017 13:45:12 +0000 (14:45 +0100)]
arm64: zynqmp: Fix broken architected timer interrupt trigger
Extract from Linux mainline patch:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.
The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: Duc Dang <dhdang@apm.com>
Acked-by: Carlo Caione <carlo@endlessm.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Soren Brinkmann [Tue, 22 Nov 2016 00:12:05 +0000 (16:12 -0800)]
arm64: zynqmp: PM: Add IRQ
PM callbacks are delivered to the NS OS. Let the PM driver handle the
IRQ and retrieve callback data from the secure HW.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jolly Shah [Wed, 14 Jun 2017 22:03:52 +0000 (15:03 -0700)]
arm64: zynqmp: Reduced min-residency time for idle state node
Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0.
Tried lower values 5ms and 8ms and it worked fine with Debug Off.
But to accommodate PM Debug On case, 10 ms is required. With this
change, low power idle state is into effect more frequently.
Measured boot time with PM debugs On and Off. No change observed
compared to 100ms value.
Signed-off-by: Jolly Shah <jollys@xilinx.com>
Acked-by: Will Wong <willw@xilinx.com>
Tested-by: Koteswararao Nayudu <kotin@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jyotheeswar Reddy [Fri, 13 Jan 2017 10:43:39 +0000 (16:13 +0530)]
arm64: zynqmp: DT: Fix typo in idle-states node definition
Fixed a typo in specifying "entry-method"
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Shubhrajyoti Datta [Mon, 13 Feb 2017 10:28:55 +0000 (15:58 +0530)]
arm64: zynqmp: Update the OPPs for cpu freq
Add operating-points-v2.
Signed-off-by: Shubhrajyoti Datta <shubhrajyoti.datta@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 6 Feb 2017 09:09:53 +0000 (10:09 +0100)]
arm64: zynqmp: Add references to cpu nodes
Add missing references to all cpu nodes.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 08:15:05 +0000 (09:15 +0100)]
arm64: zynqmp: Wire QSPI boot mode for SPL
ZynqMP qspi driver is on the way to mainline
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 31 Oct 2017 13:23:27 +0000 (14:23 +0100)]
arm64: zynqmp: Enable debug uart for zc1751 dc5
Showing uart earlier.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 2 Jun 2017 06:08:59 +0000 (08:08 +0200)]
arm64: zynqmp: Add new ID for RFSoC
This ID is available on zc1254.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 22 Aug 2017 12:58:53 +0000 (14:58 +0200)]
arm64: zynqmp: Add support for CG/EG/EV device detection
Version string has unused fields 31:20 which can be used for exporting 9
bits from efuse IPDISABLE regs to recognize eg/cg/ev devices.
These efuse bits are setup for certain devices.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 6 Nov 2017 11:55:59 +0000 (12:55 +0100)]
arm64: zynqmp: Use u32 type instead of uint32_t
Warning is reported by checkpatch.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 15 Feb 2017 08:41:53 +0000 (09:41 +0100)]
arm64: zynqmp: Add SD1 level shifter mode to alternative selection
Extend Kconfig to cover SD1 level shifter mode.
Reported-by: Jason Wu <jason.hy.wu@gmail.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 1 Aug 2017 10:54:50 +0000 (16:24 +0530)]
arm64: zynqmp: Enable config DEFINE_TCM_OCM_MMAP if CONFIG_MP defined
This modifies default value of config DEFINE_TCM_OCM_MMAP
to yes if CONFIG_MP is defined MP supports needs OCM and TCM
part of memory map.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 21 Oct 2016 10:58:17 +0000 (12:58 +0200)]
tools: mkimage: Extend mkimage to also include pmufw
The patch is adding external pmufw "Platform Management Unit firmware"
to boot.bin image. Boot.bin is a Xilinx format which bootrom is capable
to read and boot the system. pmufw is copied to the header data section
follows by u-boot-spl.bin. pmufw is consumed by PMU unit (Microblaze)
and SPL runs on a53-0.
This is generated command line when PMUFW_INIT_FILE is setup.
./tools/mkimage -T zynqmpimage -R ./"" -n
./"board/xilinx/zynqmp/pmufw.bin" -d spl/u-boot-spl.bin spl/boot.bin
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Siva Durga Prasad Paladugu [Thu, 13 Jul 2017 13:31:11 +0000 (19:01 +0530)]
arm64: zynqmp: Provide a Kconfig option to use specified memory for MMU table
This patch provides a Kconfig option to use specified
memory for MMU table using reserve_mmu platform specific
routine. Here we used TCM space for MMU table.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Siva Durga Prasad Paladugu [Tue, 1 Aug 2017 10:54:52 +0000 (16:24 +0530)]
arm64: zynqmp: mp: Correct the R5 release sequence
This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accessing TCM as with out this
A53 can do speculative and may result in ECC failures
if TCM's are not initialized. So, it is always better
to disable dcaches before accessing TCM and enable back.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com>
Reported-by: John Linn <linnj@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 07:48:48 +0000 (08:48 +0100)]
arm64: zynqmp: Remove slcr with mio status pin detection
This code is not used on this platform and it is not called.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 14:53:56 +0000 (15:53 +0100)]
ata: Fix ahci wording
s/achi_/ahci_/g
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Thu, 2 Nov 2017 09:54:48 +0000 (10:54 +0100)]
arm: zynq: Add mini u-boot configuration for zynq
Add configuration files/dtses for mini u-boot configurations which runs
out of OCM.
ram top is calculated from 0 that's why +#define CONFIG_SYS_SDRAM_BASE
0xfffc0000
+#define CONFIG_SYS_SDRAM_SIZE 0x40000
was hardcoded.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Thu, 2 Nov 2017 10:46:43 +0000 (11:46 +0100)]
arm: zynq: Sort dts names
Sort names.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Mon, 6 Nov 2017 08:16:05 +0000 (09:16 +0100)]
arm: zynq: Move ZYNQ_SERIAL to Kconfig
Move cadence/zynq serial driver via Kconfig
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Fri, 3 Nov 2017 14:53:56 +0000 (15:53 +0100)]
arm: zynq: Enable FPGA/FPGA_XILINX via Kconfig
Enabling fpga via Kconfig.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 3 Nov 2017 14:25:51 +0000 (15:25 +0100)]
arm: zynq: Return value from fdtdec_setup_memory_banksize directly
There is no reason not to return return value from above function.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 08:18:42 +0000 (09:18 +0100)]
arm: zynq: Add board support for cc108
cc108 board is wiring uart via PL which is good platform for SPL fpga
support.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Thu, 2 Nov 2017 09:46:15 +0000 (10:46 +0100)]
arm: zynq: Enable qspi for zc770_xm013
Enable qspi driver and flashes for this board.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 09:44:48 +0000 (10:44 +0100)]
arm: zynq: Enable MACRONIX flash for zc702/zc706/zc770 xm010
Enable MACRONIX flash for boards with QSPI enabled.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 09:40:57 +0000 (10:40 +0100)]
arm: zynq: Enable debug console on zc770 xm010 by default
Enable debug console.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 09:38:16 +0000 (10:38 +0100)]
arm: zynq: Enable bootz command for Xilinx platforms
bootz command is valid way how to boot Linux kernel. Enable it by
default.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 08:24:12 +0000 (09:24 +0100)]
arm: zynq: Sync location of DT properties with Linux
This is trival change which only ensures the same location with Linux
kernel.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 2 Nov 2017 08:29:15 +0000 (09:29 +0100)]
arm: zynq: Remove empty ifdef env structures from config file
All these configs were moved to Kconfig that's why this empty ifdef
structure is not needed anymore.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Sai Pavan Boddu [Mon, 6 Mar 2017 12:47:19 +0000 (18:17 +0530)]
arm: zynq: Add device-type property for zynq ethernet phy nodes
Mention device-type = "ethernet-phy", as qemu will need this in absence
of compatible.
Signed-off-by: Sai Pavan Boddu <saipava@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Chirag Parekh [Tue, 27 Dec 2016 16:37:58 +0000 (22:07 +0530)]
arm: zynq: Add SCL & SDA GPIO entries for recovery
Wire i2c pinmuxing gpio recovery for zc702.
Signed-off-by: Chirag Parekh <chiragp@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jeff Westfahl [Mon, 6 Nov 2017 08:34:46 +0000 (00:34 -0800)]
mtd: nand: zynq: Add a config option to use 1st stage bootloader timing
In legacy method, 1st stage bootloader was used to configure the HW
setting such as NAND timing. Hence, adding a config option in Zynq
NAND driver for the compatibility of device that using 1st stage
bootloder instead of U-boot SPL.
This commit is to add config option
CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS that allow NAND driver use
timing values set by the 1st stage bootloader, instead of the hard-coded
values in the Zynq NAND driver.
Signed-off-by: Jeff Westfahl <jeff.westfahl@ni.com>
Signed-off-by: Wilson Lee <wilson.lee@ni.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Cc: Keng Soon Cheah <keng.soon.cheah@ni.com>
Cc: Chen Yee Chew <chen.yee.chew@ni.com>
Cc: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Scott Wood <oss@buserror.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom McLeod [Thu, 28 Sep 2017 00:53:26 +0000 (17:53 -0700)]
arm: zynq: Add support for SYZYGY Hub board
Add the Zynq-based SYZYGY Hub board from Opal Kelly. The board
contains a Xilinx Zynq xc7z012s SoC, 1GB DDR3 RAM, and supports
booting from SD.
Signed-off-by: Tom McLeod <tom.mcleod@opalkelly.com>
Cc: Michal Simek <monstr@monstr.eu>
CC: Albert Aribaud <albert.u.boot@aribaud.net>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Heinrich Schuchardt [Thu, 12 Oct 2017 23:14:27 +0000 (01:14 +0200)]
arm64: zynqmp: remove unnecessary logical constraint
In
if (a || b)
else if (!a)
the constraint (!a) is always true if else is reached and
can be removed.
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Simon Glass [Mon, 27 Nov 2017 03:25:55 +0000 (20:25 -0700)]
test: Correct operation when tests pass
When tests pass an error message is printed because of a variable that is
not initialised. Fix this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Tue, 28 Nov 2017 01:07:47 +0000 (20:07 -0500)]
spl: TI: Do not default to SPL_FIT_IMAGE_TINY being enabled
This option prevents booting on am335x_evm at least along with most
likely other platforms.
Fixes:
337bbb629777 ("spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size")
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini [Mon, 27 Nov 2017 12:22:11 +0000 (07:22 -0500)]
Merge git://www.denx.de/git/u-boot-imx
Signed-off-by: Tom Rini <trini@konsulko.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:18 +0000 (00:02 +0530)]
configs: icore-rqs: Enable falcon mode
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:17 +0000 (00:02 +0530)]
engicam: imx6q: Return mmc dev 0 for icore
icorem6 has sd on usdhci1 which is devno 0 so return proper
devno from board_mmc_get_env_dev for icorem6 and icorem_6rqs
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:16 +0000 (00:02 +0530)]
i.MX6: engicam: Add imx6q/imx6ul boards for existing boards
Add new board names for existing board support
imx6q - icore and icore_rqs boards
imx6ul - geam6ul and isiot boards
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:15 +0000 (00:02 +0530)]
board: icore-rqs: Fix mmc get env device
As per USDHC boot eFUSE descriptions:
USDHC3 => devno 2
USDHC4 => devno 3
Linux will detect mmc0, mmc1, mmc2 based on the status
"okay" on usdhc so imx6qdl-icore-rqs.dtsi has enabled
usdhc1, usdhc3 and usdhc4.But U-Boot can detect based
on the aliases so add mmc1, mmc2 for usdhc3 and usdhc4
respectively and return the board_mmc_get_env_dev
by subtracting -1
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:14 +0000 (00:02 +0530)]
i.MX6UL: icore: Add SPL_OF_CONTROL support
Add OF_CONTROL support for SPL code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:13 +0000 (00:02 +0530)]
pinctrl: imx6ul: Fix pinctrl data overlapped with DT area
before relocation pinctrl data BSS is overlapping DT area,
when .data is using uninitialized global variable,
imx6_pinctrl_soc_info. So assign them flags ZERO_OFFSET_VALID
to prevent BSS overlap
Suggested-by: Lokesh Vutla <lokeshvutla@ti.com>
Reported-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:12 +0000 (00:02 +0530)]
i.MX6Q: icore: Add SPL_OF_CONTROL support
Add OF_CONTROL support for SPL code.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:11 +0000 (00:02 +0530)]
i.MX6Q: icorem6: Move spl load fit to common/spl
Move spl load fit code into common/spl
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Mon, 20 Nov 2017 18:32:10 +0000 (00:02 +0530)]
i.MX6: engicam: Move set_fdt_file to common
setenv_fdt_file to common code and set dtb based on
CONFIG_DEFAULT_DEVICE_TREE and cpu_type.
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Fabio Estevam [Wed, 22 Nov 2017 13:15:28 +0000 (11:15 -0200)]
mx6sxsabresd: Use PARTUUID to specify the rootfs location
mx6sxsabresd can run different kernel versions, such as NXP 4.1 or mainline.
Currently the rootfs location is passed via mmcblk number and the
problem with this approach is that the mmcblk number for the SD
card changes depending on the kernel version.
In order to avoid such issue, use the UUID method to specify the
rootfs location.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Reviewed-by: Lukasz Majewski <lukma@denx.de>
Fabio Estevam [Thu, 23 Nov 2017 12:55:33 +0000 (10:55 -0200)]
imx: Remove boolean parameter from wdog powerdown function
imx_set_wdog_powerdown() is always used to disable the power down
enable bit, so remove the boolean parameter of the function.
It is also a bit strange to write a boolean value into registers,
so this new version makes explicit that we are writing 0.
While at it, rename it to imx_wdog_disable_powerdown().
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Fabio Estevam [Thu, 23 Nov 2017 11:18:54 +0000 (09:18 -0200)]
imx: Also clear powerdown enable bit for WDOG3 on i.MX6ULL
Clear powerdown enable bit for WDOG3 on i.MX6ULL to avoid unwanted
kernel reboots.
Suggested-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Fabio Estevam [Thu, 23 Nov 2017 11:18:53 +0000 (09:18 -0200)]
mx6ull: Fix WDOG3 base address
i.MX6ULL has the same WDOG3 base address as i.MX6UL, so take this
into account in the base address definition.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Reviewed-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Stefano Babic <sbabic@denx.de>
Tom Rini [Sun, 26 Nov 2017 23:10:21 +0000 (18:10 -0500)]
Merge git://git.denx.de/u-boot-rockchip
Philipp Tomsich [Fri, 24 Nov 2017 13:44:59 +0000 (14:44 +0100)]
rockchip: defconfig: puma-rk3399: bypass ADC-based boot_mode check
The boot (and fallback/emergency boot) concept for the RK3399-Q7
differs from Rockchip's reference platforms.
On the RK3399-Q7, some of this functionality is present in the
bootloader itself (and configurable); some is backed in hardware by
the Qseven BIOS_DISABLE signal to invoke the final stages of fallbacks
(i.e. either an external boot bypassing on-module memories or falling
back to the BROM for USB recovery).
In summary: the ADC-based boot_mode check does not apply for the
RK3399-Q7 and we therefore disable it (in this commit) by setting
CONFIG_BOOT_MODE_REG to 0.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Fri, 24 Nov 2017 13:44:58 +0000 (14:44 +0100)]
rockchip: fix turning off boot-mode via Kconfig
The ROCKCHIP_BOOT_MODE_REG option defaults to a hex value, so 0 will
show as 0x0 if a default is provided and changed via Kconfig.
However, it still will show as 0, if no default is given.
Consequently, the "is set to something other than 0" test in a
Makefile is cumbersome. Instead this check can easily be performed in
the C-code.
This removes the ifeq-check from mach-rockchip/Makefile, adds a
matching #if-check to boot_mode.c and fixes resulting link issues (if
boot_mode.o was not included due to the Makefile check) by defining a
stub function (in case the functionality is not built in) for
setup_boot_mode in boot_mode.c.
Fixes: e306779 (rockchip: make boot_mode related codes reused across all platforms)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Wed, 22 Nov 2017 18:47:37 +0000 (19:47 +0100)]
rockchip: pinctrl: rk3399: add support for I2C8
The RK3399 has a total of 9 I2C controllers. To support these, the
enum in periph.h is extended and the mapping from the IRQ numbers to
the peripheral-ids is extended to ensure that pinctrl requests are
passed through to the function configuring the I2C pins.
For I2C8, the pinctrl is implemented and tested (on a RK3399-Q7) using
communication with the FAN53555 connected on I2C8.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Philipp Tomsich [Wed, 22 Nov 2017 18:45:04 +0000 (19:45 +0100)]
rockchip: clk: rk3399: change extract_bits to bitfield_extract
The RK3399 clk driver still has a left-over use of extract_bits, which
can be replaced by using bitfield_extract from include/bitfield.h.
This rewrites the invocation to use the shared function.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Fri, 24 Nov 2017 12:26:03 +0000 (13:26 +0100)]
spl: fit: add SPL_FIT_IMAGE_TINY config to reduce code-size
A minor code-size increase from the changes for tracking the os-type
of FIT images and from infrastructure for recording the loadables into
the the loaded FDT, broke the builds for sun50i and some OMAP2+ devices.
This change adds a new config option (enabled by default for
MACH_SUN50I, MACH_SUN50I_H5 and ARCH_OMAP2PLUS) that does skips these
processing steps (bringing code size down to below the limit
again). The os-type is not evaluated, but assumed to be IH_OS_UBOOT
(i.e. taking the code-paths intended for backward-compatibility).
Note that enabling this config option precludes any useful downstream
processing, such as utilising a special calling convention for ATF or
OPTEE, based on the os-type of the loadables.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:43 +0000 (21:29 +0200)]
rockchip: defconfig: lion-rk3368: sync up with SPL changes for ATF
This tracks the SPL changes for ATF for the RK3368-uQ7:
* renames ATF_SUPPORT to ATF
* drops CONFIG_SPL_ATF_TEXT_BASE (now dynamically retrieved from
the .itb file)
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:42 +0000 (21:29 +0200)]
rockchip: defconfig: puma-rk3399: sync up with SPL changes for ATF
This defconfig update makes use of the new features:
* CONFIG_ROCKCHIP_SPL_RESERVE_IRAM is now set to 0, as there is no
overlap between the M0 firmware and the ATF (we load this to DRAM
and relocate it to its final location within the ATF)
* tracks the ATF_SUPPORT -> ATF renaming
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:41 +0000 (21:29 +0200)]
rockchip: board: lion-rk3368: update .its file
For the RK3368-uQ7, we can now update the .its file to mark the
Trusted Firmware as out 'firmware' bootable and annotate both ATF and
U-Boot with an OS-type.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:40 +0000 (21:29 +0200)]
rockchip: board: puma-rk3399: update .its file to use new features
This commit updates the .its file for the RK3399-Q7 to use the new
features and demonstrates how to use those:
* it marks the ATF as the 'firmware'
* it tracks the OS-type for U-Boot and ATF
* it loads the PMU (M0) firmware to DRAM and records the location
to /fit-images (where our ATF reads it from)
With the handoff of the next-stage FDT to ATF in place, we can now use
this to pass information about the load addresses and names of each
loadables to ATF: now we can load the M0 firmware into DRAM and avoid
overwriting parts of the SPL stage. This is achieved by changing our
.its-file to use an available area of DRAM as the load-address.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:39 +0000 (21:29 +0200)]
rockchip: defconfig: firefly-rk3399: sync up with SPL changes for ATF
This tracks the SPL changes for ATF for the Firefly:
* renames ATF_SUPPORT to ATF
* drops CONFIG_SPL_ATF_TEXT_BASE
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:37 +0000 (21:29 +0200)]
spl: atf: drop the SPL_ATF_TEXT_BASE configuration item
The SPL_ATF_TEXT_BASE configuration item has become obsolete.
Remove it from Kconfig.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:36 +0000 (21:29 +0200)]
spl: rename config item SPL_ATF_SUPPORT to SPL_ATF
Having CONFIG_SPL_ATF seems more natural.
Rename it, while it it is easy and there's few boards that use it
(only RK3399 and RK3368 boards).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:35 +0000 (21:29 +0200)]
spl: atf: introduce spl_invoke_atf and make bl31_entry private
This adds a new interface spl_invoke_atf() that takes a spl_image_info
argument and then derives the necessary parameters for the ATF entry.
Based on the additional information recorded (into /fit-images) from
the FIT loadables, we can now easily locate the next boot stage.
We now pass a pointer to a FDT as the platform-specific parameter
pointer to ATF (so we don't run into the future headache of every
board/platform defining their own proprietary tag-structure), as
FDT access is already available in ATF.
With the necessary infrastructure in place, we can now update the
support for the ARM Trusted Firmware to dispatch into the
spl_invoke_atf function only if a IH_OS_ARM_TRUSTED_FIRMWARE image is
loaded.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:34 +0000 (21:29 +0200)]
spl: fit: implement recording of loadables into /fit-images
If a FDT was loaded (e.g. to append it to U-Boot image), we store it's
address and record information for all loadables into this FDT. This
allows us to easily keep track of images for multiple privilege levels
(e.g. with ATF) or of firmware images preloaded into temporary
locations (e.g. PMU firmware that may overlap the SPL stage).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:33 +0000 (21:29 +0200)]
spl: fit: implement fdt_record_loadable
During the loading of more complex FIT images (e.g. when the invoked
next stage needs to find additional firmware for a power-management
core... or if there are multiple images for different privilege levels
started in parallel), it is helpful to create a record of what images
are loaded where: if a FDT is loaded for one of the next stages, it
can be used to convey the status and location of loadables.
This adds a fdt_record_loadable() function that can be invoked to
record the status of each loadable below the /fit-images path.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:32 +0000 (21:29 +0200)]
spl: fit: simplify logic for FDT loading for non-OS boots
To better support bootin through an ATF or OPTEE, we need to
streamline some of the logic for when the FDT is appended to an image:
depending on the image type, we'd like to append the FDT not at all
(the case for the OS boot), to the 'firmware' image (if it is a
U-Boot) or to one of the loadables (if the 'firmware' is an ATF, an
OPTEE, or some other image-type and U-Boot is listed in the
loadabled).
To achieve this goal, we drop the os_boot flag and track the type of
image loaded. If it is of type IH_OS_U_BOOT, we append the FDT.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Acked-by: York Sun <york.sun@nxp.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:31 +0000 (21:29 +0200)]
spl: change load_addr and entry_point to uintptr_t
Mainly a stylistic change: convert the load_addr and entry_point
fields of struct spl_image_info to uintptr_t (from ulong).
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:30 +0000 (21:29 +0200)]
spl: add a fdt_addr field to spl_image_info
When loading a full U-Boot with detached device-tree using the SPL FIT
backend, we should store the address of the FDT loaded as part of the
SPL image info: this allows us to fixup the FDT with additional info
we may want to propagate onward.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Philipp Tomsich [Wed, 13 Sep 2017 19:29:29 +0000 (21:29 +0200)]
image: add IH_OS_ARM_TRUSTED_FIRMWARE for ARM Trusted Firmware
To boot on ARMv8 systems with ARM Trusted Firmware, we need to
assemble an ATF-specific parameter structure and also provide the
address of the images started by ATF (e.g. BL3-3, which may be the
full U-Boot).
To allow us to identify an ARM Trusted Firmware contained in a FIT
image, this adds the necessary definitions.
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Fri, 24 Nov 2017 16:45:15 +0000 (11:45 -0500)]
Merge git://git.denx.de/u-boot-arc
Alexey Brodkin [Fri, 17 Nov 2017 13:02:17 +0000 (16:02 +0300)]
arc: cache: Add required NOPs after invalidation of instruction cache
As per ARC HS databook (see chapter 5.3.3.2) it is required to add
3 NOPs after each write to IC_IVIC which we do from now on.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Alexey Brodkin [Fri, 17 Nov 2017 12:53:20 +0000 (15:53 +0300)]
arc: bootm: Move slave cores kick-starting under !fake
Currently slave cores will be kick-started even if we want
to dry run bootm which is not what we really want.
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Cc: Eugeniy Paltsev <paltsev@synopsys.com>
Eugeniy Paltsev [Mon, 16 Oct 2017 13:21:32 +0000 (16:21 +0300)]
ARC: HSDK: introduce CREG GPIO driver
The HSDK can manage some pins via CREG registers block.
Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
Tom Rini [Fri, 24 Nov 2017 03:48:35 +0000 (22:48 -0500)]
Merge git://git.denx.de/u-boot-dm
Simon Glass [Mon, 13 Nov 2017 04:52:29 +0000 (21:52 -0700)]
binman: Return non-zero exit code on test failure
Return exit code 1 when test fail so that callers can detect this.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:28 +0000 (21:52 -0700)]
binman: Add add test for using an Intel MRC binary
MRC (Memory Reference Code) is a binary blob used to set up the SDRAM
controller on some Intel boards. Add a test for this feature.
With this test coverage on binman is back up to 100%.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:27 +0000 (21:52 -0700)]
binman: Add add test for SPL with a microcode pointer
Add a test for this feature. It allows SPL to hold a pointer to the
microcode block. This is used for 64-bit U-Boot on x86.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:26 +0000 (21:52 -0700)]
binman: Add a test for x86-start16-spl
This allows us to put the 16-bit x86 start-up code in SPL. Add a test for
it.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:25 +0000 (21:52 -0700)]
binman: Add test for u-boot-spl-bss-pad
Add a test that we can pad the BSS with zero bytes.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:24 +0000 (21:52 -0700)]
binman: Check for files missing from test coverage
Files that are never imported are not shown in the test-coverage report.
Detect these and show an error.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:23 +0000 (21:52 -0700)]
binman: Increase test coverage back to 100%
Make a minor tweak to fix test coverage.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:22 +0000 (21:52 -0700)]
binman: Add a main program to the tests
Add a main program so that the tests can be executed directly, without
going through the main binman program.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:21 +0000 (21:52 -0700)]
binman: Add tests for importlib availability
Add a test that the 'entry' module works with or without importlib.
The tests are numbered so that they are executed in the correct order.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:20 +0000 (21:52 -0700)]
binman: Set up 'entry' to permit full test coverage
There is a little check at the top of entry.py which decides if importlib
is available. At present this has no test coverage. To add this we will
need to import the module twice, once with importlib and once without.
In preparation for allowing a test to control the importing of this
module, remove all global imports of the 'entry' module.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:19 +0000 (21:52 -0700)]
binman: Append to PYTHONPATH when running test coverage
Rather that overwrite this, append to it, in case the caller has already
set up the path correctly.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:17 +0000 (21:52 -0700)]
dtoc: Fix up tests
The tool has changed slightly since it was originally written. Update the
tests to suit.
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:15 +0000 (21:52 -0700)]
buildman: Fix up tests
The tests were broken by two separate commits which adjusted the output
when boards are listed. Fix this by adding back a PowerPC board and
putting the name of each board in the test.
Fixes:
b9f7d881 (powerpc, 5xx: remove some "5xx" remains)
Fixes:
8d7523c5 (buildman: Allow showing the list of boards with -n)
Signed-off-by: Simon Glass <sjg@chromium.org>
Simon Glass [Mon, 13 Nov 2017 04:52:14 +0000 (21:52 -0700)]
buildman: Allow skipping of tests which use the network
Accessing the network slows down the test and limits the environment in
which it can be run. Add an option to disable network tests.
Signed-off-by: Simon Glass <sjg@chromium.org>