Ju-Zhe Zhong [Sun, 29 Jan 2023 23:26:25 +0000 (07:26 +0800)]
RISC-V: Add vluxei8 C++ API intrinsic testcase
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vluxei8-1.C: New test.
* g++.target/riscv/rvv/base/vluxei8-2.C: New test.
* g++.target/riscv/rvv/base/vluxei8-3.C: New test.
* g++.target/riscv/rvv/base/vluxei8_mu-1.C: New test.
* g++.target/riscv/rvv/base/vluxei8_mu-2.C: New test.
* g++.target/riscv/rvv/base/vluxei8_mu-3.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tu-1.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tu-2.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tu-3.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tum-1.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tum-2.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tum-3.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tumu-2.C: New test.
* g++.target/riscv/rvv/base/vluxei8_tumu-3.C: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 23:24:01 +0000 (07:24 +0800)]
RISC-V: Add vsuxei* C++ API intrinsics testcases
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsuxei16-1.C: New test.
* g++.target/riscv/rvv/base/vsuxei16-2.C: New test.
* g++.target/riscv/rvv/base/vsuxei16-3.C: New test.
* g++.target/riscv/rvv/base/vsuxei32-1.C: New test.
* g++.target/riscv/rvv/base/vsuxei32-2.C: New test.
* g++.target/riscv/rvv/base/vsuxei32-3.C: New test.
* g++.target/riscv/rvv/base/vsuxei64-1.C: New test.
* g++.target/riscv/rvv/base/vsuxei64-2.C: New test.
* g++.target/riscv/rvv/base/vsuxei64-3.C: New test.
* g++.target/riscv/rvv/base/vsuxei8-1.C: New test.
* g++.target/riscv/rvv/base/vsuxei8-2.C: New test.
* g++.target/riscv/rvv/base/vsuxei8-3.C: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 23:18:34 +0000 (07:18 +0800)]
RISC-V: Add vsuxei C API intrinsic testcase
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsuxei16_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei16_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei16_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsuxei16_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei16_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei16_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsuxei32_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei32_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei32_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsuxei32_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei32_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei32_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsuxei64_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei64_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei64_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsuxei64_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei64_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei64_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsuxei8_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei8_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei8_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsuxei8_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsuxei8_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsuxei8_v_m-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 23:16:58 +0000 (07:16 +0800)]
RISC-V: Add vsoxei C API intrinsic testcase
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vsoxei16_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei16_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei16_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsoxei16_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei16_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei16_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsoxei32_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei32_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei32_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsoxei32_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei32_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei32_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsoxei64_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei64_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei64_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsoxei64_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei64_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei64_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vsoxei8_v-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei8_v-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei8_v-3.c: New test.
* gcc.target/riscv/rvv/base/vsoxei8_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsoxei8_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsoxei8_v_m-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 23:14:44 +0000 (07:14 +0800)]
RISC-V: Add vsoxei32 && vsoxei64 C++ API intrinsic testcase
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsoxei32-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei32-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei32-3.C: New test.
* g++.target/riscv/rvv/base/vsoxei64-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei64-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei64-3.C: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 23:11:40 +0000 (07:11 +0800)]
RISC-V: Add vsoxei8 && vsoxei16 C++ API intrinsic testcase
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsoxei16-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei16-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei16-3.C: New test.
* g++.target/riscv/rvv/base/vsoxei8-1.C: New test.
* g++.target/riscv/rvv/base/vsoxei8-2.C: New test.
* g++.target/riscv/rvv/base/vsoxei8-3.C: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 23:08:30 +0000 (07:08 +0800)]
RISC-V: Add vluxei64 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vluxei64_v-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei64_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 23:06:32 +0000 (07:06 +0800)]
RISC-V: Add vluxei32 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vluxei32_v-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei32_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 22:56:39 +0000 (06:56 +0800)]
RISC-V: Add vluxei16 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vluxei16_v-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei16_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:52:35 +0000 (23:52 +0800)]
RISC-V: Add vluxei8 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vluxei8_v-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vluxei8_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:50:34 +0000 (23:50 +0800)]
RISC-V: Add vloxei64 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vloxei64_v-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei64_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:48:46 +0000 (23:48 +0800)]
RISC-V: Add vloxei32 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vloxei32_v-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei32_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:46:54 +0000 (23:46 +0800)]
RISC-V: Add vloxei16 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vloxei16_v-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei16_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:44:24 +0000 (23:44 +0800)]
RISC-V: Add vloxei8 C API intrinsic testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vloxei8_v-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_m-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_m-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_m-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vloxei8_v_tumu-3.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:37:21 +0000 (23:37 +0800)]
RISC-V: Add indexed loads/stores constraints testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vlxei-vsxei-constraint-1.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:34:57 +0000 (23:34 +0800)]
RISC-V: Add VSETVL testcases for indexed loads/stores.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-72.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-76.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-77.c: New test.
Ju-Zhe Zhong [Sun, 29 Jan 2023 15:32:33 +0000 (23:32 +0800)]
RISC-V: Add indexed loads/stores C/C++ intrinsic support
gcc/ChangeLog:
* config/riscv/riscv-protos.h (get_vector_mode): New function.
* config/riscv/riscv-v.cc (get_vector_mode): Ditto.
* config/riscv/riscv-vector-builtins-bases.cc (enum lst_type): New enum.
(class loadstore): Adjust for indexed loads/stores support.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: New function declare.
* config/riscv/riscv-vector-builtins-functions.def (vluxei8): Ditto.
(vluxei16): Ditto.
(vluxei32): Ditto.
(vluxei64): Ditto.
(vloxei8): Ditto.
(vloxei16): Ditto.
(vloxei32): Ditto.
(vloxei64): Ditto.
(vsuxei8): Ditto.
(vsuxei16): Ditto.
(vsuxei32): Ditto.
(vsuxei64): Ditto.
(vsoxei8): Ditto.
(vsoxei16): Ditto.
(vsoxei32): Ditto.
(vsoxei64): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc
(struct indexed_loadstore_def): New class.
(SHAPE): Ditto.
* config/riscv/riscv-vector-builtins-shapes.h: Ditto.
* config/riscv/riscv-vector-builtins.cc (required_extensions_p): Adjust
for indexed loads/stores support.
(check_required_extensions): Ditto.
(rvv_arg_type_info::get_base_vector_type): New function.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_builder::add_unique_function): Adjust for indexed loads/stores
support.
(function_expander::use_exact_insn): New function.
* config/riscv/riscv-vector-builtins.h (enum rvv_base_type): Adjust for
indexed loads/stores support.
(struct rvv_arg_type_info): Ditto.
(function_expander::index_mode): New function.
(function_base::apply_tail_policy_p): Ditto.
(function_base::apply_mask_policy_p): Ditto.
* config/riscv/vector-iterators.md (unspec): New unspec.
* config/riscv/vector.md (unspec): Ditto.
(@pred_indexed_<order>load<VNX1_QHSD:mode><VNX1_QHSDI:mode>): New
pattern.
(@pred_indexed_<order>store<VNX1_QHSD:mode><VNX1_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
(@pred_indexed_<order>store<VNX2_QHSD:mode><VNX2_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
(@pred_indexed_<order>store<VNX4_QHSD:mode><VNX4_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
(@pred_indexed_<order>store<VNX8_QHSD:mode><VNX8_QHSDI:mode>): Ditto.
(@pred_indexed_<order>load<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
(@pred_indexed_<order>store<VNX16_QHS:mode><VNX16_QHSI:mode>): Ditto.
(@pred_indexed_<order>load<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
(@pred_indexed_<order>store<VNX32_QH:mode><VNX32_QHI:mode>): Ditto.
(@pred_indexed_<order>load<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
(@pred_indexed_<order>store<VNX64_Q:mode><VNX64_Q:mode>): Ditto.
Flavio Cruz [Fri, 27 Jan 2023 03:45:27 +0000 (22:45 -0500)]
Add support for x86_64-*-gnu-* targets to build x86_64 gnumach/hurd
Tested by building a toolchain and compiling gnumach for x86_64 [1].
This is the basic version without unwind support which I think is only
required to implement exceptions.
[1]
https://github.com/flavioc/cross-hurd/blob/master/bootstrap-kernel.sh.
gcc/ChangeLog:
* config.gcc: Recognize x86_64-*-gnu* targets and include
i386/gnu64.h.
* config/i386/gnu64.h: Define configuration for new target
including ld.so location.
libgcc/ChangeLog:
* config.host: Recognize x86_64-*-gnu* targets.
* config/i386/gnu-unwind.h: Update to handle __x86_64__ with a
TODO for now.
Signed-off-by: Flavio Cruz <flaviocruz@gmail.com>
Philipp Tomsich [Wed, 25 Jan 2023 19:15:14 +0000 (20:15 +0100)]
aarch64: Update Ampere-1A (-mcpu=ampere1a) to include SM4
gcc/ChangeLog:
* config/aarch64/aarch64-cores.def (AARCH64_CORE): Update
ampere1a to include SM4.
Rainer Orth [Mon, 30 Jan 2023 13:26:06 +0000 (14:26 +0100)]
testsuite: Restore TORTURE_OPTIONS in gm2/warnings/returntype/fail/warnings-returntype-fail.exp
Between
20230126 and
20230127, 1100+ gm2 tests started to FAIL for the
non-default multilib, e.g.
FAIL: gm2/calling-c/datatypes/unbounded/run/pass/m.mod compilation,
{additional_flags= -O0 -g -Werror=return-type } timeout=10
UNRESOLVED: gm2/calling-c/datatypes/unbounded/run/pass/m.mod execution,
{additional_flags= -O0 -g -Werror=return-type } timeout=10
FAIL: gm2/case/pass/testcase1.mod, -O0 -g -Werror=return-type
[...]
cc1gm2: warning: '-Werror=' argument '-Werror=return-type' is not valid for
Modula-2
I'm seeing this on all of Solaris/x86, Solaris/SPARC, and Linux/x86_64.
I could trace this to
gm2/warnings/returntype/fail/warnings-returntype-fail.exp not properly
restoring TORTURE_OPTIONS.
Tested on i386-pc-solaris2.11 and sparc-sun-solaris2.11.
2023-01-30 Rainer Orth <ro@CeBiTec.Uni-Bielefeld.DE>
gcc/testsuite:
* gm2/warnings/returntype/fail/warnings-returntype-fail.exp: Save,
restore TORTURE_OPTIONS.
Andrew Pinski [Sat, 28 Jan 2023 18:27:08 +0000 (18:27 +0000)]
Fix PR 108582: ICE due to PHI-OPT removing a still in use ssa_name.
This patch adds a check in match_simplify_replacement to make sure the middlebb
does not have any phi-nodes as we don't currently move those.
This was just a thinko from before.
Ok? Bootstrapped and tested on x86_64-linux-gnu with no regressions?
PR tree-optimization/108582
gcc/ChangeLog:
* tree-ssa-phiopt.cc (match_simplify_replacement): Add check
for middlebb to have no phi nodes.
gcc/testsuite/ChangeLog:
* gcc.dg/pr108582-1.c: New test.
Richard Biener [Mon, 30 Jan 2023 08:25:23 +0000 (09:25 +0100)]
tree-optimization/108574 - wrong-code with PRE PHI node processing
The PR108523 was too optimistic in replacing the same value with
an equivalence from a possibly not taken edge. The following
rectifies this and instead refrains from using the equivalence in
the problematic cases.
PR tree-optimization/108574
* tree-ssa-sccvn.cc (visit_phi): Instead of swapping
sameval and def, ignore the equivalence if there's the
danger of oscillating between two values.
* gcc.dg/torture/pr108574-1.c: New testcase.
* gcc.dg/torture/pr108574-2.c: Likewise.
* gcc.dg/torture/pr108574-3.c: Likewise.
Andreas Schwab [Wed, 25 Jan 2023 11:00:09 +0000 (12:00 +0100)]
riscv: Enable -fasynchronous-unwind-tables by default on Linux
This follows the example of aarch64.
gcc/:
* common/config/riscv/riscv-common.cc
(riscv_option_optimization_table)
[TARGET_DEFAULT_ASYNC_UNWIND_TABLES]: Enable
-fasynchronous-unwind-tables and -funwind-tables.
* config.gcc (riscv*-*-linux*): Define
TARGET_DEFAULT_ASYNC_UNWIND_TABLES.
YunQiang Su [Fri, 6 Jan 2023 10:15:28 +0000 (18:15 +0800)]
Set CROSS_SYSTEM_HEADER_DIR according includedir
For cross building with option:
--sysroot=/ --prefix=/usr --includedir=/usr/<triple>
just like Debian does, fixinc.sh will use the wrong header files
from /usr/include.
gcc/
* Makefile.in (CROSS_SYSTEM_HEADER_DIR): set according the
value of includedir.
Richard Biener [Mon, 30 Jan 2023 07:20:03 +0000 (08:20 +0100)]
ipa/108511 - relax assert for undefined local statics
Since we no longer promote undefined local statics extern the
assert in possibly_call_in_translation_unit_p triggers. The
following relaxes it according to Honzas advice.
PR ipa/108511
* cgraph.cc (possibly_call_in_translation_unit_p): Relax
assert.
liuhongt [Sat, 28 Jan 2023 14:27:17 +0000 (22:27 +0800)]
Change AVX512FP16 to AVX512-FP16 in the document.
The official name is AVX512-FP16.
gcc/ChangeLog:
* config/i386/i386.opt: Change AVX512FP16 to AVX512-FP16.
* doc/invoke.texi: Ditto.
GCC Administrator [Mon, 30 Jan 2023 00:16:41 +0000 (00:16 +0000)]
Daily bump.
Mikael Morin [Sun, 29 Jan 2023 20:57:24 +0000 (21:57 +0100)]
fortran: Set name for *LOC default BACK argument [PR108450]
This change fixes an ICE caused by the double resolution of MINLOC,
MAXLOC and FINDLOC expressions which get a default value for the BACK
argument at resolution time. That argument is added without name,
and argument reordering code is not prepared to handle unnamed arguments
coming after named ones, so the second resolution causes a NULL pointer
dereference.
The problem is fixed by explicitly setting the argument name.
PR fortran/108450
gcc/fortran/ChangeLog:
* check.cc (gfc_check_minloc_maxloc): Explicitly set argument name.
(gfc_check_findloc): Ditto.
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/minmaxloc_1.f90: New test.
Jerry DeLisle [Sun, 29 Jan 2023 04:00:34 +0000 (20:00 -0800)]
ICE in gfc_free_namespace. ice-on-invalid.
PR fortran/103506
gcc/fortran/ChangeLog:
* parse.cc (parse_module): Remove use of a bool error value
that prevented proper setting of the namespace pointer.
gcc/testsuite/ChangeLog:
* gfortran.dg/pr103506_1.f90: New test.
Jan Hubicka [Sun, 29 Jan 2023 00:27:26 +0000 (01:27 +0100)]
Fix find_always_executed_bbs handling of infinite loops
This patch fixes the stupid typo info find_always_executed_bbs which made
all edges to be considered as ones closing infinite loops. This fix has
somewhat snowballed as, comparing it to finite_function_p, I noticed a
divergence in handling of volatile asms (find_always_executed_bbs is conservative
and thinks that volatile statement may return or do EH, but it is really
impossible and elsewhere we expects that we dont) and I also noticed
a bug in handling early returns which made some loops to be missed.
I also noticed that function assumes that irreducible loops are marked in CFG
which is not necessarily true and it is easy to detect them during the walk.
Bootstrapped/regtested x86_64-linux, comitted.
gcc/ChangeLog:
2023-01-29 Jan Hubicka <hubicka@ucw.cz>
* ipa-utils.cc: Include calls.h, cfgloop.h and cfganal.h
(stmt_may_terminate_function_p): If assuming return or EH
volatile asm is safe.
(find_always_executed_bbs): Fix handling of terminating BBS and
infinite loops; add debug output.
* tree-ssa-alias.cc (stmt_kills_ref_p): Fix debug output
gcc/testsuite/ChangeLog:
2023-01-29 Jan Hubicka <hubicka@ucw.cz>
* gcc.dg/ipa/ipa-sra-30.c: New test.
* gcc.dg/ipa/ipa-sra-31.c: New test.
* gcc.dg/tree-ssa/modref-dse-7.c: New test.
GCC Administrator [Sun, 29 Jan 2023 00:17:14 +0000 (00:17 +0000)]
Daily bump.
Philipp Tomsich [Sat, 28 Jan 2023 23:07:09 +0000 (00:07 +0100)]
aarch64: Correct the maximum shift amount for shifted operands
The aarch64 ISA specification allows a left shift amount to be applied
after extension in the range of 0 to 4 (encoded in the imm3 field).
This is true for at least the following instructions:
* ADD (extend register)
* ADDS (extended register)
* SUB (extended register)
The result of this patch can be seen, when compiling the following code:
uint64_t myadd(uint64_t a, uint64_t b)
{
return a+(((uint8_t)b)<<4);
}
Without the patch the following sequence will be generated:
0000000000000000 <myadd>:
0:
d37c1c21 ubfiz x1, x1, #4, #8
4:
8b000020 add x0, x1, x0
8:
d65f03c0 ret
With the patch the ubfiz will be merged into the add instruction:
0000000000000000 <myadd>:
0:
8b211000 add x0, x0, w1, uxtb #4
4:
d65f03c0 ret
gcc/ChangeLog:
* config/aarch64/aarch64.cc (aarch64_uxt_size): fix an
off-by-one in checking the permissible shift-amount.
Gerald Pfeifer [Sat, 28 Jan 2023 22:19:46 +0000 (23:19 +0100)]
doc: Update link to the AVR-Libc manual
gcc/ChangeLog:
* doc/extend.texi (Named Address Spaces): Update link to the
AVR-Libc manual.
Gerald Pfeifer [Sat, 28 Jan 2023 22:07:01 +0000 (23:07 +0100)]
libstdc++: Update links in the "Contributing" manual
libstdc++-v3/ChangeLog:
* doc/xml/manual/appendix_contributing.xml: Adjust link to
ISO C++ standard at ANSI.
Move link to www.open-std.org to https.
* doc/html/manual/appendix_contributing.html: Regenerate.
Harald Anlauf [Tue, 24 Jan 2023 21:36:25 +0000 (22:36 +0100)]
Fortran: fix ICE in compare_bound_int [PR108527]
gcc/fortran/ChangeLog:
PR fortran/108527
* resolve.cc (compare_bound_int): Expression to compare must be of
type INTEGER.
(compare_bound_mpz_t): Likewise.
(check_dimension): Fix comment on checks applied to array section
and clean up associated logic.
gcc/testsuite/ChangeLog:
PR fortran/108527
* gfortran.dg/pr108527.f90: New test.
Co-authored-by: Steven G. Kargl <kargl@gcc.gnu.org>
Harald Anlauf [Sat, 28 Jan 2023 16:59:23 +0000 (17:59 +0100)]
Fortran: diagnose USE associated symbols in COMMON blocks [PR108453]
gcc/fortran/ChangeLog:
PR fortran/108453
* match.cc (gfc_match_common): A USE associated name shall not appear
in a COMMON block (F2018:C8121).
gcc/testsuite/ChangeLog:
PR fortran/108453
* gfortran.dg/common_27.f90: New test.
Gerald Pfeifer [Sat, 28 Jan 2023 18:26:46 +0000 (19:26 +0100)]
doc: Fix markup
gcc/ChangeLog:
* doc/standards.texi (Standards): Fix markup.
Gerald Pfeifer [Sat, 28 Jan 2023 18:23:35 +0000 (19:23 +0100)]
doc: Update link to Objective-C book
gcc/ChangeLog:
* doc/standards.texi (Standards): Update link to Objective-C book.
Jonathan Yong [Wed, 11 Jan 2023 09:51:02 +0000 (09:51 +0000)]
PR c/108192 - Fix test for mingw
gcc/testsuite/ChangeLog:
PR c/108192
* g++.dg/cet-notrack-1.C: Use puts instead of printf,
so function call is not mangled by __mingw_printf when
doing assembly symbol inspection.
Signed-off-by: Jonathan Yong <10walls@gmail.com>
Jonathan Yong [Sun, 8 Jan 2023 01:28:34 +0000 (01:28 +0000)]
PR c/108150 - Fix alignment test for Windows targets
gcc/testsuite/ChangeLog:
PR c/108150
* gcc.dg/attr-aligned.c: Make errors emitted on Windows
target same as on Linux.
Signed-off-by: Jonathan Yong <10walls@gmail.com>
Iain Sandoe [Sat, 28 Jan 2023 09:38:23 +0000 (09:38 +0000)]
Modula-2: Claim Wreturn-type in lang.opt.
Modula-2 handles this warning so that we need to claim it in the
language options.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
gcc/m2/ChangeLog:
* lang.opt: Claim Wreturn-type.
Gerald Pfeifer [Sat, 28 Jan 2023 10:49:13 +0000 (11:49 +0100)]
libstdc++: Move sourceforge.net links to https
libstdc++-v3/ChangeLog:
* doc/xml/manual/documentation_hacking.xml: Move sourceforge.net
links to https.
* doc/html/manual/documentation_hacking.html: Regenerate.
Gerald Pfeifer [Sat, 28 Jan 2023 10:35:40 +0000 (11:35 +0100)]
doc: Update reference to AddressSanitizer
gcc/ChangeLog:
* doc/invoke.texi (Instrumentation Options): Update reference to
AddressSanitizer.
Gerald Pfeifer [Sat, 28 Jan 2023 10:23:16 +0000 (11:23 +0100)]
doc: Update Go1 link
gcc/ChangeLog:
* doc/standards.texi: Update Go1 link.
Gerald Pfeifer [Sat, 28 Jan 2023 10:12:57 +0000 (11:12 +0100)]
libstdc++: Switch open-std.org to https (ABI manual)
libstdc++-v3/ChangeLog:
* doc/xml/manual/abi.xml: Update www.open-std.org link to https.
* doc/html/manual/abi.html: Regenerate.
Ju-Zhe Zhong [Fri, 27 Jan 2023 23:27:57 +0000 (07:27 +0800)]
RISC-V: Add vlse/vsse C/C++ intrinsic testcases
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vlse-1.C: New test.
* g++.target/riscv/rvv/base/vlse_tu-1.C: New test.
* g++.target/riscv/rvv/base/vlse_tum-1.C: New test.
* g++.target/riscv/rvv/base/vlse_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vsse-1.C: New test.
* gcc.target/riscv/rvv/base/vlse-1.c: New test.
* gcc.target/riscv/rvv/base/vlse-2.c: New test.
* gcc.target/riscv/rvv/base/vlse-3.c: New test.
* gcc.target/riscv/rvv/base/vlse-vsse-constraint-1.c: New test.
* gcc.target/riscv/rvv/base/vlse_m-1.c: New test.
* gcc.target/riscv/rvv/base/vlse_m-2.c: New test.
* gcc.target/riscv/rvv/base/vlse_m-3.c: New test.
* gcc.target/riscv/rvv/base/vlse_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vlse_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vlse_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vlse_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vlse_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vlse_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vlse_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vlse_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vlse_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vlse_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vlse_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vlse_tumu-3.c: New test.
* gcc.target/riscv/rvv/base/vsse-1.c: New test.
* gcc.target/riscv/rvv/base/vsse-2.c: New test.
* gcc.target/riscv/rvv/base/vsse-3.c: New test.
* gcc.target/riscv/rvv/base/vsse_m-1.c: New test.
* gcc.target/riscv/rvv/base/vsse_m-2.c: New test.
* gcc.target/riscv/rvv/base/vsse_m-3.c: New test.
Ju-Zhe Zhong [Fri, 27 Jan 2023 23:26:08 +0000 (07:26 +0800)]
RISC-V: Add vlse/vsse intrinsics support
gcc/ChangeLog:
* config/riscv/predicates.md (pmode_reg_or_0_operand): New predicate.
* config/riscv/riscv-vector-builtins-bases.cc (class loadstore):
Support vlse/vsse.
(BASE): Ditto.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlse): New class.
(vsse): New class.
* config/riscv/riscv-vector-builtins.cc
(function_expander::use_contiguous_load_insn): Support vlse/vsse.
* config/riscv/vector.md (@pred_strided_load<mode>): New md pattern.
(@pred_strided_store<mode>): Ditto.
Ju-Zhe Zhong [Fri, 27 Jan 2023 22:57:14 +0000 (06:57 +0800)]
RISC-V: Remove redundant attributes [NFC]
gcc/ChangeLog:
* config/riscv/vector.md (tail_policy_op_idx): Remove.
(mask_policy_op_idx): Remove.
(avl_type_op_idx): Remove.
Jerry DeLisle [Sat, 21 Jan 2023 23:47:19 +0000 (15:47 -0800)]
Fortran tests: Revise line end tests allowing windows testing.
gcc/testsuite/ChangeLog:
* gfortran.dg/ISO_Fortran_binding_17.f90: Replace (\n|\r\n|\r)
with (\r*\n+).
* gfortran.dg/array_temporaries_2.f90: Likewise.
* gfortran.dg/bind-c-contiguous-1.f90: Likewise.
* gfortran.dg/bind-c-contiguous-4.f90: Likewise.
* gfortran.dg/bind-c-contiguous-5.f90: Likewise.
* gfortran.dg/fmt_error_4.f90: Likewise.
* gfortran.dg/fmt_error_5.f90: Likewise.
* gfortran.dg/fmt_float.f90: Likewise.
* gfortran.dg/fmt_l.f90: Likewise.
* gfortran.dg/fmt_nonchar_2.f90: Likewise.
* gfortran.dg/fmt_zero_precision.f90: Likewise.
* gfortran.dg/g77/f77-edit-apostrophe-out.f: Likewise.
* gfortran.dg/g77/f77-edit-colon-out.f: Likewise.
* gfortran.dg/g77/f77-edit-h-out.f: Likewise.
* gfortran.dg/g77/f77-edit-i-out.f: Likewise.
* gfortran.dg/g77/f77-edit-s-out.f: Likewise.
* gfortran.dg/g77/f77-edit-slash-out.f: Likewise.
* gfortran.dg/g77/f77-edit-t-out.f: Likewise.
* gfortran.dg/g77/f77-edit-x-out.f: Likewise.
* gfortran.dg/namelist_40.f90: Likewise.
* gfortran.dg/namelist_47.f90: Likewise.
* gfortran.dg/namelist_print_1.f: Likewise.
* gfortran.dg/parameter_array_dummy.f90: Likewise.
GCC Administrator [Sat, 28 Jan 2023 00:16:39 +0000 (00:16 +0000)]
Daily bump.
Gaius Mulley [Fri, 27 Jan 2023 22:18:46 +0000 (22:18 +0000)]
PR-108557 Stuck compilation for empty file
Trying to compile an empty file causes cc1gm2 to hang.
The bug occurs when M2LexBuf.mod calls m2flex.GetToken after
an eof token has been seen which results in m2flex attempting
to read from stdin. The bug fix detects eof per file and
blocks subsequent calls to m2flex.GetToken.
gcc/m2/ChangeLog:
* gm2-compiler/M2Comp.mod: Import MetaString0.
(ExamineCompilationUnit): New variable Message.
Create and format error string.
* gm2-compiler/M2LexBuf.mod: New variable SeenEof.
(GetNonEofToken): New procedure.
(Init): Set SeenEof to FALSE.
(GetToken): Use GetNonEofToken instead of calls to
m2flex.GetToken and GetToken.
(AddTok): Detect eoftok and set SeenEof.
gcc/testsuite/ChangeLog:
* gm2/pim/fail/empty.mod: New test.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
Joseph Myers [Fri, 27 Jan 2023 21:38:57 +0000 (21:38 +0000)]
c: Disallow braces around C2x auto initializers
WG14 agreed at this week's meeting to remove support for braces around
auto scalar initializers, as incompatible with C++ auto handling of
braced initializers; thus remove that support in GCC.
Bootstrapped with no regressions for x86_64-pc-linux-gnu.
gcc/c/
* c-parser.cc (c_parser_declaration_or_fndef): Do not allow braces
around auto initializer.
gcc/testsuite/
* gcc.dg/c2x-auto-1.c, gcc.dg/c2x-auto-3.c: Expect braces around
auto initializers to be disallowed.
Jakub Jelinek [Fri, 27 Jan 2023 19:11:20 +0000 (20:11 +0100)]
libstdc++: Fix up FAIL in 17_intro/names.cc on glibc < 2.19 [PR108568]
On gcc112 which has glibc 2.17 I've noticed
FAIL: 17_intro/names.cc (test for excess errors)
FAIL: experimental/names.cc (test for excess errors)
These are because glibc < 2.19 used __unused as field member of various structs,
including mcontext_t in sys/ucontext.h on ppc64le.
This was changed in glibc with
https://gcc.gnu.org/pipermail/libc-alpha/2013-November/045766.html
names.cc even has
#ifdef __GLIBC_PREREQ
#if ! __GLIBC_PREREQ(2, 19)
// Glibc defines this prior to 2.19
#undef __unused
#endif
#endif
for it, but it doesn't work. The reason is that __GLIBC_PREREQ is defined in
<features.h> but nothing included that header before this spot (it is included later
from bits/stdc++.h).
The following patch on Linux/Hurd conditionally includes features.h to get
the needed macros before deciding if __unused should be undefined or not.
If needed, I could use __GLIBC_PREREQ then but would need to check if it is
defined and between 1996 and 1999 it wasn't.
2023-01-27 Jakub Jelinek <jakub@redhat.com>
PR libstdc++/108568
* testsuite/17_intro/names.cc (__unused): For linux or GNU hurd
include features.h if present and then check __GLIBC__ and
__GLIBC_MINOR__ macros for glibc prior to 2.19, instead of testing
__GLIBC_PREREQ which isn't defined yet.
Richard Sandiford [Fri, 27 Jan 2023 17:04:28 +0000 (17:04 +0000)]
testsuite: Two adjustments to gcc.dg/vect/complex
fast-math-bb-slp-complex-add-pattern-half-float.c no longer fails.
The scans in (loop test) fast-math-complex-add-half-float.c were
marked UNRESOLVED because they scanned slp1 rather than vect.
gcc/testsuite/
* gcc.dg/vect/complex/fast-math-bb-slp-complex-add-pattern-half-float.c:
Remove XFAIL.
* gcc.dg/vect/complex/fast-math-complex-add-half-float.c: Fix names
of dump files.
Richard Sandiford [Fri, 27 Jan 2023 17:04:28 +0000 (17:04 +0000)]
aarch64: Prevent simd tests from being optimised away
The vqdml[as]l[hs]_laneq_* tests were folded at compile time, meaning
that we didn't have any Advanced SIMD instructions in the assembly.
Kyrill's preference was to use wrapper functions, so this patch does
that for the failing tests and for others that had scan-assemblers
with inline intrinsics calls. (There were some tests that already
used wrapper functions, some that used volatile, some that used
inline asm barriers, and some that had no separation.)
Doing that for vqdmulhs_lane_s32.c meant that we generated the scalar
form of the instruction, rather than a vector instruction operating
on lane 0. That seems fair enough, so the patch keeps that test but
adds a second one for lane 1.
gcc/testsuite/
* gcc.target/aarch64/simd/vfma_f64.c: Use a wrapper function
rather than an asm barrier.
* gcc.target/aarch64/simd/vfms_f64.c: Likewise.
* gcc.target/aarch64/simd/vmul_f64_1.c: Use a wrapper function
rather than volatile.
* gcc.target/aarch64/simd/vmul_n_f64_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlalh_laneq_s16_1.c: Use a wrapper
function. Remove -fno-inline.
* gcc.target/aarch64/simd/vqdmlals_laneq_s32_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlslh_laneq_s16_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmlsls_laneq_s32_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhh_laneq_s16_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_laneq_s32_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_lane_s16.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhh_laneq_s16_1.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_lane_s32.c: Likewise.
* gcc.target/aarch64/simd/vqrdmulhs_laneq_s32_1.c: Likewise.
* gcc.target/aarch64/simd/vqdmulhs_lane_s32.c: Likewise.
Allow the scalar form to be used when operating on lane 0.
Add a test for lane 1.
Richard Sandiford [Fri, 27 Jan 2023 17:03:51 +0000 (17:03 +0000)]
Add support for conditional xorsign [PR96373]
This patch is an optimisation, but it's also a prerequisite for
fixing PR96373 without regressing vect-xorsign_exec.c.
Currently the vectoriser vectorises:
for (i = 0; i < N; i++)
r[i] = a[i] * __builtin_copysignf (1.0f, b[i]);
as two unconditional operations (copysign and mult).
tree-ssa-math-opts.cc later combines them into an "xorsign" function.
This works for both Advanced SIMD and SVE.
However, with the fix for PR96373, the vectoriser will instead
generate a conditional multiplication (IFN_COND_MUL). Something then
needs to fold copysign & IFN_COND_MUL to the equivalent of a conditional
xorsign. Three obvious options were:
(1) Extend tree-ssa-math-opts.cc.
(2) Do the fold in match.pd.
(3) Leave it to rtl combine.
I'm against (3), because this isn't a target-specific optimisation.
(1) would be possible, but would involve open-coding a lot of what
match.pd does for us. And, in contrast to doing the current
tree-ssa-math-opts.cc optimisation in match.pd, there should be
no danger of (2) happening too early. If we have an IFN_COND_MUL
then we're already past the stage of simplifying the original
source code.
There was also a choice between adding a conditional xorsign ifn
and simply open-coding the xorsign. The latter seems simpler,
and means less boiler-plate for target-specific code.
The signed_or_unsigned_type_for change is needed to make sure
that we stay in "SVE space" when doing the optimisation on 128-bit
fixed-length SVE.
gcc/
PR tree-optimization/96373
* tree.h (sign_mask_for): Declare.
* tree.cc (sign_mask_for): New function.
(signed_or_unsigned_type_for): For vector types, try to use the
related_int_vector_mode.
* genmatch.cc (commutative_op): Handle conditional internal functions.
* match.pd: Fold an IFN_COND_MUL+copysign into an IFN_COND_XOR+and.
gcc/testsuite/
PR tree-optimization/96373
* gcc.target/aarch64/sve/cond_xorsign_1.c: New test.
* gcc.target/aarch64/sve/cond_xorsign_2.c: Likewise.
Richard Sandiford [Fri, 27 Jan 2023 17:03:50 +0000 (17:03 +0000)]
vect/aarch64: Fix various sve/cond*.c failures
Quite a few gcc.target/aarch64/sve/cond*.c tests started failing
after g:
68e0063397ba820e71adc220b2da0581dce29ffa, but it turns out
that we were cheating passes before the patch.
The tests involve comparing the cost of N wide compares, a pack
sequence, and a narrow COND_EXPR with the cost of a single COND_EXPR
on fewer elements. The costs for the former included all operations,
but the costs for the latter didn't model the comparison embedded in
the COND_EXPR. The patch made us include the comparison on both sides,
making it apples-for-apples, but that's enough to tip the balance in
favour of using the wider types.
I think the new choice does reflect the current SVE cost model
correctly. (Whether and how the model should be tweaked is a
different question.) This patch therefore changes the tuning
vector length to one that makes the choice more obvious.
That in turn needs a tweak to compare_inside_loop_cost.
The function compares body_cost1/vf1 with body_cost2/vf2,
but for fully-amsked loops, it limits vf to the actual number
of iterations. This is so that (say) an expensive 16-element
vector body doesn't win over a cheaper 8-element vector body
when there are only 7 elements to process.
However, the limit was applied using known_le, regardless of
the tuning target. For a heuristic like this, it seems better
to use the likely minimum (which is a concept that was only
added after this code went in).
g:
68e0063397ba820e71adc220b2da0581dce29ffa also fixed
vcond_4_costly.c.
gcc/
* tree-vectorizer.cc (vector_costs::compare_inside_loop_cost):
Use the likely minimum VF when bounding the denominators to
the estimated number of iterations.
gcc/testsuite/
* gcc.target/aarch64/sve/cond_asrd_1.c: Tune for a 256-bit
vector length.
* gcc.target/aarch64/sve/cond_cnot_4.c: Likewise.
* gcc.target/aarch64/sve/cond_cnot_6.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_5.c: Likewise.
* gcc.target/aarch64/sve/cond_unary_6.c: Likewise.
* gcc.target/aarch64/sve/cond_uxt_5.c: Likewise.
* gcc.target/aarch64/sve/vcond_4_costly.c: Remove XFAILs.
Gaius Mulley [Fri, 27 Jan 2023 16:38:29 +0000 (16:38 +0000)]
Tidy up to declarations allowing files to be built by gm2
This patch adds missing declarations in export qualified lists
and fixes comparisons of an address type against NIL.
These changes allow make m2/stage2/cc1gm2 to succeed when in
maintainer mode.
gcc/m2/ChangeLog:
* gm2-compiler/M2Options.def: Export GetMQ, SetMQ.
* gm2-compiler/M2Preprocess.mod: (MakeSaveTempsFileName):
Test NewDir against NIL. Test Dumpdir against NIL.
Test GetMD () against NIL. Test GetMMD () against NIL.
Test GetMQ () against NIL. Test GetObj () against NIL.
Test tempfile against NIL.
* gm2-compiler/P2SymBuild.def: Export
BuildNoReturnAttribute.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
Jonathan Wakely [Fri, 27 Jan 2023 11:29:21 +0000 (11:29 +0000)]
libstdc++: Use constant for name of tzdata file
There's a string_view with this filename, which should have been used
instead of a string literal.
libstdc++-v3/ChangeLog:
* src/c++20/tzdb.cc (tzdata_stream): Use constant instead of
string literal.
Jonathan Wakely [Fri, 27 Jan 2023 11:28:37 +0000 (11:28 +0000)]
libstdc++: Use dg-bogus in new test [PR108554]
libstdc++-v3/ChangeLog:
PR libstdc++/108554
* testsuite/23_containers/map/modifiers/108554.cc: Use dg-bogus.
Richard Biener [Fri, 13 Jan 2023 07:57:12 +0000 (08:57 +0100)]
Clarify -shared effect on crtfastmath.o
This rewords the note to not specifically mention crtfastmath.o
but FP environment altering by -ffast-math or -Ofast.
PR target/55522
* doc/invoke.texi (-shared): Clarify effect on -ffast-math
and -Ofast FP environment side-effects.
Richard Biener [Fri, 13 Jan 2023 07:53:44 +0000 (08:53 +0100)]
mips: Don't add crtfastmath.o for -shared
Don't add crtfastmath.o for -shared to avoid altering the FP
environment when loading a shared library.
PR target/55522
* config/mips/gnu-user.h (GNU_USER_TARGET_MATHFILE_SPEC):
Don't add crtfastmath.o for -shared.
Richard Biener [Fri, 13 Jan 2023 07:52:07 +0000 (08:52 +0100)]
ia64: Don't add crtfastmath.o for -shared
Don't add crtfastmath.o for -shared to avoid altering the FP
environment when loading a shared library.
PR target/55522
* config/ia64/linux.h (ENDFILE_SPEC): Don't add crtfastmath.o
for -shared.
Richard Biener [Fri, 13 Jan 2023 07:50:14 +0000 (08:50 +0100)]
alpha: Don't add crtfastmath.o for -shared
Don't add crtfastmath.o for -shared to avoid altering the FP
environment when loading a shared library.
PR target/55522
* config/alpha/linux.h (ENDFILE_SPEC): Don't add
crtfastmath.o for -shared.
Andrew MacLeod [Mon, 16 Jan 2023 20:02:51 +0000 (15:02 -0500)]
Correctly detect shifts out of range
get_shift_range was incorrectly communicating that it couldn't calculate
a range when the shift values was always out fo range. Fix this and
alwasy return [0, 0] when the shift value is always out of range.
PR tree-optimization/108306
gcc/
* range-op.cc (operator_lshift::fold_range): Return [0, 0] not
varying for shifts that are always out of void range.
(operator_rshift::fold_range): Return [0, 0] not
varying for shifts that are always out of void range.
gcc/testsuite/
* gcc.dg/pr108306.c: New.
Andrew MacLeod [Wed, 25 Jan 2023 16:13:23 +0000 (11:13 -0500)]
Do not try to logical fold floating point relations.
relation_fold_and_or looks for relations among common operands feeding
logical ands and ors. With no knowledge of NANs, it should not attempt
to do this with floating point ssa names.
PR tree-optimization/108447
gcc/
* gimple-range-fold.cc (old_using_range::relation_fold_and_or):
Do not attempt to fold HONOR_NAN types.
gcc/testsuite/
* gcc.dg/pr108447.c: New.
Ju-Zhe Zhong [Fri, 27 Jan 2023 12:30:20 +0000 (20:30 +0800)]
RISC-V: Fix testcases check.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: Fix testcase check.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: Ditto.
Ju-Zhe Zhong [Fri, 20 Jan 2023 02:24:34 +0000 (10:24 +0800)]
RISC-V: Add vle/vse C++ overloaded API intrinsic testcases
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vle-1.C: New test.
* g++.target/riscv/rvv/base/vle_tu-1.C: New test.
* g++.target/riscv/rvv/base/vle_tum-1.C: New test.
* g++.target/riscv/rvv/base/vle_tumu-1.C: New test.
* g++.target/riscv/rvv/base/vse-1.C: New test.
* g++.target/riscv/rvv/base/riscv_vector.h: New.
Ju-Zhe Zhong [Fri, 20 Jan 2023 02:20:29 +0000 (10:20 +0800)]
RISC-V: Fix vop_m overloaded C++ API name.
According to https://github.com/riscv-non-isa/rvv-intrinsic-doc/tree/master/
For "vop_m" intrinsics, C++ overloaded API does not have "_m" suffix.
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def):
Remove _m suffix for "vop_m" C++ overloaded API name.
Ju-Zhe Zhong [Thu, 19 Jan 2023 14:31:08 +0000 (22:31 +0800)]
RISC-V: Add vse.v C API intrinsics testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vse-1.c: New test.
* gcc.target/riscv/rvv/base/vse-2.c: New test.
* gcc.target/riscv/rvv/base/vse-3.c: New test.
* gcc.target/riscv/rvv/base/vse_m-1.c: New test.
* gcc.target/riscv/rvv/base/vse_m-2.c: New test.
* gcc.target/riscv/rvv/base/vse_m-3.c: New test.
Ju-Zhe Zhong [Thu, 19 Jan 2023 14:12:49 +0000 (22:12 +0800)]
RISC-V: Add vle.v C API intrinsics testcases
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/base/vle-1.c: New test.
* gcc.target/riscv/rvv/base/vle-2.c: New test.
* gcc.target/riscv/rvv/base/vle-3.c: New test.
* gcc.target/riscv/rvv/base/vle_m-1.c: New test.
* gcc.target/riscv/rvv/base/vle_m-2.c: New test.
* gcc.target/riscv/rvv/base/vle_m-3.c: New test.
* gcc.target/riscv/rvv/base/vle_mu-1.c: New test.
* gcc.target/riscv/rvv/base/vle_mu-2.c: New test.
* gcc.target/riscv/rvv/base/vle_mu-3.c: New test.
* gcc.target/riscv/rvv/base/vle_tu-1.c: New test.
* gcc.target/riscv/rvv/base/vle_tu-2.c: New test.
* gcc.target/riscv/rvv/base/vle_tu-3.c: New test.
* gcc.target/riscv/rvv/base/vle_tum-1.c: New test.
* gcc.target/riscv/rvv/base/vle_tum-2.c: New test.
* gcc.target/riscv/rvv/base/vle_tum-3.c: New test.
* gcc.target/riscv/rvv/base/vle_tumu-1.c: New test.
* gcc.target/riscv/rvv/base/vle_tumu-2.c: New test.
* gcc.target/riscv/rvv/base/vle_tumu-3.c: New test.
Ju-Zhe Zhong [Thu, 19 Jan 2023 06:07:49 +0000 (14:07 +0800)]
RISC-V: Add vlm/vsm C/C++ API intrinsics support
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins-bases.cc (BASE): Add vlm/vsm support.
* config/riscv/riscv-vector-builtins-bases.h: Ditto.
* config/riscv/riscv-vector-builtins-functions.def (vlm): New define.
(vsm): Ditto.
* config/riscv/riscv-vector-builtins-shapes.cc (struct loadstore_def): Add vlm/vsm support.
* config/riscv/riscv-vector-builtins-types.def (DEF_RVV_B_OPS): Ditto.
(vbool64_t): Ditto.
(vbool32_t): Ditto.
(vbool16_t): Ditto.
(vbool8_t): Ditto.
(vbool4_t): Ditto.
(vbool2_t): Ditto.
(vbool1_t): Ditto.
* config/riscv/riscv-vector-builtins.cc (DEF_RVV_B_OPS): Ditto.
(rvv_arg_type_info::get_tree_type): Ditto.
(function_expander::use_contiguous_load_insn): Ditto.
* config/riscv/vector.md (@pred_store<mode>): Ditto.
gcc/testsuite/ChangeLog:
* g++.target/riscv/rvv/base/vsm-1.C: New test.
* g++.target/riscv/rvv/rvv.exp: New test.
* gcc.target/riscv/rvv/base/vlm_vsm-1.c: New test.
* gcc.target/riscv/rvv/base/vlm_vsm-2.c: New test.
* gcc.target/riscv/rvv/base/vlm_vsm-3.c: New test.
Ju-Zhe Zhong [Wed, 18 Jan 2023 03:29:15 +0000 (11:29 +0800)]
RISC-V: Finalize testcases for final version VSETVL PASS.
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-14.c: Adjust for final implementation.
* gcc.target/riscv/rvv/vsetvl/avl_single-23.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-30.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-44.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-50.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-51.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-6.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-65.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-66.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-67.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-68.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-70.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-71.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_single-9.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_back_prop-13.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-13.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-14.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-15.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-16.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-21.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-22.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-23.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-24.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-5.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-6.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-7.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_bb_prop-8.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-1.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_conflict-6.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-1.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-10.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-11.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-12.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-13.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-14.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-2.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-3.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-4.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-5.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-6.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-7.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-8.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_miss_default-9.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/vlmax_switch_vtype-10.c: Ditto.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-12.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-13.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-14.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-15.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-16.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_multiple-9.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-73.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-74.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-75.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-12.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-13.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-14.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-15.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-16.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-17.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-18.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-19.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-20.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvl-9.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-12.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-13.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-14.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-15.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-16.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-17.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-18.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-19.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-20.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/vsetvlmax-9.c: New test.
Ju-Zhe Zhong [Wed, 18 Jan 2023 03:24:34 +0000 (11:24 +0800)]
RISC-V: Finalize VSETVL PASS implementation
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (vsetvl_insn_p): Add condition to avoid ICE.
(vsetvl_discard_result_insn_p): New function.
(reg_killed_by_bb_p): rename to find_reg_killed_by.
(find_reg_killed_by): New name.
(get_vl): allow it to be called by more functions.
(has_vsetvl_killed_avl_p): Add condition.
(get_avl): allow it to be called by more functions.
(insn_should_be_added_p): New function.
(get_all_nonphi_defs): Refine function.
(get_all_sets): Ditto.
(get_same_bb_set): New function.
(any_insn_in_bb_p): Ditto.
(any_set_in_bb_p): Ditto.
(get_vl_vtype_info): Add VLMAX forward optimization.
(source_equal_p): Fix issues.
(extract_single_source): Refine.
(avl_info::multiple_source_equal_p): New function.
(avl_info::operator==): Adjust for final version.
(vl_vtype_info::operator==): Ditto.
(vl_vtype_info::same_avl_p): Ditto.
(vector_insn_info::parse_insn): Ditto.
(vector_insn_info::available_p): New function.
(vector_insn_info::merge): Adjust for final version.
(vector_insn_info::dump): Add hard_empty.
(pass_vsetvl::hard_empty_block_p): New function.
(pass_vsetvl::backward_demand_fusion): Adjust for final version.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::demand_fusion): Ditto.
(pass_vsetvl::cleanup_illegal_dirty_blocks): New function.
(pass_vsetvl::compute_local_properties): Adjust for final version.
(pass_vsetvl::can_refine_vsetvl_p): Ditto.
(pass_vsetvl::refine_vsetvls): Ditto.
(pass_vsetvl::commit_vsetvls): Ditto.
(pass_vsetvl::propagate_avl): New function.
(pass_vsetvl::lazy_vsetvl): Adjust for new version.
* config/riscv/riscv-vsetvl.h (enum def_type): New enum.
Xi Ruoyao [Fri, 27 Jan 2023 11:03:05 +0000 (19:03 +0800)]
testsuite: Use noipa attribute for pr95115 test
This prevent the compiler from deeming the NaN result "unused" and
remove the calculation raising INVALID exception. See the discussion
in PR107608 for details.
gcc/testsuite/ChangeLog:
* gcc.dg/pr95115.c (x): Add noipa attribute.
Tobias Burnus [Fri, 27 Jan 2023 10:32:19 +0000 (11:32 +0100)]
OpenMP/Fortran: Fix has_device_addr clause splitting [PR108558]
gcc/fortran/ChangeLog:
PR fortran/108558
* trans-openmp.cc (gfc_split_omp_clauses): Handle has_device_addr.
libgomp/ChangeLog:
PR fortran/108558
* testsuite/libgomp.fortran/has_device_addr.f90: New test.
Jakub Jelinek [Fri, 27 Jan 2023 10:17:35 +0000 (11:17 +0100)]
doc: Fix up return type of __builtin_va_arg_pack_len [PR108560]
__builtin_va_arg_pack_len as implemented returned int since its introduction
in 2007. The initial documentation didn't mention any return type,
which changed in 2010 in r0-103077-gab940b73bfabe2cec4 during some
documentation formatting cleanups
https://gcc.gnu.org/legacy-ml/gcc-patches/2010-09/msg01632.html
I can understand that for formatting some type was needed there
but what exactly hasn't been really discussed.
So, I think we should change documentation to match the implementation,
rather than change implementation to match the documentation.
Most people don't use more than
2147483647 arguments to inline functions,
and on poor targets with 16-bit ints I bet even having more than 65535
arguments to inline functions would be highly unexpected.
2023-01-27 Jakub Jelinek <jakub@redhat.com>
PR other/108560
* doc/extend.texi: Fix up return type of __builtin_va_arg_pack_len
from size_t to int.
Jakub Jelinek [Fri, 27 Jan 2023 10:16:43 +0000 (11:16 +0100)]
cgraph: Adjust verify_corresponds_to_fndecl [PR106061]
IPA passes redirect some calls in what it determines to be unreachable code
to builtin_decl_unreachable. But that function returns sometimes
builtin_decl_explicit (BUILT_IN_UNREACHABLE) (which was what GCC 12
and earlier did always), or builtin_decl_explicit (BUILT_IN_TRAP)
(e.g. for -funreachable-traps, -O0, -Og).
Now the cgraph verification code has a code to verify cgraph edges
and has there an exception for these redirections to BUILT_IN_UNREACHABLE,
but doesn't have for BUILT_IN_TRAP, so e.g. the following testcase
ICEs during that verification.
The following patch just adds BUILT_IN_TRAP to those exceptions.
2023-01-27 Jakub Jelinek <jakub@redhat.com>
PR ipa/106061
* cgraph.cc (cgraph_edge::verify_corresponds_to_fndecl): Allow
redirection of calls to __builtin_trap in addition to redirection
to __builtin_unreachable.
* gcc.dg/pr106061.c: New test.
Ju-Zhe Zhong [Wed, 18 Jan 2023 03:09:21 +0000 (11:09 +0800)]
RISC-V: Fix bug of before_p function
compare_with will return other than -1, so it should check less than 0
rather than check exactly with -1.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (before_p): Fix bug.
Ju-Zhe Zhong [Wed, 18 Jan 2023 03:13:05 +0000 (11:13 +0800)]
RISC-V: Refine function args of some functions.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (gen_vsetvl_pat): Refine function args.
(emit_vsetvl_insn): Ditto.
Ju-Zhe Zhong [Thu, 19 Jan 2023 07:02:58 +0000 (15:02 +0800)]
RISC-V: Fix pred_mov constraint for vle.v
The original constraint is incorrect in pred_mov pattern.
Take a look at Alternative 2, the operands[0] is "vr",
operands[1] which is mask operand can be "vm".
Such alternative matching will give the wrong codegen (vle.v v0,0(a5),v0.t)
This is illegal according to RVV ISA.
To fix this issue and not destroy the RA performance, fix this pattern in
this patch.
gcc/ChangeLog:
* config/riscv/vector.md: Fix constraints.
Ju-Zhe Zhong [Fri, 20 Jan 2023 09:33:09 +0000 (17:33 +0800)]
RISC-V: Add TARGET_MIN_VLEN > 32 into iterators of EEW = 64 vector modes
According to RVV ISA, RVV doesn't support EEW == 64 vector type for zve32x
and zve32f. So it makes sense add predicate in the iterators of EEW = 64
vector modes.
gcc/ChangeLog:
* config/riscv/vector-iterators.md: Add TARGET_MIN_VLEN > 32 predicates.
Jakub Jelinek [Fri, 27 Jan 2023 09:51:35 +0000 (10:51 +0100)]
tree: Fix up tree_code_{length,type}
On Thu, Jan 26, 2023 at 09:45:35AM -0500, Patrick Palka via Gcc-patches wrote:
> > +#define DEFTREECODE(SYM, NAME, TYPE, LENGTH) TYPE,
> > +#define END_OF_BASE_TREE_CODES tcc_exceptional,
> > +
> > +
> > /* Class of tree given its code. */
> > -extern const enum tree_code_class tree_code_type[];
> > +constexpr enum tree_code_class tree_code_type[] = {
> > +#include "all-tree.def"
> > +};
> > +
> > +#undef DEFTREECODE
> > +#undef END_OF_BASE_TREE_CODES
> >
> > /* Each tree code class has an associated string representation.
> > These must correspond to the tree_code_class entries. */
> > extern const char *const tree_code_class_strings[];
> >
> > /* Number of argument-words in each kind of tree-node. */
> > -extern const unsigned char tree_code_length[];
> > +
> > +#define DEFTREECODE(SYM, NAME, TYPE, LENGTH) LENGTH,
> > +#define END_OF_BASE_TREE_CODES 0,
> > +constexpr unsigned char tree_code_length[] = {
> > +#include "all-tree.def"
> > +};
> > +
> > +#undef DEFTREECODE
> > +#undef END_OF_BASE_TREE_CODES
>
> IIUC defining these globals as non-inline constexpr gives them internal
> linkage, and so each TU contains its own unique copy of these globals.
> This bloats cc1plus by a tiny bit and is technically an ODR violation
> because some inline functions such as tree_class_check also ODR-use
> these variables and so each defn of tree_class_check will refer to a
> "different" tree_code_class. Since inline variables are a C++17
> feature, I guess we could fix this by defining the globals the old way
> before C++17 and as inline constexpr otherwise?
And I'd argue with the tiny bit.
In my x86_64-linux cc1plus from today, I see 193 _ZL16tree_code_length vars,
374 bytes each, and 324 _ZL14tree_code_type vars, 1496 bytes each.
So, that means waste of 555016 .rodata bytes, plus being highly non-cache
friendly.
The following patch does that.
Tested on x86_64-linux in my -O0 working tree (system gcc 12
compiler) where .rodata shrunk with the patch by 928896 bytes, in last
stage of a bootstrapped tree (built by today's prev-gcc) where .rodata
shrunk by 561728 bytes (in neither case .text or most other sections
changed sizes) and on powerpc64le-linux --disable-bootstrap
(system gcc 4.8.5) to test also the non-C++17 case plus with
fully x86_64-linux, i686-linux and powerpc64le-linux bootstraps/regtests.
BTW, wonder if tree_code_type couldn't be an array of unsigned char
elements rather than enum tree_code_class and we'd then cast it
to the enum in the macro, that would shrink that array from 1496 bytes
to 374. Of course, that sounds like stage1 material.
2023-01-27 Patrick Palka <ppalka@redhat.com>
Jakub Jelinek <jakub@redhat.com>
* tree-core.h (tree_code_type, tree_code_length): For
C++17 and later, add inline keyword, otherwise don't define
the arrays, but declare extern arrays.
* tree.cc (tree_code_type, tree_code_length): Define these
arrays for C++14 and older.
Ju-Zhe Zhong [Wed, 18 Jan 2023 03:06:59 +0000 (11:06 +0800)]
RISC-V: Change parse_insn into public for future use.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.h: Change it into public.
Ju-Zhe Zhong [Wed, 18 Jan 2023 03:03:47 +0000 (11:03 +0800)]
RISC-V: Reorder VSETVL pass location
Insert before dce means we don't invoke DCE by this pass itself, and
also we can leverage the effort of BB reorder.
gcc/ChangeLog:
* config/riscv/riscv-passes.def (INSERT_PASS_BEFORE): Reorder VSETVL
pass.
Ju-Zhe Zhong [Wed, 18 Jan 2023 02:50:14 +0000 (10:50 +0800)]
RISC-V: Change VSETVL PASS always call split_all_insns
Since LCM will destroy CFG, we are going to reorder the location of VSETVL PASS
at least before bbro (block-reorder PASS) which is before split3 PASS. We need
to call it in VSETVL PASS to get final RVV instructions patterns.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (pass_vsetvl::execute): Always call split_all_insns.
Ju-Zhe Zhong [Wed, 18 Jan 2023 02:44:15 +0000 (10:44 +0800)]
RISC-V: Fix incorrect attributes of vsetvl instructions pattern
gcc/ChangeLog:
* config/riscv/vector.md: Fix incorrect attributes.
Iain Sandoe [Thu, 26 Jan 2023 13:49:11 +0000 (13:49 +0000)]
Modula-2: Add claimed command line options to lang.opt [PR108555].
This is a partial reversion of the changes in r13-5373-g80cf2c5e8f496b.
As observed in the PR, handling the C and Driver options in the Modula-2
lang-specific code could be difficult to emulate; This reverts to adding
the required options to the language-specific .opt file.
Signed-off-by: Iain Sandoe <iain@sandoe.co.uk>
PR modula2/108555
PR modula2/108182
PR modula2/102343
gcc/m2/ChangeLog:
* gm2-lang.cc (gm2_langhook_option_lang_mask): Do not claim CL_C
or CL_DRIVER.
(gm2_langhook_init_options): Handle options that we want to pass
to the preprocessor.
* lang-specs.h: Pass -B and -save-temps to regular compile lines.
* lang.opt: Add C and Driver options that Modula-2 intercepts for
internal use. Reorder options into two sections and to collate.
Tobias Burnus [Fri, 27 Jan 2023 08:13:16 +0000 (09:13 +0100)]
gomp/declare-variant-1*.f90: Update for Windows
Replace target selector 'lp64' by '! ilp32' to handle
Windows which uses 32bit long (and vice versa for '! lp64').
gcc/testsuite/ChangeLog:
* gfortran.dg/gomp/declare-variant-10.f90: Update scan-tree's
target selector to handle Windows.
* gfortran.dg/gomp/declare-variant-11.f90: Likewise.
* gfortran.dg/gomp/declare-variant-12.f90: Likewise.
Richard Biener [Fri, 13 Jan 2023 08:01:12 +0000 (09:01 +0100)]
LoongArch: Don't add crtfastmath.o for -shared
Don't add crtfastmath.o for -shared to avoid altering the FP
environment when loading a shared library.
PR target/55522
* config/loongarch/gnu-user.h (GNU_USER_TARGET_MATHFILE_SPEC):
Don't add crtfastmath.o for -shared.
Alexandre Oliva [Fri, 27 Jan 2023 01:52:07 +0000 (22:52 -0300)]
[docs] note that -g opts are implicitly negatable too
Back in 2017, I made -g* options implicitly negatable, without
realizing there was documentation that required updating. Oops.
Fixed, at last!
for gcc/ChangeLog
* doc/options.texi (option, RejectNegative): Mention that
-g-started options are also implicitly negatable.
GCC Administrator [Fri, 27 Jan 2023 00:17:53 +0000 (00:17 +0000)]
Daily bump.
Gaius Mulley [Thu, 26 Jan 2023 21:43:22 +0000 (21:43 +0000)]
PR-108551 gcc/m2/gm2-libs-pim/Termbase.mod:128:1 error end of non-void
cc1gm2 generates an error: control reaches end of non-void function when
compiling Termbase.mod if -Werror=return-type is present.
../gcc/m2/gm2-libs-pim/Termbase.mod: In function 'Termbase_KeyPressed':
../gcc/m2/gm2-libs-pim/Termbase.mod:128:1: error: control reaches end
of non-void function [-Werror=return-type]
128 | END KeyPressed ;
| ^~~
This occurs as cc1gm2 does skips over the <* noreturn *> attribute. This
patch records the <* noreturn *> attribute in the m2 symbol table and
later on sets TREE_THIS_VOLATILE when creating the function decl.
The patch also contains a fix for the main scaffold which also omitted
a return 0 after the exception handler code.
gcc/m2/ChangeLog:
* gm2-compiler/M2GCCDeclare.mod: Import IsProcedureNoReturn.
(DeclareProcedureToGccWholeProgram): New variable declared and set
returnType. Pass returnType to BuildEndFunctionDeclaration.
Extra parameter IsProcedureNoReturn passed to
BuildEndFunctionDeclaration.
* gm2-compiler/M2Quads.mod (BuildM2MainFunction): Correct
scaffold comment and add extra return 0.
* gm2-compiler/P2Build.bnf: Import BuildNoReturnAttribute.
(ProcedureHeading): Process EndBuildFormalParameters before
parsing AttributeNoReturn.
(DefProcedureHeading): Process EndBuildFormalParameters before
parsing AttributeNoReturn.
(AttributeNoReturn): Call BuildNoReturnAttribute.
* gm2-compiler/P2SymBuild.def (BuildNoReturnAttribute): New
procedure.
* gm2-compiler/P2SymBuild.mod (BuildNoReturnAttribute): New
procedure.
* gm2-compiler/SymbolTable.def (PutProcedureInline): Corrected
comment.
(PutProcedureNoReturn): New procedure.
(IsProcedureNoReturn): New procedure function.
* gm2-compiler/SymbolTable.mod (SymProcedure): IsNoReturn
new field.
(MakeProcedure): Initialize IsNoReturn to FALSE.
(PutProcedureNoReturn): New procedure.
(IsProcedureNoReturn): New procedure function.
* gm2-gcc/m2decl.cc (m2decl_BuildEndFunctionDeclaration):
Add extra parameter isnoreturn. Set TREE_THIS_VOLATILE
to isnoreturn.
* gm2-gcc/m2decl.def (BuildEndFunctionDeclaration): Add
extra parameter isnoreturn.
* gm2-gcc/m2decl.h (m2decl_BuildEndFunctionDeclaration): Add
extra parameter isnoreturn.
* gm2-gcc/m2except.cc (m2except_InitExceptions): Change all
function decl to pass an extra parameter isnoreturn.
gcc/testsuite/ChangeLog:
* gm2/warnings/returntype/fail/badreturn.mod: New test.
* gm2/warnings/returntype/fail/warnings-returntype-fail.exp:
New test.
* gm2/warnings/returntype/pass/Termbase.mod: New test.
* gm2/warnings/returntype/pass/goodreturn.mod: New test.
* gm2/warnings/returntype/pass/keypressedsimple.mod: New test.
* gm2/warnings/returntype/pass/warnings-returntype-pass.exp:
New test.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
Gaius Mulley [Thu, 26 Jan 2023 21:41:53 +0000 (21:41 +0000)]
Fix comment so that /* does not appear inside a comment.
The block comment in m2.flex associated with splitSlashStar
contains /* which causes a warning. This patch obfuscates
the comment /* symbols.
* m2.flex (splitSlashStar): Fix comment so that /* does not
appear inside the comment.
Signed-off-by: Gaius Mulley <gaiusmod2@gmail.com>
Kito Cheng [Tue, 17 Jan 2023 16:14:57 +0000 (00:14 +0800)]
RISC-V: Use get_typenode_from_name to get fixed-width integer type nodes
[u]int32_t are using different type between glibc and newlib, so getting
those node by int or long type isn't portable way, I also update all
other fixed-width integer types to prevent this happened again in future :P
gcc/ChangeLog:
* config/riscv/riscv-vector-builtins.cc (register_builtin_types):
Use get_typenode_from_name to get fixed-width integer type
nodes.
* config/riscv/riscv-vector-builtins.def: Update define with
fixed-width integer type nodes.
Ju-Zhe Zhong [Mon, 9 Jan 2023 23:38:38 +0000 (07:38 +0800)]
RISC-V: Add testcases for AVL=REG support
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/avl_single-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-20.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-21.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-22.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-23.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-24.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-25.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-26.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-27.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-28.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-29.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-30.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-31.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-32.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-33.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-34.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-35.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-36.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-37.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-38.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-39.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-40.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-41.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-42.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-43.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-44.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-45.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-46.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-47.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-48.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-49.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-50.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-51.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-52.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-53.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-54.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-55.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-56.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-57.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-58.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-59.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-60.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-61.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-62.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-63.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-64.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-65.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-66.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-67.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-68.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-69.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-12.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-13.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-14.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-15.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-16.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-17.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-18.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-19.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-70.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-71.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/avl_single-9.c: New test.
Ju-Zhe Zhong [Wed, 4 Jan 2023 13:48:48 +0000 (21:48 +0800)]
RISC-V: Add testcases for IMM (0 ~ 31) AVL
gcc/testsuite/ChangeLog:
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-12.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-13.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_bb_prop-9.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_conflict-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-10.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-11.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-12.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-13.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-14.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-15.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-16.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-17.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_loop_invariant-9.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-1.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-2.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-3.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-4.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-5.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-6.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-7.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-8.c: New test.
* gcc.target/riscv/rvv/vsetvl/imm_switch-9.c: New test.
Ju-Zhe Zhong [Mon, 9 Jan 2023 23:29:11 +0000 (07:29 +0800)]
RISC-V: Fix bugs of supporting AVL=REG (single-real-def) in VSETVL PASS
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (same_bb_and_before_p): Remove it.
(real_insn_and_same_bb_p): New function.
(same_bb_and_after_or_equal_p): Remove it.
(before_p): New function.
(reg_killed_by_bb_p): Ditto.
(has_vsetvl_killed_avl_p): Ditto.
(get_vl): Move location so that we can call it.
(anticipatable_occurrence_p): Fix issue of AVL=REG support.
(available_occurrence_p): Ditto.
(dominate_probability_p): Remove it.
(can_backward_propagate_p): Remove it.
(get_all_nonphi_defs): New function.
(get_all_predecessors): Ditto.
(any_insn_in_bb_p): Ditto.
(insert_vsetvl): Adjust AVL REG.
(source_equal_p): New function.
(extract_single_source): Ditto.
(avl_info::single_source_equal_p): Ditto.
(avl_info::operator==): Adjust for AVL=REG.
(vl_vtype_info::same_avl_p): Ditto.
(vector_insn_info::set_demand_info): Remove it.
(vector_insn_info::compatible_p): Adjust for AVL=REG.
(vector_insn_info::compatible_avl_p): New function.
(vector_insn_info::merge): Adjust AVL=REG.
(vector_insn_info::dump): Ditto.
(pass_vsetvl::merge_successors): Remove it.
(enum fusion_type): New enum.
(pass_vsetvl::get_backward_fusion_type): New function.
(pass_vsetvl::backward_demand_fusion): Adjust for AVL=REG.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::demand_fusion): Ditto.
(pass_vsetvl::prune_expressions): Ditto.
(pass_vsetvl::compute_local_properties): Ditto.
(pass_vsetvl::cleanup_vsetvls): Ditto.
(pass_vsetvl::commit_vsetvls): Ditto.
(pass_vsetvl::init): Ditto.
* config/riscv/riscv-vsetvl.h (enum fusion_type): New enum.
(enum merge_type): New enum.
Ju-Zhe Zhong [Mon, 9 Jan 2023 23:17:20 +0000 (07:17 +0800)]
RISC-V: Add probability model of each block to prevent endless loop of Phase 3
Notice that the PASS is just simpily pick the probability >= 50%
to do the backward fusion which will create endless loop on Phase 3.
Adding this probability to fix this bug.
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc
(vector_infos_manager::vector_infos_manager): Add probability.
(vector_infos_manager::dump): Ditto.
(pass_vsetvl::compute_probabilities): Ditto.
* config/riscv/riscv-vsetvl.h (struct vector_block_info): Ditto.
Ju-Zhe Zhong [Mon, 9 Jan 2023 23:10:59 +0000 (07:10 +0800)]
RISC-V: Remove dirty_pat since it is redundant
gcc/ChangeLog:
* config/riscv/riscv-vsetvl.cc (vector_insn_info::operator==): Remove dirty_pat.
(vector_insn_info::merge): Ditto.
(vector_insn_info::dump): Ditto.
(pass_vsetvl::merge_successors): Ditto.
(pass_vsetvl::backward_demand_fusion): Ditto.
(pass_vsetvl::forward_demand_fusion): Ditto.
(pass_vsetvl::commit_vsetvls): Ditto.
* config/riscv/riscv-vsetvl.h: Ditto.