intel/fs: fix size_read() for LOAD_PAYLOAD

With Anv/Zink, the piglit test :

  arb_shader_storage_buffer_object-max-ssbo-size -auto -fbo fsexceed

is failing validation after copy propagation :

load_payload(8) vgrf15:F, vgrf1+0.12<0>:F, vgrf1+0.0<0>:F, vgrf1+0.4<0>:F, vgrf1+0.8<0>:F, vgrf1+0.12<0>:F
../src/intel/compiler/brw_fs_validate.cpp:191: A <= B failed
  A = inst->src[i].offset / REG_SIZE + regs_read(inst, i) = 2
  B = alloc.sizes[inst->src[i].nr] = 1

In most cases it works because src[0] would be at offset 0 and so
reading a full reg passes validation, but Anv/Zink started emitting
slightly different code adding an offset maybe the size read 2 GRFs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Cc: mesa-stable
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23126>

nir: Fix serializing pointer initializers.

Found by manual inspection.

Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Fixes: 7acc81056f7 ("compiler/nir: Add support for variable initialization from a pointer")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22355>

ci: disable anholt's farm

Its http cache proxy has been returning `curl: (52) Empty reply from
server` for a while and rebooting it didn't help, so turn it off for now.

Suggested-by: Emma Anholt <emma@anholt.net>
Signed-off-by: Eric Engestrom <eric@igalia.com>

v3d: remove v3d_get_internal_type_bpp_for_output_format

This is a one-line wrapper, so let's just use the v3d_X or v3dX macros
instead.

Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23172>

v3d: remove v3d_tfu_supports_tex_format

This is a one-line wrapper, so let's just use the v3d_X or v3dX macros
instead.

Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23172>

v3d: remove v3d_create_texture_shader_state_bo

This is a one-line wrapper, so let's just use the v3d_X or v3dX macros
instead.

Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23172>

v3d: use more an auxiliar devinfo

Improve readability by using an auxiliar
        struct v3d_device_info *devinfo = &screen->devinfo;

this was triggered by the use of the v3d_X macro, where just having a
devinfo makes is more friendly. As we are here, we used it on other
places of the code.

Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Juan A. Suarez <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23172>

v3dv: simplify too small Z viewport scale workaround

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23167>

v3dv/pipeline: don't prepack up early-z configuration

False (so zero) is already the default value, so those prepacks are
basically superfluous.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23167>

v3d/ci: make traces test mandatory

Similar to other drivers, let's run always the traces tests.

Acked-by: David Heidelberg <david.heidelberg@collabora.com>
Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23135>

v3d/ci: run GPU piglit profile

Instead of running all the tests, run only the GPU related ones, which
should make the CI faster.

Acked-by: Iago Toral Quiroga <itoral@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23135>

radv: apply a bug workaround for smoothing on GFX6

This fixes smooth lines on GFX6.

Fixes: 85cbdba3559 ("radv: add support for smooth lines")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23168>

zink: infer types from load_const instrs to avoid more bitcasts

this walks to uses list for the ssa def to infer a type from one of the
uses to reduce the need to bitcast

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: store and use alu types for ntv defs

this adds indexing for ssa/reg defs with the accompanying current
type of a given def (inaccurate for objects but whatever), enabling
that type to be used directly in order to avoid bitcasts in some places

this upends the assumption that all stored srcs are uint type

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: dynamically emit non-bool register values using local_vars spirv buffer

this will be useful in a future commit

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: write out register variables to a separate spirv buffer

this will enable registers to be written more dynamically with correct
type values to cut down on bitcasts

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: manually memcpy the spirv instruction buffer

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: move get_alu_type() up in file

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: use void return for store_dest

not sure why this had returns, but it doesn't seem necessary

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: delete unnecessary bitcast in load_shared/scratch

if the mem is loaded as uint and stored as uint, then
the loaded and stored value must be uint, so a bitcast to uint
is as pointless as this commit message

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: also declare int size caps inline with signed int type usage

Fixes: 854fd242faf ("zink: declare int/float size caps inline with type usage")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22934>

zink: promote flushed clears to unordered cmdbuf when possible

this reuses the unordered_blitting codepath for fb clears

for #9016

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23056>

vk/graphics_state: handle null pipeline state structs in creation

when these members are null, the corresponding graphics states should be
initialized with sensible default values

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22236>

anv: more correctly handle null pipeline states

it's not necessary to check whether dynamic states are set before
the null checks since any issues there would be VU errors

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22236>

lavapipe: more correctly handle null pipeline states

it's not necessary to check whether dynamic states are set before
the null checks since any issues there would be VU errors

Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22236>

zink: flag 'has_work' on batch when promoting a cmd

has_work controls whether a flush can be deferred, i.e., when unset
a flush may be deferred

since a promoted cmd must still be flushed to take effect, ensure this
is always set when promoted cmds are pending

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: explicitly disable promotion on images that are both unflushed and non-reorderable

until #9016 is resolved, be more cautious and consider any image with unflushed
access as un-promotable to avoid layout desync

affects:
KHR-GLES3.packed_pixels.varied_rectangle.rgb

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: explicitly disable reordering after restricted swapchain readback blits

when needs_present_readback is set, reordering is disabled without hitting
the path that would normally disable promotion for the resource, so this
needs to be changed manually to avoid layout desync on the swapchain

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: disable unordered blits when swapchain images need aqcuire

this is consistent with other cmdbuf reordering for blits

Fixes: 3a9f7d70383 ("zink: implement unordered u_blitter calls")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: track/check submit info on resource batch usage

resources use a private refcount to avoid overhead from atomics on
descriptor binds, but this has the side effect of evading batch usage,
meaning that the usage may not be properly removed once the batch state
is reset, which will cause issues with detecting whether usage exists
for a given resource

to fix this, the mechanism for tc fence disambiguation can be reused,
namely adding the batch state's submit count to the usage info and
then using that to add a second set of comparisons such that it becomes
possible to check both whether the batch usage for a resource matches
a given batch AND whether the batch usage is the current state of the
batch

affects:
KHR-GLES3.copy_tex_image_conversions.required.cubemap_posy_cubemap_negz

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: move batch usage to substruct on zink_bo objects

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: move zink_batch_state::submit_count to zink_batch_usage

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: use batch usage function for a simple case

no functional changes

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

zink: add special-casing for (not) reordering certain image barriers

in a scenario where an ordered read op occurs for an image,
successive read-only barriers SHOULD be able to be promoted

...but they can't, because there isn't yet a mechanism for handling layout
transitions between the unordered cmdbuf and the ordered cmdbuf,
meaning that promoting e.g., a SHADER_READ_ONLY barrier after a TRANSFER_SRC
barrier will leave the image with the wrong layout for the transfer op:

TRANSFER_SRC(unordered) -> COPY(ordered) -> SHADER_READ_ONLY(unordered)

becomes

TRANSFER_SRC(unordered) -> SHADER_READ_ONLY(unordered) -> COPY(ordered)

ideally I'll get around to figuring this out at some point

affects:
dEQP-GLES31.functional.copy_image.non_compressed.viewclass_32_bits.r32i_r32i.texture2d_array_to_renderbuffer

Fixes: bf0af0f8ede ("zink: move all barrier-related functions to c++")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23035>

iris: Use known formats for tex_cache_flush_hack

Instead of using ISL_FORMAT_UNSUPPORTED, use the known format to avoid
extra cache flushes.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23087>

intel/blorp: Add and use blorp_copy_get_formats

This is useful for iris to know what formats will be used for copy
operations.

The new function introduces a couple refactors. It makes use of the
ISL_GFX_VER() macro and it also makes more use of the
isl_surf_usage_is_depth() function.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23087>

intel/blorp: Change condition for CCS_E copy formats

In blorp_copy, instead of checking if the surface's aux-usage is CCS_E,
check if its format supports CCS_E.

ISL won't report that a surface supports CCS_E if its format doesn't, so
this should strictly widen the scope of surfaces included in this path.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23087>

intel/blorp: Add depth usage check for copy format

We will soon update the CCS_E aux-usage check to a CCS_E format check.
Since depth formats support CCS_E on gfx12+, add another check for the
depth usage to prevent depth surfaces from falling into the CCS_E copy
format case.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23087>

intel/blorp: Use the depth copy format more on BDW+

Sampling with HiZ is introduced on BDW+. For BLORP copies, instead of
using the depth format when the source uses HiZ, use it for all depth
sampling on BDW+.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23087>

radv: do not use a pipe offset for aliased images

Fixes dEQP-VK.ycbcr.plane_view.memory_alias.* on raven2.

Fixes: 1c065650260 ("radv: expose disjoint image support")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23143>

ac/surface: print tile_swizzle as well

swizzle modes that are *_X or *_T depend on tile_swizzle.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23143>

amd/drm-shim: add raven2

It differs from raven in interesting ways (e.g., GB_ADDR_CONFIG).

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23143>

panfrost: expose PIPE_CAP_POLYGON_OFFSET_CLAMP

This gives us ARB_polygon_offset_clamp and EXT_polygon_offset_clamp, and
most of the actual state plumbing was already in place.

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23169>

mesa/st: Set pipe_shader_image::single_layer_view

Pass it through from the API.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23142>

gallium: Add pipe_image_view::single_layer_view

OpenGL has a goofy feature that allows creating an image view of a single layer
of an array texture... in which case that image is treated as non-arrayed in
shader. If you have a 16x16x16 3D texture and bind the third layer, you get a
16x16 2D texture instead of a 16x16x1 3D texture. That distinction matters to
the hardware on AGX, since the texture dimension needs to match between the
shader and the pipe_image_view. If the shader is going to use image2D, we need
to know that the pipe_image_view should be treated as 2D (even though the
underlying resource is 3D).

"But, Alyssa, we already have first_layer and last_layer. Surely you can just
check if first_layer == last_layer?" you ask. The problem is that doesn't
distinguish a 16x16x1 3D texture (accessed as image3D in the shader) from a
16x16 slice (accessed as image2D in the shader) of a 16x16x16 3D texture. To
solve, we add a boolean flag indicating we want to create a view (with a lower
dimension than the underlying resource). This provides an unambiguous way to
communicate this case to drivers.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Acked-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23142>

radv/ci: switch to b2c v0.9.10

This brings a fix for the steam decks which may boot too fast sometimes,
and have the network adapter not being enumerated by the time it tries
to connect to the gateway...

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23170>

mesa/spirv: Provide more specific error message for glSpecializeShader()

Distinguish between the "entry point not found" and "parsing error"
cases in the error text.  For consistency, identify the unhandled
specialization index case as part of the verification function.

The verification function was renamed to make clearer its scope and
what module it belongs.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22976>

pan/mdg: Use nir_lower_image_atomics_to_global

We were already lowering image atomics to lea_image + global atomic. It's a lot
nicer to make that lowering explicit in the NIR. This is much bigger win than in
the Bifrost compiler since here lea_image is used only for atomics, and here it
wasn't well abstracted in the compiler.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23120>

pan/bi: Use nir_lower_image_atomics_to_global

We were already lowering image atomics to lea_attr_tex + global atomic, might as
well make that lowering explicit in the NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23120>

pan/bi: Fix atomic exchange on Valhall

Copypaste fail when switching to unified atomics, missed becuase I don't have
any Valhall hardware and Valhall isn't in CI. (Good news, that means it probably
didn't affect anyone in the mean time :-p)

Fixes crashes with lots of dEQP-GLES31 tests observed under drm-shim.

Fixes: e258083e072 ("pan/bi: Use unified atomics")
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23120>

nir: Add pass to lower image atomics

Hardware that lacks dedicated image atomics can still implement image atomics
with regular atomics on global memory, as long as there is a way to get the
address of a texel in memory. I've open-coded this lowering in my first 2
compilers, so before I add another crappy vendored version in my 3rd, let's add
a common NIR pass to do the lowering.

Thanks to unified atomics, the pass itself is fairly concise.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23120>

nir: Add image_texel_address intrinsics

Some hardware has an instruction to load the address of a texel in a writeable
image, given the coordinates ("LEA_IMAGE"). This operation is defined only for
uncompressed images, but it is well-defined regardless of the underlying
twiddling. As such, it is not expected to be produced by APIs but is useful for
internal lowering when it is known that images will be uncompressed (e.g.
because image_store does not support compression on the hardware).

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23120>

nir: Document extra image source

I was scratching my head about this for a few minutes until I found the answer
in spirv_to_nir. Hopefully this saves someone else some head scratching in turn.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23120>

docs: use meson instead invoking ninja directly

This approach is available since meson 0.47.0 which we depend on.

Reviewed-by: Sergi Blanch-Torné <sergi.blanch.torne@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23127>

zink: try update fb resource refs when starting new renderpass

in the case where a draw is triggered after a flush, zink_update_descriptor_refs
will be called to set batch tracking for descriptors. this function also
handles refs for fb attachments, and everything is usually fine there

the problem with this approach is that tracking is no longer set on view
objects at renderpass begin, which makes them susceptible to early deletion
if a rp isn't started from a draw call

instead, apply batch tracking to fb attachment resources on renderpass
begin if the BATCH_CHANGED flag is set (need to rename this at some point)
in order to guarantee that the resource (object) lifetime will match the
cmdbuf runtime [since imageviews are now only freed upon batch completion]

fixes #9059

Fixes: f6bbd7875a8 ("zink: remove batch tracking/usage from view types"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23132>

anv: fix push descriptor deferred surface state packing

Yuzu is running into a segfault because it writes the push descriptor
twice with 2 different layouts, but without a draw/dispatch in
between.

First vkCmdPushDescriptorSetKHR() writes descriptor 0 & 1 with a
uniform buffer. We toggle the 2 first bits of
anv_descriptor_set::generate_surface_states.

Second vkCmdPushDescriptorSetKHR() writes descriptor 0 with uniform
buffer and descriptor 1 with an image view. The first bit of
anv_descriptor_set::generate_surface_states stays, but the second bit
was already set before and it should now be off.

When we finally flush the push descriptor, we try to generate a
surface state for descriptor 1, but there is no valid buffer view for
it, we access an invalid pointer and segfault.

This fix resets the anv_descriptor_set::generate_surface_states when
the descriptor layout changes.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b49b18f0b7 ("anv: reduce BT emissions & surface state writes with push descriptors")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23156>

r300: workaround GCC 12+ warning, declare NULL value as unreachable

Solution recommended in the https://gcc.gnu.org/bugzilla/show_bug.cgi?id=109716#c3

Suggested-by: Eric Engestrom <eric@engestrom.ch>
Acked-by: Filip Gawin <filip@gawin.net>
Reviewed-by: Pavel Ondračka <pavel.ondracka@gmail.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23148>

broadcom/compiler: skip jumps in non-uniform if/then when block cost is small

We have an optimization for non-uniform if/else where if all channels meet the
jump condition we emit a branch to jump straight to the ELSE block. Similarly,
if at the end of the THEN block we don't have any channels that would execute
the ELSE block, we emit a branch to jump straight to the AFTER block.

This optimization has a cost though: we need to emit the condition for the
branch and a branch instruction (which also comes with a 3 delay slot), so for
very small blocks (just a couple of ALU for example) emitting the branch
instruction is typically worse. Futher, if the condition for the branch is not
met, we still pay the cost for no benefit at all.

Here is an example:

nop                           ; fmul.ifa rf26, 0x3e800000, rf54
xor.pushz -, rf52, 2          ; nop
bu.alla  32, r:unif (0x00000000 / 0.000000)
nop                           ; nop
nop                           ; nop
nop                           ; nop
xor.pushz -, rf52, 3          ; nop
nop                           ; mov.ifa rf52, 0
nop                           ; mov.pushz -, rf52
nop                           ; mov.ifa rf26, 0x3f800000

The bu instruction here is setup to jump over the following 4 instructions
(the last 4 instructions in there). To do this, we pay the price of the xor
to generate the condition, the bu instruction, and the 3 delay slots right
after it, so we end up paying 6 instructions to skip over 4 which we pay
always, even if the branch is not taken and we still have to execute those
4 instructions. With this change, we produce:

nop                           ; fmul.ifa rf56, 0x3e800000, rf28
xor.pushz -, rf9, 3           ; nop
nop                           ; mov.ifa rf9, 0
nop                           ; mov.pushz -, rf9
nop                           ; mov.ifa rf56, 0x3f800000

Now we don't try to skip the small block, ever. At worse, if all channels
would have met the branch condition, we only pay the cost of the 4
instructions instead of 6, at best, if any channel wouldn't take the
branch, we save ourselves 5 cycles for the branch condition, the branch
instruction and its 3 delay slots.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23161>

radv: fix radv_emit_userdata_vertex for vertex offset -1

-1 is a legit vertex offset upon vkCmdDrawIndexed and other cmds. This
change fixes to track last_vertex_offset with an additional valid bit.

Cc: mesa-stable
Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23157>

radv: enable smoothLines

For Zink.

This marks one piglit test as expected failure because polygon
smoothing can't be implemented properly in Vulkan.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

radv: add support for smooth lines

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

radv: lower nir_intrinsic_load_poly_line_smooth_enabled_amd

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

radv: declare a new user SGPR for the dynamic line rasterization mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

radv: determine if smooth lines can be used in the pipeline key

Really complicated to reduce the scope because everything can be
dynamic and with GPL you can't even know if the pipeline draws lines
when compiling the fragment shader.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

radv: track if the smoothLines features is enabled in the device

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

nir: lower smooth lines conditionally using the new intrinsic

RADV will enable/disable this based on a dynamic state.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

radeonsi: lower nir_intrinsic_load_poly_line_smooth_enabled_amd

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

nir: add nir_intrinsic_load_poly_line_smooth_enabled

To lower smooth lines conditionally in fragment shaders for RADV
because the line rasterization mode in Vulkan can be dynamic.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/21587>

radv: remove useless check about USAGE_STORAGE for TC-compat HTILE

This should never happen.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23122>

radv: disable IMAGE_USAGE_STORAGE with depth-only and stencil-only formats

This shouldn't have been enabled at all. Depth-stencil formats were
accidentally disabled but not depth-only or stencil-only formats.

This doesn't seem allowed by DX12 and both AMD/NVIDIA don't enable it.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23122>

radv: bump the global VRS image size to maximum supported FB dimensions

Super sampling on a 4K screen could hit this. 16k seems pretty big
but this image is only created on RDNA2 and on-demand if VRS attachments
are used without depth-stencil attachments, which should be rare
enough to care.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23105>

util: add Pixel Game Maker MV workaround

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8918
Cc: mesa-stable
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23095>

ci/v3dv: add often timeouting ssbo.layout.3_level_array.std140.column_major_mat4

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23153>

ci/radv: add another raven flake dEQP-VK.draw.dynamic_rendering.primary_cmd_buff.linear_interpolation

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23152>

radv: Clear query dirty flags when flushing them.

This is just to make their code consistent with other similar
functions.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

radv: Move empty dynamic states check to caller.

Improves the CPU overhead of radv_emit_all_graphics_states.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

radv: Move indirect check from index buffer emission to caller.

This improves the CPU overhead of radv_emit_all_graphics_states.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

radv: Slight refactor to late_scissor_emission.

There is no need to set context_roll_without_scissor_emitted
when pipeline, rbplus state, or binning state changes,
because radv_need_late_scissor_emission already checks
their dirty flags.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

radv: Set last_index_type in radv_before_draw.

This function is always inlined so checking info->indexed can be
constant folded by the compiler. So it is better to set this
in before_draw.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

radv: Move ignore forced VRS code to more optimal place.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

radv: Compute tess info when emitting patch control points.

Some tess info needs to be calculated in the command buffer when
dynamic patch control points are enabled.

Move this calculation from radv_emit_all_graphics states to where
it actually matters.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

radv: Emit primitive reset index with primitive restart enable.

The VGT_MULTI_PRIM_IB_RESET_INDX register has no effect when
primitive restart is disabled, so we can move this out of the
hot path.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20659>

asahi: Drop Asahi-as-a-swrast hack

Now that we've dropped macOS support in the driver, this is all dead code and
gets garbage collected.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23138>

gallium: Drop Asahi-as-a-swrast hack

Now that we've dropped macOS support, these paths are deadcode.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23138>

docs: update crosvm networking options

Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22892>

ci/crosvm: update cmdline options

```
[WARN  crosvm::crosvm::cmdline] `--host-ip`, `--netmask`, and `--mac` are deprecated;
```

Reviewed-by: Corentin Noël <corentin.noel@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22892>

nir: Assert that we don't shrink bit-sizes in nir_lower_bit_size()

The idea of this pass is to promote small bit-sizes to larger, supported
bit-sizes for certain operations.  It doesn't handle emulating large
bit-size operations on smaller bit-sizes; passes like nir_lower_int64
and nir_lower_doubles handle that.

So, assert that we aren't shrinking the bit-size, as this will almost
certainly produce incorrect results.

Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23123>

intel/compiler: Fix 64-bit ufind_msb, find_lsb, and bit_count

We only support 32-bit versions of ufind_msb, find_lsb, and bit_count,
so we need to lower them via nir_lower_int64.

Previously, we were failing to do so on platforms older than Icelake
and let those operations fall through to nir_lower_bit_size, which
used a callback to determine it should lower them for bit_size != 32.
However, that pass only emulates small bit-size operations by promoting
them to supported, larger bit-sizes (i.e. 16-bit using 32-bit).  It
doesn't support emulating larger operations (i.e. 64-bit using 32-bit).

So nir_lower_bit_size would just u2u32 the 64-bit source, causing us to
flat ignore half of the bits.

Commit 78a195f252d (intel/compiler: Postpone most int64 lowering to
brw_postprocess_nir) provoked this bug on Icelake and later as well,
by moving the nir_lower_int64 handling for ufind_msb until late in
compilation, allowing it to reach nir_lower_bit_size which broke it.

To fix this, we always set int64 lowering for these opcodes, and also
correct the nir_lower_bit_size callback to ignore 64-bit operations.

Cc: mesa-stable
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23123>

nir: Add find_lsb lowering to nir_lower_int64.

Some GPUs can only handle 32-bit find_lsb.

Cc: mesa-stable
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23123>

microsoft/compiler: Better and simpler bitcast reduction

Using nir_gather_ssa_types works much better. There's 2 differences
compared to what I was doing before:
1. Multiple passes to allow data to propagate forward and backward
   through the whole shader.
2. Allowing a value to have indeterminate types due to having both
   int and float usages.

So this deletes some code and gets better results. Wish I'd known
this existed last week.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23062>

iris: Fix return of xe_batch_submit() when exec fails

When intel_ioctl(DRM_IOCTL_XE_EXEC) fails it returns -1 sets errno
with the fail reason.
This fail reason is than is used to know if engine was banned in
context_or_engine_was_banned().

Not adding a fixes tag because Xe is not enabled by default.

Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23139>

anv: Nuke ANV_BO_ALLOC_WRITE_COMBINE

In i915 if the device has local memory it can only mmap bo with
I915_MMAP_OFFSET_FIXED, so all this set of ANV_BO_ALLOC_WRITE_COMBINE
were useless.

In Xe KMD there is no way to change mmap mode for all GPUs types.

So we can nuke bo->map_wc, ANV_BO_ALLOC_WRITE_COMBINE and related
dead code.

No changes in behavior expected here.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22483>

anv: Fix ANV_BO_ALLOC_NO_LOCAL_MEM flag

VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT is also set in all memory types of
integrated GPUs.
This flag means that memory will be allocated in the most efficient
place for the GPU to access, which is true in integrated GPUs.

However, this was causing ANV_BO_ALLOC_WRITE_COMBINE to be set in
integrated GPUs in the block right below when allocating in the non-cached memory type.
But the comment only talks about lmem, so to still keep the write
combine behavior for iGPUs it was used VkMemoryPropertyFlags in mmap_calc_flags().

Additionally, this was causing anv_bo.has_implicit_ccs to always be
set, which could change the expected behavior of
anv_BindImageMemory2() in MTL.

Fixes: fbd32a04daf8 ("anv: add a third memory type for LLC configuration") added a new heap
Fixes: 582bf4d9f72f ("anv: flag BO for write combine when CPU visible and potentially in lmem")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22483>

ci/lava: Renable SSH sessions for panfrost jobs

The devices' IP dictionary for sun50i and vim3 are fixed now.

Signed-off-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23137>

freedreno: Add some A6/7xx registers

Can be found in recent downstream kernels.

Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22901>

anv: assume context isolation support

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7265
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23102>

anv: defer binding table block allocation to when necessary

There are cases where we never need a binding table block, for example
compute only command buffers.

This has also the nice effect of not having
dEQP-VK.api.object_management.* tests allocate 1Gb of binding tables
which are staying around forever after you run those tests.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/8806
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23079>

rusticl/types: fix clippy new() not returning Self

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23129>

rusticl/program: fix clippy cast to the same type

Reviewed-by: Karol Herbst <kherbst@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23129>

CODEOWNERS: Update panfrost

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23109>