Tom Rini [Mon, 13 Mar 2023 15:39:21 +0000 (11:39 -0400)]
Merge tag 'efi-2023-04-rc4' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-04-rc4
Documentation:
* man-page for panic command
UEFI:
* Correct parameter check for SetVariable()
Other:
* Provide unit test for crc8
Heinrich Schuchardt [Fri, 3 Mar 2023 21:04:26 +0000 (22:04 +0100)]
efi_loader: describe term_get_char()
Add a function description.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Masahisa Kojima [Tue, 21 Feb 2023 02:33:17 +0000 (11:33 +0900)]
efi_loader: update SetVariable attribute check
UEFI specification v2.10 says that
EFI_VARIABLE_AUTHENTICATED_WRITE_ACCESS is deprecated and
EFI_UNSUPPORTED should be returned in SetVariable variable service.
Current implementation returns EFI_INVALID_PARAMETER,
let's fix the return value.
Together with above change, this commit also updates the SetVariable
attribute check to be aligned with the EDK2 reference implementation.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Fri, 3 Mar 2023 21:48:27 +0000 (22:48 +0100)]
doc: man-page for panic command
Provide a man-page for the panic command.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Vincent Stehlé [Mon, 20 Feb 2023 14:37:29 +0000 (15:37 +0100)]
doc: uefi: fix links
Fix a couple of links so that they are rendered correctly with sphinx.
Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com>
Cc: Heinrich Schuchardt <xypron.glpk@gmx.de>
Cc: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Heinrich Schuchardt [Wed, 22 Feb 2023 01:10:20 +0000 (02:10 +0100)]
test: unit test for crc8
Add a unit test for the crc8() function.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Sat, 11 Mar 2023 00:10:14 +0000 (19:10 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-usb
Two minimal Kconfig/Makefile fixes for USB.
Tom Rini [Sat, 11 Mar 2023 00:09:59 +0000 (19:09 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-sh
Assorted Renesas fixes below, namely MMC clocking breakage fix, clock
Kconfig fix, pin control unused symbols removal, and sysinfo fix and
enablement on now fixed platforms.
Tom Rini [Fri, 10 Mar 2023 21:01:52 +0000 (16:01 -0500)]
Merge tag 'dm-pull-10mar23' of https://source.denx.de/u-boot/custodians/u-boot-dm
fixes and tests for the fdt command
Tam Nguyen [Mon, 27 Feb 2023 22:58:48 +0000 (23:58 +0100)]
ARM: dts: renesas: Enable sysinfo on R-Car D3 Draak
Enable support for sysinfo on R-Car D3 Draak board. The sysinfo is used
e.g. to access and decode board-specific information and then in turn
used by board-info to print those information.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77995.dtsi already.
Drop status = "okay" from EEPROM node.
Add dts: tag.
Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
Tam Nguyen [Mon, 27 Feb 2023 22:58:47 +0000 (23:58 +0100)]
ARM: dts: renesas: Enable sysinfo on R-Car V3H Condor/Condor-I
Add new sysinfo IDs for R-Car V3H Condor/Condor-I .
Enable support for sysinfo on R-Car V3H Condor/Condor-I. The sysinfo is
used e.g. to access and decode board-specific information and then in
turn used by board-info to print those information.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
[Marek: Drop compatible from I2C node, this is in r8a77980.dtsi already.
Drop status = "okay" from EEPROM node.
Add dts: tag.
Update the commit message, note the new sysinfo IDs.
Fix Kconfig EEPROM address to be 0x50 and match the DT, sync config.]
Tam Nguyen [Mon, 27 Feb 2023 22:58:46 +0000 (23:58 +0100)]
sysinfo: rcar3: Fix Draak and Eagle board code
Correct the board code ID based on the hardware documentation
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com>
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Tue, 28 Feb 2023 06:25:53 +0000 (07:25 +0100)]
pinctrl: renesas: Drop non-existent PFC info table entries
Remove PFC info table entries which are never instantiated,
since there are no drivers for those. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Tue, 28 Feb 2023 21:16:02 +0000 (22:16 +0100)]
clk: renesas: Always select DM_RESET to prevent inobvious failure of rst_gen3 subdriver
The CLK_RCAR_GEN3 registers two subdrivers, clk_gen3 and rst_gen3.
The former depends on the clock framework, which is always enabled
in this context of clock framework driver, while the later depends
on reset framework which may not always be enabled.
Ensure the reset framework is also always enabled to prevent inobvious
early boot time bind failure of the CPG driver, which leads to system
showing no activity and is difficult to debug.
Note that one possible approach to debug this is to use CONFIG_DEBUG_UART
and add debug printascii()s into the drivers/clk/renesas/clk-rcar-gen3.c .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Feb 2023 22:49:28 +0000 (23:49 +0100)]
mmc: renesas-sdhi: Add proper probe error fail path
In case one of the calls in probe fail, trigger a fail path and
undo all the steps done in probe until the point of failure.
The current implementation failed to stop controller clock and
free claimed clock, so fix that. Furthermore, print return code
in error prints for easier debugging.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Mon, 27 Feb 2023 22:49:27 +0000 (23:49 +0100)]
mmc: renesas-sdhi: Always configure default SDnH clock rate to 800 MHz
The prior stage bootloader might have left the SDnCKCR register in completely
arbitrary state before passing control to U-Boot, which includes the register
being populated with incorrect values. Currently the SDHI driver will attempt
to use clock framework to configure SDn clock, which may fail in case SDnCKCR
contains invalid values for the SDnH clock, because the clock framework would
not be able to determine SDnH clock rate and would get -EINVAL instead, which
in turn would not allow the clock framework to determine the correct SDn clock
divider ratio.
This failure occurs specifically in case SDnCKCR reads back 0x209 .
Correct the problem by first setting default SDnH clock rate to 800 MHz, thus
assuring the SDnCKCR SDnH bits are correct, and only afterward set up the SDn
clock rate to default 200 MHz.
Note that the SDHI driver may reconfigure SDnH clock later based on IOS
settings obtained from the attached card, the 800 MHz set up here is only
the default value.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Heinrich Schuchardt [Wed, 25 Jan 2023 18:40:16 +0000 (19:40 +0100)]
usb: move CONFIG_USB_HUB_DEBOUNCE_TIMEOUT to USB
This configuration setting is only relevant if the board supports USB.
It should not be in the main menu but in the USB menu.
The setting is only relevant in USB host mode.
Fixes:
5454dea3137d ("usb: hub: allow to increase HUB_DEBOUNCE_TIMEOUT")
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Heinrich Schuchardt [Wed, 25 Jan 2023 18:40:15 +0000 (19:40 +0100)]
usb: USB hubs require host mode
USB hubs run in host mode not in gadget mode. Hence, compiling usb_hub.c
should not be selected by CONFIG_USB_GADGET.
Suggested-by: Marek Vasut <marex@denx.de>
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Marek Vasut [Thu, 2 Mar 2023 03:08:40 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt bootcpu
Add 'fdt bootcpu' test which works as follows:
- Create basic FDT, map it to sysmem
- Print the FDT bootcpu
- Set the FDT bootcpu and read the value back using 'fdt header get'
- Perform the previous step twice to validate bootcpu overwrite
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:38 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt rm
Add 'fdt rm' test which works as follows:
- Create fuller FDT, map it to sysmem
- Selectively delete nodes or properties by both path and aliases
- Verify created nodes or properties using fdt print command
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:37 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt mknode
Add 'fdt mknode' test which works as follows:
- Create fuller FDT, map it to sysmem
- Create node either in / or subnode
- Attempt to create node over existing node, which fails
- Attempt to create subnodes in non-existing nodes or aliases
- Verify created nodes using fdt list command
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:36 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt set
Add 'fdt set' test which works as follows:
- Create fuller FDT, map it to sysmem
- Set either existing property to overwrite it, or new property
- Test setting both single properties as well as string and integer arrays
- Test setting to non-existent nodes and aliases
- Verify set values using 'fdt get value'
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:35 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt get size
Add 'fdt get size' test which works as follows:
- Create fuller FDT, map it to sysmem
- Get size of various properties
- Get node count of available nodes
- Test non-existent nodes and properties
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:34 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt get addr
Add 'fdt get addr' test which works as follows:
- Create fuller FDT, map it to sysmem
- Get address of various properties
- Compare addresses calculated by UT and fdt command
This test is special in that it has to go through gruesome remapping scheme
where the test calculates:
- pointer offsets of the generated FDT root and the property being tested
- map_sysmem() result of environment variable "fdtaddr" and the one set
by the test matching address of property being tested
- difference between the later and the former, to obtain offset of the
DT property from start of DT
The offsets must match in both the UT and the tested U-Boot, if they do
not, the test fails.
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:33 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt get name
Add 'fdt get name' test which works as follows:
- Create fuller FDT, map it to sysmem
- Get name of / node 0, 1 and /clk-test node 0
- Compare output and validate the node name
- Get name of / node 2 and /clk-test node 1
- Compare output and validate the node is not present
- Get name of / node -1 and /clk-test node -1
- Compare output and validate the node name equals node 0 name
- Check nonexistent node, verify the command errors out
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:31 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt resize
Add 'fdt resize' test which works as follows:
- Create simple FDT with extra size 0, map it to sysmem
- 'resize' the FDT by 0x2000 bytes
- Verify the new space has been added to the FDT
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:30 +0000 (04:08 +0100)]
test: cmd: fdt: Test fdt move
Add 'fdt move' test which works as follows:
- Create simple FDT, map it to sysmem
- 'move' the FDT into new zeroed out sysmem location
- Verify newly active FDT is in the new location
- Compare both locations
The test case can be triggered using:
"
./u-boot -Dc 'ut fdt'
"
To dump the full output from commands used during test, add '-v' flag.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:29 +0000 (04:08 +0100)]
test: cmd: fdt: Test both string and integer arrays in 'fdt get value'
The 'fdt get value' subcommand now supports extraction of integer value
from integer arrays, add test for it, including a test for special case
unindexed integer array read, which is handled as hash and treated as a
long string instead of integer.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:28 +0000 (04:08 +0100)]
test: cmd: fdt: Test alias resolution in 'fdt get value'
The 'fdt' command help contains the following note:
"
Dereference aliases by omitting the leading '/', e.g. fdt print ethernet0.
"
Add test for it.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:27 +0000 (04:08 +0100)]
test: cmd: fdt: Generate fuller DT internally and switch fdt get value to it
Implement function to generate internal test DT fragment and switch
the 'fdt get value' test to this instead of depending on the sandbox
DT. Rename clk-test node to test-node node. This FDT fragment will be
reused by other tests. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:26 +0000 (04:08 +0100)]
test: cmd: fdt: Rename fdt_test_get() to fdt_test_get_value()
The 'fdt get' command has a 'get value' subcommand, rename the fdt_test_get()
to fdt_test_get_value() to avoid confusion about what it is testing. There is
currently no get 'get name', 'get addr', 'get size' subcommand test.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:25 +0000 (04:08 +0100)]
test: cmd: fdt: Rename fdt_test_resize() to fdt_test_addr_resize()
The 'fdt' command has a 'resize' subcommand, rename the fdt_test_resize()
to fdt_test_addr_resize() to avoid confusion about what it is testing.
There is currently no resize test.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:24 +0000 (04:08 +0100)]
test: Add ut_assert_nextline_empty() empty line helper
Add helper macro to test for empty lines, which is an inobvious
wrapper around ut_assert_nextline("%s", "") .
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:23 +0000 (04:08 +0100)]
cmd: fdt: Add support for integer arrays in fdt get value with index
Currently any integer array value is set as long up-to-40 character
hexadecimal string into environment variable when extracted from an
FDT using 'fdt get value path prop index', because the support for
handling integer arrays is not implemented, and fdt_value_env_set()
code falls back into the hash handling behavior instead.
Implement this support simply by checking whether user supplied any
index. If index is set and the property length is multiple of four,
then this is an integer array, and the code would extract value at
specified index.
There is a subtle change where default index is set to -1 instead of 0.
This is OK, since the only place which checks for index to be less or
equal zero is the string array handling code in fdt_value_env_set() and
that code would work perfectly well with index -1 too.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:22 +0000 (04:08 +0100)]
cmd: fdt: Map address returned from fdt get addr to sysmem
The address returned from 'fdt get addr' command must be mapped
into sysmem, as this is a working FDT. Access to this address
without mapping it would lead to crash e.g. in sandbox.
The following command triggers the crash:
"
./u-boot -Dc 'fdt addr $fdtcontroladdr ; fdt get addr var / compatible ; md $var'
"
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:21 +0000 (04:08 +0100)]
cmd: fdt: Handle 64bit pointers in fdt get addr
The command assumed 32bit pointers so far, with 64bit pointer the
command would overwrite a piece of stack. Fix it by extending the
array size to cater for 64bit pointer, and use snprintf() to avoid
writing past the end of the array ever again.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:20 +0000 (04:08 +0100)]
cmd: fdt: Align checksign parameter names in help text
The help text references 'addr' as an optional key start address,
but the explanation references the same as 'start', make sure they
both read as 'addr'. Also update the abbreviated 'addr' in the
explanation to 'address'.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:19 +0000 (04:08 +0100)]
cmd: fdt: Check argc before accessing argv in fdt memory
On case 'fdt memory' is invoked without parameters, argv[2]/argv[3]
is not valid and this command would SEGFAULT in sandbox environment.
Add missing argc test to avoid the crash and rather print usage help
message.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:18 +0000 (04:08 +0100)]
cmd: fdt: Check argc before accessing argv in fdt bootcpu
On case 'fdt bootcpu' is invoked without parameters, argv[2] is not
valid and this command would SEGFAULT in sandbox environment. Add
missing argc test to avoid the crash and rather print usage help
message.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:17 +0000 (04:08 +0100)]
cmd: fdt: Fix fdt rsvmem behavior on non-existent index and error message space
In case 'fdt rsvmem delete index' is passed a non-existent index, one
which does not exist in 'fdt rsvmem print', then the following command
triggers a print of help message for 'fdt' command instead of erroring
out:
=> fdt rsvmem delete 1234
This is because the subcommand errornously returns 'err' instead of
CMD_RET_FAILURE, fix it. Furthermore, align the number of spaces past
fdt_del_mem_rsv() and fdt_add_mem_rsv() in error message with the rest
of the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:16 +0000 (04:08 +0100)]
cmd: fdt: Fix fdt rm behavior on non-existent property and error message space
In case an FDT contains a node '/test-node@1234' , with no property
called 'noprop' in that node, the following command triggers a print
of help message for 'fdt' command instead of erroring out:
=> fdt rm /test-node@1234 noprop
This is because the subcommand errornously returns 'err' instead of
CMD_RET_FAILURE, fix it. Furthermore, align the number of spaces past
fdt_delprop() in error message with the rest of the code.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:15 +0000 (04:08 +0100)]
cmd: fdt: Fix handling of empty properties for fdt get addr and fdt get size
It is perfectly valid to request an address or size of FDT property
without value, the only special case if requesting of the value of
FDT property without value. Invert the test such, that properties
without value still set the variable from 'fdt get addr/size' to
address of the property or size of the property, where the later
is 0.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Thu, 2 Mar 2023 03:08:14 +0000 (04:08 +0100)]
cmd: fdt: Import is_printable_string() from DTC to fix u32 misprint
Import is_printable_string() implementation from DTC 1.7.0 as of
DTC commit 039a994 ("Bump version to v1.7.0") . This fixes a print
of u32 property which so far used to be printed as string by U-Boot
fdt print command.
We might see the case where the parsed property value, in this case
it is a 32-bit integer, identified as a printable string or a null byte
(concatenated strings) because of its last character happens to be:
0x00 (null character), 0xB (vertical tab character) or
0x10 (line feed character)
In this situation, if the string is identified as printable string,
it will be displayed as character instead of hex value
When the isprint() condition is true, there are two possibilities:
1) The character is ASCII character (except the first 32)
2) The character is extended ASCII character
For example,
NG property in device tree:
clock-frequency = <
16640000>;
by default, would be displayed as
clock-frequency = "", "ýè";
and with this patch applied, would be displayed as
clock-frequency = <0x00fde800>;
Full investigation was done by Nam and Hai, patch reworked by Marek
to use common code from DTC.
Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Signed-off-by: Nam Nguyen <nam.nguyen.yh@renesas.com>
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 6 Mar 2023 19:56:05 +0000 (14:56 -0500)]
Merge https://source.denx.de/u-boot/custodians/u-boot-marvell
- mvebu: Use 4K sector for Thecus N2350 SPI flash (Tony)
Tony Dinh [Fri, 17 Feb 2023 03:34:31 +0000 (19:34 -0800)]
arm: mvebu: Use 4K sector for Thecus N2350 SPI flash
Since the SPI flash chip mx25l3205d on this board has 4K-sector
capability, enable it for the envs.
Signed-off-by: Tony Dinh <mibodhi@gmail.com>
Reviewed-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 1 Mar 2023 21:07:24 +0000 (16:07 -0500)]
Merge tag 'dm-pull-29feb23' of https://source.denx.de/u-boot/custodians/u-boot-dm
minor sandbox fixes
a37xx fix
Add camel-case tool, since the conversion will take a while
Ralph Siemsen [Wed, 22 Feb 2023 20:56:59 +0000 (15:56 -0500)]
tools: binman: minor formatting fix in docs
This should fix a rendering oddity when viewing the docs online at
https://u-boot.readthedocs.io/en/latest/develop/package/binman.html
Signed-off-by: Ralph Siemsen <ralph.siemsen@linaro.org>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Wed, 22 Feb 2023 00:39:18 +0000 (01:39 +0100)]
sandbox: fix building with CONFIG_SPL_TIMER=y
Building sandbox_defconfig with CONFIG_SPL_TIMER=y results in an error
include/dm/platdata.h:63:33: error: static assertion failed:
"Cannot use U_BOOT_DRVINFO with of-platdata.
Please use devicetree instead"
Add a missing condition in the sandbox driver.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 18 Feb 2023 09:38:11 +0000 (10:38 +0100)]
MAINTAINERS: assign sandbox drivers to SANDBOX
Drivers should have a maintainer.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Heinrich Schuchardt [Sat, 18 Feb 2023 08:33:51 +0000 (09:33 +0100)]
sandbox: allow building sandbox_spl with CONFIG_DEBUG
Building sandbox_spl with CONFIG_DEBUG leads to errors due to missing
symbols:
/usr/bin/ld: common/spl/spl_fit.o: in function `spl_fit_upload_fpga':
common/spl/spl_fit.c:595: undefined reference to `fpga_load'
/usr/bin/ld: test/test-main.o: in function `dm_test_post_run':
test/test-main.c:124: undefined reference to `crc8'
/usr/bin/ld: test/test-main.o: in function `dm_test_pre_run':
test/test-main.c:95: undefined reference to `crc8'
collect2: error: ld returned 1 exit status
This is due to -Og not eliminating unused functions.
Add FPGA and CRC8 support to the defconfig. Sandbox tests for
SPL_FPGA and CRC8 should be created. So enabling these setting
is advised anyway.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
Robert Marko [Tue, 17 Jan 2023 14:08:15 +0000 (15:08 +0100)]
arm64: a37xx: pinctrl: probe after binding
Currently, pinctrl drivers are getting probed during post-bind, however
that is being reverted, and on A37XX pinctrl driver is the one that
registers the GPIO driver during the probe.
So, if the pinctrl driver doesn't get probed GPIO-s won't get registered
and thus they cannot be used.
This is a problem on the Methode eDPU as it just uses SB pins as GPIO-s
and without them being registered networking won't work as it only has
one SFP slot and the TX disable GPIO is on the SB controller.
So, lets just add a flag only to A37XX driver to probe after binding
in order for the GPIO driver to always get registered.
Signed-off-by: Robert Marko <robert.marko@sartura.hr>
Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Suchanek [Sat, 22 Oct 2022 21:22:01 +0000 (23:22 +0200)]
sandbox: Correctly define BITS_PER_LONG
SANDBOX_BITS_PER_LONG is the number of bits in long on the sandbox
platform.
Signed-off-by: Michal Suchanek <msuchanek@suse.de>
Simon Glass [Sat, 29 Jan 2022 21:14:20 +0000 (14:14 -0700)]
RFC: tools: Add a camel-case conversion script
This is only for posterity, since once the conversion is done, the script
is of no use.
Signed-off-by: Simon Glass <sjg@chromium.org>
Tom Rini [Wed, 1 Mar 2023 14:39:18 +0000 (09:39 -0500)]
Merge tag 'u-boot-at91-fixes-2023.04-a' of https://source.denx.de/u-boot/custodians/u-boot-at91
First set of u-boot-at91 fixes for the 2023.04 cycle:
This fixes set include one clock index fix for sama7g5 and two board
configuration alignments for pm9g45.
Tom Rini [Wed, 1 Mar 2023 01:24:25 +0000 (20:24 -0500)]
Merge tag 'u-boot-rockchip-
20230228' of https://source.denx.de/u-boot/custodians/u-boot-rockchip
Please pull the updates for rockchip platform:
- Add support for rk3588 soc;
- Add rk3588 Edgeble Neu6 board and Radxa ROCK5B board;
- Add rk3308 Radxa ROCK Pi S board;
- Add rk3568 Radxa ROCK 3 board,
- Add rk3566 Radxa Compute Module 3 board;
- Add support for sdram reg info version 3
- Refactor rockchip OTP/eFuse driver and add more soc support;
- Add external TPL support for binman;
binman support for mkimage ignore missing entry is based on [1];
[1] https://patchwork.ozlabs.org/project/uboot/patch/
20230219220158.4160763-7-jonas@kwiboo.se/
Eugen Hristev [Wed, 22 Feb 2023 09:05:13 +0000 (11:05 +0200)]
board: rock5b-rk3588: add memory gaps into kernel's DTB
RK3588 has two memory gaps when using 16 GiB DRAM size:
[0x3fc000000 , 0x3fc500000]
and
[0x3fff00000 , 0x3ffffffff]
If the kernel is agnostic to these gaps, accessing the area causes
a SError panic.
Hence, add reserved memory areas in kernel's DTB before booting.
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Eugen Hristev [Wed, 22 Feb 2023 09:05:12 +0000 (11:05 +0200)]
board: rockchip: add Radxa ROCK5B Rk3588 board
ROCK 5B is a Rockchip RK3588 based SBC (Single Board Computer) by Radxa.
There are tree variants depending on the DRAM size : 4G, 8G and 16G.
Specification:
Rockchip Rk3588 SoC
4x ARM Cortex-A76, 4x ARM Cortex-A55
4/8/16GB memory LPDDR4x
Mali G610MC4 GPU
MIPI CSI 2 multiple lanes connector
eMMC module connector
uSD slot (up to 128GB)
2x USB 2.0, 2x USB 3.0
2x HDMI output, 1x HDMI input
Ethernet port
40-pin IO header including UART, SPI, I2C and 5V DC power in
USB PD over USB Type-C
Size: 85mm x 54mm
Kernel commits:
a1d3281450ab ("arm64: dts: rockchip: Add rock-5b board")
6fb13f888f2a ("arm64: dts: rockchip: Update sdhci alias for rock-5b")
Signed-off-by: Eugen Hristev <eugen.hristev@collabora.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Vasily Khoruzhick [Thu, 23 Feb 2023 21:03:32 +0000 (13:03 -0800)]
clk: rockchip: rk3568: add more supported clk rates for sdmmc and emmc
SDHCI driver may attempt to set 26MHz clock, but clk_rk3568
will return error in this case. Apparently, SDHCI silently ignores the
error and as a result eMMC initialization fails.
Add 25 MHz and 26 MHz clk rates for sdmmc and emmc on rk3568 to fix that.
Signed-off-by: Vasily Khoruzhick <anarsoul@gmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:41 +0000 (22:44 +0000)]
rockchip: rk3588: Read cpuid from otp
Read cpuid from otp and set ethaddr for RK3588.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:41 +0000 (22:44 +0000)]
rockchip: rk3568: Read cpuid from otp
The cpuid on RK3568 is located at 0xa instead of 0x7 as all other SoCs.
Add and use a CFG_CPUID_OFFSET to define this offset.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:40 +0000 (22:44 +0000)]
rockchip: misc: Set eth1addr mac address
Set eth1addr in addition to ethaddr.
Also allow fdt fixup of ethernet mac addresses when CMD_NET is disabled.
Set ethaddr and eth1addr based on HASH and SHA256 options.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:40 +0000 (22:44 +0000)]
rockchip: efuse: Add support for RK3036
Add support for rk3036 compatible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:40 +0000 (22:44 +0000)]
rockchip: efuse: Add support for RK3128
Add support for rk3128 compatible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:40 +0000 (22:44 +0000)]
rockchip: efuse: Add support for RK3328
Add support for rk3328 compatible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:40 +0000 (22:44 +0000)]
rockchip: efuse: Add support for RK3288 and more
Add support for rk3066a, rk3188, rk322x and rk3288 compatible.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:39 +0000 (22:44 +0000)]
rockchip: efuse: Refactor to use driver data and ops
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.
Move handling of the aligned bounce buffer to main read op in order to
keep the SoC unique read op simple.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:39 +0000 (22:44 +0000)]
rockchip: otp: Add dump_otp debug command
Add a simple debug command to dump the content of the otp.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:39 +0000 (22:44 +0000)]
rockchip: otp: Add support for RK3588
Add support for rk3588 compatible.
Adjust offset using driver data in main read op.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:39 +0000 (22:44 +0000)]
rockchip: otp: Add support for RK3568
Add support for rk3568 compatible.
Handle allocation of an aligned bounce buffer in main read op in order
to keep the SoC unique read op simple.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Wed, 22 Feb 2023 22:44:38 +0000 (22:44 +0000)]
rockchip: otp: Refactor to use driver data and ops
Refactor the driver to use driver data and ops to simplify handling
of SoCs that require a unique read op.
Use readl_poll_sleep_timeout instead of a custom poll loop, and add
validation of input parameter to main read op.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:49 +0000 (20:27 +0530)]
board: rockchip: Add Edgeble Neural Compute Module 6
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
On module WiFi6/BT5 is available in the following Neu6 variants.
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.
Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.
Boot log for the record,
DDR Version V1.08
20220617
LPDDR4X, 2112MHz
channel[0] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[1] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[2] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
channel[3] BW=16 Col=10 Bk=8 CS0 Row=16 CS1 Row=16 CS=2 Die BW=16 Size=2048MB
Manufacturer ID:0x6
CH0 RX Vref:31.7%, TX Vref:21.8%,21.8%
CH1 RX Vref:30.7%, TX Vref:22.8%,23.8%
CH2 RX Vref:30.7%, TX Vref:22.8%,22.8%
CH3 RX Vref:30.7%, TX Vref:21.8%,21.8%
change to F1: 528MHz
change to F2: 1068MHz
change to F3: 1560MHz
change to F0: 2112MHz
out
U-Boot SPL 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Trying to boot from MMC1
INFO: Preloader serial: 2
NOTICE: BL31: v2.3():v2.3-391-g856309329:derrick.huang
NOTICE: BL31: Built : 14:15:50, Jul 18 2022
INFO: ext 32k is not valid
INFO: GICv3 without legacy support detected.
INFO: ARM GICv3 driver initialized in EL3
INFO: system boots from cpu-hwid-0
INFO: idle_st=0x21fff, pd_st=0x11fff9, repair_st=0xfff70001
INFO: dfs DDR fsp_params[0].freq_mhz= 2112MHz
INFO: dfs DDR fsp_params[1].freq_mhz= 528MHz
INFO: dfs DDR fsp_params[2].freq_mhz= 1068MHz
INFO: dfs DDR fsp_params[3].freq_mhz= 1560MHz
INFO: BL31: Initialising Exception Handling Framework
INFO: BL31: Initializing runtime services
WARNING: No OPTEE provided by BL2 boot loader, Booting device without OPTEE initialization. SMC`s destined for OPTEE will return SMC_UNK
ERROR: Error initializing runtime service opteed_fast
INFO: BL31: Preparing for EL3 exit to normal world
INFO: Entry point address = 0xa00000
INFO: SPSR = 0x3c9
U-Boot 2023.01-00952-g1d1785a516-dirty (Jan 30 2023 - 19:53:55 +0530)
Model: Edgeble Neu6A IO Board
DRAM: 7.5 GiB (effective 3.7 GiB)
Core: 71 devices, 15 uclasses, devicetree: separate
MMC: mmc@
fe2c0000: 0
Loading Environment from nowhere... OK
In: serial@
feb50000
Out: serial@
feb50000
Err: serial@
feb50000
Model: Edgeble Neu6A IO Board
Net: No ethernet found.
Hit any key to stop autoboot: 0
=>
Add support for Edgeble Neu6 Model A IO Board.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:47 +0000 (20:27 +0530)]
ARM: dts: rockchip: rk3588s-u-boot: Add sdmmc node
Booting from SDMMC is one of the fast and easy booting methods
for initial support of any SoC to upstream more features.
This patch is trying to add the sdmmc node for rk3588 and added
as u-boot specific node in -u-boot.dtsi as upstream Linux is not
supporting yet.
As soon as Linux supports it, a sync of the Linux device tree
would eventually drop this node.
Clock properties as added according to the rockchip mmc driver
but the actual definition might add scmi clocks into 0 and 1
indexes. This is due to scmi clock are not supporting in upstream
U-Boot. Properly addition of scmi clock would eventually follow
sdmmc clock definition of Linux once they upstreamed.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Jagan Teki [Mon, 30 Jan 2023 14:57:46 +0000 (20:27 +0530)]
ARM: dts: rockchip: Add rk3588-u-boot.dtsi
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RK3588 SoC to boot the SPL.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:45 +0000 (20:27 +0530)]
arm: rockchip: Add RK3588 arch core support
The Rockchip RK3588 is a ARM-based SoC with quad-core Cortex-A76
and quad-core Cortex-A55 including NEON and GPU, 6TOPS NPU,
Mali-G610 MP4, HDMI Out, HDMI In, DP, eDP, MIPI DSI, MIPI CSI2,
LPDDR4/4X/5, eMMC5.1, SD3.0/MMC4.5, USB OTG 3.0, Type-C, USB 2.0,
PCIe 3.0, SATA 3, Ethernet, SDIO3.0 I2C, UART, SPI, GPIO and PWM.
Add arch core support for it.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:44 +0000 (20:27 +0530)]
arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A IO
Neural Compute Module 6(Neu6) IO board is an industrial form factor
ready-to-use IO board from Edgeble AI.
IO board offers plenty of peripherals and connectivity options and
this patch enables basic eMMC and UART which is enough to successfully
boot Linux.
Neu6 needs to mount on top of this IO board in order to create a
complete Edgeble Neural Compute Module 6(Neu6) IO platform.
commit <
a5079a534554> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A IO")
Add support for Edgeble Neu6 Model A IO Board.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:43 +0000 (20:27 +0530)]
arm64: dts: rockchip: rk3588: Add Edgeble Neu6 Model A SoM
Neural Compute Module 6(Neu2) is a 96boards SoM-CB compute module
based on Rockchip RK3588 from Edgeble AI.
General features:
- Rockchip RK3588
- up to 32GB LPDDR4x
- up to 128GB eMMC
- 2x MIPI CSI2 FPC
On module WiFi6/BT5 is available in the following Neu6 variants.
Neu6 needs to mount on top of associated Edgeble IO boards for
creating complete platform solutions.
Enable eMMC for now to boot Linux successfully.
commit <
3d9a2f7e7c5e> ("arm64: dts: rockchip: rk3588: Add Edgeble Neu6
Model A SoM")
Add support for Edgeble Neu6 Model A SoM.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:42 +0000 (20:27 +0530)]
arm64: dts: rockchip: Add base DT for rk3588 SoC
This initial version supports CPU, dma, interrupts, timers, UART and
SDHCI (everything necessary to boot Linux on this system on chip) as
well as Ethernet, I2C, PWM and SPI.
The DT is split into rk3588 and rk3588s, which is a reduced version
(i.e. with less peripherals) of the former.
commit <
9fb232e9911f> (" arm64: dts: rockchip: Add base DT for rk3588
SoC")
commit <
d68a97d501f8> ("arm64: dts: rockchip: Add rk3588 pinctrl data")
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:41 +0000 (20:27 +0530)]
arm: rockchip: Add ioc header for rk3588
Add IOC unit header include for rk3588.
Signed-off-by: Steven Liu <steven.liu@rock-chips.com>
Signed-off-by: Joseph Chen <chenjh@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:40 +0000 (20:27 +0530)]
dt-bindings: reset: add rk3588 reset definitions
Add reset ID defines for rk3588.
commit <
0a8eb7dae617> ("dt-bindings: reset: add rk3588 reset
definitions")
Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:39 +0000 (20:27 +0530)]
dt-bindings: power: Add power-domain header for rk3588
Add power-domain header for RK3588 SoC from description in TRM.
commit <
67944950c2d0> ("dt-bindings: power: add power-domain header for
rk3588")
Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:38 +0000 (20:27 +0530)]
ram: rockchip: Add rk3588 ddr driver support
Add ddr driver for rk3588 to get the ram capacity.
Co-developed-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:37 +0000 (20:27 +0530)]
clk: rockchip: pll: Add pll_rk3588 type for rk3588
Add RK3588 pll set and get rate clock support.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:36 +0000 (20:27 +0530)]
clk: rockchip: Add rk3588 clk support
Add clock driver support for Rockchip RK3588 SoC.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:35 +0000 (20:27 +0530)]
dt-bindings: clk: Add dt-binding header for RK3588
Add the dt-bindings header for the Rockchip RK3588, that gets
shared between the clock controller and the clock references
in the dts.
commit <
f204a60e545c> ("dt-bindings: clock: add rk3588 clock
definitions")
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:34 +0000 (20:27 +0530)]
arm: rockchip: Add grf header for rk3588
Add GRF header for Rockchip RK3588.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:33 +0000 (20:27 +0530)]
arm: rockchip: Add cru header for rk3588
Add clock and reset unit header include for rk3588.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Mon, 30 Jan 2023 14:57:32 +0000 (20:27 +0530)]
rockchip: mkimage: Add rk3588 support
Add support for rk3588 package header in mkimage tool.
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:42 +0000 (16:27 -0600)]
evb-rk3568: Update MAINTAINERS and documentation
Update the MAINTAINERS file to include the devicetree for the
rk3568-evb1-v10 board.
Also update Rockchip board docs to include information on building
RK3568 based devices.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:41 +0000 (16:27 -0600)]
arm64: dts: rockchip: add gpio-ranges property to gpio nodes
Add gpio-ranges property to GPIO nodes so that the bank ID can
be correctly derived for each GPIO bank.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:39 +0000 (16:27 -0600)]
rockchip: rk3568: enable automatic power savings
It enables automatic clock gating on idle, disables the eDP phy by
default, and sets the core pvtpll ring length. It is reported this
lowers the temperature on at least one SoC by 7C.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:38 +0000 (16:27 -0600)]
rockchip: rk3568: add boot device detection
Enable spl to detect which device it was booted from.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:37 +0000 (16:27 -0600)]
arm64: dts: rockchip: Sync rk356x from Linux main
Sync rk3566 and rk3568 from the mainline Linux kernel (6.2-rc2 as of
this writing).
Note that this will rename the rk3568-evb to rk3568-evb1-v10.
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:35 +0000 (16:27 -0600)]
dts: rockchip: px30: add gpio-ranges property to gpio nodes
Add the gpio-ranges property to each GPIO node for use in deriving
the correct bank ID. Note that invoking "gpio status -a" no longer
causes the board to hit a "Synchronous Abort".
Fixes:
537b1a277479 ("rockchip: add px30 devicetrees")
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Chris Morgan [Mon, 13 Feb 2023 22:27:34 +0000 (16:27 -0600)]
gpio: gpio-rockchip: parse gpio-ranges for bank id
Use the new devicetree property of gpio-ranges to determine the GPIO
bank ID. Preserve the "old" way of doing things too, so that boards
can be migrated and tested gradually (I only have a 3566 and 3326 to
test).
Signed-off-by: Chris Morgan <macromorgan@hotmail.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Manoj Sai [Fri, 17 Feb 2023 11:58:45 +0000 (17:28 +0530)]
rk3566: radxa-cm3: Enable USB2.0, USB3.0 support
=> usb start
starting USB...
Bus usb@
fd000000: Register 2000140 NbrPorts 2
Starting the controller
USB XHCI 1.10
Bus usb@
fd800000: USB EHCI 1.00
scanning bus usb@
fd000000 for devices... cannot reset port 1!?
2 USB Device(s) found
scanning bus usb@
fd800000 for devices... 4 USB Device(s) found
scanning usb for storage devices... 2 Storage Device(s) found
=> usb tree
USB device tree:
1 Hub (5 Gb/s, 0mA)
| U-Boot XHCI Host Controller
|
+-2 Mass Storage (5 Gb/s, 224mA)
SanDisk Dual Drive
04019c9b2e1a58f24ee318c3c123aa5
1 Hub (480 Mb/s, 0mA)
| u-boot EHCI Host Controller
|
+-2 Hub (480 Mb/s, 100mA)
| USB 2.0 Hub
|
+-3 Mass Storage (480 Mb/s, 500mA)
| JetFlash Mass Storage Device 19M7I4ZQFTSC08SU
|
+-4 Human Interface (12 Mb/s, 98mA)
Logitech USB Receiver
Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Manoj Sai [Fri, 17 Feb 2023 11:58:44 +0000 (17:28 +0530)]
rockchip: rk3568: Select DM_REGULATOR_FIXED
Select the DM_REGULATOR_FIXED on RK3568 platform.
Co-developed-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Fri, 17 Feb 2023 11:58:43 +0000 (17:28 +0530)]
rockchip: rk3568: add rk3568 pinctrl driver
Add driver supporting pin multiplexing on rk3568 platform.
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Fri, 17 Feb 2023 11:58:42 +0000 (17:28 +0530)]
arm64: dts: rk356x-u-boot: Drop combphy1 assigned-clocks/rates
combphy1 is failing to probe due to unhandled assigned-clocks and
assigned-clocks-rates.
=> usb start
starting USB...
Bus usb@
fd000000: Failed to get PHY1 for usb@
fd000000
Port not available.
Bus usb@
fd800000: USB EHCI 1.00
There is no real requirement for them in U-Boot to handle, hence
mark them as deleted-properties for the probe to success
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jagan Teki [Fri, 17 Feb 2023 11:58:41 +0000 (17:28 +0530)]
drivers: phy: add naneng combphy for rk3568
RK3568 has three combo phys, and PCIe/USB3/SATA/QSGMII controllers
share one pipe interface for each combo phy, here is the diagram
of the complex connection.
+----------------+
| | +------+
| USB3 OTG CTRL0 |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY0 |
+----------------+ | | | |
| | | | +------------+
| SATA CTRL0 |---->| |
| | +------+
+----------------+
+----------------+
| | +------+
| USB3 HOST CTRL1|---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY1 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL1 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | | +------+
| QSGMII CTRL |---->| |
| | | | +------------+
+----------------+ | PIPE | | |
| MUX |---->| Combo PHY2 |
+----------------+ | | | |
| |---->| | +------------+
| SATA CTRL2 | -->| |
| | | +------+
+----------------+ |
|
+----------------+ |
| | |
| PCIe2 1-Lane |---
| |
+----------------+
Co-developed-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Co-developed-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Yifeng Zhao <yifeng.zhao@rock-chips.com>
Signed-off-by: Jagan Teki <jagan@edgeble.ai>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Manoj Sai [Fri, 17 Feb 2023 11:58:40 +0000 (17:28 +0530)]
phy: rockchip-inno-usb2: Add USB2 PHY for rk3568
RK3568 has two USB 2.0 PHYs, and each PHY has two ports, the OTG port
of PHY0 support OTG mode with charging detection function, they are
similar to previous Rockchip SoCs.
However, there are three different designs for RK3568 USB 2.0 PHY.
1. RK3568 uses independent USB GRF module for each USB 2.0 PHY.
2. RK3568 accesses the registers of USB 2.0 PHY IP directly by APB.
3. The two ports of USB 2.0 PHY share one interrupt.
This patch only PHY1 with necessary attributes required to function
USBPHY1 on U-Boot.
Co-developed-by: Ren Jianing <jianing.ren@rock-chips.com>
Signed-off-by: Ren Jianing <jianing.ren@rock-chips.com>
Co-developed-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>