llvmpipe: unmap display target of shader image/sampler

Revive hooks for cleaning up shader sampler and image data and when
finalizing llvmpipe_draw_vbo. In cleanup routines, for any sampler or
image that was set up with displaytarget_map, call displaytarget_unmap.

This fixes leaks of mmap calls of the underlying displaytarget
resources.

v2 (Daniel Stone):
    - Use a single cleanup function for sampler/image to simplify patchset

v3 (Emil Velikov):
    - use llvmpipe_resource_[un]map instead of open-coding through
    winsys

v4:
    - check tex/image for NULL before calling into
    llvmpipe_resource_unmap (fixes dEQP crash of llvmpipe runner)

Signed-off-by: Heinrich Fink <hfink@snap.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11741>

nir/lower_subgroups: Pad ballot values before bitcasting

Otherwise, if we cast from a uint32_t to a uint64_t, the bitcast will
fail before we pad.  This happens on Intel.

Fixes: e4e79de2a420 "nir/subgroups: Support > 1 ballot components"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5045
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11786>

android: Restore android/Android.mk

It was accidentally dropped as part of d4b482d378e3 but it's the one
Android makefile we want to keep.

Fixes: d4b482d378e3 "android: Drop the Android.mk build system"
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11798>

ac,radv: implement the cs_regalloc_hang HW bug workaround

Might fix spurious failures on GFX6 and some GFX7 chips.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11675>

docs: update zink requirements

We currently require VK_EXT_line_rasterization with *all* optional
features to render all kinds of lines required. Because some (if not
all) of these can be emulated, let's make the list explicit, so it's
easy to remove items as we implement emulation.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11795>

zink: fill in the right line-mode based on state

We need to fill in the right line-mode here based on the state to get
the correct rasterization; bresenham isn't always the right one.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11795>

zink: support line stippling

VK_EXT_line_rasterization allows us to specify a line-stilling pattern.
So let's do that.

While we're at it, use more bit-allocation here.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11795>

zink: use bit-allocation for boolean rasterizer-state

This reduces the size of the struct a bit, and we're about to add some
more bit-allocated stuff in the next commit.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11795>

zink: hook up line-rasterization ext

The VK_EXT_line_rasterization extension allows to specify the
correct line-rasterization rules, which is needed for correct OpenGL
rendering.

So, let's prepare for filling this one out. Right now, it does a whole
lot of nothing, but that's about to change.

Reviewed-By: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11795>

ir3: add newly found shlg.b16 instruction

Example of blob's output:
  (nop3) shlg.b16 hr8.x, (r)8, (r)hr8.x, 12

It does: (src2 << src1) | src2

src1 and src2 could be GPRs, relative GPRs, relative consts,
or immidiates. However, they could not be plain const registers.

Blob does use it in conjuncture with "samgq" instruction.

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11760>

aco: use nir_ssa_def_is_unused() to determine if atomic dest is used

Instead of duplicating this chunk everywhere.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11793>

vulkan/wsi/wayland: Add support for more SRGB formats.

This is required by the Vulkan specification:

If pSurfaceFormats includes an entry whose value for colorSpace is
VK_COLOR_SPACE_SRGB_NONLINEAR_KHR and whose value for format is a UNORM
(or SRGB) format and the corresponding SRGB (or UNORM) format is a color
renderable format for VK_IMAGE_TILING_OPTIMAL, then pSurfaceFormats must also
contain an entry with the same value for colorSpace and format equal to the
corresponding SRGB (or UNORM) format.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Adam Jackson <ajax@redhat.com>
Reviewed-by: Simon Ser <contact@emersion.fr>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11778>

v3dv/format: expose properly that some formats are not filterable

Specifically A8B8G8R8_UINT_PACK32, A8B8G8R8_SINT_PACK32, and
A2B10G10R10_UINT_PACK32. They are based on the internal types RGBA8UI,
RGBA8I, and RGB10_A2UI, that are not filterable.

That gets several failing CTS like this:
  dEQP-VK.api.copy_and_blit.core.blit_image.all_formats.color.3d.a8b8g8r8_uint_pack32.a8b8g8r8_uint_pack32.optimal_optimal_linear_stripes_x

To properly skip instead of fail. So we also update the ci
expectation.

Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11794>

ci: Add Fedora release build job

The intention is for this to more or less match the Fedora package
build. The main benefit right now is GCC 11 build test coverage.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11412>

ci: Add Fedora 34 based x86 build docker image

v2:
* Do not install weak dependencies in Fedora docker image.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11412>

ci: Rename Debian based build jobs from meson-* to debian-*

meson has been the only build system in tree for some time, so the
meson- prefix was a bit meaningless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11412>

ci: Add debian/ prefix to job names for Debian based docker images

And move the image build scripts to a subdirectory correspondingly.

Preparation for adding images based on other OSs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11412>

turnip: Mark local variable ASSERTED

It's only used in assert. Avoids compiler warning/error with assertions disabled:

../src/freedreno/vulkan/tu_cs.h: In function 'tu_cs_reserve':
../src/freedreno/vulkan/tu_cs.h:208:13: error: unused variable 'result' [-Werror=unused-variable]
  208 |    VkResult result = tu_cs_reserve_space(cs, reserved_size);
      |             ^~~~~~

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11412>

dlist: skip NOP command at the head of a list

If we build a dlist starting with a NOP (for alignment purpose),
we don't have to execute the NOP.

Instead shift the start value by one.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: remove unused _mesa_dlist_alloc

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: remove _mesa_dlist_alloc_aligned

It was only used in _mesa_dlist_alloc_vertex_list, so inline it there
instead.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: store all dlist in a continuous memory block

This reduces cache-misses in execute_list for apps using lots of small
dlist, like viewperf.
This is only done for small dlist (fitting in one block) because doing
this for larger ones wouldn't bring any benefit.

For instance, in vp13/snx test 10: the % of cache-misses events in
_mesa_glthread_execute_list/execute_list goes down from 17%/10% to 4%/3%.

If "struct gl_display_list" were stored in an array this would also
remove source of cache-misses since currently they're malloc-ed
individually.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: increment/check list nesting when handling OPCODE_CALL_LIST(S)

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: use a new OPCODE to avoid loading cold data

Also add a 'bool copy_to_current' param to vbo_save_playback_vertex_list:
this way we can decide if we need to call playback_copy_to_current without
loading any cold data.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: use a separate opcode for vbo replay using loopback

Remember is the current list needs to fallback to loopback,
and patch the list in glEndList.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: split hot/cold data from vertex_list

Store data not used in the hot-path (= vbo_save_playback_vertex_list) in a
pointer, to reduce the size of vbo_save_vertex_list.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

util/idalloc: add util_idalloc_alloc_range

v2: fixed infinite loop (Pierre-Eric)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

util/idalloc: add exists and foreach helpers

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

util/idalloc: hide or remove unused public functions

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

util/idalloc: reserving an ID that already exists should be no-op

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

util/idalloc: fold the size call into init

It's required, otherwise idalloc would fail.

v2: renamed util_idalloc_(mt_)init param initial_num_ids  (Pierre-Eric)

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com> (v2)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

util/idalloc: change num_elements to units of elements instead of bits

and use memset in resize().

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: always use merged primitive for drawing

OpenGL 4.6 compatibility profile spec, Appendix B:

   21.  For any GL and framebuffer state, and for any group of GL commands and
        arguments, the resulting GL and framebuffer state is identical whether the
        GL commands and arguments are executed normally or from a display list.
        The only exception to this corollary is for built-in shader variables
        gl_VertexID and gl_PrimitiveID, which are not defined when drawing
        geometry within a display list.

(thanks Ian Romanick for pointing this out in piglit !419 MR)

Remove the code introduced in ebb228bec52a to determine if merged draws can be used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: use an union instead of allocating a 1-sized array

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: unindent code

Use a goto instead of wrapping the main part of the function
in a if() {}

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: remove InstSize

Instead store the instruction size alongside the opcode.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: remove OPCODE_EXT_0

This should have been removed in bb108bdec73 ("dlist: remove ListExt feature")

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: prelock ctx->Shared->DisplayList before execute_list

Together with the glCallList change this transforms this sequence:
  lock - execute - unlock - lock - execute - unlock - ...
In this sequence :
  lock - execute - execute - execute - ... - unlock

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

dlist: add locked param to _mesa_lookup_list

This allows to take the lock once and reduce the cpu-overhead of
locking/unlocking multiple times when executing multiple lists.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

glthread: merge sucessive glCallList

Then unmarshalling a glCallList cmd if the next command(s) are also
glCallList, they are batched in a single glCallLists.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

glthread: use custom marshal/unmarshal for CallList

Will be used in the next commit.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

glthread: return consumed bytes

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

glthread: add a last parameter to unmarshal functions

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11493>

ir3/nir: Lower indirect references of compact variables

Fixes Sascha Willems "tessellation" demo on Turnip (it contains
indirect dereference of tessellation levels).

Fixes: 643f2cb ("ir3, tu: Cleanup indirect i/o lowering")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11781>

Remove redundant assignment

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4957
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11780>

radv: fix applying radv_disable_dcc for DOOM and Wolfenstein II

Mismatch between executable and application names.

Fixes: 28e1b02a6f1 ("radv: disable DCC for DOOM 2016 and Wolfenstein II")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5024
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11708>

egl/android: only apply front rendering usage in shared buffer mode

When EGL_KHR_mutable_render_buffer extension is enabled, advertised
configs unconditionally include EGL_MUTABLE_RENDER_BUFFER_BIT_KHR bit.

However, f61337b5 starts requesting front rendering usage bit when
EGL_MUTABLE_RENDER_BUFFER_BIT_KHR is seen on the SurfaceType, which
essentially forces linear usage on all winsys BOs for gallium dri and
i965 drivers on Android when cros gralloc is in use.

This patch dynamically appends or strips the front rendering usage bit
depends on whether EGL_RENDER_BUFFER is EGL_SINGLE_BUFFER or
EGL_BACK_BUFFER. The next dequeuBuffer call will switch the buffer
sharing mode while re-allocating winsys BOs given the updated gralloc
usage bits if necessary.

v2: handle ANativeWindow_setUsage on error

Fixes: f61337b5 ("egl/android: check front rendering support for cros gralloc")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Reviewed-by: Rob Clark <robdclark@chromium.org> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11787>

venus: fix empty submits with BOs

Empty submits with BOs (!batch_count && bo_count) were incorrectly
skipped.

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11791>

docs: Update relnotes for panfrost/asahi

Big changes of the branch point.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11773>

android: Drop the Android.mk build system

Android.mk files haven't really been supported by Mesa devs for a long
time.  Most of us have been willing to update Makefile.sources if we
remember and sometimes we try to blind code some Android.mk for a new
generator.  However, the reality is that it breaks regularly and ends up
being maintained by the Android community.  To address this problem
another approach was implemented in !10183 utilizing the maintained
meson build system.  The old Android.mk files are no longer required.

This commit was created with the following commands:

    git rm **/Android.mk
    git rm **/Android.*.mk
    git rm **/Makefile.sources
    git rm CleanSpec.mk

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4487
Acked-by: Roman Stratiienko <r.stratiienko@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9728>

radeonsi: enable uniform inlining by default

I think there is no reason to keep this disabled because it improves
viewperf and it might improve other things.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

ac,radeonsi: move late alloc computation into common code and shader states

This also fixes a rare deadlock when a scratch buffer is used.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

radeonsi: move an incorrectly placed comment about late alloc

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

radeonsi,radv: fix a late alloc deadlock with <= 6 CUs per SA

We should always prevent 1 CU from executing VS and GS waves
to prevent a deadlock.

Fixes: c377f45c1833052 "radeonsi/gfx10: rewrite late alloc computation"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

ac/surface/tests: fix the ARM build

Fixes: 8771d45a "ac/surface/tests: fix a random segfault in the modifier test"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/4655

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

radeonsi: rewrite a confusing comment in si_upload_and_prefetch_VB_descriptors

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

ac/llvm: rework how negative W affects culling to not call accept_func twice

Always execute the bbox code regardless of negative W, and then simply
use || to discard the result if any W is negative. This is expected to be
rare. (it only happens when a primitive intersects the near plane)

This allows us to eliminate the else statement, which is no longer
executed for accepted primitives with negative W, which are the only
primitives that needed the else branch.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

ac/llvm: don't return a status from ac_cull_triangle because it's unused

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

radeonsi: drop smoothing quality to 4xAA for better performance

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11754>

nir: Drop nir_ssa_def::name and nir_register::name

We say that they're for debug only but we don't really have a good
policy around when to set them and when not to.  In particular,
nir_lower_system_values and nir_lower_vars_to_ssa which are the chief
producers of SSA values which might reasonably have a name do not bother
to set one.  We have some names set from things like BLORP and RADV's
meta shaders but AFAICT, they're setting a name more because it's there
than because they actually care.

Also, most things other than nir_clone and nir_serialize don't bother to
try and preserve them.  You can see in the diffstat of this commit
exactly what passes attempt to preserve names.  Notably missing from the
list is opt_algebraic which is the single largest source of SSA def
churn and it happily throws names away.

These observations lead me to question whether or not names are actually
useful at all or if they're just taking up space (8B per instruction)
and wasting CPU cycles (to ralloc_strdup on the off chance we do have
one).  I don't think I can think of a single time in recent history
where I've been debugging a shader issue and a SSA value name has been
there and been useful.  If anything, the few times they are there, they
just throw me off because they mess up the indentation in nir_print.

iris shader-db on my system gets runtime -2.07734% +/- 1.26933% (n=5)

Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5439>

vulkan/wsi: fix select_memory_type when all MTs are local

The intention is to pick the system memory for the prime blit dst, but
that is not possible when all memory types are advertised to be local.

This fixes venus over vtest (i.e., unix socket) because the driver
provides no PCI bus info and wsi_device_matches_drm_fd returns false.  A
driver might also use can_present_on_device to force prime blit.

Fixes: 469875596a6 ("vulkan/wsi: Fix prime blits to use system memory for the destination")

Signed-off-by: Chia-I Wu <olvaffe@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11774>

tu: Update subgroup properties

Everything should be in place for this to actually work. Support a size
of 128, unlike the blob. I've also plumbed through ballot support, so
enable that.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3/legalize: Fix loop convergence behavior

This prevents the previous commit from being undone by the jump
optimizations in legalize, and fixes another potential case where
instead of a continue we have an if/else at the end of a loop.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Fix convergence behavior for loops with continues

When loops have continue statements, it's expected that when we execute
a divergent continue (i.e. a continue where not all of the threads
active at the start take it) we keep going with the rest of the loop
body and then reconverge at the start of the next iteration. However the
Adreno ISA seems to always take a branch that jumps backwards, assuming
it's the bottom of a loop, so we get a different, undesired convergence
behavior. There's no way I know of to control this behavior in the
instruction set, so we have to instead insert a "continue block" at the
end of the loop where continue statements reconverge which then jumps
back to the top of the loop. Since this doesn't correspond 1:1 with any
NIR block we have to make control flow handling in NIR->ir3 a bit more
complicated, unfortunately.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Implement nir subgroup intrinsics

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Handle shared registers in lower_parallelcopy

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Add subgroup pseudoinstructions

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Support any/all/getone branches

This plumbs through the support in the IR.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Cleanup ir3_legalize jump optimization

Do the optimization parts in their own loop, and be more robust when
detecting the useless jumps.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3/sched: Handle branch condition in split_pred()

Before this, if there was a block with multiple things writing p0.x,
it was a tossup whether the right one would be used as the branch
condition. Found by inspection.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Fix infinite loop in scheduler when splitting

When we go to split e.g. a p0.x producer, the only other instructions
ready to schedule are often only p0.x producers. It could happen that
they all have a lower priority than the split instruction. Then we would
immediately schedule the split instruction again, then again try to
schedule one of the other producers, be blocked, and split it, around
and around again, leading to an infinite loop. The following commit
triggered this with
dEQP-GLES3.functional.shaders.discard.dynamic_loop_always on a3xx.

Fixes: d2f4d33 ("freedreno/ir3: new pre-RA scheduler")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Make MOVMSK use repeat

MOVMSK is a bit of a special case, because it takes multiple cycles (and
therefore reduces the nops needed if it's between some other assigner
and consumer) however weird things happen if you try to start reading
the first component while it isn't finished yet. On balance making it
use repeat seems to result in a fewer special cases.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Fix shared reg delay

Based on computerator experiments, this is actually 6, including for
movmsk.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Actually allow shared reg moves to be folded

I realized that shared registers were never actually getting folded,
even after adding them to valid_flags, because the move wasn't even
being considered.

I looked at the other uses of is_same_type_mov(), and they should be ok
with this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Better valid flags for shared regs

Shared registers seem to use the same port as consts, so the same
restrictions for cat2/cat3 apply to them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Prevent propagating shared regs out of loops

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Handle unreachable blocks

This fixes a pre-existing bug in ir3, but it showed up even more due to
other changes in this series and it interacts with the logical/physical
CFG split. When both sides of an if end with a jump, a block may become
unreachable via the logical CFG, which can cause problems because it has
no predecessors to figure out the location of live-in non-shared
values. In this case we assume that nir_opt_if has removed any code in
these blocks and just skip processing live-ins for these blocks,
pretending that they aren't live.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3: Handle shared register liveness correctly

As explained in the comments added, we need to add extra edges to the
CFG which are ignored except for shared registers. This plumbs through
support for this.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

ir3/nir: Call nir_lower_subgroups

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

tu, ir3: Plumb through support for CS subgroup size/id

The way that the blob obtains the subgroup id on compute shaders is by
just and'ing gl_LocalInvocationIndex with 63, since it advertizes a
subgroupSize of 64. In order to support VK_EXT_subgroup_size_control and
expose a subgroupSize of 128, we'll have to do something a little more
flexible. Sometimes we have to fall back to a subgroup size of 64 due to
various constraints, and in that case we have to fake a subgroup size of
128 while actually using 64 under the hood, by just pretending that the
upper 64 invocations are all disabled. However when computing the
subgroup id we need to use the "real" subgroup size. For this purpose we
plumb through a driver param which exposes the real subgroup size. If
the user forces a particular subgroup size then we lower
load_subgroup_size in nir_lower_subgroups, otherwise we let it through,
and we assume when translating to ir3 that load_subgroup_size means
"give me the *actual* subgroup size that you decided in RA" and give you
the driver param.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

nir: Add read_invocation_cond_ir3 intrinsic

On qualcomm, we have shared registers similar to SGPR's on AMD. However,
there is no readlane or readfirstlane primitive. shared registers can
only be written to when just one lane is active. This means that we have
to lower readInvocation(val, id) to something like:

if (gl_SubgroupInvocation == id) {
    scalar_reg = val;
}

return scalar_reg;

However it's a bit difficult to actually get the value of
gl_SubgroupInvocation in the backend, because for compute it requires
some calculations and we don't have any CSE support in the backend. This
intrinsic lets us turn it into
"readInvocationCond(val, id == gl_SubgroupInvocation)" in NIR at which
point the backend code generation is a lot easier.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

nir/subgroups: Support > 1 ballot components

Qualcomm has a mode with a subgroup size of 128, so just emitting larger
integer operations and then lowering them later isn't an option. This
makes the pass able to handle the lowering itself, so that we don't have
to go down to 64-thread wavefronts when ballots are used.

(The GLSL and legacy SPIR-V extensions only support a maximum of 64
threads, but I guess we'll cross that bridge when we come to it...)

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

nir/subgroups: Replace lower_vote_eq_to_ballot with lower_vote_eq

Lower it to a vote instead of a ballot. This was only used for AMD, and
in that case they're pretty much the same. However Qualcomm has a vote
builtin, which we want to use instead of ballots.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6752>

radv: Set parameter cache oversubscription according to the PC lines.

This matches how RadeonSI also sets this register.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11711>

radv: Allow enabling vertex grouping, fix NGG info with it disabled.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11711>

radv: Move radv_optimize_nir_algebraic to a separate function.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11711>

radv: Add last_vgt_api_stage and use it to simplify some code.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11711>

zink: ensure sparse allocations aren't marked host-visible

Fixes: 5fee58bf599 ("zink: collapse host_visible and non-coherent alignment alloc cases")

Reviewed-by: Dave Airlie <airlied@redhat.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11768>

aco: fix shared_atomic_comp_swap if the second source isn't a VGPR

Only VGPRs are valid with DS instructions.

Cc: 21.1 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11777>

vulkan/wsi/wayland: handle dmabuf params allocation failure

Return VK_ERROR_OUT_OF_HOST_MEMORY if
zwp_linux_dmabuf_v1_create_params fails.

Signed-off-by: Simon Ser <contact@emersion.fr>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11589>

vulkan/wsi/wayland: fix wsi_wl_image_init error code

If image->buffer cannot be allocated, the value returned by
wsi_create_native_image is returned. However, if we got that far,
that value is VK_SUCCESS.

Fix it and return VK_ERROR_OUT_OF_HOST_MEMORY.

Signed-off-by: Simon Ser <contact@emersion.fr>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11589>

vulkan/wsi/wayland: remove unnecessary wl_proxy_set_queue call

A wl_proxy inherits its queue from its parent.
display->dmabuf.wl_dmabuf already has its queue correctly set up,
so it's unnecessary to set it again on the child
zwp_linux_buffer_params_v1 proxy.

Signed-off-by: Simon Ser <contact@emersion.fr>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11589>

vulkan/wsi/wayland: remove swapchain wl_drm wrapper

The sole purpose of this wl_proxy is to set the queue to
chain->display->queue. However, wl_proxy inherit their queue from
their parent, so the original wl_drm proxy already has its queue
set up properly (inherited from wl_registry).

Signed-off-by: Simon Ser <contact@emersion.fr>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11589>

st/mesa: fix size miss match for some check

While we shrink some variable from "GLuint" to "ubyte",
need to update the check from "x != ~0U" to "x != 0xff" too.

This fixes the crash for SPECviewperf 13 benchmark medical
case.

Fixes: d947e3e2c8c2 "st/mesa: decrease the size of st_vertex_program"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11757>

nir_to_tgsi: Declare immediates as float on non-native-ints hardware.

Makes the values more legible on i915g, and may keep us from tripping
asserts on nouveau's non-native-integer HW.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11744>

nir_to_tgsi: Run copy prop (and thus dce) after lower_bool_to_float.

Fixes some i915g instruction count failures by eliminating some MOVs from
translating b2f32s.

Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11744>

i915g: Fix writemasking of SEQ/SNE/SSG.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11744>

softpipe: add missing sentinel to debug option array

Add DEBUG_NAMED_VALUE_END to finalize debug option array (see
lp_screen.c). Otherwise debug_get_flags_option might attempt to read
debug_named_value::name at an offset and SIGSEGV.

Signed-off-by: Heinrich Fink <hfink@snap.com>
Fixes: 991def0edc8 ("softpipe: Convert to comma-separated SOFTPIPE_DEBUG for debug options.")
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11742>

ci: fix source-deps for radv on windows

If we're giong to build RADV on Windows, we need to make sure we trigger
the build on all RADV-changes.

Fixes: d18563ea58b ("ci: Update Windows image to build RADV")
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11731>

iris: Force device local memory for u_upload_mgr buffers

We try to place persistent/coherent buffers from the application in
system memory, because they want the CPU-GPU coherency.

However, our internal u_upload_mgr buffers are also flagged persistent +
coherent, but we absolutely want most of them in device local memory.

Mark had done this correctly in an earlier patch series, but I made a
mistake when refactoring things during upstreaming, and accidentally
put these in SMEM again.  This fixes that mistake.

Tested-by: Luis Felipe Strano Moraes <luis.strano@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11681>