Pavel Iliin [Wed, 28 Dec 2022 16:55:16 +0000 (16:55 +0000)]
[AArch64] Fix AArch64TargetParser.def includes for standalone builds.
Mark de Wever [Wed, 28 Dec 2022 17:10:39 +0000 (18:10 +0100)]
[NFC][libc++] Replaces tabs by spaces.
Jordan Rupprecht [Wed, 28 Dec 2022 16:43:04 +0000 (08:43 -0800)]
[test] Exclude //llvm/unittests:llvm_exegesis_tests due to buildkite environment.
Buildkite does not allow user perf monitoring and fails: https://buildkite.com/llvm-project/upstream-bazel/builds/49579.
```
[ RUN ] PerfHelperTest.FunctionalTest
Unable to open event. ERRNO: Permission denied. Make sure your kernel allows user space perf monitoring.
You may want to try:
$ sudo sh -c 'echo -1 > /proc/sys/kernel/perf_event_paranoid'
llvm_exegesis_tests: external/llvm-project/llvm/tools/llvm-exegesis/lib/PerfHelper.cpp:111: llvm::exegesis::pfm::Counter::Counter(llvm::exegesis::pfm::PerfEvent &&): Assertion `FileDescriptor != -1 && "Unable to open event"' failed.
```
bixia1 [Tue, 27 Dec 2022 20:28:29 +0000 (12:28 -0800)]
[mlir][sparse] Use DLT in the mangled function names for insertion.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D140484
Jordan Rupprecht [Wed, 28 Dec 2022 16:13:20 +0000 (08:13 -0800)]
[bazel] Restore libpfm as a conditional dependency for exegesis.
We used to have `pfm` built into exegesis, although since it's an external dependency we marked it as a manual target. Because of this we didn't have buildbot coverage and so we removed it in D134510 after we had a few breakages that weren't caught. This adds it back, but with three possible states similar to the story with `mpfr`, i.e. it can either be disabled, built from external sources (git/make), or use whatever `-lpfm` is installed on the system.
This change is modeled after D119547. Like that patch, the default is off (matching the status quo), but unlike that patch we don't enable it for CI because IIRC we don't have the package installed there, and building from source might be expensive. We could enable it later either after installing it on buildbot machines or by measuring build cost and deeming it OK.
Reviewed By: GMNGeoffrey
Differential Revision: https://reviews.llvm.org/D138470
Mark de Wever [Wed, 28 Dec 2022 16:04:43 +0000 (17:04 +0100)]
[NFC][libc++] Fixes ADL calls.
Sanjay Patel [Wed, 28 Dec 2022 15:28:23 +0000 (10:28 -0500)]
[InstCombine] preserve signbit semantics of NAN with fold to fabs
As discussed in issue #59279, we want fneg/fabs to conform to the
IEEE-754 spec for signbit operations - quoting from section 5.5.1
of IEEE-754-2008:
"negate(x) copies a floating-point operand x to a destination in
the same format, reversing the sign bit"
"abs(x) copies a floating-point operand x to a destination in the
same format, setting the sign bit to 0 (positive)"
"The operations treat floating-point numbers and NaNs alike."
So we gate this transform with "nnan" in addition to "nsz":
(X > 0.0) ? X : -X --> fabs(X)
Without that restriction, we could have for example:
(+NaN > 0.0) ? +NaN : -NaN --> -NaN
(because an ordered compare with NaN is always false)
That would be different than fabs(+NaN) --> +NaN.
More fabs/fneg patterns demonstrated here:
https://godbolt.org/z/h8ecc659d
(without any FMF, these are correct independently of this patch -
no fabs should be created)
The code change is a one-liner, but we have lots of tests diffs
because there are many variations of the basic pattern.
Differential Revision: https://reviews.llvm.org/D139785
Alexey Bataev [Wed, 21 Dec 2022 21:44:30 +0000 (13:44 -0800)]
[SLP]Use ShuffleInstructionBuilder for vector shrinking.
We can use ShuffleInstructionBuilder now for shrinking shuffle emission.
It allows to remove extra shuffle from the emitted code and reuse
original vector.
Part of D110978
Differential Revision: https://reviews.llvm.org/D140499
Roman Lebedev [Wed, 28 Dec 2022 13:56:20 +0000 (16:56 +0300)]
[NFC][exegesis] By default, don't dump objects to disk
It's a strictly-developer feature, which is useless most of the time.
Fixes https://github.com/llvm/llvm-project/issues/59082
Reviewed By: RKSimon, gchatelet
Differential Revision: https://reviews.llvm.org/D140700
v1nh1shungry [Wed, 28 Dec 2022 12:34:41 +0000 (13:34 +0100)]
[clangd] Fix action `RemoveUsingNamespace` for inline namespace
Existing version ignores symbols declared in an inline namespace `ns`
when removing `using namespace ns`
Reviewed By: tom-anders
Differential Revision: https://reviews.llvm.org/D138028
Christian Sigg [Wed, 28 Dec 2022 11:08:37 +0000 (12:08 +0100)]
[mlir] NFC: work around gcc-aarch64 v8.3 compilation issue in getRegionBranchSuccessorOperands implementation.
Timm Bäder [Wed, 28 Dec 2022 11:08:29 +0000 (12:08 +0100)]
[clang][Interp][NFC] Fix typo in comment
Hsiangkai Wang [Wed, 28 Dec 2022 03:42:53 +0000 (03:42 +0000)]
[RISCV][NFC] Remove redundant setOperationAction.
ISD::INSERT_VECTOR_ELT is already set above.
Differential Revision: https://reviews.llvm.org/D140716
Freddy Ye [Wed, 28 Dec 2022 08:44:54 +0000 (16:44 +0800)]
[X86] Rename CMPCCXADD intrinsics.
"__cmpccxadd_epi*" -> "_cmpccxadd_epi*"
This is to align with other intrinsics to follow single leading "_" style. Gcc
and intrinsic guide website will also apply this change.
Reviewed By: LuoYuanke, skan
Differential Revision: https://reviews.llvm.org/D140281
Jie Fu [Wed, 28 Dec 2022 08:32:44 +0000 (16:32 +0800)]
[RISCV] Fix typos in RISCVUsage.rst
Fix typos `riscv-toolchai-convention` --> `riscv-toolchain-convention`
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D140717
Qiu Chaofan [Wed, 28 Dec 2022 06:23:32 +0000 (14:23 +0800)]
Fix failure of ldst-16-byte.mir
Qiu Chaofan [Wed, 28 Dec 2022 06:06:01 +0000 (14:06 +0800)]
[PowerPC] Enable track-subreg-liveness by default
This option helps some MMA related cases to reduce unnecessary copies.
Reviewed By: shchenz
Differential Revision: https://reviews.llvm.org/D108902
Jacques Pienaar [Wed, 28 Dec 2022 05:56:58 +0000 (21:56 -0800)]
[mlir][py] Fix negative cached value in attribute builder
Previously this was incorrectly assigning py::none to where function was
expected which resulted in failure if one used a non-attribute for
attribute without registered builder.
Yonghong Song [Wed, 28 Dec 2022 03:57:30 +0000 (19:57 -0800)]
[MC][BPF] Add bpf guard for MC test data-section-prefix.ll
Commit
f27c4903c43b ("MC: Add .data. and .rodata. prefixes to MCContext
section classification") added a test assuming bpf target. But it
is possible bpf target is not configured in the clang build.
Let us add explicit bpf-target requirement for the test
so the test can be ingored properly for clang build without enabling
bpf target.
jacquesguan [Tue, 27 Dec 2022 04:45:06 +0000 (12:45 +0800)]
[mlir][vector] Fix typo, NFC.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D140681
Shilei Tian [Wed, 28 Dec 2022 03:18:57 +0000 (22:18 -0500)]
[OpenMP] Introduce basic JIT support to OpenMP target offloading
This patch adds the basic JIT support for OpenMP. Currently it only works on Nvidia GPUs.
The support for AMDGPU can be extended easily by just implementing three interface functions. However, the infrastructure requires a small extra extension (add a pre process hook) to support portability for AMDGPU because the AMDGPU backend reads target features of functions. https://github.com/shiltian/llvm-project/commit/
02bc7effccc6ff2f5ab3fe5218336094c0485766#diff-321c2038035972ad4994ff9d85b29950ba72c08a79891db5048b8f5d46915314R432 shows how it roughly works.
As for the test, even though I added the corresponding code in CMake files, the test still cannot be triggered because some code is missing in the new plugin CMake file, which has nothing to do with this patch. It will be fixed later.
In order to enable JIT mode, when compiling, `-foffload-lto` is needed, and when linking, `-foffload-lto -Wl,--embed-bitcode` is needed. That implies that, LTO is required to enable JIT mode.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D139287
Shilei Tian [Wed, 28 Dec 2022 02:52:07 +0000 (21:52 -0500)]
Revert "[OpenMP] Introduce basic JIT support to OpenMP target offloading"
This reverts commit
58906e4901ec5b7ed230d7fa96123654f6a974af because it breaks AMD's buildbot.
Michael Maitland [Fri, 16 Dec 2022 21:44:52 +0000 (13:44 -0800)]
[LV] Remove duplicate name set of vector header basic block. NFC
The preheader was named explicitly in
256c6b0ba14e8a7ab6373b61b7193ea8c0a3651c
which makes setting the name in prior commit
95b2aa511eea1f31e183a2a3aed4d2aa852d089c
unnecessary.
Differential Revision: https://reviews.llvm.org/D140246
Hui Li [Wed, 28 Dec 2022 01:12:09 +0000 (09:12 +0800)]
[LLDB][LoongArch] Optimize EmulateInstructionLoongArch related code
This is a code optimization patch that does not include feature additions
or deletions.
Reviewed By: SixWeining
Differential Revision: https://reviews.llvm.org/D140616
Aart Bik [Tue, 27 Dec 2022 23:47:02 +0000 (15:47 -0800)]
[mlir][sparse] move emitter ownership into environment
last bits and pieces of the environment refactoring
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D140709
Florian Hahn [Wed, 28 Dec 2022 00:09:52 +0000 (00:09 +0000)]
[SCEV] Properly clean up duplicated FoldCacheUser ID entries.
The current code did not properly handled duplicated FoldCacheUser ID
entries when overwriting an existing entry in the FoldCache.
This triggered verification failures reported by @uabelho and #59721.
The patch fixes that by removing stale IDs when overwriting an existing
entry in the cache.
Fixes #59721.
Shilei Tian [Wed, 28 Dec 2022 00:07:24 +0000 (19:07 -0500)]
[OpenMP] Introduce basic JIT support to OpenMP target offloading
This patch adds the basic JIT support for OpenMP. Currently it only works on Nvidia GPUs.
The support for AMDGPU can be extended easily by just implementing three interface functions. However, the infrastructure requires a small extra extension (add a pre process hook) to support portability for AMDGPU because the AMDGPU backend reads target features of functions. https://github.com/shiltian/llvm-project/commit/
02bc7effccc6ff2f5ab3fe5218336094c0485766#diff-321c2038035972ad4994ff9d85b29950ba72c08a79891db5048b8f5d46915314R432 shows how it roughly works.
As for the test, even though I added the corresponding code in CMake files, the test still cannot be triggered because some code is missing in the new plugin CMake file, which has nothing to do with this patch. It will be fixed later.
In order to enable JIT mode, when compiling, `-foffload-lto` is needed, and when linking, `-foffload-lto -Wl,--embed-bitcode` is needed. That implies that, LTO is required to enable JIT mode.
Reviewed By: jdoerfert
Differential Revision: https://reviews.llvm.org/D139287
Dave Marchevsky [Tue, 27 Dec 2022 23:56:47 +0000 (15:56 -0800)]
MC: Add .data. and .rodata. prefixes to MCContext section classification
Commit
463da422f019 ("MC: make section classification a bit more
thorough") changed MCContext::getELFSection section classification logic
to default to SectionKind::getText (previously default was
SectionKind::getReadOnly) and added some matching based on section name
to determine internal section classification.
The BPF runtime implements global variables using 'BPF map'
datastructures, specifically the arraymap BPF map type. Global variables
in a section are placed in a single arraymap value at predictable byte
offsets. Variables in different sections are placed in separate
arraymaps, so in this example:
#define SEC(name) __attribute__((section(name)))
SEC(".data.A") u32 one;
SEC(".data.A") u32 two;
SEC(".data.B") u32 three;
SEC(".data.B") u32 four;
variables one and two would correspond to some byte offsets (probably 0
and 4) in one arraymap, while three and four would be in a separate
arraymap. Variables of a bpf_spin_lock type are considered to protect
next-generation BPF datastructure types in the same arraymap value and
there can only be a single bpf_spin_lock variable per arraymap value -
and thus per section.
As a result it's necessary to keep bpf_spin_locks and the datastructures
they guard in separate data sections. Before the aforementioned commit,
a section whose name starts with ".data." - like ".data.A" - would be
classified as SectionKind::getReadOnly, whereas after it is
SectionKind::getText. If 4-byte padding is required in such a section due to
alignment of some symbol within it, classification of the section as
SectionKind::getText will result in compilation of those variables to
BPF backend failing with an error like "unable to write nop sequence of
4 bytes". This is due to nop instruction emitted in
BPFAsmBackend::writeNopData being 8 bytes, so the function fails since
it cannot emit a 4-byte nop instruction.
Let's follow the pattern of matching section names starting with ".bss."
and ".tbss." prefixes resulting in proper classification of the section
as data by adding similar matches for ".data." and ".rodata." prefixes.
This will bring padding behavior for these sections back to what it was
before that commit and fix the crash.
Differential Revision: https://reviews.llvm.org/D138477
Weverything [Tue, 27 Dec 2022 23:23:28 +0000 (15:23 -0800)]
[libc++] Remove self-include from header file NFC
Florian Hahn [Tue, 27 Dec 2022 23:24:21 +0000 (23:24 +0000)]
[IVUsers] Precommit test for zext SCEV invalidation issue.
Test case for issue reported by @uabelho and #59721
Florian Hahn [Tue, 27 Dec 2022 23:01:40 +0000 (23:01 +0000)]
[LV] Convert a few tests to use opaque pointers (NFC).
Pavel Iliin [Wed, 21 Dec 2022 11:29:53 +0000 (11:29 +0000)]
Reland "[AArch64] FMV support and necessary target features dependencies."
This relands commits
e43924a75145d2f9e722f74b673145c3e62bfd07,
a43f36142c501e2d3f4797ef938db4e0c5e0eeec,
bf94eac6a3f7c5cd8941956d44c15524fa3751bd with MSan buildbot
https://lab.llvm.org/buildbot/#/builders/5/builds/30139
use-of-uninitialized-value errors fixed.
Differential Revision: https://reviews.llvm.org/D127812
Peiming Liu [Tue, 27 Dec 2022 18:23:21 +0000 (18:23 +0000)]
[mlir][sparse] refactoring loop emitter into its own files.
Reviewed By: aartbik
Differential Revision: https://reviews.llvm.org/D140701
Aart Bik [Fri, 23 Dec 2022 01:20:52 +0000 (17:20 -0800)]
[sparse][mlir][vectorization] add support for shift-by-invariant
Reviewed By: Peiming
Differential Revision: https://reviews.llvm.org/D140596
Florian Hahn [Tue, 27 Dec 2022 18:08:31 +0000 (18:08 +0000)]
[LV] Sink scalar operands and merge regions repeatedly.
Merging regions can enable new sinking opportunities (e.g. if users of a
scalar value are moved from different VPBBs into the same VPBB). Sinking
in turn can also enable new merging opportunities (e.g. if a recipe
between to merge-able regions is moved.
To enable more sinking opportunities, repeat sinking & merging if
regions could be merged.
Also fix mergeReplicateRegions to return the correct Changed status.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D139788
Craig Topper [Tue, 27 Dec 2022 17:41:29 +0000 (09:41 -0800)]
[RISCV] Use SmallVector::append to replace some for loops in intrinsic creation. NFC
Reviewed By: eopXD
Differential Revision: https://reviews.llvm.org/D140678
zhongyunde [Tue, 27 Dec 2022 17:17:55 +0000 (01:17 +0800)]
[AArch64][MachineScheduler] Set no side effect for movprfx
The movprfx is a vector copy, so it doesn't access memory. Set the
value of hasSideEffects 0 to avoid return true for the hasUnmodeledSideEffects(),
which will block the machine scheduler which load/store instructions.
Reviewed By: paulwalker-arm
Differential Revision: https://reviews.llvm.org/D140680
Schuyler Eldridge [Thu, 22 Dec 2022 22:34:27 +0000 (17:34 -0500)]
[mlir] Fix missing OpInterface docs newline
Fix incorrect markdown generated by mlir-tblgen for an InterfaceMethod
that includes a body. Previously, this would cause the next method to
show up on the same line and produce incorrect markdown. Newlines would
only be added if the method did _not_ provide a body. E.g., previously
this was generating markdown like:
some function comment#### `next method`
This change makes this generate as:
some function comment
#### `next method`
Signed-off-by: Schuyler Eldridge <schuyler.eldridge@sifive.com>
Reviewed By: rriddle
Differential Revision: https://reviews.llvm.org/D140590
Nikita Popov [Tue, 27 Dec 2022 16:00:24 +0000 (17:00 +0100)]
[InstCombine] Remove redundant evaluateGEPOffsetExpression() fold (NFCI)
If we go through the generic EmitGEPOffset code, the resulting
expression can be (and is) reduced in the same way this code did
manually. There are no changes in lit tests or llvm-test-suite.
This fold predates the time where we started adding nsw to the adds
created by EmitGEPOffset, so it was likely needed back then.
This might not actually be NFC due to worklist order changes etc.
Nikita Popov [Tue, 27 Dec 2022 15:34:04 +0000 (16:34 +0100)]
[InstCombine] Convert test to opaque pointers (NFC)
Slightly adjust the test so it uses non-zero GEP indices, otherwise
these would get folded away with opaque pointers.
Nikita Popov [Tue, 27 Dec 2022 15:22:10 +0000 (16:22 +0100)]
[InstCombine] Convert some tests to opaque pointers (NFC)
Check lines for these were regenerated, but without any
significant changes (mostly different GEP source element types).
Nikita Popov [Tue, 27 Dec 2022 15:21:31 +0000 (16:21 +0100)]
[InstCombine] Regenerate test checks (NFC)
Nikita Popov [Tue, 27 Dec 2022 15:19:13 +0000 (16:19 +0100)]
Revert "[InstCombine] Convert some tests to opaque pointers (NFC)"
This reverts commit
66cea84681e16f3d4ebdc69031824b114a0d5681.
I did not intend to commit all the changes in here, but only the
ones with no significant differences.
Nikita Popov [Tue, 27 Dec 2022 14:49:19 +0000 (15:49 +0100)]
[InstCombine] Convert some tests to opaque pointers (NFC)
Nicolas Vasilache [Tue, 27 Dec 2022 14:14:58 +0000 (06:14 -0800)]
[mlir][Linalg] Properly propagate transform result in ScalarizeOp
Denis Antrushin [Tue, 29 Nov 2022 11:47:35 +0000 (18:47 +0700)]
[RS4GC] Rematerialize derived pointers before uses.
Introduce an option to rematerialize derived pointers immediately
before their uses instead of after every statepoint. This can be
beneficial when pointer is live across many statepoints but has
few uses.
Initial implementation is simple and rematerializes derived pointer
before every use, even if there are several uses in the same block
or rematerialization instructions can be hoisted etc.
Transformation is considered profitable if we would insert less
instructions than we would insert after every live statepoint.
Depends on D138910, D138911
Reviewed By: anna, skatkov
Differential Revision: https://reviews.llvm.org/D138912
Alexey Bataev [Tue, 27 Dec 2022 13:12:16 +0000 (05:12 -0800)]
[SLP]Fix PR59693: Do not crash trying to set insert point for buildvector
of extractvalues.
No need to get the last instruction only for vectorized extractvalues,
for gathered(buildvector sequence) still need to get the insertion
point.
Nicolas Vasilache [Tue, 27 Dec 2022 13:47:02 +0000 (05:47 -0800)]
[mlir] NFC - Expose scf::canonicalizeMinMaxOp
Nikita Popov [Tue, 27 Dec 2022 11:20:05 +0000 (12:20 +0100)]
Reapply [MergedLoadStoreMotion] Convert tests to opaque pointers (NFC)
Reapply after reapplying dependent revision.
Nikita Popov [Tue, 27 Dec 2022 12:09:25 +0000 (13:09 +0100)]
[LoadStoreVectorizer] Convert tests to opaque pointers (NFC)
Nikita Popov [Tue, 27 Dec 2022 11:57:52 +0000 (12:57 +0100)]
[LoadStoreVectorize] Regenerate test checks (NFC)
Nikita Popov [Tue, 27 Dec 2022 11:53:30 +0000 (12:53 +0100)]
[LoadStoreVectorizer] Convert some tests to opaque pointers (NFC)
Nikita Popov [Tue, 27 Dec 2022 11:52:22 +0000 (12:52 +0100)]
[LoopBoundSplit] Convert tests to opaque pointers (NFC)
Nikita Popov [Tue, 27 Dec 2022 11:17:58 +0000 (12:17 +0100)]
Reapply [MergeLoadStoreMotion] Don't require GEP for sinking
Reapply with a fix for a failing debuginfo assignment tracking test.
-----
Allow sinking stores where both operands are the same, don't require
them to have an identical GEP in each block.
This came up when migrating tests to opaque pointers, where
zero-index GEPs are omitted.
Nikita Popov [Tue, 27 Dec 2022 11:44:17 +0000 (12:44 +0100)]
[GVNHoist] Make test more robust (NFC)
Make sure these stores cannot be sunk, which might defeat the
intent of the test.
Nikita Popov [Tue, 27 Dec 2022 11:37:49 +0000 (12:37 +0100)]
Revert "[MergeLoadStoreMotion] Don't require GEP for sinking"
I missed a test failure in the DebugInfo directory.
This reverts commit
2c15b9d9e1a898cfd849db81b36d278eac3ef24e.
This reverts commit
fb435e1cb5842e1437436e9e7378dfc4106fdad8.
Nikita Popov [Tue, 27 Dec 2022 11:20:05 +0000 (12:20 +0100)]
[MergedLoadStoreMotion] Convert tests to opaque pointers (NFC)
Nikita Popov [Tue, 27 Dec 2022 11:17:58 +0000 (12:17 +0100)]
[MergeLoadStoreMotion] Don't require GEP for sinking
Allow sinking stores where both operands are the same, don't require
them to have an identical GEP in each block.
This came up when migrating tests to opaque pointers, where
zero-index GEPs are omitted.
Nikita Popov [Tue, 27 Dec 2022 11:03:59 +0000 (12:03 +0100)]
[MergedLoadStoreMotion] Add tests for store without GEPs (NFC)
MergedLoadStoreMotion currently only handles the case where each
store has it's own GEP. It fails to handle the case where the
store argument is exactly the same.
Nikita Popov [Tue, 27 Dec 2022 10:52:33 +0000 (11:52 +0100)]
[Tests] Rename InstMerge -> MergedLoadStoreMotion (NFC)
These are tests for the MergeLoadStoreMotion pass, so name them
accordingly.
Guillaume Chatelet [Tue, 27 Dec 2022 08:25:32 +0000 (08:25 +0000)]
[reland][libc][NFC] Add -fno-lax-vector-conversions compilation flag
Now that
a3d2c344773cc4fc95136fd67245880b34d8e335 has been submitted.
Guillaume Chatelet [Tue, 27 Dec 2022 10:16:23 +0000 (10:16 +0000)]
[libc][NFC] Fix lax vector conversion for aarch64
Nikita Popov [Tue, 27 Dec 2022 09:57:34 +0000 (10:57 +0100)]
[InterleavedAccess] Convert tests to opaque pointers (NFC)
Nikita Popov [Tue, 27 Dec 2022 09:56:49 +0000 (10:56 +0100)]
[LCSSA] Convert tests to opaque pointers (NFC)
Nikita Popov [Tue, 27 Dec 2022 09:54:35 +0000 (10:54 +0100)]
[Internalize] Convert tests to opaque pointers (NFC)
Nikita Popov [Tue, 27 Dec 2022 09:53:42 +0000 (10:53 +0100)]
[InferFunctionAttrs] Convert tests to opaque pointers (NFC)
serge-sans-paille [Mon, 26 Dec 2022 08:19:09 +0000 (09:19 +0100)]
[clang] Use a StringRef instead of a raw char pointer to store builtin and call information
This avoids recomputing string length that is already known at compile time.
It has a slight impact on preprocessing / compile time, see
https://llvm-compile-time-tracker.com/compare.php?from=
3f36d2d579d8b0e8824d9dd99bfa79f456858f88&to=
e49640c507ddc6615b5e503144301c8e41f8f434&stat=instructions:u
This a recommit of
e953ae5bbc313fd0cc980ce021d487e5b5199ea4 and the subsequent fixes
caa713559bd38f337d7d35de35686775e8fb5175 and
06b90e2e9c991e211fecc97948e533320a825470.
The above patchset caused some version of GCC to take eons to compile clang/lib/Basic/Targets/AArch64.cpp, as spotted in
aa171833ab0017d9732e82b8682c9848ab25ff9e.
The fix is to make BuiltinInfo tables a compilation unit static variable, instead of a private static variable.
Differential Revision: https://reviews.llvm.org/D139881
Guillaume Chatelet [Tue, 27 Dec 2022 08:30:19 +0000 (08:30 +0000)]
Revert "[libc][NFC] Add -fno-lax-vector-conversions compilation flag"
This breaks aarch64 build.
This reverts commit
32f4c3f1033e32b7d2b7ba310c46c8c0d4013eb0.
Guillaume Chatelet [Tue, 27 Dec 2022 08:25:32 +0000 (08:25 +0000)]
[libc][NFC] Add -fno-lax-vector-conversions compilation flag
eopXD [Thu, 22 Dec 2022 09:20:09 +0000 (01:20 -0800)]
[NFC][Clang][RISCV] Rename data member 'DefaultPolicy' to 'PolicyAttrs'
The naming here is strange since the value may still be updated.
Reviewed By: kito-cheng, khchen
Differential Revision: https://reviews.llvm.org/D140389
Shilei Tian [Tue, 27 Dec 2022 02:39:33 +0000 (21:39 -0500)]
[RFC][OpenMP] Update to Python3 for lit test
I think it's reasonable to upgrade to Python 3 for LIT test requirement because `lit` itself (`llvm/utils/lit/lit.py`) already switched to Python 3. In addition, LLVM already requires Python 3.6 to be the minimum version (https://llvm.org/docs/GettingStarted.html#software).
Reviewed By: jdoerfert, jhuber6
Differential Revision: https://reviews.llvm.org/D139855
Max Kazantsev [Tue, 27 Dec 2022 01:58:12 +0000 (08:58 +0700)]
[Test] Add tests with logical AND/OR
Fangrui Song [Tue, 27 Dec 2022 01:37:03 +0000 (17:37 -0800)]
[mlir] Include type_traits to support latest libc++
for std::make_unsigned_t
Nikolas Klauser [Tue, 20 Dec 2022 20:13:12 +0000 (21:13 +0100)]
[libc++] Granularize <type_traits> includes in <iterator>
Reviewed By: Mordante, #libc
Spies: libcxx-commits
Differential Revision: https://reviews.llvm.org/D140621
Kai Sasaki [Tue, 27 Dec 2022 00:30:00 +0000 (09:30 +0900)]
[mlir] Typos in affine dialect
Florian Hahn [Mon, 26 Dec 2022 22:46:24 +0000 (22:46 +0000)]
[VPlan] Remove redundant blocks by merging them into predecessors.
Add and run VPlan transform to fold blocks with a single predecessor
into the predecessor. This remove redundant blocks and addresses a TODO
to replace special handling for the vector latch VPBB.
Reviewed By: Ayal
Differential Revision: https://reviews.llvm.org/D139927
Roman Lebedev [Mon, 26 Dec 2022 20:45:37 +0000 (23:45 +0300)]
[DAGCombine] `combineShuffleToZeroExtendVectorInReg()`: widen shuffle elements before trying to match
We might have sunk a bitcast into shuffle, and now it might be operating
on more fine-grained elements than what we'd match, so we must not be
dependent on whatever the granularity the shuffle happened to be in,
but transform it into the one canonical for us - with widest elements.
Roman Lebedev [Mon, 26 Dec 2022 21:41:59 +0000 (00:41 +0300)]
[NFC][X86] Add some tests that can be matched as ZERO_EXTEND_VECTOR_INREG
Roman Lebedev [Mon, 26 Dec 2022 19:49:01 +0000 (22:49 +0300)]
[DAG] `combineShuffleToZeroExtendVectorInReg()`: try to match w/ commuted operands
We don't have any reason to expect that the operand we will match
is on any particular hand of the shuffle, so we should try both.
Roman Lebedev [Mon, 26 Dec 2022 18:46:20 +0000 (21:46 +0300)]
[AArch64] Custom lower `ISD::ZERO_EXTEND_VECTOR_INREG`
The baseline legalization for `ISD::ZERO_EXTEND_VECTOR_INREG`
(`VectorLegalizer::ExpandZERO_EXTEND_VECTOR_INREG`),
blends-in the zeros, but as mentioned e.g.
in
b4bd0a404fe26071dab0854dfd9767974909c7c4,
there is no such thing for AArch64.
So some of the shuffles that would be nicely lowered
by `LowerVECTOR_SHUFFLE()`, e.g. into `ZIP1`,
would now be unrecognizable after round-tripping
through `ISD::ZERO_EXTEND_VECTOR_INREG` recognition & legalization.
The most obvious solution is to just custom-lower
`ISD::ZERO_EXTEND_VECTOR_INREG` as the `ZIP1`-with-zeros,
like it would have been originally in that test case.
Roman Lebedev [Sun, 25 Dec 2022 19:16:30 +0000 (22:16 +0300)]
[DAGCombiner] Add a most basic `combineShuffleToZeroExtendVectorInReg()`
Sometimes we end up with a shuffles in DAG that would be
better represented as a `ISD::ZERO_EXTEND_VECTOR_INREG`,
and a failure to do so causes suboptimal codegen in a number of cases,
especially when we will then cast vector to scalar.
I acknowledge, the test changes here are rather underwhelming,
but as with all of codegen, it's always a yak shawing,
and this is the most stripped down version of the patch
that shows *some* effect without having insurmountable amount
of fallout to deal with. The next change resolves this regression.
The transformation will be extended in follow-ups.
Roman Lebedev [Mon, 26 Dec 2022 18:06:20 +0000 (21:06 +0300)]
[NFC][AArch64] Add a few vector shuffle tests that should be `zip1`
At least, they are equivalent to the `@vzipNoBlend`, which is lowered into zip1.
tlattner [Mon, 26 Dec 2022 19:29:44 +0000 (11:29 -0800)]
Commit changes to the Code of Conduct that make it more clear regarding behavior outside of LLVM spaces that impact the safety of our community members. Discussion may be found here: https://discourse.llvm.org/t/code-of-conduct-changes-related-to-llvm-project-policy-changes/64197
Sanjay Patel [Mon, 26 Dec 2022 18:12:44 +0000 (13:12 -0500)]
[InstCombine] do not add "nuw" to 1<<X if the "1" has undefined elements
This was noted as a potential miscompile in the post-commit feedback
for the patch that added this fold:
d4493dd1ed58ac3f1eab0
Sanjay Patel [Mon, 26 Dec 2022 17:34:47 +0000 (12:34 -0500)]
[InstCombine] replace undef in vector tests with poison; NFC
I left a few of the existing undef tests in place for extra
coverage and because one of those was noted as a miscompile in
the post-commit feedback for
d4493dd1ed58ac3f1eab0, but we are
transitioning to poison, so it is more valuable to test the
expected IR going forward.
Michał Górny [Mon, 26 Dec 2022 13:30:35 +0000 (14:30 +0100)]
[lldb] [utils] Fix linking lit-cpuid to LLVM dylib
Use `LINK_COMPONENTS` instead of manual `target_link_libraries` to link
lit-cpuid to LLVM components. This ensures that dylib is used along
with `LLVM_LINK_LLVM_DYLIB` rather than linking to component libraries
that may not be installed.
This fixes build failure on Gentoo after a dep on TargetParser component
was added in
f09cf34d00625e57dea5317a3ac0412c07292148.
Differential Revision: https://reviews.llvm.org/D140671
Florian Hahn [Mon, 26 Dec 2022 16:02:59 +0000 (16:02 +0000)]
Revert "[IPSCCP] Enable specialization of functions."
This reverts commit
2656572d485127cc30b8fe9752024d2a0f1c50db.
It looks like CINT2017rate/502.gcc_r gets mis-compiled with LTO + PGO on
AArch64 with function specialization.
Danila Malyutin [Fri, 23 Dec 2022 16:47:31 +0000 (19:47 +0300)]
[TwoAddressInstruction] Constrain RegClass when processing a statepoint
This transformation could've triggered a verifier assert if RegA and RegB
were of different reg classes. Fix this by constraining as the comment
for replaceRegWith suggests.
Differential Revision: https://reviews.llvm.org/D140672
Andrei Safronov [Mon, 26 Dec 2022 11:00:00 +0000 (12:00 +0100)]
[Xtensa 10/10] Add relaxations and fixups. Add rest part of Xtensa Core Instructions
Add branch/jump/call/l32r instructions and fixups support. Add R_XTENSA_32/R_XTENSA_SLOT0_OP
relocations in object files generation. Modify tests to support new instructions.
Add tests for relocations and fixups.
Differential Revision: https://reviews.llvm.org/D64836
Andrei Safronov [Mon, 26 Dec 2022 10:58:36 +0000 (11:58 +0100)]
[Xtensa 9/10] Add basic support of Xtensa disassembler
Differential Revision: https://reviews.llvm.org/D64835
Andrei Safronov [Mon, 26 Dec 2022 10:56:06 +0000 (11:56 +0100)]
[Xtensa 8/10] Add support of the Xtensa shift/load/store/move and processor control instructions
Add new subset of Core Instructions (not full yet). Add appropriate operands description,
modify asm parser, printer and code emitter. Modify tests to support new instructions.
Differential Revision: https://reviews.llvm.org/D64834
Andrei Safronov [Mon, 26 Dec 2022 10:55:06 +0000 (11:55 +0100)]
[Xtensa 7/10] Add Xtensa instruction printer
Add printer for current instructions and operands subsets.
Also add basic tests of the Xtensa instructions.
Differential Revision: https://reviews.llvm.org/D64833
Andrei Safronov [Mon, 26 Dec 2022 10:53:44 +0000 (11:53 +0100)]
[Xtensa 6/10] Add Xtensa basic assembler parser
Currently parse just described in *.td files Xtensa instructions and operands subsets.
Differential Revision: https://reviews.llvm.org/D64832
Andrei Safronov [Mon, 26 Dec 2022 10:52:38 +0000 (11:52 +0100)]
[Xtensa 5/10] Add Xtensa MCTargetDescr initial functionality
Differential Revision: https://reviews.llvm.org/D64831
Andrei Safronov [Mon, 26 Dec 2022 10:49:11 +0000 (11:49 +0100)]
[Xtensa 4/10] Add basic *td files with Xtensa architecture description
Add initial Xtensa.td file with target machine description. Add XtensaInstrInfo.td,
currently describe just susbet of Core Instructions like ALU, Processor control,
memory barrier and some move instructions. Add descriptions of the instructions
formats(XtensaInstrInfo.td) and some immediate instruction operands(XtensaOperands.td).
Add General Registers and Special Registers classes.
Differential Revision: https://reviews.llvm.org/D64830
Andrei Safronov [Mon, 26 Dec 2022 10:45:59 +0000 (11:45 +0100)]
[Xtensa 3/10] Add initial version of the Xtensa backend
Add Xtensa MCTargetDesc stub. Add XtensaTargetMachine and XtensaTargetInfo.
Modify llib/Target/LLVMBuild.txt. Now Xtensa target could be builded as EXPERIMENTAL.
Differential Revision: https://reviews.llvm.org/D64829
Andrei Safronov [Mon, 26 Dec 2022 10:39:46 +0000 (11:39 +0100)]
[Xtensa 2/10] Add Xtensa ELF definitions
Add file with Xtensa ELF relocations. Add Xtensa support to ELF.h,
ELFObject.h and ELFYAML.cpp. Add simple test of Xtensa ELF representation in YAML.
Differential Revision: https://reviews.llvm.org/D64827
Andrei Safronov [Mon, 26 Dec 2022 10:37:28 +0000 (11:37 +0100)]
[Xtensa 1/10] Recognize Xtensa in triple parsing code
I'm sharing initial set of patches that adds LLVM backend for Xtensa architecture.
It is based on this LLVM fork https://github.com/espressif/llvm-xtensa.
I prepared patches by similar way like it was already successfully done for RISCV, i.e. incrementally add an initial MC layer for Xtensa by small chunks which could be reviewable.
Differential Revision: https://reviews.llvm.org/D64826
WANG Xuerui [Mon, 26 Dec 2022 12:15:55 +0000 (20:15 +0800)]
[LoongArch][test] Regenerate checks for the ghc-cc.ll test case
Seems the codegen was stale (the extra `ret` after the tail call should
not be there, and indeed it is not emitted by the current code), plus
the whitespaces are different from the update_llc_test_checks.py style.
Simply regenerate it to fix the test failure.
Differential Revision: https://reviews.llvm.org/D140670
Lin Runze [Mon, 26 Dec 2022 10:37:09 +0000 (18:37 +0800)]
[LoongArch] Add GHC Calling Convention
This is modeled after [[ https://reviews.llvm.org/D89788 | the RISCV GHC calling convention]]
and matches [[ https://gitlab.haskell.org/ghc/ghc/-/merge_requests/9292 | the corresponding GHC change ]].
Reviewed By: xen0n, wangleiat
Differential Revision: https://reviews.llvm.org/D137495