review.tizen.org Git - platform/upstream/mesa.git/log

intel/nir: Set has_base_workgroup_id for lower_compute_system_values

This option didn't exist half a decade ago when I first implemented base
workgroup support in ANV. It's cleaner to just have split system values
like all the other zero_base+base things do.

We currently only do this for COMPUTE and not KERNEL because it lets us
avoid changing intel_clc for now. We can add KERNEL later if needed.
We also don't do this lowering for task/mesh.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>

hasvk: Implement lower_base_workgroup_id

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>

anv: Implement lower_base_workgroup_id

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>

crocus: Lower load_base_workgroup_id to zero

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>

iris: Lower load_base_workgroup_id to zero

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>

intel/fs: Support load_workgroup_id_zero_base

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>

nir/divergence: Handle base_workgroup_id and workgrpu_id_zero_base

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20068>

radv: Remove the old LBVH shader.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>

radv: Switch to new LBVH implementation.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>

radv: Add new LBVH shaders.

Contrary to the previous implementation, this actually implements an LBVH builder.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>

radv: Handle nodes with 2 invalid children in internal node converter.

Fixes: 682dc5c28e4 ("radv: Add conversion shader for internal nodes")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19891>

panfrost: Enable AFBC of more formats

Enable AFBC for all RGBA UNORM formats possible in v5. This does not
cover the AFBC rules for newer gens, nor for YUV.

Noticed with an uncompressed R8 UNORM texture in SuperTuxKart.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>

panfrost: Enable AFBC of sRGB formats

AFBC of sRGB formats should just work. We just need to flip it on and enjoy
the improved performance.

In particular, this means that RGBA8 UNORM and RGBA8 sRGB UNORM are now
considered compatible formats for AFBC. That's a bug fix, because
GALLIUM_HUD use will act like a texture view between sRGB and linear
views. For FBOs, that will "just" result in a decompression, hurting
performance. For window system rendering with AFBC, that will cause an
assertion failure, as we cannot decompress SHARED resources.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>

panfrost: Enable AFBC of cube maps

Missed by mistake. This is not the same as 3D AFBC, it's just like a 2D
array. Noted in a supertuxkart pandecode.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>

panfrost: Handle all RGB AFBC modes on v9

We're about to enable AFBC on more formats in the core AFBC code. The plane
descriptor packing needs to be aware of these new formats.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19758>

aco: Use wave size specific opcode for s_or in cube map coord code.

Cc: mesa-stable
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20041>

nir/builder: Also short-circuit for auto-generated nir_t2t<N>()

This makes nir_i2i32(b, x) behave exactly like nir_i2iN(b, x, 32) etc.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7787
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>

nir/builder: Rework the boolean conversion helpers

Move them up to where the other conversion helpers. For nir_b2<T>(),
suffix them with N like all the others and make them use
nir_type_convert() as well.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>

nir/builder: Drop nir_i2i and nir_u2u in favor of nir_x2xN

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>

nir/builder: Move conversions higher in nir_builder.h

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>

nir/builder: Short-circuit in nir_type_convert if no conversion happens

If both types are the same or both are integer types with the same bit
size, no actual conversion happens and nir_type_conversion_op() will
return nir_op_mov. In this case, there's no point in emitting the move
and we can just return src instead.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>

nir/builder: Fix indentation of nir_type_convert

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>

nir: Fix builder usage in lower_mediump_vars()

In our handling of load_deref, we were calling builder helpers to create
conversions and then adjusting the destination bit size of the load. We
should adjust the bit size first because the builder sometimes looks at
the bit sizes of SSA values passed in as arguments.

Even though it's not strictly necessary, adjust the store_deref case as
well to make it fully symmetric with the load_deref case.

Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20067>

pan/mdg: Emulate 8-bit with the 16-bit pipe

We don't care to support i8vec16, we just need a bit of 8-bit support to
implement format packing/unpacking in blend shaders. We're already doing
this by using the 16-bit pipe, we just need to commit to it all the way
-- reporting the correct sizes in max_bitsize_for_alu so the mask
packing logic works as intended -- and dropping the imov-specific hack
that was introduced to workaround a similar class of bugs.

With the previous patch, fixes:

dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1

Fixes: 39e4b7279dc ("pan/midg: Fix swizzling on 8-bit sources")
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>

pan/mdg: Refuse to schedule CSEL.vector to SMUL

Even if we only mask a single component from the result of CSEL.vector,
in our IR we treat its semantics as vector which causes trouble with
when scheduled to a scalar unit.

The problematic bundle looks like this:

   vmul.MOV.i32 R31, TMP0.xxxx, R0.yzww
   sadd.MAX.i32 TMP0.y, R0.y, #65408
   smul.CSEL.vector.i32 R0.y, TMP0.y, #127

As the comment in midgard.h illuminates, these CSEL instructions are
actually operating per-bit, lining up with the all-1's booleans in
Midgard. The Bifrost analogue is MUX.i32.bit, not CSEL.i32. We should
probably rename the Midgard instruction to make that clear.

Anyhoo, on the scalar unit, CSEL/MUX operates on the bottom 32-bits of
its source. That's ok for the usual r31.w case, because that's secretly
replicating to its nonexistent register, I think? But that doesn't work
with the CSEL.vector (MUX.vector) form, because the condition it's
actually muxing on is r31.x, which here is R0.y, not the intended R0.x.

Rather than adding more special cases to the already overcomplicated
scheduler (for the dubious benefit of avoiding a small shaderdb
regression), just avoid scheduling CSEL.vector to smul.

With the next patch, fixes:

dEQP-GLES31.functional.draw_buffers_indexed.random.max_required_draw_buffers.1

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19763>

ci: Rebalance radv/grunt testing

We've recently rebalanced our lab devices to get a fewer number of
grunts. Switch to scheduling only on the newer shinier ones, running
fewer tests. We'll evaluate the runtime, and if they're quick enough
then we can increase the amount of testing we do.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20081>

pvr: Add support to submit occlusion query sub cmds.

Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Create a separate compute context for queries.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Set isp userpass to dirty for secondary command buffers.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Process queries and emit write program when ending sub_cmd.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Kick job and end sub_cmd if barrier_store is set in vkCmdExecuteCommands.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Process secondary buffer queries in vkCmdExecuteCommands.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Save error result in cmd_buffer state.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Implement vkCmdCopyQueryPoolResults API.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Implement vkCmdResetQueryPool API.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Add support to generate query programs.

This commit adds support to generate three types of query related
programs. PVR_QUERY_TYPE_AVAILABILITY_WRITE allows to submit the
queries, PVR_QUERY_TYPE_RESET_QUERY_POOL allows to reset the pool
and PVR_QUERY_TYPE_COPY_QUERY_RESULTS is to copy the results.

Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Add PVR_SUB_CMD_TYPE_OCCLUSION_QUERY type sub cmd.

Co-authored-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Create device specific compute query programs.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Implement vkCmdEndQuery API.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Implement vkCmdBeginQuery API.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Sequential dependency should be NONE for 0 constant shared regs.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Implement vkGetQueryPoolResults API.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Add support to generate update compute kernel.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Add support to generate compute kernel to update shared regs.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

pvr: Change CDM to compute, TA to geometry and 3D to fragment.

Signed-off-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19371>

r600: Store nir shaders serialized to save memory

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7247

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20061>

aco: Don't prematurely emit s_andn2.

Split s_not + s_and allows more inverse comparision and s_cbranch_vccz
optimizations.

Foz-DB Navi21:
Totals from 516 (0.38% of 134913) affected shaders:
CodeSize: 7273724 -> 7273720 (-0.00%)
Instrs: 1364408 -> 1364407 (-0.00%)
Latency: 14604862 -> 14604858 (-0.00%)

Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19143>

Revert "radeonsi/ci: update stoney fail -> flakes"

This is partial reverts commit 5ed2265fbf7971800df5fdcf025886f5554f8598.
As the xfail should not be removed from radeonsi-stoney-fails.txt
that point out by Emma Anholt

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>

ci: Update radeonsi-raven xfail to flake

Partial revert "ci/amd: add raven flakes which was previously failing"

This reverts commit fbf93ef82145978858779e95385364b53e2385a4.

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7738
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>

ci: Add intel kbl xfail to flake

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/7738

Signed-off-by: Yonggang Luo <luoyonggang@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19860>

v3dv: pre-allocate actual events instead of event descriptors

Instead of keeping a free list of "event descriptors" which are
just the offsets in the BO state that are available, pre-allocate
the events. This is simpler as it doesn't require to allocate these
event descriptors at all.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20053>

commit_in_branch.py: variables cleanup

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>

commit_in_branch.py: add support for checking staging branches

Or any branch that contains a `/` slash.

Cc: mesa-stable
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>

commit_in_branch.py: fix tests

Apparently these were backported since I wrote these tests ^^

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19988>

ir3: Don't save/restore disasm string pointer

It's not in the key, so it randomly may or may not be present, and if it
is present then we don't actually save/restore the contents, so we will
save/restore random pointer values from the last run. Turnip already
disables searching the shader cache when assembly is requested, but
still wrote the final ir3_shader_variant which resulted in trying to
save random stale pointers when saving off the executable if a
subsequent compile hit that cache entry.

This fixes flakes in
dEQP-VK.pipeline.pipeline_library.shader_module_identifier.pipeline_from_id.*
for me.

Fixes: 56909868cd1 ("turnip: implement VK_KHR_pipeline_executable_properties")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20056>

tu: Fix binding NULL descriptor sets

This fixes the new test
dEQP-VK.pipeline.pipeline_library.graphics_library.misc.other.null_descriptor_set_in_monolithic_pipeline.

Fixes: e9f5de11d40 ("tu: Initial implementation of VK_EXT_graphics_pipeline_library")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20057>

radv: enable lower shader call vectorizing

Totals from 5 (71.43% of 7) affected shaders:
MaxWaves: 48 -> 50 (+4.17%)
Instrs: 32012 -> 32070 (+0.18%)
CodeSize: 172672 -> 172932 (+0.15%)
VGPRs: 512 -> 496 (-3.12%)
Latency: 715333 -> 715279 (-0.01%); split: -0.03%, +0.02%
InvThroughput: 149540 -> 146150 (-2.27%); split: -2.29%, +0.02%
VClause: 900 -> 897 (-0.33%)
Copies: 4173 -> 4199 (+0.62%); split: -0.12%, +0.74%
Branches: 1512 -> 1511 (-0.07%)
PreVGPRs: 475 -> 469 (-1.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20075>

radv: stop emitting R_00B8A0_COMPUTE_PGM_RSRC3 from the CS preamble

It will be always emitted as part of the compute pipeline.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: disable VRS entirely on GFX11

Based on registers, VRS changed a lot and it's unclear how to program
it. This disable VK_KHR_fragment_shading_rate, VRS flat shading and
RADV_FORCE_VRS.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: do not enable NGG culling on GFX11

RadeonSI disables it as well. It's really unclear if it will help or
not (eg. NGG culling never helped on GFX10).

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: do not enable DCC for MSAA images without FMASK

I don't know how this is supposed to work, especially for fast clears
because CMASK should be cleared to 0xC but FMASK implies CMASK.
This fixes a bunch of MSAA test failures on GFX10.3 with
RADV_DEBUG=nofmask.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: set INTERPOLATE_COMP_Z to 0 on GFX11

Ported from RadeonSI to fix a EQAA bug.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

radv: set missing SPI_SHADER_PGM_xxx registers on GFX11

Found by inspection.

Cc: 22.3 mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20054>

nir: Add helper to create passthrough GS shader

Based on nir_create_passthrough_tcs and d3d12_make_passthrough_gs, this
creates a passthrough geometry shader that can be used by drivers that
needs to emulate some graphics features in the geometry shader.

Reviewed-by: Rob Clark <robclark@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19987>

anv: enable lower_shader_calls vectorizing

On Q2RTX RT shaders :

Totals from 7 (22.58% of 31) affected shaders:
Instrs: 15453 -> 14418 (-6.70%)
Cycles: 232647 -> 224959 (-3.30%)
Send messages: 574 -> 481 (-16.20%)
Spill count: 118 -> 106 (-10.17%)
Fill count: 156 -> 140 (-10.26%)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

nir/lower_shader_calls: enable vectorizer

We cannot fully use the vectorizer outside of this pass because once
stack load/store operations have been lower to global load/store, the
robustness rule applies to those as they would to application
load/store.

But this is all internal and we know it doesn't require out of bound
checking. So doing the vectorizing here is the best solution. We just
have to teach the vectorizer about our intrinsics.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

nir/lower_shader_calls: add a pass to split load/store into scalars

We'll run this pass prior to opt_load_store_vectorize to maximize the
effect of the optimization.

At the moment opt_load_store_vectorize is unable to pack this :

  store vec3
  store vec3
  store vec2

into this :

  store vec4
  store vec3

If your backend can only do vec4 stores max.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

nir/lower_shader_calls: avoid moving loads into loops

This is similar to what opt_gcm is doing. Moving a load inside a loop
will increase memory bandwidth.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20058>

panfrost/blend: Fix invalid const values leading to NIR validation errors

Using a designated initializer like this leaves padding bits, which form
part of the aliasing u64/f64 member of the union, uninitialised, but a
nir_const_value must always have the unused bits zeroed out. Thus, use
the nir_const_value_for_float helper instead like everywhere else which
will do a memset 0 for us first.

Without this, using the pan_blend shader in a build with validation
enabled fails with:

  NIR validation failed after nir_lower_vars_to_ssa
  ...
            vec4 32 ssa_58 = load_const (0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f7cfcfd /* 0.988235 */, 0x3f800000 /* 1.000000 */)
  error: memcmp(val, &cmp_val, sizeof(cmp_val)) == 0 (../src/compiler/nir/nir_validate.c:976)

Fixes: 1378c67bcf9e ("panfrost/blend: Inline blend constants")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20071>

venus: fix android wsi with global fencing disabled

Fixes: b21e4a7990c ("venus: put android wsi on the sub-optimal path")

Signed-off-by: Yiwei Zhang <zzyiwei@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20049>

radeonsi/vcn: set current pic index correctly

video corruption observed while running decode test for av1
content in chromeos.

solution is when target buffer is found in render pic list and when
target codec is null, set curr_pic_indx as index to the
pic in render pic list.

Cc: mesa-stable
Signed-off-by: Sajeesh Sidharthan <sajeesh.sidharthan@amd.com>
Reviewed-by: Boyuan Zhang <Boyuan.Zhang@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20000>

nir/lower_int64: fix shift lowering

Starting with !19748 lowered 64 bit shifts were showing wrong results for
shifts with insignificant bits set.

nir shifts are defined to only look at the least significant bits. The
lowering has take this into account.

So there are two things going on:
1. the `ieq` and `uge` further down depend on `y` being masked.
2. the calculation of `reverse_count` actually depends on a masked `y` as
well, due to the `(iabs (iadd y -32))` giving a different result for
shifts > 31;

Fixes: 41f3e9e5f5d ("nir: Implement lowering of 64-bit shift operations")
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19995>

ci/freedreno: Add another blend_equation_advanced flake.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20066>

panfrost: add GALLIUM_HUD=draw-calls

Signed-off-by: Italo Nicola <italonicola@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20063>

tu: Use right enum for compute active_shader_stages

This is VkShaderStageFlags, not VkPipelineStageFlags. Fixes preloading
descriptors for compute dispatches.

Fixes: d862a2ebcbf ("turnip: Only emit descriptor loads for active stages in the pipeline.")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20059>

turnip: Drop the cs argument from tu6_emit_cache_flush*().

It's always draw_cs or cs.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>

turnip: Clean up a repeated pattern around tu6_emit_flushes().

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>

turnip: Make tu_emit_cache_flush_ccu manage flush bits like other paths.

Everyone else sets the cache bits directly then calls tu6_emit_flushes on
them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19939>

radv: inline gfx10_emit_streamout_{begin,end}()

Instead of having 2 different paths.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Tatsuyuki Ishi <ishitatsuyuki@gmail.com
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19632>

meson: Enable system_has_kms_drm for android

This allows to build libgbm when system = 'android' is set in
the cross_file.

Cc: "22.3" "22.2" mesa-stable
Signed-off-by: Roman Stratiienko <r.stratiienko@gmail.com>
Acked-by: Mauro Rossi <issor.oruam@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20033>

radv: compile GS copy shader after geometry shader

This affects the pipeline feedback durations: GS copy shader compilation
is now included in the GS compilation duration.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: remove old streamout code

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: remove old GS copy shader code

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: implement GS copy shaders using NIR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv: make radv_use_llvm_for_stage device parameter const

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv: lower streamout in NIR

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

radv,aco: export legacy vertex outputs in NIR

This new behaviour will let us insert exports in GS copy shader control
flow.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18898>

pvr: Add missing valgrind includes and fix unused return value.

On including the header the compiler started throwing warnings
about the return value not being used when setting and getting the
vbits.

This commit adds the missing valgrind related headers and fixes the
warnings caused by including them.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Matt Coster <matt.coster@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20035>

docs/zink: document missing max-image requirements

This should bring Zink's documentation up to speed with the previous
commit.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

mesa/main: verify more texture-limits for GL 4.1

OpenGL 4.1 also increased the minimum 3D and cube texture size as
well as the minimum number of texture-array layers. Let's also
verify these to prevent enbaling too recent GL versions on layered
drivers link Zink, VirGL etc.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

zink: check maxImageDimension1D as well as maxImageDimension2D

According to the docs for PIPE_CAP_MAX_TEXTURE_2D_SIZE, it's the limit
both for 2D *and* 1D textures. So let's take the min of the two vulkan
features here instead of assuming they're the same.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

freedreno: fix PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS for a6xx

We're reporting 2048 for VkPhysicalDeviceLimits::maxImageArrayLayers on
Turnip, so we should be able to use 2048 for OpenGL as well. And that's
the minimum required value for OpenGL 4.1 support.

According to http://vulkan.gpuinfo.org/, it seems like values of 2048
should be possible for at least as low as some Adreno 4xx GPUs. But
since we don't support recent GL versions on those, we this won't make a
big difference. So let's leave that up to someone who actually knows
what they're doing!

Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

d3d12: fix return-value for PIPE_CAP_MAX_TEXTURE_3D_LEVELS

D3D12_REQ_TEXTURE3D_U_V_OR_W_DIMENSION is 2^11, not 2^10 like the
comment said, and the code assumed. We need to add one to account for
the base-level.

Let's add a static_assert here to prove that this is the right value.

Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

d3d12: fix max-array-layers

We used to need this, because we incorrectly multiplied the cube array
sizes by 6. Now that this has been fixed, we can actually support the
OpenGL 4.1 limit for this.

Fixes: 7118b2136e9 ("d3d12: Don't multiply cube array sizes by 6")
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19780>

radv: use HTILE for VRS image only on GFX10.3

Based on registers, GFX11 no longer uses HTILE.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>

radv: do not clear VRS_HTILE_ENCODING on GFX11

This field no longer exists.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19962>

pvr: Query kernel for free list max size

Signed-off-by: Sarah Walker <sarah.walker@imgtec.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19976>

tu: Fix fault with variable-count inline uniform blocks

This seems to have been triggered by some recent CTS changes which
changed the random number generation. I'm seeing context faults in
dEQP-VK.binding_model.descriptorset_random.sets4.dynindexed.ubolimitlow.sbolimitlow.sampledimghigh.lowimgnotex.iublimitlow.nouab.comp.noia.0
that are fixed by this.

Fixes: 37cde2c6348 ("tu: Rewrite inline uniform implementation")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20039>