platform/kernel/linux-rpi.git
4 years agodrm/nouveau: gr/gk20a: Use firmware version 0
Thierry Reding [Wed, 3 Jun 2020 14:20:02 +0000 (16:20 +0200)]
drm/nouveau: gr/gk20a: Use firmware version 0

Tegra firmware doesn't actually use any version numbers and passing -1
causes the existing firmware binaries not to be found. Use version 0 to
find the correct files.

Fixes: ef16dc278ec2 ("drm/nouveau/gr/gf100-: select implementation based on available FW")
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/gm200-: detect and potentially disable HDA support on some SORs
Ben Skeggs [Wed, 3 Jun 2020 02:51:03 +0000 (12:51 +1000)]
drm/nouveau/disp/gm200-: detect and potentially disable HDA support on some SORs

Some HDA pin widgets may be disabled by BIOS, and unavailable from a
SOR.  Our SOR allocation policy uses this information to allocate an
appropriate SOR when HDA is supported by a display.

Thank you to NVIDIA for providing the information to determine this.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/gp100: split SOR implementation from gm200
Ben Skeggs [Thu, 4 Jun 2020 04:22:32 +0000 (14:22 +1000)]
drm/nouveau/disp/gp100: split SOR implementation from gm200

GP100 needs different HDA detection.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp: modify OR allocation policy to account for HDA requirements
Ben Skeggs [Wed, 3 Jun 2020 01:43:23 +0000 (11:43 +1000)]
drm/nouveau/disp: modify OR allocation policy to account for HDA requirements

Since GM200, SORs are no longer tied to a specific connector, and we
allocate them instead, with the assumption that all SORs are equally
capable.

However, there's a 1<->1 mapping between SOR and HDA pin widget, and
it turns out that it's possible for some widgets to be disabled...

In order to avoid picking a SOR without a valid pin widget, some new
rules need to be added.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp: split part of OR allocation logic into a function
Ben Skeggs [Wed, 3 Jun 2020 01:40:47 +0000 (11:40 +1000)]
drm/nouveau/disp: split part of OR allocation logic into a function

No logical changes here, this is just moving the code to make the
changes in the next commit more obvious.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp: provide hint to OR allocation about HDA requirements
Ben Skeggs [Wed, 3 Jun 2020 01:37:56 +0000 (11:37 +1000)]
drm/nouveau/disp: provide hint to OR allocation about HDA requirements

Will be used by a subsequent commit to influence SOR allocation policy.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms/gt215-: fix race with audio driver runpm
Ben Skeggs [Fri, 29 May 2020 07:57:29 +0000 (17:57 +1000)]
drm/nouveau/kms/gt215-: fix race with audio driver runpm

The audio driver can call into nouveau right while we're in the middle
of re-fetching the EDID, and decide it no longer needs to be awake.

Stop depending on EDID in the audio component get_eld() callback, and
instead cache whether audio support is present from the prior modeset.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/gm200-: fix NV_PDISP_SOR_HDMI2_CTRL(n) selection
Ben Skeggs [Fri, 29 May 2020 05:18:47 +0000 (15:18 +1000)]
drm/nouveau/disp/gm200-: fix NV_PDISP_SOR_HDMI2_CTRL(n) selection

This is a SOR register, and not indexed by the bound head.

Fixes display not coming up on high-bandwidth HDMI displays under a
number of configurations.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/dispnv50: fix runtime pm imbalance on error
Dinghao Liu [Wed, 20 May 2020 10:47:48 +0000 (18:47 +0800)]
drm/nouveau/dispnv50: fix runtime pm imbalance on error

pm_runtime_get_sync() increments the runtime PM usage counter even
the call returns an error code. Thus a pairing decrement is needed
on the error handling path to keep the counter balanced.

Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau: fix runtime pm imbalance on error
Dinghao Liu [Wed, 20 May 2020 10:36:04 +0000 (18:36 +0800)]
drm/nouveau: fix runtime pm imbalance on error

pm_runtime_get_sync() increments the runtime PM usage counter even
the call returns an error code. Thus a pairing decrement is needed
on the error handling path to keep the counter balanced.

Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau: fix runtime pm imbalance on error
Dinghao Liu [Wed, 20 May 2020 10:25:49 +0000 (18:25 +0800)]
drm/nouveau: fix runtime pm imbalance on error

pm_runtime_get_sync() increments the runtime PM usage counter even
the call returns an error code. Thus a pairing decrement is needed
on the error handling path to keep the counter balanced.

Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/debugfs: fix runtime pm imbalance on error
Dinghao Liu [Wed, 20 May 2020 10:14:53 +0000 (18:14 +0800)]
drm/nouveau/debugfs: fix runtime pm imbalance on error

pm_runtime_get_sync() increments the runtime PM usage counter even
the call returns an error code. Thus a pairing decrement is needed
on the error handling path to keep the counter balanced.

Signed-off-by: Dinghao Liu <dinghao.liu@zju.edu.cn>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/nouveau/hmm: fix migrate zero page to GPU
Ralph Campbell [Wed, 20 May 2020 18:36:52 +0000 (11:36 -0700)]
drm/nouveau/nouveau/hmm: fix migrate zero page to GPU

When calling OpenCL clEnqueueSVMMigrateMem() on a region of memory that
is backed by pte_none() or zero pages, migrate_vma_setup() will fill the
source PFN array with an entry indicating the source page is zero.
Use this to optimize migration to device private memory by allocating
GPU memory and zero filling it instead of failing to migrate the page.

Signed-off-by: Ralph Campbell <rcampbell@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocations
Ralph Campbell [Tue, 21 Apr 2020 23:11:07 +0000 (16:11 -0700)]
drm/nouveau/nouveau/hmm: fix nouveau_dmem_chunk allocations

In nouveau_dmem_init(), a number of struct nouveau_dmem_chunk are allocated
and put on the dmem->chunk_empty list. Then in nouveau_dmem_pages_alloc(),
a nouveau_dmem_chunk is removed from the list and GPU memory is allocated.
However, the nouveau_dmem_chunk is never removed from the chunk_empty
list nor placed on the chunk_free or chunk_full lists. This results
in only one chunk ever being actually used (2MB) and quickly leads to
migration to device private memory failures.

Fix this by having just one list of free device private pages and if no
pages are free, allocate a chunk of device private pages and GPU memory.

Signed-off-by: Ralph Campbell <rcampbell@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST
Lyude Paul [Mon, 11 May 2020 22:41:27 +0000 (18:41 -0400)]
drm/nouveau/kms/nv50-: Share DP SST mode_valid() handling with MST

Currently, the nv50_mstc_mode_valid() function is happy to take any and
all modes, even the ones we can't actually support sometimes like
interlaced modes.

Luckily, the only difference between the mode validation that needs to
be performed for MST vs. SST is that eventually we'll need to check the
minimum PBN against the MSTB's full PBN capabilities (remember-we don't
care about the current bw state here). Otherwise, all of the other code
can be shared.

So, we move all of the common mode validation in
nouveau_connector_mode_valid() into a separate helper,
nv50_dp_mode_valid(), and use that from both nv50_mstc_mode_valid() and
nouveau_connector_mode_valid(). Note that we allow for returning the
calculated clock that nv50_dp_mode_valid() came up with, since we'll
eventually want to use that for PBN calculation in
nv50_mstc_mode_valid().

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes()
Lyude Paul [Mon, 11 May 2020 22:41:26 +0000 (18:41 -0400)]
drm/nouveau/kms/nv50-: Move 8BPC limit for MST into nv50_mstc_get_modes()

This just limits the BPC for MST connectors to a maximum of 8 from
nv50_mstc_get_modes(), instead of doing so during
nv50_msto_atomic_check(). This doesn't introduce any functional changes
yet (other then userspace now lying about the max bpc, but we can't
support that yet anyway so meh). But, we'll need this in a moment so
that we can share mode validation between SST and MST which will fix
some real world issues.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms/gv100-: Add support for interlaced modes
Lyude Paul [Mon, 11 May 2020 22:41:25 +0000 (18:41 -0400)]
drm/nouveau/kms/gv100-: Add support for interlaced modes

We advertise being able to set interlaced modes, so let's actually make
sure to do that. Otherwise, we'll end up hanging the display engine due
to trying to set a mode with timings adjusted for interlacing without
telling the hardware it's actually an interlaced mode.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing support
Lyude Paul [Mon, 11 May 2020 22:41:24 +0000 (18:41 -0400)]
drm/nouveau/kms/nv50-: Probe SOR and PIOR caps for DP interlacing support

Right now, we make the mistake of allowing interlacing on all
connectors. Nvidia hardware does not always support interlacing with DP
though, so we need to make sure that we don't allow interlaced modes to
be set in such situations as otherwise we'll end up accidentally hanging
the display HW.

This fixes some hangs with Turing, which would be caused by attempting
to set an interlaced mode on hardware that doesn't support it. This
patch likely fixes other hardware hanging in the same way as well.

Note that we say we probe PIOR caps, but they don't actually have any
interlacing caps. So, the get_caps() function for PIORs just sets
interlacing support to true.

Changes since v1:
* Actually probe caps correctly this time, both on EVO and NVDisplay.
Changes since v2:
* Fix probing for < GF119
* Use vfunc table, in prep for adding more caps in the future.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms/nv50-: Initialize core channel in nouveau_display_create()
Lyude Paul [Mon, 11 May 2020 22:41:23 +0000 (18:41 -0400)]
drm/nouveau/kms/nv50-: Initialize core channel in nouveau_display_create()

We'll need the core channel initialized and ready by the time that we
start creating modesetting objects, so that we can call the
NV507D_GET_CAPABILITIES method to make the hardware expose it's
modesetting capabilities for later probing.

So, when loading the driver prepare the core channel from within
nouveau_display_create(). Everywhere else, we initialize the core
channel during resume.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/hda/gv100-: NV_PDISP_SF_AUDIO_CNTRL0 register moved
Ben Skeggs [Wed, 6 May 2020 04:41:01 +0000 (14:41 +1000)]
drm/nouveau/disp/hda/gv100-: NV_PDISP_SF_AUDIO_CNTRL0 register moved

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/hda/gf119-: select HDA device entry based on bound head
Ben Skeggs [Wed, 6 May 2020 04:40:58 +0000 (14:40 +1000)]
drm/nouveau/disp/hda/gf119-: select HDA device entry based on bound head

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/hda/gf119-: add HAL for programming device entry in SF
Ben Skeggs [Wed, 6 May 2020 04:40:56 +0000 (14:40 +1000)]
drm/nouveau/disp/hda/gf119-: add HAL for programming device entry in SF

Register has moved on GV100.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/hda/gt215-: pass head to nvkm_ior.hda.eld()
Ben Skeggs [Wed, 6 May 2020 04:40:52 +0000 (14:40 +1000)]
drm/nouveau/disp/hda/gt215-: pass head to nvkm_ior.hda.eld()

We're going to use the bound head to select HDA device entry.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/nv50-: increase timeout on pio channel free() polling
Ben Skeggs [Wed, 6 May 2020 04:40:45 +0000 (14:40 +1000)]
drm/nouveau/disp/nv50-: increase timeout on pio channel free() polling

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Fix regression by audio component transition
Takashi Iwai [Thu, 16 Apr 2020 07:54:28 +0000 (09:54 +0200)]
drm/nouveau/kms: Fix regression by audio component transition

Since the commit 742db30c4ee6 ("drm/nouveau: Add HD-audio component
notifier support"), the nouveau driver notifies and pokes the HD-audio
HPD and ELD via audio component, but this seems broken.  The culprit
is the naive assumption that crtc->index corresponds to the HDA pin.
Actually this rather corresponds to the MST dev_id (alias "pipe" in
the audio component framework) while the actual port number is given
from the output ior id number.

This patch corrects the assignment of port and dev_id arguments in the
audio component ops to recover from the HDMI/DP audio regression.

Fixes: 742db30c4ee6 ("drm/nouveau: Add HD-audio component notifier support")
BugLink: https://bugzilla.kernel.org/show_bug.cgi?id=207223
Cc: <stable@vger.kernel.org>
Signed-off-by: Takashi Iwai <tiwai@suse.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/device: use regular PRI accessors in chipset detection
Ben Skeggs [Thu, 30 Apr 2020 04:08:53 +0000 (14:08 +1000)]
drm/nouveau/device: use regular PRI accessors in chipset detection

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/device: detect vGPUs
Karol Herbst [Tue, 28 Apr 2020 16:54:04 +0000 (18:54 +0200)]
drm/nouveau/device: detect vGPUs

Using ENODEV as this prevents probe failed errors in dmesg.

v2: move check further down

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/device: detect if changing endianness failed
Karol Herbst [Tue, 28 Apr 2020 16:54:03 +0000 (18:54 +0200)]
drm/nouveau/device: detect if changing endianness failed

v2: relax the checks a little

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/device: rework mmio mapping code to get rid of second map
Karol Herbst [Tue, 28 Apr 2020 16:54:02 +0000 (18:54 +0200)]
drm/nouveau/device: rework mmio mapping code to get rid of second map

Fixes warnings on GPUs with smaller a smaller mmio region like vGPUs.

Signed-off-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/mmu: Remove unneeded semicolon
Zheng Bin [Fri, 24 Apr 2020 07:36:01 +0000 (15:36 +0800)]
drm/nouveau/mmu: Remove unneeded semicolon

Fixes coccicheck warning:

drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.h:307:2-3: Unneeded semicolon
drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.c:583:2-3: Unneeded semicolon

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zheng Bin <zhengbin13@huawei.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau: Use generic helper to check _PR3 presence
Kai-Heng Feng [Thu, 23 Apr 2020 06:23:58 +0000 (14:23 +0800)]
drm/nouveau: Use generic helper to check _PR3 presence

Replace nouveau_pr3_present() in favor of a more generic one,
pci_pr3_present().

Also the presence of upstream bridge _PR3 doesn't need to go hand in
hand with device's _DSM, so check _PR3 before _DSM.

Signed-off-by: Kai-Heng Feng <kai.heng.feng@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/acr: Use kmemdup instead of kmalloc and memcpy
Zou Wei [Tue, 21 Apr 2020 12:37:31 +0000 (20:37 +0800)]
drm/nouveau/acr: Use kmemdup instead of kmalloc and memcpy

Fixes coccicheck warning:

drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c:103:23-30: WARNING opportunity for kmemdup
drivers/gpu/drm/nouveau/nvkm/subdev/acr/hsfw.c:113:22-29: WARNING opportunity for kmemdup

Fixes: 22dcda45a3d1 ("drm/nouveau/acr: implement new subdev to replace "secure boot"")
Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: Zou Wei <zou_wei@huawei.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/core/memory: remove redundant assignments to variable ret
Colin Ian King [Sat, 29 Feb 2020 00:53:07 +0000 (00:53 +0000)]
drm/nouveau/core/memory: remove redundant assignments to variable ret

The variable ret is being initialized with a value that is never
read and it is being updated later with a new value. The initialization
is redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/svm: map pages after migration
Ralph Campbell [Wed, 4 Mar 2020 00:13:39 +0000 (16:13 -0800)]
drm/nouveau/svm: map pages after migration

When memory is migrated to the GPU, it is likely to be accessed by GPU
code soon afterwards. Instead of waiting for a GPU fault, map the
migrated memory into the GPU page tables with the same access permissions
as the source CPU page table entries. This preserves copy on write
semantics.

Signed-off-by: Ralph Campbell <rcampbell@nvidia.com>
Cc: Christoph Hellwig <hch@lst.de>
Cc: Jason Gunthorpe <jgg@mellanox.com>
Cc: "Jérôme Glisse" <jglisse@redhat.com>
Cc: Ben Skeggs <bskeggs@redhat.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/disp/gv100-: expose capabilities class
Ben Skeggs [Wed, 12 Feb 2020 23:39:34 +0000 (09:39 +1000)]
drm/nouveau/disp/gv100-: expose capabilities class

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/bios: move ACPI _ROM handling
Ben Skeggs [Wed, 29 Jan 2020 08:27:39 +0000 (18:27 +1000)]
drm/nouveau/bios: move ACPI _ROM handling

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau: remove open-coded version of remove_conflicting_pci_framebuffers()
Ben Skeggs [Sun, 2 Feb 2020 03:55:23 +0000 (13:55 +1000)]
drm/nouveau: remove open-coded version of remove_conflicting_pci_framebuffers()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/gr/gk20a: move MODULE_FIRMWARE firmware definitions
Ben Skeggs [Fri, 7 Feb 2020 02:39:25 +0000 (12:39 +1000)]
drm/nouveau/gr/gk20a: move MODULE_FIRMWARE firmware definitions

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/ibus: use nvkm_subdev_new_()
Ben Skeggs [Tue, 11 Feb 2020 07:36:49 +0000 (17:36 +1000)]
drm/nouveau/ibus: use nvkm_subdev_new_()

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/core: add nvkm_subdev_new_() for bare subdevs
Ben Skeggs [Tue, 11 Feb 2020 07:34:58 +0000 (17:34 +1000)]
drm/nouveau/core: add nvkm_subdev_new_() for bare subdevs

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Support NVIDIA format modifiers
James Jones [Mon, 10 Feb 2020 23:15:55 +0000 (15:15 -0800)]
drm/nouveau/kms: Support NVIDIA format modifiers

Allow setting the block layout of a nouveau FB
object using DRM format modifiers.  When
specified, the format modifier block layout and
kind overrides the GEM buffer's implicit layout
and kind.  The specified format modifier is
validated against the list of modifiers supported
by the target display hardware.

v2: Used Tesla family instead of NV50 chipset compare
v4: Do not cache kind, tile_mode in nouveau_framebuffer
v5: Resolved against nouveau_framebuffer cleanup

Signed-off-by: James Jones <jajones@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Check framebuffer size against bo
James Jones [Mon, 10 Feb 2020 23:15:54 +0000 (15:15 -0800)]
drm/nouveau/kms: Check framebuffer size against bo

Make sure framebuffer dimensions and tiling
parameters will not result in accesses beyond the
end of the GEM buffer they are bound to.

v3: Return EINVAL when creating FB against BO with
    unsupported tiling
v5: Resolved against nouveau_framebuffer cleanup

Signed-off-by: James Jones <jajones@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Add format mod prop to base/ovly/nvdisp
James Jones [Mon, 10 Feb 2020 23:15:53 +0000 (15:15 -0800)]
drm/nouveau/kms: Add format mod prop to base/ovly/nvdisp

Advertise support for the full list of format
modifiers supported by each class of NVIDIA
desktop GPU display hardware.  Stash the array
of modifiers in the nouveau_display struct for
use when validating userspace framebuffer
creation requests, which will be supportd in
a subsequent change.

Signed-off-by: James Jones <jajones@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/acr: ensure falcon providing acr functions is bootstrapped first
Ben Skeggs [Mon, 10 Feb 2020 22:45:04 +0000 (08:45 +1000)]
drm/nouveau/acr: ensure falcon providing acr functions is bootstrapped first

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Remove struct nouveau_framebuffer
Thomas Zimmermann [Thu, 6 Feb 2020 10:19:42 +0000 (11:19 +0100)]
drm/nouveau/kms: Remove struct nouveau_framebuffer

After its cleanup, struct nouveau_framebuffer is only a wrapper around
struct drm_framebuffer. Use the latter directly.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Remove field nvbo from struct nouveau_framebuffer
Thomas Zimmermann [Thu, 6 Feb 2020 10:19:41 +0000 (11:19 +0100)]
drm/nouveau/kms: Remove field nvbo from struct nouveau_framebuffer

The buffer object stored in nvbo is also available GEM object in obj[0]
of struct drm_framebuffer. Therefore remove nvbo in favor obj[0] and
replace all references accordingly. This may require an additional cast.

With this change we can already replace nouveau_user_framebuffer_destroy()
and nouveau_user_framebuffer_create_handle() with generic GEM helpers.
Calls to nouveau_framebuffer_new() receive a GEM object.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Move struct nouveau_framebuffer.vma to struct nouveau_fbdev
Thomas Zimmermann [Thu, 6 Feb 2020 10:19:40 +0000 (11:19 +0100)]
drm/nouveau/kms: Move struct nouveau_framebuffer.vma to struct nouveau_fbdev

The vma field of struct nouveau_framebuffer is a special field for the
the accelerated fbdev console. Hence there's at most one single instance
for the active console. Moving it into struct nouveau_fbdev makes struct
nouveau_framebuffer slightly smaller and brings it closer to struct
drm_framebuffer.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau/kms: Remove unused fields from struct nouveau_framebuffer
Thomas Zimmermann [Thu, 6 Feb 2020 10:19:39 +0000 (11:19 +0100)]
drm/nouveau/kms: Remove unused fields from struct nouveau_framebuffer

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm/nouveau: fix out-of-tree module build
Ben Skeggs [Wed, 29 Jan 2020 07:32:22 +0000 (17:32 +1000)]
drm/nouveau: fix out-of-tree module build

The $(srctree) addition a while back busted building the out-of-tree
version of the module, and I've been hacking it up ever since.

This allows us to work around the issue.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agodrm: Generalized NV Block Linear DRM format mod
James Jones [Wed, 11 Dec 2019 20:55:47 +0000 (12:55 -0800)]
drm: Generalized NV Block Linear DRM format mod

Builds upon the existing NVIDIA 16Bx2 block linear
format modifiers by adding more "fields" to the
existing parameterized
DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK format modifier
macro that allow fully defining a unique-across-
all-NVIDIA-hardware bit layout using a minimal
set of fields and values.  The new modifier macro
DRM_FORMAT_MOD_NVIDIA_BLOCK_LINEAR_2D is
effectively backwards compatible with the existing
macro, introducing a superset of the previously
definable format modifiers.

Backwards compatibility has two quirks.  First,
the zero value for the "kind" field, which is
implied by the DRM_FORMAT_MOD_NVIDIA_16BX2_BLOCK
macro, must be special cased in drivers and
assumed to map to the pre-Turing generic kind of
0xfe, since a kind of "zero" is reserved for
linear buffer layouts on all GPUs.

Second, it is assumed backwards compatibility
is only needed when running on Tegra GPUs, and
specifically Tegra GPUs prior to Xavier.  This
is based on two assertions:

-Tegra GPUs prior to Xavier used a slightly
 different raw bit layout than desktop GPUs,
 making it impossible to directly share block
 linear buffers between the two.

-Support for the existing block linear modifiers
 was incomplete, making them useful only for
 exporting buffers created by nouveau and
 importing them to Tegra DRM as framebuffers for
 scan out.  There was no support for adding
 framebuffers using format modifiers in nouveau,
 nor importing dma-buf/PRIME GEM objects into
 nouveau userspace drivers with modifiers in Mesa.

Hence it is assumed the prior modifiers were not
intended for use on desktop GPUs, and as a
corollary, were not intended to support sharing
block linear buffers across two different NVIDIA
GPUs.

v2:
  - Added canonicalize helper function

v3:
  - Added additional bit to compression field to
    support Tesla (NV5x,G8x,G9x,GT1xx,GT2xx) class
    chips.

Signed-off-by: James Jones <jajones@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
4 years agoMerge tag 'drm-intel-next-fixes-2020-05-20' of git://anongit.freedesktop.org/drm...
Dave Airlie [Thu, 21 May 2020 00:44:32 +0000 (10:44 +1000)]
Merge tag 'drm-intel-next-fixes-2020-05-20' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Fix for TypeC power domain toggling on resets (Cc: stable).
Two compile time warning fixes.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200520123227.GA21104@jlahtine-desk.ger.corp.intel.com
4 years agoMerge tag 'exynos-drm-next-for-v5.8' of git://git.kernel.org/pub/scm/linux/kernel...
Dave Airlie [Thu, 21 May 2020 00:24:37 +0000 (10:24 +1000)]
Merge tag 'exynos-drm-next-for-v5.8' of git://git./linux/kernel/git/daeinki/drm-exynos into drm-next

Check imported buffer mapping in generic way
- This patch reworks exynos_drm_gem_prime_import_sg_table function,
  which checks if the imported buffer has been mapped as contiguous
  or not in generic way, and flag a exynos gem buffer type properly
  according to the mapped way.

Fixups
- Drop a reference count to in_bridge_node correctly.
- Enable the runtime power management correctly.
  . The runtime pm should be enabled before calling compont_add().

Cleanups
- Do not register "by hand" a sysfs file, and use dev_groups instead.
- Drop internal 'pages' array which aren't needed.
- Remove dead-code.
- Correct type casting.
- Drop unnecessary error messages.

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Inki Dae <inki.dae@samsung.com>
Link: https://patchwork.freedesktop.org/patch/msgid/1589952785-24210-1-git-send-email-inki.dae@samsung.com
4 years agoMerge tag 'drm-intel-next-2020-05-15' of git://anongit.freedesktop.org/drm/drm-intel...
Dave Airlie [Wed, 20 May 2020 03:36:44 +0000 (13:36 +1000)]
Merge tag 'drm-intel-next-2020-05-15' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

UAPI Changes:

- drm/i915: Show per-engine default property values in sysfs

    By providing the default values configured into the kernel via sysfs, it
    is much more convenient for userspace to restore those sane defaults, or
    at least know what are considered good baseline. This is useful, for
    example, to cleanup after any failed userspace prior to commencing new
    jobs.

Cross-subsystem Changes:

- video/hdmi: Add Unpack only function for DRM infoframe
- Includes pull request gvt-next-2020-05-12

Driver Changes:

- Restore Cherryview back to full-ppgtt (Chris, Mika)
- Document locking guidelines for i915 (Chris, Daniel, Joonas)
- Fix GitLab #1746: Handle idling during i915_gem_evict_something busy loops (Chris)
- Display WA #1105: Require linear fb stride to be multiple of 512 bytes on
  gen9/glk (Ville)
- Add Wa_14010685332 for ICP/ICL (Matt R)
- Restrict w/a 1607087056 for EHL/JSL (Swathi)
- Fix interrupt handling for DP AUX transactions on Tigerlake (Imre)
- Revert "drm/i915/tgl: Include ro parts of l3 to invalidate" (Mika)
- Fix HDC pipeline flush hardware bit on Gen12 (Mika)
- Flush L3 when flushing render on Gen12 (Mika)
- Invalidate aux table entries forcibly between BB on Gen12 (Mika)
- Add aux table invalidate for all engines on Gen12 (Mika)
- Force pte cacheline to main memory Gen8+ (Mika)
- Add and enable TGL+ SAGV support (Stanislav)
- Implement vm_ops->access on i915 mmaps for GDB (Chris, Kristian)
- Replace zero-length array with flexible-array (Gustavo)
- Improve batch buffer pool effectiveness to mitigate soft-rc6 hit (Chris)
- Remove wait priority boosting (Chris)
- Keep driver module referenced when PMU is active (Chris)
- Sanitize RPS interrupts upon resume (Chris)
- Extend pcode read timeout to 20 ms (Chris)
- Wait for ACT sent before enabling MST pipe (Ville)
- Extend support to async relocations to SNB (Chris)
- Remove CNL pre-prod workarounds (Ville)
- Don't enable WaIncreaseLatencyIPCEnabled when IPC is disabled (Sultan)
- Record the active CCID from before reset (Chris)
- Mark concurrent submissions with a weak-dependency (Chris)
- Peel dma-fence-chains for await to allow engine-to-engine sync (Lionel)
- Prevent using semaphores to chain up to external fences (Chris)
- Fix GLK watermark calculations (Ville)
- Emit await(batch) before MI_BB_START (Chris)
- Reset execlists registers before HWSP (Chris)
- Drop no-semaphore boosting in favor of fast timeslicing (Chris)
- Fix enabled infoframe states of lspcon (Gwan-gyeong)
- Program DP SDPs on pipe updates (Gwan-gyeong)
- Stop sending DP SDPs on ddi disable (Gwan-gyeong)
- Store CS timestamp frequency in Hz (Ville)

- Remove unused HAS_FWTABLE macro (Pascal)
- Use batchbuffer chaining for relocations to save ring space (Chris)
- Try different engines for relocs if MI ops not supported (Chris, Tvrtko)
- Lazily acquire the device wakeref for freeing objects (Chris)
- Streamline display code arithmetics around rounding etc. (Ville)
- Use bw state for per crtc SAGV evaluation (Stanislav)
- Track active_pipes in bw_state (Stanislav)
- Nuke mode.vrefresh usage (Ville)
- Warn if the FBC is still writing to stolen on removal (Chris)
- Added new PCode commands prepping for QGV rescricting (Stansilav)
- Stop holding onto the pinned_default_state (Chris)
- Propagate error from completed fences (Chris)
- Ignore submit-fences on the same timeline (Chris)
- Pull waiting on an external dma-fence into its routine (Chris)
- Replace the hardcoded I915_FENCE_TIMEOUT with Kconfig (Chris)
- Mark up the racy read of execlists->context_tag (Chris)
- Tidy up the return handling for completed dma-fences (Chris)
- Introduce skl_plane_wm_level accessor (Stanislav)
- Extract SKL SAGV checking (Stanislav)
- Make active_pipes check skl specific (Stanislav)
- Suspend tasklets before resume sanitization (Chris)
- Remove redundant exec_fence (Chris)
- Mark the addition of the initial-breadcrumb in the request (Chris)
- Transfer old virtual breadcrumbs to irq_worker (Chris)
- Read the DP SDPs from the video DIP (Gwan-gyeong)
- Program DP SDPs with computed configs (Gwan-gyeong)
- Add state readout for DP VSC and DP HDR Metadata Infoframe SDP
  (Gwan-gyeong)
- Add compute routine for DP PSR VSC SDP (Gwan-gyeong)
- Use new DP VSC SDP compute routine on PSR (Gwan-gyeong)
- Restrict qgv points which don't have enough bandwidth. (Stanislav)
- Nuke pointless div by 64bit (Ville)

- Static checker code fixes (Nathan, Mika, Chris)
- Add logging function for DP VSC SDP (Gwan-gyeong)
- Include HDMI DRM infoframe, DP HDR metadata and DP VSC SDP in the
  crtc state dump (Gwan-gyeong)
- Make timeslicing explicit engine property (Chris, Tvrtko)
- Selftest and debugging improvements (Chris)
- Align variable names with BSpec (Ville)
- Tidy up gen8+ breadcrumb emission code (Chris)
- Turn intel_digital_port_connected() in a vfunc (Ville)
- Use stashed away hpd isr bits in intel_digital_port_connected() (Ville)
- Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}() (Ville)

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200515160703.GA19043@jlahtine-desk.ger.corp.intel.com
4 years agoMerge tag 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux...
Dave Airlie [Wed, 20 May 2020 03:28:04 +0000 (13:28 +1000)]
Merge tag 'amd-drm-next-5.8-2020-05-19' of git://people.freedesktop.org/~agd5f/linux into drm-next

amd-drm-next-5.8-2020-05-19:

amdgpu:
- Improved handling for CTF (Critical Thermal Fault) situations
- Clarify AC/DC mode switches
- SR-IOV fixes
- XGMI fixes for RAS
- Misc cleanups
- Add autodump debugfs node to aid in GPU hang debugging

UAPI:
- Add a MEM_SYNC IB flag for handling proper acquire memory semantics if UMDs expect the kernel to handle this
  Used by AMDVLK: https://github.com/GPUOpen-Drivers/pal/blob/dev/src/core/os/amdgpu/amdgpuQueue.cpp#L1262

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Alex Deucher <alexdeucher@gmail.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200519202505.4126-1-alexander.deucher@amd.com
4 years agodrm/i915: Fix AUX power domain toggling across TypeC mode resets
Imre Deak [Thu, 14 May 2020 20:45:53 +0000 (23:45 +0300)]
drm/i915: Fix AUX power domain toggling across TypeC mode resets

Make sure to select the port's AUX power domain while holding the TC
port lock. The domain depends on the port's current TC mode, which may
get changed under us if we're not holding the lock.

This was left out from
commit 8c10e2262663 ("drm/i915: Keep the TypeC port mode fixed for detect/AUX transfers")

Cc: <stable@vger.kernel.org> # v5.4+
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: José Roberto de Souza <jose.souza@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514204553.27193-1-imre.deak@intel.com
(cherry picked from commit ae9b6cfe1352da25931bce3ea4acfd4dc1ac8a85)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
4 years agodrm/i915: Mark check_shadow_context_ppgtt as maybe unused
Nathan Chancellor [Sat, 16 May 2020 02:35:45 +0000 (19:35 -0700)]
drm/i915: Mark check_shadow_context_ppgtt as maybe unused

When CONFIG_DRM_I915_DEBUG_GEM is not set, clang warns:

drivers/gpu/drm/i915/gvt/scheduler.c:884:1: warning: function
'check_shadow_context_ppgtt' is not needed and will not be emitted
[-Wunneeded-internal-declaration]
check_shadow_context_ppgtt(struct execlist_ring_context *c, struct
intel_vgpu_mm *m)
^
1 warning generated.

This warning is similar to -Wunused-function but rather than warning
that the function is completely unused, it warns that it is used in some
expression within the file but that expression will be evaluated to a
constant or be optimized away in the final assembly, essentially making
it appeared used but really isn't. Usually, this happens when a function
or variable is only used in sizeof, where it will appear to be used but
will be evaluated at compile time and not be required to be emitted.

In this case, the function is only used in GEM_BUG_ON, which is defined
as BUILD_BUG_ON_INVALID, which intentionally follows this pattern. To
fix this warning, add __maybe_unused to make it clear that this is
intentional depending on the configuration.

Fixes: bec3df930fbd ("drm/i915/gvt: Support PPGTT table load command")
Link: https://github.com/ClangBuiltLinux/linux/issues/1027
Signed-off-by: Nathan Chancellor <natechancellor@gmail.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200516023545.3332334-1-natechancellor@gmail.com
(cherry picked from commit 993fa32eb3d5ffb79e86a770ca982eb9c9f54011)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
4 years agodrm/i915: avoid unused scale_user_to_hw() warning
Arnd Bergmann [Tue, 28 Apr 2020 21:30:50 +0000 (23:30 +0200)]
drm/i915: avoid unused scale_user_to_hw() warning

After the function is no longer marked 'inline', there
is now a new warning pointing out that the only caller
is inside of an #ifdef:

drivers/gpu/drm/i915/display/intel_panel.c:493:12: warning: 'scale_user_to_hw' defined but not used [-Wunused-function]
  493 | static u32 scale_user_to_hw(struct intel_connector *connector,
      |            ^~~~~~~~~~~~~~~~

Move the function itself into that #ifdef as well.

Fixes: 81b55ef1f47b ("drm/i915: drop a bunch of superfluous inlines")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20200428213106.3139170-1-arnd@arndb.de
(cherry picked from commit 794bdcf71f47b98f6e003190069d5064123067ed)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
4 years agodrm/amdgpu: Add a UAPI flag for user to call mem_sync
Andrey Grodzovsky [Tue, 28 Apr 2020 05:28:43 +0000 (01:28 -0400)]
drm/amdgpu: Add a UAPI flag for user to call mem_sync

When this flag is set in the CS IB flags, it causes
a memory cache flush of the GFX.

v2:
Move new flag to drm_amdgpu_cs_chunk_ib.flags
Bump up UAPI version
Remove condition on job != null to emit mem_sync

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: apply AMDGPU_IB_FLAG_EMIT_MEM_SYNC to compute IBs too (v3)
Marek Olšák [Mon, 27 Apr 2020 20:04:47 +0000 (16:04 -0400)]
drm/amdgpu: apply AMDGPU_IB_FLAG_EMIT_MEM_SYNC to compute IBs too (v3)

Compute IBs need this too.

v2: split out version bump
v3: squash in emit frame count fixes

Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Add mem_sync implementation for all the ASICs.
Andrey Grodzovsky [Fri, 8 May 2020 18:34:26 +0000 (14:34 -0400)]
drm/amdgpu: Add mem_sync implementation for all the ASICs.

Implement the .mem_sync hook defined earlier.

v2: Rename functions

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Add new ring callback to insert memory sync
Andrey Grodzovsky [Tue, 24 Mar 2020 20:37:01 +0000 (16:37 -0400)]
drm/amdgpu: Add new ring callback to insert memory sync

Used to flush and invalidate various caches.

v2: Rename function hook

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: optimize amdgpu device attribute code
Kevin Wang [Mon, 27 Apr 2020 15:45:49 +0000 (23:45 +0800)]
drm/amdgpu: optimize amdgpu device attribute code

unified amdgpu device attribute node functions:
1. add some helper functions to create amdgpu device attribute node.
2. create device node according to device attr flags on different VF mode.
3. rename some functions name to adapt a new interface.

v2:
1. remove ATTR_STATE_DEAD, ATTR_STATE_ALIVE enum.
2. rename callback function perform to attr_update.
3. modify some variable names

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: add amdgpu_virt_get_vf_mode helper function
Kevin Wang [Wed, 29 Apr 2020 10:49:23 +0000 (18:49 +0800)]
drm/amdgpu: add amdgpu_virt_get_vf_mode helper function

the swsmu or powerplay(hwmgr) need to handle task according to different VF mode,
this function to help query vf mode.

vf mode:
1. SRIOV_VF_MODE_BARE_METAL: the driver work on host  OS (PF)
2. SRIOV_VF_MODE_ONE_VF    : the driver work on guest OS with one VF
3. SRIOV_VF_MODE_MULTI_VF  : the driver work on guest OS with multi VF

Signed-off-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Add autodump debugfs node for gpu reset v8
Jiange Zhao [Sun, 26 Apr 2020 09:57:00 +0000 (17:57 +0800)]
drm/amdgpu: Add autodump debugfs node for gpu reset v8

When GPU got timeout, it would notify an interested part
of an opportunity to dump info before actual GPU reset.

A usermode app would open 'autodump' node under debugfs system
and poll() for readable/writable. When a GPU reset is due,
amdgpu would notify usermode app through wait_queue_head and give
it 10 minutes to dump info.

After usermode app has done its work, this 'autodump' node is closed.
On node closure, amdgpu gets to know the dump is done through
the completion that is triggered in release().

There is no write or read callback because necessary info can be
obtained through dmesg and umr. Messages back and forth between
usermode app and amdgpu are unnecessary.

v2: (1) changed 'registered' to 'app_listening'
    (2) add a mutex in open() to prevent race condition

v3 (chk): grab the reset lock to avoid race in autodump_open,
          rename debugfs file to amdgpu_autodump,
          provide autodump_read as well,
          style and code cleanups

v4: add 'bool app_listening' to differentiate situations, so that
    the node can be reopened; also, there is no need to wait for
    completion when no app is waiting for a dump.

v5: change 'bool app_listening' to 'enum amdgpu_autodump_state'
    add 'app_state_mutex' for race conditions:
(1)Only 1 user can open this file node
(2)wait_dump() can only take effect after poll() executed.
(3)eliminated the race condition between release() and
   wait_dump()

v6: removed 'enum amdgpu_autodump_state' and 'app_state_mutex'
    removed state checking in amdgpu_debugfs_wait_dump
    Improve on top of version 3 so that the node can be reopened.

v7: move reinit_completion into open() so that only one user
    can open it.

v8: remove complete_all() from amdgpu_debugfs_wait_dump().

Signed-off-by: Jiange Zhao <Jiange.Zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/exynos-vidi: convert platform driver to use dev_groups
Emil Velikov [Sun, 17 May 2020 19:36:55 +0000 (20:36 +0100)]
drm/exynos-vidi: convert platform driver to use dev_groups

Platform drivers now have the option to have the platform core create
and remove any needed sysfs attribute files.  So take advantage of that
and do not register "by hand" a sysfs file.

Cc: Inki Dae <inki.dae@samsung.com>
Cc: Joonyoung Shim <jy0922.shim@samsung.com>
Cc: Seung-Woo Kim <sw0312.kim@samsung.com>
Cc: Kyungmin Park <kyungmin.park@samsung.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/exynos: dsi: Remove bridge node reference in error handling path in probe function
Christophe JAILLET [Sat, 16 May 2020 10:57:36 +0000 (12:57 +0200)]
drm/exynos: dsi: Remove bridge node reference in error handling path in probe function

'exynos_dsi_parse_dt()' takes a reference to 'dsi->in_bridge_node'.
This must be released in the error handling path.

In order to do that, add an error handling path and move the
'exynos_dsi_parse_dt()' call from the beginning to the end of the probe
function to ease the error handling path.
This function only sets some variables which are used only in the
'transfer' function.

The call chain is:
   .transfer
    --> exynos_dsi_host_transfer
      --> exynos_dsi_init
        --> exynos_dsi_enable_clock  (use burst_clk_rate and esc_clk_rate)
          --> exynos_dsi_set_pll     (use pll_clk_rate)

While at it, also handle cases where 'component_add()' fails.

This patch is similar to commit 70505c2ef94b ("drm/exynos: dsi: Remove bridge node reference in removal")
which fixed the issue in the remove function.

Signed-off-by: Christophe JAILLET <christophe.jaillet@wanadoo.fr>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/exynos: mixer: Fix enabling of the runtime power management
Marek Szyprowski [Thu, 14 May 2020 10:08:12 +0000 (12:08 +0200)]
drm/exynos: mixer: Fix enabling of the runtime power management

Runtime power management is essential for the Exynos Mixer driver
operation. It should be enabled before adding its DRM component, because
in some cases (when deferred probe takes place due to the IOMMU
availability) the DRM driver might be initialized directly from the
Mixer's component_add() call, what results in starting the driver
operation without enabling the runtime power management.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/exynos: make pointer to const data const type
Bernard Zhao [Sun, 26 Apr 2020 09:01:42 +0000 (02:01 -0700)]
drm/exynos: make pointer to const data const type

Maybe keep pointer which points to global const string data
in const type is better, make sure not change const data.

Signed-off-by: Bernard Zhao <bernard@vivo.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/exynos: gem: Get rid of the internal 'pages' array
Marek Szyprowski [Thu, 23 Apr 2020 05:43:49 +0000 (14:43 +0900)]
drm/exynos: gem: Get rid of the internal 'pages' array

Internal pages array and scatter-list for them is not really needed for
anything. FBDev emulation can simply rely on the DMA-mapping framework
to create a proper kernel mapping for the buffer, while all other buffer
use cases don't really need that array at all.

Suggested-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/exynos: gem: rework scatter-list contiguity check on prime import
Marek Szyprowski [Wed, 22 Apr 2020 11:40:59 +0000 (13:40 +0200)]
drm/exynos: gem: rework scatter-list contiguity check on prime import

Explicitly check if the imported buffer has been mapped as contiguous in
the DMA address space, what is required by all Exynos DRM CRTC drivers.
While touching this, set buffer flags depending on the availability of
the IOMMU.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/exynos: gem: Remove dead-code
Marek Szyprowski [Tue, 7 Apr 2020 13:42:54 +0000 (15:42 +0200)]
drm/exynos: gem: Remove dead-code

The ExynosDRM page fault handler is never used, drm_gem_mmap()
always calls exynos_drm_gem_mmap() function, which perform
complete mapping for the given virtual address-space area.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/exynos: Delete an error message in three functions
Markus Elfring [Sun, 5 Apr 2020 12:10:09 +0000 (14:10 +0200)]
drm/exynos: Delete an error message in three functions

The function “platform_get_irq” can log an error already.
Thus omit redundant messages for the exception handling in the
calling functions.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Inki Dae <inki.dae@samsung.com>
4 years agodrm/i915: Update DRIVER_DATE to 20200515
Joonas Lahtinen [Fri, 15 May 2020 11:49:24 +0000 (14:49 +0300)]
drm/i915: Update DRIVER_DATE to 20200515

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
4 years agoMerge tag 'drm-misc-next-2020-05-14' of git://anongit.freedesktop.org/drm/drm-misc...
Dave Airlie [Fri, 15 May 2020 01:58:55 +0000 (11:58 +1000)]
Merge tag 'drm-misc-next-2020-05-14' of git://anongit.freedesktop.org/drm/drm-misc into drm-next

drm-misc-next for 5.8:

UAPI Changes:

Cross-subsystem Changes:

 * dma-buf: use atomic64_fetch_add() for context id
 * Documentation: document bindings for ASUS ZOOT TM5P5, BOE NV133FHM-N62,
                  hpd-gpios

Core Changes:

Driver Changes:

 * drm/ast: fix supend; cleanups
 * drm/i2c: cleanups
 * drm/panel: add MODULE_LICENSE to panel-visinox-rm69299; add support for
              ASUS TM5P5i, BOE NV133FHM-N62i; fix size and bpp of BOE NV133FHM-N61
      add hpd-gpio to panel-simple
 * drm/mcde: fix return value check in mcde_dsi_bind()
 * drm/mgag200: use managed drmm_mode_config_init(); cleanups
 * fbdev/pxa168fb: cleanups

Signed-off-by: Dave Airlie <airlied@redhat.com>
From: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514070819.GA6930@linux-uq9g
4 years agodrm/amdgpu: Updated XGMI power down control support check
John Clements [Thu, 14 May 2020 03:21:01 +0000 (11:21 +0800)]
drm/amdgpu: Updated XGMI power down control support check

Updated SMC FW version check to determine if XGMI power down control is supported

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Update RAS XGMI error inject sequence
John Clements [Wed, 13 May 2020 12:23:51 +0000 (20:23 +0800)]
drm/amdgpu: Update RAS XGMI error inject sequence

Disable XGMI link power down prior to issuing a XGMI RAS error

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Add DPM function for XGMI link power down control
John Clements [Wed, 13 May 2020 09:45:57 +0000 (17:45 +0800)]
drm/amdgpu: Add DPM function for XGMI link power down control

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Add cmd to control XGMI link sleep
John Clements [Wed, 13 May 2020 09:45:06 +0000 (17:45 +0800)]
drm/amdgpu: Add cmd to control XGMI link sleep

Added host to SMU FW cmd to enable/disable XGMI link power down

Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: John Clements <john.clements@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: remove redundant assignment to variable ret
Colin Ian King [Tue, 12 May 2020 12:48:06 +0000 (13:48 +0100)]
drm/amdgpu: remove redundant assignment to variable ret

The variable ret is being initializeed with a value that is never read
and it is being updated later with a new value. The initialization
is redundant and can be removed.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: turn back rlcg write for gfx_v10
Yintian Tao [Tue, 12 May 2020 10:10:42 +0000 (18:10 +0800)]
drm/amdgpu: turn back rlcg write for gfx_v10

There is no need to use amdgpu_mm_wreg_mmio_rlc()
during initialization time because this interface
is only designed for debugfs case to access the
registers which are only permitted by RLCG during
run-time. Therefore, turn back rlcg write for gfx_v10.
If we not turn back it, it will raise amdgpu load failure.
[   54.904333] amdgpu: SMU driver if version not matched
[   54.904393] amdgpu: SMU is initialized successfully!
[   54.905971] [drm] kiq ring mec 2 pipe 1 q 0
[   55.115416] amdgpu 0000:00:06.0: [drm:amdgpu_ring_test_helper [amdgpu]] *ERROR* ring gfx_0.0.0 test failed (-110)
[   55.118877] [drm:amdgpu_device_init [amdgpu]] *ERROR* hw_init of IP block <gfx_v10_0> failed -110
[   55.126587] amdgpu 0000:00:06.0: amdgpu_device_ip_init failed
[   55.133466] amdgpu 0000:00:06.0: Fatal error during GPU init

Signed-off-by: Yintian Tao <yttao@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: report correct AC/DC event based on ctxid V2
Evan Quan [Fri, 8 May 2020 09:55:42 +0000 (17:55 +0800)]
drm/amd/powerplay: report correct AC/DC event based on ctxid V2

'ctxid' is used to distinguish different events raised from SMC.
0x3 and 0x4 are for AC and DC power mode.

V2: update the way to retrieve the ctxid and change the log level
    to debug

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: shutdown on HW CTF
Evan Quan [Sat, 9 May 2020 05:49:26 +0000 (13:49 +0800)]
drm/amd/powerplay: shutdown on HW CTF

To prevent further damage.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amd/powerplay: try to do a graceful shutdown on SW CTF
Evan Quan [Sat, 9 May 2020 05:26:00 +0000 (13:26 +0800)]
drm/amd/powerplay: try to do a graceful shutdown on SW CTF

Normally this(SW CTF) should not happen. And by doing graceful
shutdown we can prevent further damage.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion
Andrey Grodzovsky [Tue, 24 Mar 2020 20:39:37 +0000 (16:39 -0400)]
drm/amdgpu: Add AQUIRE_MEM PACKET3 fields defintion

Add this for gfx10 and gfx9.

v2: Fix identation

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Luben Tuikov <luben.tuikov@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
4 years agodrm/i915: Document locking guidelines
Joonas Lahtinen [Fri, 30 Aug 2019 10:50:53 +0000 (13:50 +0300)]
drm/i915: Document locking guidelines

To ensure cross-driver locking compatibility, document the expected
guidelines for implementing the GEM locking in i915. Note that this
is a description of how things should end up after being reworked,
and does not reflect the current state of things.

v2: Use rst note:: tag (Rodrigo)

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Matthew Auld <matthew.auld@intel.com>
Cc: Abdiel Janulgue <abdiel.janulgue@linux.intel.com>
Cc: CQ Tang <cq.tang@intel.com>
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Acked-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20190830105053.17491-1-joonas.lahtinen@linux.intel.com
4 years agodrm/i915: Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}()
Ville Syrjälä [Mon, 2 Mar 2020 14:39:42 +0000 (16:39 +0200)]
drm/i915: Extract i915_cs_timestamp_{ns_to_ticks,tick_to_ns}()

Pull the code to do the CS timestamp ns<->ticks conversion into
helpers and use them all over.

The check in i915_perf_noa_delay_set() seems a bit dubious,
so we switch it to do what I assume it wanted to do all along
(ie. make sure the resulting delay in CS timestamp ticks
doesn't exceed 32bits)?

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302143943.32676-5-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
4 years agodrm/i915: Store CS timestamp frequency in Hz
Ville Syrjälä [Mon, 2 Mar 2020 14:39:39 +0000 (16:39 +0200)]
drm/i915: Store CS timestamp frequency in Hz

kHz isn't accurate enough for storing the CS timestamp
frequency on some of the platforms. Store the value
in Hz instead.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302143943.32676-2-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agodrm/i915: Nuke pointless div by 64bit
Ville Syrjälä [Mon, 2 Mar 2020 14:39:38 +0000 (16:39 +0200)]
drm/i915: Nuke pointless div by 64bit

Bunch of places use a 64bit divisor needlessly. Switch
to 32bit divisor.

Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200302143943.32676-1-ville.syrjala@linux.intel.com
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
4 years agodrm/i915: Enable SAGV support for Gen12
Stanislav Lisovskiy [Thu, 14 May 2020 07:48:53 +0000 (10:48 +0300)]
drm/i915: Enable SAGV support for Gen12

Flip the switch and enable SAGV support
for Gen12 also.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-4-stanislav.lisovskiy@intel.com
4 years agodrm/i915: Restrict qgv points which don't have enough bandwidth.
Stanislav Lisovskiy [Thu, 14 May 2020 07:48:52 +0000 (10:48 +0300)]
drm/i915: Restrict qgv points which don't have enough bandwidth.

According to BSpec 53998, we should try to
restrict qgv points, which can't provide
enough bandwidth for desired display configuration.

Currently we are just comparing against all of
those and take minimum(worst case).

v2: Fixed wrong PCode reply mask, removed hardcoded
    values.

v3: Forbid simultaneous legacy SAGV PCode requests and
    restricting qgv points. Put the actual restriction
    to commit function, added serialization(thanks to Ville)
    to prevent commit being applied out of order in case of
    nonblocking and/or nomodeset commits.

v4:
    - Minor code refactoring, fixed few typos(thanks to James Ausmus)
    - Change the naming of qgv point
      masking/unmasking functions(James Ausmus).
    - Simplify the masking/unmasking operation itself,
      as we don't need to mask only single point per request(James Ausmus)
    - Reject and stick to highest bandwidth point if SAGV
      can't be enabled(BSpec)

v5:
    - Add new mailbox reply codes, which seems to happen during boot
      time for TGL and indicate that QGV setting is not yet available.

v6:
    - Increase number of supported QGV points to be in sync with BSpec.

v7: - Rebased and resolved conflict to fix build failure.
    - Fix NUM_QGV_POINTS to 8 and moved that to header file(James Ausmus)

v8: - Don't report an error if we can't restrict qgv points, as SAGV
      can be disabled by BIOS, which is completely legal. So don't
      make CI panic. Instead if we detect that there is only 1 QGV
      point accessible just analyze if we can fit the required bandwidth
      requirements, but no need in restricting.

v9: - Fix wrong QGV transition if we have 0 planes and no SAGV
      simultaneously.

v10: - Fix CDCLK corruption, because of global state getting serialized
       without modeset, which caused copying of non-calculated cdclk
       to be copied to dev_priv(thanks to Ville for the hint).

v11: - Remove unneeded headers and spaces(Matthew Roper)
     - Remove unneeded intel_qgv_info qi struct from bw check and zero
       out the needed one(Matthew Roper)
     - Changed QGV error message to have more clear meaning(Matthew Roper)
     - Use state->modeset_set instead of any_ms(Matthew Roper)
     - Moved NUM_SAGV_POINTS from i915_reg.h to i915_drv.h where it's used
     - Keep using crtc_state->hw.active instead of .enable(Matthew Roper)
     - Moved unrelated changes to other patch(using latency as parameter
       for plane wm calculation, moved to SAGV refactoring patch)

v12: - Fix rebase conflict with own temporary SAGV/QGV fix.
     - Remove unnecessary mask being zero check when unmasking
       qgv points as this is completely legal(Matt Roper)
     - Check if we are setting the same mask as already being set
       in hardware to prevent error from PCode.
     - Fix error message when restricting/unrestricting qgv points
       to "mask/unmask" which sounds more accurate(Matt Roper)
     - Move sagv status setting to icl_get_bw_info from atomic check
       as this should be calculated only once.(Matt Roper)
     - Edited comments for the case when we can't enable SAGV and
       use only 1 QGV point with highest bandwidth to be more
       understandable.(Matt Roper)

v13: - Moved max_data_rate in bw check to closer scope(Ville Syrjälä)
     - Changed comment for zero new_mask in qgv points masking function
       to better reflect reality(Ville Syrjälä)
     - Simplified bit mask operation in qgv points masking function
       (Ville Syrjälä)
     - Moved intel_qgv_points_mask closer to gen11 SAGV disabling,
       however this still can't be under modeset condition(Ville Syrjälä)
     - Packed qgv_points_mask as u8 and moved closer to pipe_sagv_mask
       (Ville Syrjälä)
     - Extracted PCode changes to separate patch.(Ville Syrjälä)
     - Now treat num_planes 0 same as 1 to avoid confusion and
       returning max_bw as 0, which would prevent choosing QGV
       point having max bandwidth in case if SAGV is not allowed,
       as per BSpec(Ville Syrjälä)
     - Do the actual qgv_points_mask swap in the same place as
       all other global state parts like cdclk are swapped.
       In the next patch, this all will be moved to bw state as
       global state, once new global state patch series from Ville
       lands

v14: - Now using global state to serialize access to qgv points
     - Added global state locking back, otherwise we seem to read
       bw state in a wrong way.

v15: - Added TODO comment for near atomic global state locking in
       bw code.

v16: - Fixed intel_atomic_bw_* functions to be intel_bw_* as discussed
       with Jani Nikula.
     - Take bw_state_changed flag into use.

v17: - Moved qgv point related manipulations next to SAGV code, as
       those are semantically related(Ville Syrjälä)
     - Renamed those into intel_sagv_(pre)|(post)_plane_update
       (Ville Syrjälä)

v18: - Move sagv related calls from commit tail into
       intel_sagv_(pre)|(post)_plane_update(Ville Syrjälä)

v19: - Use intel_atomic_get_bw_(old)|(new)_state which is intended
       for commit tail stage.

v20: - Return max bandwidth for 0 planes(Ville)
     - Constify old_bw_state in bw_atomic_check(Ville)
     - Removed some debugs(Ville)
     - Added data rate to debug print when no QGV points(Ville)
     - Removed some comments(Ville)

v21, v22, v23: - Fixed rebase conflict

v24: - Changed PCode mask to use ICL_ prefix
v25: - Resolved rebase conflict

v26: - Removed redundant NULL checks(Ville)
     - Removed redundant error prints(Ville)

v27: - Use device specific drm_err(Ville)
     - Fixed parenthesis ident reported by checkpatch
       Line over 100 warns to be fixed together with
       existing code style.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
Cc: Ville Syrjälä <ville.syrjala@intel.com>
Cc: James Ausmus <james.ausmus@intel.com>
[vsyrjala: Drop duplicate intel_sagv_{pre,post}_plane_update() prototypes
           and drop unused NUM_SAGV_POINTS define]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-3-stanislav.lisovskiy@intel.com
4 years agodrm/i915: Add TGL+ SAGV support
Stanislav Lisovskiy [Thu, 14 May 2020 07:48:51 +0000 (10:48 +0300)]
drm/i915: Add TGL+ SAGV support

Starting from TGL we need to have a separate wm0
values for SAGV and non-SAGV which affects
how calculations are done.

v2: Remove long lines
v3: Removed COLOR_PLANE enum references
v4, v5, v6: Fixed rebase conflict
v7: - Removed skl_plane_wm_level accessor from skl_allocate_pipe_ddb(Ville)
    - Removed sagv_uv_wm0(Ville)
    - can_sagv->use_sagv_wm(Ville)

v8: - Moved tgl_crtc_can_enable_sagv function up(Ville)
    - Changed comment regarding pipe_wm usage(Ville)
    - Call intel_can_enable_sagv and tgl_compute_sagv_wm only
      for Gen12(Ville)
    - Some sagv debugs removed(Ville)
    - skl_print_wm_changes improvements(Ville)
    - Do assignment instead of memcpy in
      skl_pipe_wm_get_hw_state(Ville)

v9: - Removed can_sagv variable(Ville)
    - Removed spurious line(Ville)
    - Changed u32 to unsigned int as agreed(Ville)
    - Assign sagv only for gen12 in
      skl_pipe_wm_get_hw_state(Ville)

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
[vsyrjala: Remove the dead 'return false' from intel_crtc_can_enable_sagv()]
Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514074853.9508-2-stanislav.lisovskiy@intel.com
4 years agoMerge tag 'gvt-next-2020-05-12' of https://github.com/intel/gvt-linux into drm-intel...
Joonas Lahtinen [Thu, 14 May 2020 15:02:22 +0000 (18:02 +0300)]
Merge tag 'gvt-next-2020-05-12' of https://github.com/intel/gvt-linux into drm-intel-next-queued

gvt-next-2020-05-12

- Support PPGTT update via LRI cmd (Zhenyu)
- Remove extra kmap for shadow ctx update (Zhenyu)
- Move workload cleanup out of execlist handling code (Zhenyu)

Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
From: Zhenyu Wang <zhenyuw@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200512094017.GX18545@zhen-hp.sh.intel.com
4 years agodrm/i915/psr: Use new DP VSC SDP compute routine on PSR
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:32 +0000 (09:07 +0300)]
drm/i915/psr: Use new DP VSC SDP compute routine on PSR

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it uses a new psr vsc sdp compute routine.
Because PSR routine has its own scenario and timings of writing a VSC SDP,
the current PSR routine needs to have its own drm_dp_vsc_sdp structure
member variable on struct i915_psr.

In order to calculate colorimetry information, intel_psr_update()
function and intel_psr_enable() function extend a drm_connector_state
argument.

There are no changes to PSR mechanism.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Rebased
v8: Rebased
v10: When a PSR is enabled, it needs to add DP_SDP_VSC to
     infoframes.enable.
     It is needed for comparing between HW and pipe_state of VSC_SDP.
v11: If PSR is disabled by flag, it don't enable psr on pipe compute.
v12: Fix an inconsistent indenting

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-15-gwan-gyeong.mun@intel.com
4 years agodrm/i915/dp: Add compute routine for DP PSR VSC SDP
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:31 +0000 (09:07 +0300)]
drm/i915/dp: Add compute routine for DP PSR VSC SDP

In order to use a common VSC SDP Colorimetry calculating code on PSR,
it adds a compute routine for PSR VSC SDP.
As PSR routine can not use infoframes.vsc of crtc state, it also adds new
writing of DP SDPs (Secondary Data Packet) for PSR.
PSR routine has its own scenario and timings of writing a VSC SDP.

v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: 1) Fix packing of VSC SDP where Pixel Encoding/Colorimetry Format is
        not supported.
     2) Change a checking of PSR state.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-14-gwan-gyeong.mun@intel.com
4 years agodrm/i915: Stop sending DP SDPs on ddi disable
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:30 +0000 (09:07 +0300)]
drm/i915: Stop sending DP SDPs on ddi disable

Call intel_dp_set_infoframes(false) function on intel_ddi_post_disable_dp()
to make sure not to send VSC SDP and HDR Metadata Infoframe SDP.

v5: Polish commit message [Uma]

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-13-gwan-gyeong.mun@intel.com
4 years agodrm/i915: Program DP SDPs on pipe updates
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:29 +0000 (09:07 +0300)]
drm/i915: Program DP SDPs on pipe updates

Call intel_dp_set_infoframes() function on pipe updates to make sure
that we send VSC SDP and HDR Metadata Infoframe SDP (when applicable)
on fastsets.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-12-gwan-gyeong.mun@intel.com
4 years agodrm/i915: Fix enabled infoframe states of lspcon
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:28 +0000 (09:07 +0300)]
drm/i915: Fix enabled infoframe states of lspcon

Compared to implementation of DP and HDMI's encoder->infoframes_enabled,
the lspcon's implementation returns its active state. (we expect enabled
infoframe states of HW.) It leads to pipe state mismatch error
when ddi_get_config is called.

Because the current implementation of lspcon is not ready to support
readout infoframes, we need to return 0 here.

In order to support readout to lspcon, we need to implement read_infoframe
and infoframes_enabled. And set_infoframes also have to set an appropriate
bit on crtc_state->infoframes.enable

Cc: Ville Syrjälä <ville.syrjala@linux.intel.com>
Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-11-gwan-gyeong.mun@intel.com
4 years agodrm/i915: Add state readout for DP VSC SDP
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:27 +0000 (09:07 +0300)]
drm/i915: Add state readout for DP VSC SDP

Added state readout for DP VSC SDP and enabled state validation
for DP VSC SDP.

v2: Minor style fix
v3: Replace a structure name to drm_dp_vsc_sdp from intel_dp_vsc_sdp
v4: Use struct drm_device logging macros
v10: Skip checking of VSC SDP when a crtc config has psr.

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-10-gwan-gyeong.mun@intel.com
4 years agodrm/i915: Add state readout for DP HDR Metadata Infoframe SDP
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:26 +0000 (09:07 +0300)]
drm/i915: Add state readout for DP HDR Metadata Infoframe SDP

Added state readout for DP HDR Metadata Infoframe SDP.

v9: Rebased
v10: Rebased

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-9-gwan-gyeong.mun@intel.com
4 years agodrm/i915: Program DP SDPs with computed configs
Gwan-gyeong Mun [Thu, 14 May 2020 06:07:25 +0000 (09:07 +0300)]
drm/i915: Program DP SDPs with computed configs

In order to use computed config for DP SDPs (DP VSC SDP and DP HDR Metadata
Infoframe SDP), it replaces intel_dp_vsc_enable() function and
intel_dp_hdr_metadata_enable() function to intel_dp_set_infoframes()
function.
And it removes unused functions.

Before:
 intel_dp_vsc_enable() and intel_dp_hdr_metadata_enable() compute sdp
 configs and program sdp registers on enable callback of encoder.

After:
 It separates computing of sdp configs and programming of sdp register.
 The compute config callback of encoder calls computing sdp configs.
 The enable callback of encoder calls programming sdp register.

v3: Rebased
v5: Polish commit message [Uma]
v10: Rebased

Signed-off-by: Gwan-gyeong Mun <gwan-gyeong.mun@intel.com>
Reviewed-by: Uma Shankar <uma.shankar@intel.com>
Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200514060732.3378396-8-gwan-gyeong.mun@intel.com