Martin Storsjö [Mon, 6 Jun 2022 20:56:31 +0000 (23:56 +0300)]
[doc] Add release notes about SEH unwind information on ARM
Differential Revision: https://reviews.llvm.org/D127150
Matthias Springer [Tue, 7 Jun 2022 22:04:54 +0000 (00:04 +0200)]
[mlir][bufferize] Improve buffer writability analysis
Find writability conflicts (writes to buffers that are not allowed to be written to) by checking SSA use-def chains. This is better than the current writability analysis, which is too conservative and finds false positives.
Differential Revision: https://reviews.llvm.org/D127256
Chuanqi Xu [Wed, 8 Jun 2022 07:45:21 +0000 (15:45 +0800)]
[NFC] Remove commented cerr debugging loggings
There are some unused cerr debugging loggings in the codes. It is weird
to remain such commented debug helpers in the product.
David CARLIER [Wed, 8 Jun 2022 07:55:10 +0000 (08:55 +0100)]
[Sanitizers] intercept FreeBSD procctl
Reviewers: vitalybuka, emaster
Reviewed-By: viatelybuka
Differential Revision: https://reviews.llvm.org/D127069
Benjamin Kramer [Tue, 7 Jun 2022 17:30:10 +0000 (19:30 +0200)]
[mlir][MemRef] Fix a crash when expanding a scalar shape
In this case the reassociation is empty, yielding no strides for the
result type.
Differential Revision: https://reviews.llvm.org/D127232
LLVM GN Syncbot [Wed, 8 Jun 2022 07:20:40 +0000 (07:20 +0000)]
[gn build] Port
638b0fb4d651
Nathan James [Wed, 8 Jun 2022 07:20:28 +0000 (08:20 +0100)]
[ADT][NFC] Early bail out for ComputeEditDistance
The minimun bound for number of edits is the size difference between the 2 arrays.
If MaxEditDistance is smaller than this, we can bail out early without needing to traverse any of the arrays.
Reviewed By: dblaikie
Differential Revision: https://reviews.llvm.org/D127070
lorenzo chelini [Wed, 8 Jun 2022 06:46:36 +0000 (08:46 +0200)]
[MLIR][SCF] Improve doc (NFC)
Kito Cheng [Wed, 8 Jun 2022 05:05:35 +0000 (13:05 +0800)]
Revert "[SplitKit] Handle early clobber + tied to def correctly"
Revert due to failed on LLVM_ENABLE_EXPENSIVE_CHECKS.
This reverts commit
e14d04909df4e52e531f6c2e045c3cf9638dd817.
Fangrui Song [Wed, 8 Jun 2022 04:22:38 +0000 (21:22 -0700)]
[CMake] Enable LLVM_ENABLE_PER_TARGET_RUNTIME_DIR by default on Linux
This makes the LLVM_ENABLE_PROJECTS mode (supported for compiler-rt, deprecated
(D112724) for libcxx/libcxxabi/libunwind) closer to
https://libcxx.llvm.org/BuildingLibcxx.html#bootstrapping-build .
The layout is arguably superior because different libraries of target triples
are in different directories, similar to GCC/Debian multiarch.
When LLVM_DEFAULT_TARGET_TRIPLE is x86_64-unknown-linux-gnu,
`lib/clang/15.0.0/lib/libclang_rt.asan-x86_64.a`
is moved to
`lib/clang/15.0.0/lib/x86_64-unknown-linux-gnu/libclang_rt.asan.a`.
In addition, if the host compiler supports -m32 (multilib),
`lib/clang/15.0.0/lib/libclang_rt.asan-i386.a`
is moved to
`lib/clang/15.0.0/lib/i386-unknown-linux-gnu/libclang_rt.asan.a`.
Reviewed By: mstorsjo, ldionne, #libc
Differential Revision: https://reviews.llvm.org/D107799
python3kgae [Wed, 8 Jun 2022 01:38:29 +0000 (18:38 -0700)]
[DirectX][Fail crash in DXILPrepareModule pass when input has typed ptr.
Check supportsTypedPointers instead of hasSetOpaquePointersValue when query if has typed ptr.
Reviewed By: beanz
Differential Revision: https://reviews.llvm.org/D127268
Kito Cheng [Thu, 26 May 2022 10:43:04 +0000 (18:43 +0800)]
[SplitKit] Handle early clobber + tied to def correctly
Spliter will try to extend a live range into `r` slot for a use operand,
that's works on most situaion, however that not work correctly when the operand
has tied to def, and the def operand is early clobber.
Give an example to demo what's wrong:
0 %0 = ...
16 early-clobber %0 = Op %0 (tied-def 0), ...
32 ... = Op %0
Before extend:
%0 = [0r, 0d) [16e, 32d)
The point we want to extend is 0d to 16e not 16r in this case, but if
we use 16r here we will extend nothing because that already contained
in [16e, 32d).
This patch add check for detect such case and adjust the extend point.
Detailed explanation for testcase: https://reviews.llvm.org/D126047
Reviewed By: MatzeB
Differential Revision: https://reviews.llvm.org/D126048
Kito Cheng [Wed, 8 Jun 2022 02:23:35 +0000 (10:23 +0800)]
[RISCV] Testcase to show wrong register allocation result of subreg liveness
This testcase show the live range isn't construct correctly when subreg
liveness is enabled.
In the testcase `early-clobber-tied-def-subreg-liveness.ll`, first operand of
`vsext.vf2 v8, v16, v0.t` is both def and use, and the use is come from
the memory location of `.L__const._Z3foov.var_49`, it's load and spilled
into stack, and then...v8 is overwrite by another instructions.
```
lui a0, %hi(.L__const._Z3foov.var_49)
addi a0, a0, %lo(.L__const._Z3foov.var_49)
...
vle16.v v8, (a0) # Load value from var_49
...
addi a0, sp, 16
...
vs2r.v v8, (a0) # Spill
...
vl2r.v v8, (a1) # Reload
...
lui a0, %hi(.L__const._Z3foov.var_40)
addi a0, a0, %lo(.L__const._Z3foov.var_40)
vle16.v v8, (a0) # Load value...into v8???
vmsbc.vx v0, v8, a0 # And use that.
...
vsext.vf2 v8, v16, v0.t # But v8 is here...which is expect value from the reload
```
The `early-clobber-tied-def-subreg-liveness.mir` has more detailed
infomation for that, `%25.sub_vrm2_0` is defined in 64, and used in 464,
and defined again in 464, and we has used an inline asm to clobber all
vector register for trigger spliter.
```
0B bb.0.entry:
16B %0:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_49
32B %1:gpr = ADDI %0:gpr, target-flags(riscv-lo) @__const._Z3foov.var_49
48B dead $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
64B undef %25.sub_vrm2_0:vrn4m2nov0 = PseudoVLE16_V_M2 %1:gpr, 2, 4, implicit $vl, implicit $vtype
80B %3:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_48
96B %4:gpr = ADDI %3:gpr, target-flags(riscv-lo) @__const._Z3foov.var_48
112B %5:vr = PseudoVLE8_V_M1 %4:gpr, 2, 3, implicit $vl, implicit $vtype
128B %6:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_46
144B %7:gpr = ADDI %6:gpr, target-flags(riscv-lo) @__const._Z3foov.var_46
160B %25.sub_vrm2_1:vrn4m2nov0 = PseudoVLE16_V_M2 %7:gpr, 2, 4, implicit $vl, implicit $vtype
176B %9:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_45
192B %10:gpr = ADDI %9:gpr, target-flags(riscv-lo) @__const._Z3foov.var_45
208B %25.sub_vrm2_2:vrn4m2nov0 = PseudoVLE16_V_M2 %10:gpr, 2, 4, implicit $vl, implicit $vtype
224B INLINEASM &"" [sideeffect] [attdialect], $0:[clobber], ...
240B %12:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_44
256B %13:gpr = ADDI %12:gpr, target-flags(riscv-lo) @__const._Z3foov.var_44
272B dead $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
288B %25.sub_vrm2_3:vrn4m2nov0 = PseudoVLE16_V_M2 %13:gpr, 2, 4, implicit $vl, implicit $vtype
304B $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
320B %16:gpr = LUI target-flags(riscv-hi) @__const._Z3foov.var_40
336B %17:gpr = ADDI %16:gpr, target-flags(riscv-lo) @__const._Z3foov.var_40
352B %18:vrm2 = PseudoVLE16_V_M2 %17:gpr, 2, 4, implicit $vl, implicit $vtype
368B $x0 = PseudoVSETIVLI 2, 73, implicit-def $vl, implicit-def $vtype
384B %20:gpr = LUI 1048572
400B %21:gpr = ADDIW %20:gpr, 928
416B early-clobber %22:vr = PseudoVMSBC_VX_M2 %18:vrm2, %21:gpr, 2, 4, implicit $vl, implicit $vtype
432B $x0 = PseudoVSETIVLI 2, 9, implicit-def $vl, implicit-def $vtype
448B $v0 = COPY %22:vr
464B early-clobber %25.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %25.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, killed $v0, 2, 4, 0, implicit $vl, implicit $vtype
480B %26:gpr = LUI target-flags(riscv-hi) @var_47
496B %27:gpr = ADDI %26:gpr, target-flags(riscv-lo) @var_47
512B PseudoVSSEG4E16_V_M2 %25:vrn4m2nov0, %27:gpr, 2, 4, implicit $vl, implicit $vtype
528B PseudoRET
```
When spliter will try to split %25:
```
selectOrSplit VRN4M2NoV0:%25 [64r,160r:4)[160r,208r:0)[208r,288r:1)[288r,464e:2)[464e,512r:3) 0@160r 1@208r 2@288r 3@464e 4@64r L0000000000000030 [160r,512r:0) 0@160r L00000000000000C0 [208r,512r:0) 0@208r L0000000000000300 [288r,512r:0) 0@288r L000000000000000C [64r,464e:1)[464e,512r:0) 0@464e 1@64r weight:1.179245e-02 w=1.179245e-02
```
```
Best local split range: 64r-208r, 6.999861e-03, 3 instrs
enterIntvBefore 64r: not live
leaveIntvAfter 208r: valno 1
useIntv [64B;216r): [64B;216r):1
blit [64r,160r:4): [64r;160r)=1(%29)(recalc)
blit [160r,208r:0): [160r;208r)=1(%29)(recalc)
blit [208r,288r:1): [208r;216r)=1(%29)(recalc) [216r;288r)=0(%28)(recalc)
blit [288r,464e:2): [288r;464e)=0(%28)(recalc)
blit [464e,512r:3): [464e;512r)=0(%28)(recalc)
rewr %bb.0 464e:0 early-clobber %28.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %25.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
rewr %bb.0 288r:0 %28.sub_vrm2_3:vrn4m2nov0 = PseudoVLE16_V_M2 %13:gpr, 2, 4, implicit $vl, implicit $vtype
rewr %bb.0 208r:1 %29.sub_vrm2_2:vrn4m2nov0 = PseudoVLE16_V_M2 %10:gpr, 2, 4, implicit $vl, implicit $vtype
rewr %bb.0 160r:1 %29.sub_vrm2_1:vrn4m2nov0 = PseudoVLE16_V_M2 %7:gpr, 2, 4, implicit $vl, implicit $vtype
rewr %bb.0 64r:1 undef %29.sub_vrm2_0:vrn4m2nov0 = PseudoVLE16_V_M2 %1:gpr, 2, 4, implicit $vl, implicit $vtype
rewr %bb.0 464B:0 early-clobber %28.sub_vrm2_0:vrn4m2nov0 = PseudoVSEXT_VF2_M2_MASK %28.sub_vrm2_0:vrn4m2nov0(tied-def 0), %5:vr, $v0, 2, 4, 0, implicit $vl, implicit $vtype
rewr %bb.0 512B:0 PseudoVSSEG4E16_V_M2 %28:vrn4m2nov0, %27:gpr, 2, 4, implicit $vl, implicit $vtype
rewr %bb.0 216B:1 undef %28.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0 = COPY %29.sub_vrm1_0_sub_vrm1_1_sub_vrm1_2_sub_vrm1_3_sub_vrm1_4_sub_vrm1_5:vrn4m2nov0
queuing new interval: %28 [216r,288r:0)[288r,464e:1)[464e,512r:2) 0@216r 1@288r 2@464e L000000000000000C [216r,216d:0)[464e,512r:1) 0@216r 1@464e L0000000000000300 [288r,512r:0) 0@288r L00000000000000C0 [216r,512r:0) 0@216r L0000000000000030 [216r,512r:0) 0@216r weight:8.706897e-03
Enqueuing %28
queuing new interval: %29 [64r,160r:0)[160r,208r:1)[208r,216r:2) 0@64r 1@160r 2@208r L000000000000000C [64r,216r:0) 0@64r L00000000000000C0 [208r,216r:0) 0@208r L0000000000000030 [160r,216r:0) 0@160r weight:1.097826e-02
Enqueuing %29
```
The live range of first part subreg of %25 is become [216r,216d:0)[464e,512r:1),
however first live range should live until 464e rather than just live
and [216r,216d:0).
And then the register allocator allocated wrong result accroding the
live range info.
Reviewed By: craig.topper
Differential Revision: https://reviews.llvm.org/D126047
Nathan Lanza [Wed, 8 Jun 2022 02:55:05 +0000 (22:55 -0400)]
[MLIR] Add an install target for mlir-libraries
This is required for the distribution system for installing the
mlir-libraries component. This is copied from clang's equivalent
feature.
Differential Revision: https://reviews.llvm.org/D126837
Chuanqi Xu [Tue, 24 May 2022 06:09:18 +0000 (14:09 +0800)]
[Debug] [Coroutines] Add deref operator for non complex expression
Background:
When we construct coroutine frame, we would insert a dbg.declare
intrinsic for it:
```
%hdl = call void @llvm.coro.begin() ; would return coroutine handle
call void @llvm.dbg.declare(metadata ptr %hdl, metadata
![[DEBUG_VARIABLE: __coro_frame]], metadata !DIExpression())
```
And in the splitted coroutine, it looks like:
```
define void @coro_func.resume(ptr *hdl) {
entry.resume:
call void @llvm.dbg.declare(metadata ptr %hdl, metadata
![[DEBUG_VARIABLE: __coro_frame]], metadata !DIExpression())
}
```
And we would salvage the debug info by inserting a new alloca here:
```
define void @coro_func.resume(ptr %hdl) {
entry.resume:
%frame.debug = alloca ptr
call void @llvm.dbg.declare(metadata ptr %frame.debug, metadata
![[DEBUG_VARIABLE: __coro_frame]], metadata !DIExpression())
store ptr %hdl, %frame.debug
}
```
But now, the problem comes since the `dbg.declare` refers to the address
of that alloca instead of actual coroutine handle. I saw there are codes
to solve the problem but it only applies to complex expression only. I
feel if it is OK to relax the condition to make it work for
`__coro_frame`.
Reviewed By: jmorse
Differential Revision: https://reviews.llvm.org/D126277
Nathan Lanza [Wed, 8 Jun 2022 02:48:24 +0000 (22:48 -0400)]
Update the ProgrammersManual explanation for ilist and iplist
They are now `using` aliases and thus the comments about iplist are now
incorrect. Remove them here.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D95210
Sunho Kim [Wed, 8 Jun 2022 01:17:26 +0000 (18:17 -0700)]
[JITLink][ELF][AArch64] Implement ADR_GOT_PAGE, LD64_GOT_LO12_NC.
This patch implements two most commonly used Global Offset Table relocations in
ELF/AARCH64: R_AARCH64_ADR_GOT_PAGE and R_AARCH64_LD64_GOT_LO12_NC. It
implements the GOT table manager by extending the existing
PerGraphGOTAndPLTStubsBuilder. A future patch will unify this with the MachO
implementation to produce a generic aarch64 got table manager.
Reviewed By: lhames
Differential Revision: https://reviews.llvm.org/D127057
Leonard Chan [Wed, 8 Jun 2022 01:09:48 +0000 (18:09 -0700)]
Reland "[NFC][compiler-rt][asan] Unify asan and lsan allocator settings"
I believe this should've been fixed with
4b15e665f8d99d3b67b30e615544279654392745
which landed after this initial patch, but I reverted too early before I
saw the builder turn green again.
Joe Loser [Tue, 7 Jun 2022 18:54:57 +0000 (12:54 -0600)]
Revert "[libc++][test] Mark ranges.transform.pass.cpp UNSUPPORTED for AIX"
This reverts commit
3583826bb52a7f129b55df043e29860aeab9906d.
Instead of marking the test unsupported for AIX, the choice is to bump the
timeout for CI as done in
76c7e1f2a8820b057de1a241422294bf25fdea2d and
222bd83d505728fca2bbe16cef8b93c321dd8c13
Differential Revision: https://reviews.llvm.org/D127242
Wael Yehia [Fri, 27 May 2022 03:09:54 +0000 (03:09 +0000)]
[InstCombine] decomposeSimpleLinearExpr should bail out on negative operands.
InstCombine tries to rewrite
%prod = mul nsw i64 %X, Scale
%acc = add nsw i64 %prod, Offset
%0 = alloca i8, i64 %acc, align 4
%1 = bitcast i8* %0 to i32*
Use ( %1 )
into
%prod = mul nsw i64 %X, Scale/4
%acc = add nsw i64 %prod, Offset/4
%0 = alloca i32, i64 %acc, align 4
Use (%0)
But it assumes Scale is unsigned, and performs an unsigned division.
So we should bail out if Scale cannot be interpreted as an unsigned safely.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D126546
Lang Hames [Wed, 8 Jun 2022 00:48:09 +0000 (17:48 -0700)]
[JITLink][ELF][AArch64] Implement R_AARCH64_ABS64 relocation type.
Implement R_AARCH64_ABS64 relocation entry. This relocation type is generated
when creating a static function pointer to symbol.
Reviewed By: lhames, sgraenitz
Differential Revision: https://reviews.llvm.org/D126658
Kevin Athey [Wed, 8 Jun 2022 00:52:03 +0000 (17:52 -0700)]
[MSAN] exclude android from pthread_getaffinity_np interceptor
Depends on https://reviews.llvm.org/D127185.
Differential Revision: https://reviews.llvm.org/D127264
Leonard Chan [Wed, 8 Jun 2022 00:33:24 +0000 (17:33 -0700)]
Revert "[NFC][compiler-rt][asan] Unify asan and lsan allocator settings"
This reverts commit
dd045ddffc51db0a5ff9e00b1d55220af20614be.
This broke the sanitizer-windows builder at https://lab.llvm.org/buildbot/#/builders/127/builds/30751.
Sunho Kim [Wed, 8 Jun 2022 00:16:41 +0000 (17:16 -0700)]
[JITLink][ELF][AArch64] Implement R_AARCH64_LDST*_ABS_LO12_NC relocation types.
Implement R_AARCH64_LDST*_ABS_LO12_NC relocaiton entries by reusing PageOffset21
generic relocation edge. The difference between MachO backend is that in ELF,
the shift value is explicitly given by relocation type. lld generates the
relocation type that matches with instruction bitwidth, so getting the shift
value implicitly from instruction bytes should be fine in typical use cases.
Leonard Chan [Wed, 8 Jun 2022 00:28:24 +0000 (17:28 -0700)]
Fix for
e1d84c421df1bd496918bc4dd30f040d47906a77
One of the checks in realloc_too_big.c actually printed a regular warning
and not an OOM error, so the check shouldn't be updated.
Leonard Chan [Wed, 1 Jun 2022 21:12:13 +0000 (14:12 -0700)]
[compiler-rt][lsan] Choose lsan allocator via SANITIZER_CAN_USE_ALLOCATOR64
Rather than checking a bunch of individual platforms.
Differential Revision: https://reviews.llvm.org/D126825
Leonard Chan [Fri, 3 Jun 2022 21:35:47 +0000 (14:35 -0700)]
[NFC][compiler-rt][asan] Unify asan and lsan allocator settings
This updates existing asan allocator settings to use the same allocator settings as what lsan uses for platforms where they already match.
Differential Revision: https://reviews.llvm.org/D126927
Derek Schuff [Tue, 7 Jun 2022 23:45:23 +0000 (16:45 -0700)]
[WebAssembly][Objcopy] Check that --only-keep-debug removes known sections
NFC; Just update the test to ensure that both known and custom sections
are removed.
Review left over from https://reviews.llvm.org/D126509
Leonard Chan [Tue, 7 Jun 2022 23:45:01 +0000 (16:45 -0700)]
[compiler-rt][sanitizer] Have all OOM-related error messages start with the same format
This way downstream tools that read sanitizer output can differentiate between OOM errors
reported by sanitizers from other sanitizer errors.
Changes:
- Introduce ErrorIsOOM for checking if a platform-specific error code from an "mmap" is an OOM err.
- Add ReportOOMError which just prepends this error message to the start of a Report call.
- Replace some Reports for OOMs with calls to ReportOOMError.
- Update necessary tests.
Differential Revision: https://reviews.llvm.org/D127161
Lang Hames [Tue, 7 Jun 2022 23:42:10 +0000 (16:42 -0700)]
[ORC-RT] Remove a stale comment.
Sunho Kim [Tue, 7 Jun 2022 21:03:52 +0000 (14:03 -0700)]
[JITLink][ELF][AArch64] Implement ADR_PREL_PG_HI21, ADD_ABS_LO12_NC.
Implements R_AARCH64_ADR_PREL_PG_HI21 and R_AARCH64_ADD_ABS_LO12_NC fixup edges
using the generic aarch64 patch edges.
Reviewed By: lhames, sgraenitz
Differential Revision: https://reviews.llvm.org/D126287
Kevin Athey [Tue, 7 Jun 2022 07:00:20 +0000 (00:00 -0700)]
[MSAN] Add interceptor for pthread_getaffinity_np.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D127185
Kevin Athey [Tue, 7 Jun 2022 03:50:19 +0000 (20:50 -0700)]
Add checks for -lresolv to sanitizer-ld test.
These were missed in https://reviews.llvm.org/D127145.
Reviewed By: vitalybuka
Differential Revision: https://reviews.llvm.org/D127177
Wolfgang Pieb [Tue, 7 Jun 2022 22:13:29 +0000 (15:13 -0700)]
Revert "[Metadata] Add a resize capability to MDNodes and add a push_back interface to MDNodes"
This reverts commit
e3f6eda8c6ebc567755377911746d4ca2367e649.
Failure in unittest on https://lab.llvm.org/buildbot*builders/171/builds/15666
Sanjay Patel [Tue, 7 Jun 2022 20:54:11 +0000 (16:54 -0400)]
[InstCombine] [InstCombine] reduce left-shift-of-right-shifted constant via demanded bits
If we don't demand low bits and it is valid to pre-shift a constant:
(C2 >> X) << C1 --> (C2 << C1) >> X
https://alive2.llvm.org/ce/z/_UzTMP
This is the reverse-order shift sibling to
82040d414b3c ( D127122 ).
It seems likely that we would want to add this to the SDAG version of
the code too to keep it on par with IR.
Sanjay Patel [Tue, 7 Jun 2022 19:49:22 +0000 (15:49 -0400)]
[InstCombine] add tests for left-shift-of-right-shifted constant; NFC
The tests are adapted from the sibling folds' tests (see D127122).
Sanjay Patel [Tue, 7 Jun 2022 17:42:43 +0000 (13:42 -0400)]
[InstCombine] reduce code duplication for accessing type; NFC
owenca [Tue, 7 Jun 2022 10:05:18 +0000 (03:05 -0700)]
[clang-format] Skip parsing a block if it's nested too deep
Fixes #55912.
Differential Revision: https://reviews.llvm.org/D127183
Pengxuan Zheng [Tue, 7 Jun 2022 17:24:30 +0000 (10:24 -0700)]
[NFC][test] Improve ecsymbols.test
* The yaml input is inlined into the test file.
* Unnecessary members and fields are removed.
Reviewed By: thieta
Differential Revision: https://reviews.llvm.org/D127235
Nico Weber [Tue, 7 Jun 2022 22:13:13 +0000 (18:13 -0400)]
[gn build] (manually) port
f3966eaf86 (_LIBCPP_ENABLE_DEBUG_MODE)
Douglas Yung [Tue, 7 Jun 2022 21:58:10 +0000 (14:58 -0700)]
Revert "[clang-diff] Fix assertion error when dealing with wide strings"
This reverts commit
e80748ff8840a10bd7c7336eb5e98664480ba1ba.
This was causing a test failure on a buildbot: https://lab.llvm.org/buildbot/#/builders/139/builds/22964
Paul Kirth [Mon, 6 Jun 2022 18:14:20 +0000 (18:14 +0000)]
[compiler-rt] Avoid truncating Symbolizer output
Repalce the fixed buffer in SymbolizerProcess with InternalScopedString,
and simply append to it when reading data.
Fixes #55460
Reviewed By: vitalybuka, leonardchan
Differential Revision: https://reviews.llvm.org/D126580
Wolfgang Pieb [Mon, 16 May 2022 18:22:46 +0000 (11:22 -0700)]
[Metadata] Add a resize capability to MDNodes and add a push_back interface to MDNodes
A change to the allocation characteristics of MDNodes, introducing the ability
to add operands one at a time. This functionality is restricted to MDTuples.
Reviewed By: dexonsmith
Differential Revision: https://reviews.llvm.org/D125998
Jason Molenda [Tue, 7 Jun 2022 21:31:56 +0000 (14:31 -0700)]
Skip TestConcurrentWatchBreak.py on Darwin arm64
This test depends on multiple threads with one of them
hitting a watchpoint at the same time as a breakpoint, and
can fail because of the way arm64 watchpoints are handled.
I added skips to most of these via
```
commit
bef4da4a6aef8196f007f44e3e9c8e3419ffb623
Author: Jason Molenda <jason@molenda.com>
Date: Wed May 25 16:05:16 2022 -0700
Skip testing of watchpoint hit-count/ignore-count on multithreaded
```
but missed that this test is susceptable to the same issue.
Aart Bik [Tue, 7 Jun 2022 00:27:27 +0000 (17:27 -0700)]
[mlir][sparse] updated our sparse dialect doc with some recent changes
The `init` and `tensor` ops are renamed (and one moved to another dialect).
Reviewed By: springerm
Differential Revision: https://reviews.llvm.org/D127169
Vitaly Buka [Tue, 7 Jun 2022 16:37:53 +0000 (09:37 -0700)]
[NFC] Exctract getNoSanitizeMask lambda
Vitaly Buka [Tue, 7 Jun 2022 04:43:47 +0000 (21:43 -0700)]
[NFC] Move part of SanitizerMetadata into private method
Mitch Phillips [Tue, 7 Jun 2022 04:21:15 +0000 (21:21 -0700)]
[NFC] Clang-format parts of D126929 and D126100
Mitch Phillips [Tue, 7 Jun 2022 04:18:33 +0000 (21:18 -0700)]
[NFC][CodeGen] Rename method
Extracted from D84652.
Christopher Bate [Tue, 7 Jun 2022 20:42:42 +0000 (14:42 -0600)]
Revert "[mlir][vector] Allow unroll of contraction in arbitrary order"
Reverts commit
1469ebf8382107e0344173f362b690d19e24029d (original commit)
Reverts commit
a392a39f75af586e3d3cd046a8361939277e067f (build fix for above commit)
The commit broke tests in out-of-tree projects, indicating that some logical
error was made in the previous change but not covered by current tests.
Jason Molenda [Tue, 7 Jun 2022 20:27:16 +0000 (13:27 -0700)]
Track transition from launch dyld to shared-cache dyld
On macOS, a process will be launched with /usr/lib/dyld (the
dynamic linker) and the main binary by the kernel. The
first thing the standalone dyld will do is call into the dyld
in the shared cache image. This patch tracks the transition
between the dyld's at the very beginning of process startup.
In DynamicLoaderMacOS::NotifyBreakpointHit() there are two new
cases handled:
`dyld_image_dyld_moved` which is the launch /usr/lib/dyld indicating
that it is about call into the shared cache dyld ane evict itself.
lldb will remove the notification breakpoint it set, clear the binary
image list entirely, get the notification function pointer value out
of the dyld_all_image_infos struct (which is the notification fptr
in the to-be-run shared-cache dyld) and put an address breakpoint
there.
`dyld_notify_adding` is then called by shared-cache dyld, and we
detect this case by noticing that we have an empty binary image list,
normally impossibe, and treating this as if we'd just started a
process attach/launch.
Differential Revision: https://reviews.llvm.org/D127247
rdar://
84222158
Louis Dionne [Fri, 1 Apr 2022 20:38:30 +0000 (16:38 -0400)]
[libc++] Make the Debug mode a configuration-time only option
The debug mode has been broken pretty much ever since it was shipped
because it was possible to enable the debug mode in user code without
actually enabling it in the dylib, leading to ODR violations that
caused various kinds of failures.
This commit makes the debug mode a knob that is configured when
building the library and which can't be changed afterwards. This is
less flexible for users, however it will actually work as intended
and it will allow us, in the future, to add various kinds of checks
that do not assume the same ABI as the normal library. Furthermore,
this will make the debug mode more robust, which means that vendors
might be more tempted to support it properly, which hasn't been the
case with the current debug mode.
This patch shouldn't break any user code, except folks who are building
against a library that doesn't have the debug mode enabled and who try
to enable the debug mode in their code. Such users will get a compile-time
error explaining that this configuration isn't supported anymore.
In the future, we should further increase the granularity of the debug
mode checks so that we can cherry-pick which checks to enable, like we
do for unspecified behavior randomization.
Differential Revision: https://reviews.llvm.org/D122941
Philip Reames [Tue, 7 Jun 2022 20:27:13 +0000 (13:27 -0700)]
[GuardWidening] Fix a nasty cast bug in c2eccc6
c2eccc6 introduced a call to etHasNoUnsignedWrap which implicitly assumes that Inst is a OverflowingBinaryOperator. This is frequently untrue, but was not caught because cast<Ty>(X) has been broken, see https://discourse.llvm.org/t/cast-x-is-broken-implications-and-proposal-to-address/63033 for context.
I considered reverting this, but since doing so re-introduces a nasty miscompile of its own, I decided to fix forward instead.
I'll note that this is a particularly nasty form of the cast<Ty>(X) issue. Because the cast was succeeding unexpected, we were writing data to instructions which weren't OBOs. This could result in near arbitrary data or memory corruption. I'm a bit shocked that the sanitizers didn't find this TBH.
Philip Reames [Tue, 7 Jun 2022 20:09:48 +0000 (13:09 -0700)]
Revert "[MemDep][NFCI] Remove redundant dyn_cast, replace with cast"
This reverts commit
180d3f251d1ad5473705d3f00e6d426b5f8162e6. This commit is simply wrong. IsLoad is set within the same file based on modref state, not whether the instruction is a LoadInst.
This went uncaught because cast<Ty>(X) has been broken. See https://discourse.llvm.org/t/cast-x-is-broken-implications-and-proposal-to-address/63033 for context.
Sunho Kim [Tue, 7 Jun 2022 19:29:12 +0000 (12:29 -0700)]
[JITLink][AArch64] Refactor isLoadStoreImm12 check out of getPageOffset12Shift.
The separate isLoadStoreImm12 predicate will be used for validating ELF/aarch64
ldst relocation types.
Reviewed By: lhames, sgraenitz
Differential Revision: https://reviews.llvm.org/D126628
Florian Hahn [Tue, 7 Jun 2022 20:00:49 +0000 (21:00 +0100)]
[VPlan] Handle VPInst without underlying instr in VPInterleavedAccess.
This violation is hidden while `cast` is missing an isa assertion after
D123901.
Joseph Huber [Mon, 6 Jun 2022 17:08:01 +0000 (13:08 -0400)]
[Binary] Make the OffloadingImage type own the memory
Summary:
The OffloadingBinary uses a convenience struct to help manage the memory
that will be serialized using the binary format. This currently uses a
reference to an existing buffer, but this should own the memory instead
so it is easier to work with seeing as its only current use requires
saving the buffer anyway.
Joseph Huber [Sat, 4 Jun 2022 20:56:45 +0000 (16:56 -0400)]
[Binary] Align the image offset in OffloadBinary
Summary:
The OffloadBinary wraps around an embedded device image, commonly an ELF
or LLVM BC file. These file formats have alignment requirements for
parsing, so if the image is stored at an un-aligned offset from the
beginning of the file we will be unable to parse the embeded image
without copying the image buffer. This patch adds alignment padding
before the binary image is appended to ensure we can parse the symbolic
file it contains in-place without copying memory.
Aaron Ballman [Tue, 7 Jun 2022 19:52:28 +0000 (15:52 -0400)]
Update the C2x status page from latest working draft
This adds the papers for the Jun, Sep, and Dec 2021 meetings. 2022
papers will be handled in a follow-up.
Philip Reames [Tue, 7 Jun 2022 19:23:43 +0000 (12:23 -0700)]
Revert "[LLVM][Casting.h] Add trivial self-cast"
This reverts commit
0809f63826d36c89574d6ac056ebf46a4b6f29ff. The patch appears not to have included corresponding isa<Ty> support.
This was revealed when reintroducing the required isa<Ty> asserts in cast<Ty>. See https://discourse.llvm.org/t/cast-x-is-broken-implications-and-proposal-to-address/63033 for context.
Here's the template instantiation error:
In file included from /home/preames/llvm-repo/llvm-project/llvm/unittests/Support/Casting.cpp:9:
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h: In instantiation of ‘static bool llvm::isa_impl<To, From, Enabler>::doit(const From&) [with To = llvm::bar*; From = llvm::bar; Enabler = void]’:
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:110:36: required from ‘static bool llvm::isa_impl_cl<To, const From*>::doit(const From*) [with To = llvm::bar*; From = llvm::bar]’
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:137:41: required from ‘static bool llvm::isa_impl_wrap<To, FromTy, FromTy>::doit(const FromTy&) [with To = llvm::bar*; FromTy = const llvm::bar*]’
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:129:13: required from ‘static bool llvm::isa_impl_wrap<To, From, SimpleFrom>::doit(const From&) [with To = llvm::bar*; From = const llvm::bar* const; SimpleFrom = const llvm::bar*]’
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:263:62: required from ‘static bool llvm::CastIsPossible<To, From, Enable>::isPossible(const From&) [with To = llvm::bar*; From = const llvm::bar*; Enable = void]’
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:517:38: required from ‘static bool llvm::CastInfo<To, From, typename std::enable_if<(! llvm::is_simple_type<From>::value), void>::type>::isPossible(From&) [with To = llvm::bar*; From = llvm::bar* const]’
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:556:46: required from ‘bool llvm::isa(const From&) [with To = llvm::bar*; From = llvm::bar*]’
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:585:3: required from ‘decltype(auto) llvm::cast(From*) [with To = llvm::bar*; From = llvm::bar]’
/home/preames/llvm-repo/llvm-project/llvm/unittests/Support/Casting.cpp:181:27: required from here
/home/preames/llvm-repo/llvm-project/llvm/include/llvm/Support/Casting.h:64:64: error: ‘classof’ is not a member of ‘llvm::bar*’
64 | static inline bool doit(const From &Val) { return To::classof(&Val); }
Martin Sebor [Tue, 7 Jun 2022 19:45:10 +0000 (13:45 -0600)]
[InstCombine] Fold memchr of sequences of same characters
Enhance memchr libcall folder to handle constant arrays consisting
of one or two sequences of cosecutive equal characters.
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D126515
Martin Sebor [Tue, 7 Jun 2022 18:54:31 +0000 (12:54 -0600)]
[InstCombine] Add substr helper function (NFC).
Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D126515
Sam Estep [Tue, 7 Jun 2022 19:17:00 +0000 (19:17 +0000)]
[clang][dataflow][NFC] Fix filename typos in tests
Reviewed By: ymandel
Differential Revision: https://reviews.llvm.org/D127008
Joe Nash [Wed, 18 May 2022 19:01:20 +0000 (15:01 -0400)]
Reland [AMDGPU] gfx11 vop3dpp instructions
There was an issue with encoding wide (>64 bit) instructions on
BigEndian hosts, which is fixed in D127195. Therefore reland this.
gfx11 adds the ability to use dpp modifiers on vop3 instructions.
This patch adds machine code layer support for that. The MCCodeEmitter
is changed to use APInt instead of uint64_t to support these wider
instructions.
Patch 16/N for upstreaming of AMDGPU gfx11 architecture
Differential Revision: https://reviews.llvm.org/D126483
Derek Schuff [Mon, 6 Jun 2022 22:42:24 +0000 (15:42 -0700)]
[WebAssembly] Add WASM_SEC_LAST_KNOWN to BinaryFormat section types list [NFC]
There are 3 places where we were using WASM_SEC_TAG as the "last" known
section type, which requires updating (or leaves a bug) when a new known
section type is added. Instead add a "last type" to the enum for this
purpose.
Differential Revision: https://reviews.llvm.org/D127164
Sunho Kim [Tue, 7 Jun 2022 18:39:05 +0000 (11:39 -0700)]
[JITLink][ELF][AArch64] Lift MachO/arm64 edges into aarch64.h, reuse for ELF.
This patch moves the aarch64 fixup logic from the MachO/arm64 backend to
aarch64.h header so that it can be re-used in the ELF/aarch64 backend. This
significantly expands relocation support in the ELF/aarch64 backend.
Reviewed By: lhames, sgraenitz
Differential Revision: https://reviews.llvm.org/D126286
William Huang [Tue, 7 Jun 2022 18:48:24 +0000 (18:48 +0000)]
[ValueTracking] Add support to deduce a PHI node being a power of 2 if each incoming value is a power of 2.
Reviewed By: davidxl
Differential Revision: https://reviews.llvm.org/D124889
Reid Kleckner [Fri, 3 Jun 2022 17:27:02 +0000 (10:27 -0700)]
[config] Remove vestigial LLVM_VERSION_INFO
This has been superseded by the llvm/Support/VCSRevision.h header. So
far as I can tell, nothing in the CMake build sets LLVM_VERSION_INFO. It
was always undefined, and the ifdefs using it were dead. However, CMake
is very flexible, so it's possible that I missed some ways to set this
variable. One could, for example, probably pass -DLLVM_VERSION_INFO=x on
the command line and get that through to configure_file, or set the
variable in an obscure way (`set(${proj}_VERSION_INFO "x")`). I'm
reasonably confident that isn't happening, but I'd like a second
opinion.
Update the Bazel and gn builds accordingly.
Differential Revision: https://reviews.llvm.org/D126977
Reid Kleckner [Fri, 3 Jun 2022 23:21:42 +0000 (16:21 -0700)]
[config] Remove RETSIGTYPE from config.h.cmake, NFC
This doesn't need to be configurable. It was hardcoded to void in all
LLVM build systems.
Erich Keane [Tue, 7 Jun 2022 18:29:03 +0000 (11:29 -0700)]
[CodeGen] Fix an issue when the 'extern C' replacement names broke
Originally broken by me in D122608, this is a regression where we
attempt to replace an extern-C thing with 'itself'. The problem is that
we end up deleting it, causing the value to fail when it gets put into
llvm.used.
Philip Reames [Tue, 7 Jun 2022 14:43:00 +0000 (07:43 -0700)]
[PointerUnionTest] Fix an incorrectly written test
The test being change appears to have been intended to exercise PointerUnion, but what it actually did was cast<> a double to a double*. This only worked because cast<> was missing the required assertion. Adding the assertion reveals a template error where isa<const double*>(double) fails to compile.
Kaining Zhong [Tue, 7 Jun 2022 17:39:46 +0000 (19:39 +0200)]
[clang-diff] Fix assertion error when dealing with wide strings
Directly using StringLiteral::getString for wide string is not
currently supported; therefore in ASTDiff, getStmtValue will fail when
asserting that the StringLiteral has a width of 1. This patch also
covers cases for UTF16 and UTF32 encoding, along with corresponding
test cases.
Fixes https://github.com/llvm/llvm-project/issues/55771.
Reviewed By: johannes
Differential Revision: https://reviews.llvm.org/D126651
Jay Foad [Tue, 7 Jun 2022 09:41:50 +0000 (10:41 +0100)]
[CodeEmitter] Fix encoding wide instructions on big-endian hosts
For instructions wider than 64 bits the InstBits table is initialized in
64-bit chunks from APInt::getRawData, but it was being read with
LoadIntFromMemory which is byte-based.
Fix this by reading the table with the APInt constructor that takes an
ArrayRef to the raw data instead.
This is currently NFC for in-tree targets but fixes AMDGPU failures on
big-endian hosts that were caused by D126483 until it was reverted.
Differential Revision: https://reviews.llvm.org/D127195
David Green [Tue, 7 Jun 2022 17:57:59 +0000 (18:57 +0100)]
[AArch64] Remove isDef32
isDef32 would attempt to make a guess at which SelectionDag nodes were
32bit sources, and use the nature of 32bit AArch64 instructions
implicitly zeroing the upper register half to not emit zext that were
expected to already be zero. This was a bit fragile though, needing to
guess at the correct opcodes that do not become 32bit defs later in
ISel.
This patch removed isDef32, relying on the AArch64MIPeephole optimizer
to remove redundant SUBREG_TO_REG nodes. A part of
SelectArithExtendedRegister was left with the same logic as a heuristic
to prevent some regressions from it picking less optimal sequences.
The AArch64MIPeepholeOpt pass also needs to be taught that a COPY from a
FPR will become a FMOVSWr, which it lowers immediately to make sure that
remains true through register allocation.
Fixes #55833
Differential Revision: https://reviews.llvm.org/D127154
Vince Bridgers [Mon, 6 Jun 2022 12:23:08 +0000 (08:23 -0400)]
[analyzer] Fix null pointer deref in CastValueChecker
A crash was seen in CastValueChecker due to a null pointer dereference.
The fix uses QualType::getAsString to avoid the null dereference
when a CXXRecordDecl cannot be obtained. A small reproducer is added,
and cast value notes LITs are updated for the new debug messages.
Reviewed By: steakhal
Differential Revision: https://reviews.llvm.org/D127105
Sanjay Patel [Tue, 7 Jun 2022 16:42:12 +0000 (12:42 -0400)]
[InstCombine] reduce right-shift-of-left-shifted constant via demanded bits
If we don't demand high bits (zeros) and it is valid to pre-shift a constant:
(C2 << X) >> C1 --> (C2 >> C1) << X
https://alive2.llvm.org/ce/z/P3dWDW
There are a variety of related patterns, but I haven't found a single solution
that gets all of the motivating examples - so pulling this piece out of
D126617 along with more tests.
We should also handle the case where we shift-right followed by shift-left,
but I'll make that a follow-on patch assuming this one is ok. It seems likely
that we would want to add this to the SDAG version of the code too to keep it
on par with IR.
Differential Revision: https://reviews.llvm.org/D127122
Sanjay Patel [Tue, 7 Jun 2022 12:54:38 +0000 (08:54 -0400)]
[InstCombine] add vector tests for shift-shift; NFC
D127122
Groverkss [Tue, 7 Jun 2022 17:19:34 +0000 (22:49 +0530)]
[MLIR][Presburger] Fix subtract processing extra inequalities
This patch fixes a bug in PresburgeRelation::subtract that made it process the
inequality at index 0, multiple times. This was caused by allocating memory
instead of reserving memory in llvm::SmallVector.
Reviewed By: arjunp
Differential Revision: https://reviews.llvm.org/D127228
Alan Zhao [Thu, 2 Jun 2022 23:42:37 +0000 (19:42 -0400)]
[llvm-ml] Remove all file extension restrictions
After D126425 was submitted, hans@ observed that MSVC's ml.exe doesn't
care about the file's extension at all. Now, we check if the file exists
to determine whether an input filename is a valid assembly file.
To keep things consistent with clang-cl and lld-link, llvm-ml will treat
everything that's not a flag as a filename.
Reviewed By: hans
Differential Revision: https://reviews.llvm.org/D126931
Mark de Wever [Tue, 31 May 2022 16:58:54 +0000 (18:58 +0200)]
[libc++] Removes _LIBCPP_AVAILABILITY_TO_CHARS.
After moving the std::to_chars base 10 implementation from the dylib to
the header the integral overloads of std::to_chars are available on all
platforms.
Remove the _LIBCPP_AVAILABILITY_TO_CHARS availability macro and update
the tests.
Depends on D125704
Reviewed By: ldionne, #libc
Differential Revision: https://reviews.llvm.org/D125745
Philip Reames [Tue, 7 Jun 2022 16:54:23 +0000 (09:54 -0700)]
Add initial coverage for invalid instruction costs in LoopRotate
Once extended with a case which requires duplication, will serve as test for crash being fixed in D127131.
Mark de Wever [Mon, 30 May 2022 16:34:15 +0000 (18:34 +0200)]
[libc++][CI] Updates Docker image.
- Updates the image to use Ubuntu Jammy.
- Installs GCC-12 as preparation to migrate to that GCC version.
Reviewed By: ldionne, #libc, jloser
Differential Revision: https://reviews.llvm.org/D126666
Mark de Wever [Thu, 2 Jun 2022 06:16:40 +0000 (08:16 +0200)]
[libc++] Don't use static constexpr in headers.
This was noticed in the review of D125704. In that commit only the new
table has been adapted. This adapts the existing tables.
Note since libc++'s charconv is backported to C++11 it's not possible to
use inline constexpr variables. The were introduced in C++17.
Reviewed By: #libc, ldionne
Differential Revision: https://reviews.llvm.org/D126887
David Penry [Tue, 29 Mar 2022 17:13:55 +0000 (10:13 -0700)]
[NFC] Fix spelling/newlines in comments/debug messages
Just a few spelling mistakes and missing newlines
Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D127162
Benjamin Kramer [Tue, 7 Jun 2022 16:17:40 +0000 (18:17 +0200)]
[format] Fix an uninitialized variable
parseBlock may decide to leave it unchanged. Found by msan.
Joseph Huber [Tue, 31 May 2022 14:08:25 +0000 (10:08 -0400)]
[Libomptarget] Do not use retaining attributes for the static library
When we build the libomptarget device runtime library targeting bitcode,
we need special care to make sure that certain functions are not
optimized out. This is because we manually internalize and optimize
these definitions, ignoring their standard linkage semantics. When we
build with the static library, we can maintain these semantics and we do
not need these to be kept-alive. Furthermore, if they are kept-alive it
prevents them from being removed during LTO. This prevents us from
completely internalizing `IsSPMDMode` and removing several other
functions. This patch removes these for the static library target by
using a macro definition to enable them.
Reviewed By: JonChesterfield
Differential Revision: https://reviews.llvm.org/D126701
Simon Pilgrim [Tue, 7 Jun 2022 15:42:15 +0000 (16:42 +0100)]
[DAG] combineShuffleOfSplatVal - fold shuffle(splat,undef) -> splat, iff the splat contains no UNDEF elements
As noticed on D127115 - we were missing this fold, instead just having the shuffle(shuffle(x,undef,splatmask),undef) fold. We should be able to merge these into one using SelectionDAG::isSplatValue, but we'll need to match the shuffle's undef handling first.
This also exposed an issue in SelectionDAG::isSplatValue which was incorrectly propagating the undef mask across a bitcast (it was trying to just bail with a APInt::isSubsetOf if it found any undefs but that was actually the wrong way around so didn't fire for partial undef cases).
Muhammad Omair Javaid [Tue, 7 Jun 2022 15:30:24 +0000 (19:30 +0400)]
[LLDB] Remove decorator from XPASSes AArch64/Windows
This patch remove XFAIL decorator from tests which as passing on AArch64
Windows. This is tested on surface pro x using tot llvm and clang 14.0.3
as compiler with visual studio 2019 x86_arm64 environment.
Muhammad Omair Javaid [Tue, 7 Jun 2022 13:47:50 +0000 (17:47 +0400)]
[LLDB] Fix TestBase.generateSource for AArch64/Windows
This patch adds a minor fix in lldbtest.py TestBase.generateSource
function. Generated Python source with directory paths was not being
escaped properly. This fix makes sure we treat dir path as raw string.
Craig Topper [Tue, 7 Jun 2022 15:21:20 +0000 (08:21 -0700)]
[LoopFlatten] Fix crash if the inner loop trip count comes from a sext instruction.
If we look through a truncate in matchLinearIVUser, it's possible
we find a sext/zext instruction that didn't come from widening.
This will fail the MatchedItCount->getType() == InnerInductionPHI->getType()
assertion.
Fix this by checking that we did not look through a truncate already.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D127149
Craig Topper [Tue, 7 Jun 2022 15:20:59 +0000 (08:20 -0700)]
[LoopFlatten] Replace unchecked dyn_cast with cast.
Spotted while reading through the code.
Reviewed By: SjoerdMeijer
Differential Revision: https://reviews.llvm.org/D127146
Craig Topper [Tue, 7 Jun 2022 15:07:49 +0000 (08:07 -0700)]
[RISCV] Scalarize gather/scatter on RV64 with Zve32* extension.
i64 indices aren't supported on Zve32*. Scalarize gathers to prevent
generating illegal instructions.
Since InstCombine will aggressively canonicalize GEP indices to
pointer size, we're pretty much always going to have an i64 index.
Trying to predict when SelectionDAG will find a smaller index from
the TTI hook used by the ScalarizeMaskedMemIntrinPass seems fragile.
To optimize this we probably need an IR pass to rewrite it earlier.
Test RUN lines have also been added to make sure the strided load/store
optimization still works.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D127179
Alexey Bataev [Tue, 7 Jun 2022 15:02:14 +0000 (08:02 -0700)]
[SLP]Add a test for geps with non-const indeces in scatter vectorize
nodes, NFC.
LLVM GN Syncbot [Tue, 7 Jun 2022 14:38:58 +0000 (14:38 +0000)]
[gn build] Port
47c8ec811f78
David Truby [Mon, 6 Jun 2022 11:15:38 +0000 (12:15 +0100)]
[clang][AArch64][SVE] Improve diagnostics for SVE operators
This patch corrects some diagnostics for the SVE sizeless vector
operators, including correctly diagnosing when the vectors are
different sizes.
Differential Revision: https://reviews.llvm.org/D126377
Benjamin Kramer [Tue, 7 Jun 2022 14:29:06 +0000 (16:29 +0200)]
[DX][ObjYAML] Zero out unused fields that get written to the output file
Found by msan
Matt Arsenault [Mon, 6 Jun 2022 13:17:55 +0000 (09:17 -0400)]
llvm-reduce: Add -abort-on-invalid-reduction to MIR tests
Ideally reductions would never produce invalid IR, and we shouldn't
regress on cases that already avoid doing so.
Matt Arsenault [Mon, 6 Jun 2022 13:21:02 +0000 (09:21 -0400)]
llvm-reduce: Don't set generic instruction operands to undef
The intention is that these should never have undef operands. It turns
out the restriction the verifier enforces is too lax. The verifier
enforces that registers without a register class cannot be undef, but
it's valid to use a register with a register class and type. The
verifier needs to change to be based on the opcode.
Matt Arsenault [Fri, 22 Apr 2022 15:44:37 +0000 (11:44 -0400)]
llvm-reduce: Add pass to remove register uses
Try to delete implicit uses, and add undef flags to explicit ones.
Jay Foad [Mon, 6 Jun 2022 14:51:18 +0000 (15:51 +0100)]
[AMDGPU] Add support for the .reloc directive
Differential Revision: https://reviews.llvm.org/D127117